tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Thu Jun 29 14:35:57 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m707d.tst reading test file: tests\m707d.tst comment: M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER comment: comment: ICs are VERTICAL on PCB REV D. comment: comment: Rev D adds AB1 ECHO input. comment: comment: does not test AV2 20MA OUTPUT, use scope and pulldown comment: comment: or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) comment: pins: PINS pins: 1 O BJ1 +3V pins: 2 I BF2 CLEAR FLAG 2-N (NORMALLY 3V) pins: 3 I BE2 I/O CLEAR (NORMALLY INITIALIZE) pins: 4 I BP2 2 X BAUD CLOCK INPUT pins: 5 I AE1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB04-N) pins: 6 I AE2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB03-N) pins: 7 I AF1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB06) pins: 8 I AF2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB05-N) pins: 9 I AH2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB08-N) pins: 10 I AJ2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB07-N) pins: 11 I AN1 (FORCE SELECT-N) (NORMALLY HI) NAND(DEVICE SELECT-N)=(SELECTED) pins: 12 I BH2 I/O SKP. STROBE (NORMALLY IOT 1) pins: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) pins: 14 O BK2 P.I.REQ-N (FLAG-N) pins: 15 I BD2 CLEAR FLAG 1 (NORMALLY IOT 2) pins: 16 I AS1 LOAD BUFFER (NORMALLY IOT 4) pins: 17 I AR1 LOAD BUFFER STROBE-N (NAND SELECTED, LOAD BUFFER) pins: 18 I BS2 WAIT-N (PROLONGS STOP BITS) (NORMALLY 3V) pins: 19 O BR2 STOP 1-N pins: 20 O BP1 STOP 1.5-N pins: 21 O BN1 STOP 2-N pins: 22 I BN2 (STOP SELECT) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) pins: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) pins: 25 I AK1 (CHARACTER LOADED) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) pins: 27 I AH1 (DECODE INPUT 8) (NORMALLY CONNECTS TO (ENABLE-N) pins: 28 I AN2 ENABLE (NORMALLY 3V) pins: 29 I AP2 BIT 8 (NORMALLY AC4) pins: 30 I AR2 BIT 7 (NORMALLY AC5) pins: 31 I AL2 BIT 6 (NORMALLY AC6) pins: 32 I AM2 BIT 5 (NORMALLY AC7) pins: 33 I AU2 BIT 4 (NORMALLY AC8) pins: 34 I AS2 BIT 3 (NORMALLY AC9) pins: 35 I AT2 BIT 2 (NORMALLY AC10) pins: 36 I AU1 BIT 1 (NORMALLY AC11) pins: 37 O AD1 ACTIVE pins: 38 O AD2 LINE pins: 39 O AV2 20MA OUTPUT (PNP TO +) pins: 40 I AB1 ECHO (ORS WITH LINE -> 20MA OUTPUT) pins: direction: OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI comment: ; set CLEAR FLAG 2-N, I/O CLEAR comment: ; note: STOP FF outputs are unknown. comment: ; note: 20MA output can not test (open emitter) test 1: 111000000010110011XXX00001110000000001X1 comment: ; remove I/O CLEAR test 2: 0 comment: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs test 3: 1 1 test 4: 0 test 5: 1 1 test 6: 0 test 7: 1 1 test 8: 0 comment: ; set (STOP SELECT since all 3 STOP FFs are HI) test 9: 1 comment: ; comment: ; test DEVICE DECODER comment: ; comment: ; turn on LOAD BUFFER (normally IOP4) test 10: 1 comment: ; comment: ; set up to load ENABLE/55h (alternating ones) comment: ; test 11: 101010101 comment: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO comment: ; (ENABLE) will go HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) will go LO test 12: 111111 0 1 0 comment: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 13: 0 comment: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI comment: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) test 14: 000000 1 1 comment: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO test 15: 0 0 test 16: 1 1 comment: ; test all DEVICE ADDRESS combinations test 17: 000000 1 test 18: 000001 1 test 19: 000010 1 test 20: 000011 1 test 21: 000100 1 test 22: 000101 1 test 23: 000110 1 test 24: 000111 1 test 25: 001000 1 test 26: 001001 1 test 27: 001010 1 test 28: 001011 1 test 29: 001100 1 test 30: 001101 1 test 31: 001110 1 test 32: 001111 1 test 33: 010000 1 test 34: 010001 1 test 35: 010010 1 test 36: 010011 1 test 37: 010100 1 test 38: 010101 1 test 39: 010110 1 test 40: 010111 1 test 41: 011000 1 test 42: 011001 1 test 43: 011010 1 test 44: 011011 1 test 45: 011100 1 test 46: 011101 1 test 47: 011110 1 test 48: 011111 1 test 49: 100000 1 test 50: 100001 1 test 51: 100010 1 test 52: 100011 1 test 53: 100100 1 test 54: 100101 1 test 55: 100110 1 test 56: 100111 1 test 57: 101000 1 test 58: 101001 1 test 59: 101010 1 test 60: 101011 1 test 61: 101100 1 test 62: 101101 1 test 63: 101110 1 test 64: 101111 1 test 65: 110000 1 test 66: 110001 1 test 67: 110010 1 test 68: 110011 1 test 69: 110100 1 test 70: 110101 1 test 71: 110110 1 test 72: 110111 1 test 73: 111000 1 test 74: 111001 1 test 75: 111010 1 test 76: 111011 1 test 77: 111100 1 test 78: 111101 1 test 79: 111110 1 test 80: 111111 0 comment: ; remove LOAD BUFFER (normally IOP4) test 81: 01 comment: ; remove DEVICE ADDRESS test 82: 000000 comment: ; comment: ; comment: ; send the 0x55 character comment: ; comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 83: 1 10 test 84: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 85: 1 000 test 86: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 87: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 88: 0 comment: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 89: 1 test 90: 0 test 91: 1 test 92: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 93: 1 0 0 test 94: 0 test 95: 1 test 96: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) shifts test 97: 1 1 1 test 98: 0 test 99: 1 test 100: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE test 101: 1 0 0 test 102: 0 test 103: 1 test 104: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 105: 1 0 1 test 106: 0 test 107: 1 test 108: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 109: 1 0 test 110: 0 test 111: 1 test 112: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 113: 1 1 test 114: 0 test 115: 1 test 116: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 117: 1 0 test 118: 0 test 119: 1 test 120: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 121: 1 0 01 test 122: 0 comment: ; STOP FFs bits start counting... test 123: 1 1 test 124: 0 test 125: 1 1 test 126: 0 test 127: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 128: 1 test 129: 0 test 130: 1 test 131: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 132: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 133: 10 test 134: 01 comment: ; turn off DEVICE ADDRESS bits test 135: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 136: 1 test 137: 0 comment: ; turn on DEVICE ADDRESS bits test 138: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 139: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 140: 111 test 141: 0 comment: ; turn off I/O SKP. STROBE test 142: 0 comment: ; turn off DEVICE ADDRESS bits test 143: 000000 test 144: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xAA comment: ; comment: ; comment: ; set up to load ENABLE/0xAA (alternating ones) test 145: 110101010 comment: ; turn on DEVICE ADDRESS bits test 146: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 147: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 148: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 149: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 150: 01 comment: ; remove DEVICE ADDRESS test 151: 000000 comment: ; comment: ; shift out the 0xAA character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 152: 1 10 test 153: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 154: 1 000 test 155: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 156: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 157: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 158: 1 test 159: 0 test 160: 1 test 161: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 162: 1 1 1 test 163: 0 test 164: 1 test 165: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 166: 1 1 0 test 167: 0 test 168: 1 test 169: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 170: 1 0 1 test 171: 0 test 172: 1 test 173: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 174: 1 0 0 test 175: 0 test 176: 1 test 177: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 178: 1 1 test 179: 0 test 180: 1 test 181: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 182: 1 0 test 183: 0 test 184: 1 test 185: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 186: 1 1 test 187: 0 test 188: 1 test 189: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 190: 1 0 01 test 191: 0 comment: ; STOP FFs bits start counting... test 192: 1 1 test 193: 0 test 194: 1 1 test 195: 0 test 196: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 197: 1 test 198: 0 test 199: 1 test 200: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 201: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 202: 10 test 203: 01 comment: ; turn off DEVICE ADDRESS bits test 204: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 205: 1 test 206: 0 comment: ; turn on DEVICE ADDRESS bits test 207: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 208: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 209: 111 test 210: 0 comment: ; turn off I/O SKP. STROBE test 211: 0 comment: ; turn off DEVICE ADDRESS bits test 212: 000000 test 213: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0x00 comment: ; comment: ; comment: ; set up to load ENABLE/0x00 (all zeroes) test 214: 100000000 comment: ; turn on DEVICE ADDRESS bits test 215: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes LO comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 216: 10 01 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 217: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 218: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 219: 01 comment: ; remove DEVICE ADDRESS test 220: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 221: 1 10 test 222: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 223: 1 000 test 224: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 225: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 226: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 227: 1 test 228: 0 test 229: 1 test 230: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 231: 1 0 0 test 232: 0 test 233: 1 test 234: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 235: 1 1 0 test 236: 0 test 237: 1 test 238: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 239: 1 0 0 test 240: 0 test 241: 1 test 242: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 243: 1 0 0 test 244: 0 test 245: 1 test 246: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 247: 1 0 test 248: 0 test 249: 1 test 250: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 251: 1 0 test 252: 0 test 253: 1 test 254: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 255: 1 0 test 256: 0 test 257: 1 test 258: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 259: 1 0 01 test 260: 0 comment: ; STOP FFs bits start counting... test 261: 1 1 test 262: 0 test 263: 1 1 test 264: 0 test 265: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 266: 1 test 267: 0 test 268: 1 test 269: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 270: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 271: 10 test 272: 01 comment: ; turn off DEVICE ADDRESS bits test 273: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 274: 1 test 275: 0 comment: ; turn on DEVICE ADDRESS bits test 276: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 277: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 278: 111 test 279: 0 comment: ; turn off I/O SKP. STROBE test 280: 0 comment: ; turn off DEVICE ADDRESS bits test 281: 000000 test 282: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xFF comment: ; comment: ; comment: ; set up to load ENABLE/0xFF (all ones) test 283: 111111111 comment: ; turn on DEVICE ADDRESS bits test 284: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 285: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 286: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 287: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 288: 01 comment: ; remove DEVICE ADDRESS test 289: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 290: 1 10 test 291: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 292: 1 000 test 293: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 294: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 295: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 296: 1 test 297: 0 test 298: 1 test 299: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 300: 1 1 1 test 301: 0 test 302: 1 test 303: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 304: 1 1 1 test 305: 0 test 306: 1 test 307: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 308: 1 0 1 test 309: 0 test 310: 1 test 311: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 312: 1 1 test 313: 0 test 314: 1 test 315: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 316: 1 1 test 317: 0 test 318: 1 test 319: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 320: 1 1 test 321: 0 test 322: 1 test 323: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 324: 1 1 test 325: 0 test 326: 1 test 327: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 328: 1 0 01 test 329: 0 comment: ; STOP FFs bits start counting... test 330: 1 1 test 331: 0 test 332: 1 1 test 333: 0 test 334: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 335: 1 test 336: 0 test 337: 1 test 338: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 339: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 340: 10 test 341: 01 comment: ; turn off DEVICE ADDRESS bits test 342: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 343: 11 test 344: 01 comment: ; turn on DEVICE ADDRESS bits test 345: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 346: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 347: 111 test 348: 0 comment: ; turn off I/O SKP. STROBE test 349: 0 comment: ; turn off DEVICE ADDRESS bits test 350: 000000 test 351: 11000000001011001111110001110101010101X1 comment: ; comment: ; test ECHO input (need to scope AV2 20MA OUTPUT) comment: ; comment: ; set ECHO-N lo, 20MA OUTPUT goes LO test 352: X0 test 353: X1 end: END summary column 1: offset 3, mask 0x4000 column 2: offset 2, mask 0x0080 column 3: offset 2, mask 0x0040 column 4: offset 3, mask 0x0040 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 1, mask 0x1000 column 12: offset 3, mask 0x0001 column 13: offset 3, mask 0x0002 column 14: offset 3, mask 0x0004 column 15: offset 2, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0400 column 18: offset 4, mask 0x0001 column 19: offset 3, mask 0x0080 column 20: offset 3, mask 0x0200 column 21: offset 3, mask 0x0400 column 22: offset 3, mask 0x0020 column 23: offset 0, mask 0x0100 column 24: offset 1, mask 0x0001 column 25: offset 1, mask 0x8000 column 26: offset 1, mask 0x4000 column 27: offset 0, mask 0x0200 column 28: offset 1, mask 0x0008 column 29: offset 1, mask 0x0010 column 30: offset 1, mask 0x0020 column 31: offset 1, mask 0x0002 column 32: offset 1, mask 0x0004 column 33: offset 2, mask 0x0001 column 34: offset 1, mask 0x0040 column 35: offset 1, mask 0x0080 column 36: offset 2, mask 0x8000 column 37: offset 0, mask 0x1000 column 38: offset 0, mask 0x0010 column 39: offset 2, mask 0x0002 column 40: offset 0, mask 0x4000 direction bits (1=input) 0xB1F0 0x6901 0x7F1A 0xFF9E 0xF0FE pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4210 0x5408 0x00C0 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 2: 0x4210 0x5408 0x0080 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 3: 0x4210 0x5408 0x0080 0x40C6 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 4: 0x4210 0x5408 0x0080 0x4086 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 5: 0x4210 0x5408 0x0080 0x42C6 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 6: 0x4210 0x5408 0x0080 0x4286 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 7: 0x4210 0x5408 0x0080 0x46C6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 8: 0x4210 0x5408 0x0080 0x4686 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 9: 0x4210 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 10: 0x4210 0x5608 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 11: 0x4210 0x566C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 12: 0x4E1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 13: 0x4C1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 14: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 15: 0x4010 0x826D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 16: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 17: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 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0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 246: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 247: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 248: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 249: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 250: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 251: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 252: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 253: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 254: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 255: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 256: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 257: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 258: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 259: 0x4210 0x5408 0x0080 0x4062 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 260: 0x4210 0x5408 0x0080 0x4022 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 261: 0x4210 0x5408 0x0080 0x40E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 262: 0x4210 0x5408 0x0080 0x40A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 263: 0x4210 0x5408 0x0080 0x42E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 264: 0x4210 0x5408 0x0080 0x42A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 265: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 266: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 267: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 268: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 269: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 270: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 271: 0x4E1F 0x5408 0x0080 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 272: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 273: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 274: 0x4210 0x5408 0x0080 0x46A3 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 275: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 276: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 277: 0x4E1F 0x5408 0x0080 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 278: 0x4E1F 0x5408 0x00A0 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 279: 0x4E1F 0x5408 0x0080 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 280: 0x4E1F 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 281: 0x4210 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 282: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 283: 0x4210 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 284: 0x4E1F 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 285: 0x4F1F 0x12FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 286: 0x4F1F 0x92FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 287: 0x4D1F 0x92FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 288: 0x4D1F 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 289: 0x4110 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 290: 0x5100 0x94FF 0x8081 0x46E6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 291: 0x5100 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 292: 0x5100 0x94FF 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 293: 0x5100 0x94FF 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 294: 0x5110 0xD4FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 295: 0x5110 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 296: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 297: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 298: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 299: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 300: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 301: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 302: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 303: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 304: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 305: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 306: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 307: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 308: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 309: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 310: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 311: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 312: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 313: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 314: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 315: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 316: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 317: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 318: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 319: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 320: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 321: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 322: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 323: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 324: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 325: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 326: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 327: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 328: 0x4210 0x54FE 0x8081 0x4062 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 329: 0x4210 0x54FE 0x8081 0x4022 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 330: 0x4210 0x54FE 0x8081 0x40E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 331: 0x4210 0x54FE 0x8081 0x40A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 332: 0x4210 0x54FE 0x8081 0x42E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 333: 0x4210 0x54FE 0x8081 0x42A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 334: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 335: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 336: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 337: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 338: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 339: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 340: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 341: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 342: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 343: 0x4210 0x54FE 0x8081 0x46A3 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 344: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 345: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 346: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 347: 0x4E1F 0x54FE 0x80A1 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 348: 0x4E1F 0x54FE 0x8081 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 349: 0x4E1F 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 350: 0x4210 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 351: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 352: 0x0210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 353: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I OIIIOIO I IIGI P GOIIIIOIIIIIIIIO O OO G P GIIIIOO IIOI UUT inputs: 28 UUT outputs: 12 pins used: 40 not used: 26 353 'test steps' 643 lines M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER ICs are VERTICAL on PCB REV D. Rev D adds AB1 ECHO input. does not test AV2 20MA OUTPUT, use scope and pulldown or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) PINS Main menu Thu Jun 29 14:36:06 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 14:36:08 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 0, total passes 28 Main menu Thu Jun 29 14:36:16 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 14:38:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 1110000000101100111000000111000000000111 step 2 1100000000101100111000000111000000000111 step 3 1101000000101100111100000111000000000111 step 4 1100000000101100111100000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 11 1100000000101101111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 0 1 0 step 12 1100111111101101011111010011000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 13 1100111111101101011111010001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 1 1 step 14 1100000000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 0 step 15 1100000000001101011111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 16 1100000000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 17 1100000000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 18 1100000001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 19 1100000010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 20 1100000011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 21 1100000100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 22 1100000101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 23 1100000110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 24 1100000111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 25 1100001000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 26 1100001001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 27 1100001010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 28 1100001011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 29 1100001100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 30 1100001101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 31 1100001110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 32 1100001111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10000 step 33 1100010000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 34 1100010001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 35 1100010010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 36 1100010011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 37 1100010100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 38 1100010101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 39 1100010110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 40 1100010111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 41 1100011000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 42 1100011001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 43 1100011010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 44 1100011011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 45 1100011100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 46 1100011101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 47 1100011110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 48 1100011111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100000 step 49 1100100000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 50 1100100001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 51 1100100010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 52 1100100011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 53 1100100100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 54 1100100101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 55 1100100110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 56 1100100111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 57 1100101000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 58 1100101001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 59 1100101010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 60 1100101011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 61 1100101100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 62 1100101101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 63 1100101110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 64 1100101111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10000 step 65 1100110000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 66 1100110001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 67 1100110010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 68 1100110011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 69 1100110100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 70 1100110101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 71 1100110110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 72 1100110111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 73 1100111000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 74 1100111001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 75 1100111010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 76 1100111011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 77 1100111100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 78 1100111101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 79 1100111110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 80 1100111111101101011111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 81 1100111111101100111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 82 1100000000101100111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 step 83 1101000000101100111111011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 84 1100000000101100111111011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 000 step 85 1101000000101100110001011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 86 1100000000101100110001011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 93 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 94 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 95 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 96 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 101 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 102 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 103 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 104 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 105 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 106 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 107 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 108 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 109 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 110 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 111 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 112 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 113 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 114 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 115 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 116 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 117 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 118 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 119 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 120 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 01 step 121 1101000000101000110001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 122 1100000000101000110001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 123 1101000000101000111001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 124 1100000000101000111001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 125 1101000000101000111101000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 126 1100000000101000111101000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 127 1101000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 128 1101000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 129 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 130 1101000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 131 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 132 1100111111101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 133 1100111111110000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 134 1100111111101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 135 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 136 1100000000111000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 137 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 138 1100111111101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 139 1100111111110000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111 step 140 1100111111111110111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 141 1100111111111100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 142 1100111111101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 143 1100000000101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 144 1100000000101100111111000111000001010111 fail ^ ^ step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 156 1101000000101100110001101101101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 157 1101000000101100110001100101101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 158 1101000000101100110001100111101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 159 1100000000101100110001100111101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 160 1101000000101100110001100111101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 161 1100000000101100110001100111101010101011 fail ^ step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 174 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 175 1100000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 176 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 177 1100000000101100110001000111101010101111 fail ^ step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 182 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 183 1100000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 184 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 185 1100000000101100110001000111101010101111 fail ^ step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 0 0101 step 213 1100000000101100111111000111000001010111 fail ^ ^ step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 225 1101000000101100110001101101000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 226 1101000000101100110001100101000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 227 1101000000101100110001100111000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 228 1100000000101100110001100111000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 229 1101000000101100110001100111000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 230 1100000000101100110001100111000000001011 fail ^ step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 243 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 244 1100000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 245 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 246 1100000000101100110001000111000000001111 fail ^ step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 251 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 252 1100000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 253 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 254 1100000000101100110001000111000000001111 fail ^ step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 282 1100000000101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 1 1 step 283 1100000000101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 284 1100111111101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 11 0 step 285 1100111111101101011111110011101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 286 1100111111101101011111111011101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 287 1100111111101101011111111001101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 288 1100111111101100111111111001101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 289 1100000000101100111111111001101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 step 290 1101000000101100111111111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 291 1100000000101100111111111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 000 step 292 1101000000101100110001111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 293 1100000000101100110001111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 300 1101000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 301 1100000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 302 1101000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 303 1100000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 308 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 309 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 310 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 311 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 312 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 313 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 314 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 315 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 316 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 317 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 318 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 319 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 320 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 321 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 322 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 323 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 324 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 325 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 326 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 327 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 0 step 328 1101000000101000110001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 329 1100000000101000110001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 330 1101000000101000111001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 331 1100000000101000111001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 332 1101000000101000111101000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 333 1100000000101000111101000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 334 1101000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 335 1101000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 336 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 337 1101000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 338 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 339 1100111111101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 340 1100111111110000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 341 1100111111101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 342 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 343 1100000000111000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 344 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 345 1100111111101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 346 1100111111110000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111 step 347 1100111111111110111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 348 1100111111111100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 349 1100111111101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 350 1100000000101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 0 0 0 step 351 1100000000101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 352 1100000000101100111111000111000001010110 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 353 1100000000101100111111000111000001010111 fail ^ ^ test 1: *** FAIL *************************** 235 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O I I O all fails O I I O was hi 11111111111111111111111111111 1 11111111 rising ^^^^^^^^^^^^^^ ^^^^^^^^^ ^ ^ ^^^^^^ ^ falling vvvvvvvvvvvvvvv vvv vvvvv v v vvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails O I I O was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvv vvvvv v v vvvvvv v rising ^^^^^^^^^^^^^^ ^^^^^^^^^ ^ ^ ^^^^^^ ^ was hi 11111111111111111111111111111 1 11111111 total fails 1, total passes 0 Main menu Thu Jun 29 15:10:11 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 15:10:14 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 11 1100000000101101111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 0 1 0 step 12 1100111111101101011111010011000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 13 1100111111101101011111010001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 1 1 step 14 1100000000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 0 step 15 1100000000001101011111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 16 1100000000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 17 1100000000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 18 1100000001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 19 1100000010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 20 1100000011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 21 1100000100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 22 1100000101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 23 1100000110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 24 1100000111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 25 1100001000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 26 1100001001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 27 1100001010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 28 1100001011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 29 1100001100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 30 1100001101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 31 1100001110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 32 1100001111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10000 step 33 1100010000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 34 1100010001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 35 1100010010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 36 1100010011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 37 1100010100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 38 1100010101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 39 1100010110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 40 1100010111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 41 1100011000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 42 1100011001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 43 1100011010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 44 1100011011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 45 1100011100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 46 1100011101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 47 1100011110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 48 1100011111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100000 step 49 1100100000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 50 1100100001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 51 1100100010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 52 1100100011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 53 1100100100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 54 1100100101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 55 1100100110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 56 1100100111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 57 1100101000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 58 1100101001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 59 1100101010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 60 1100101011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 61 1100101100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 62 1100101101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 63 1100101110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 64 1100101111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10000 step 65 1100110000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 66 1100110001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 67 1100110010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 68 1100110011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 69 1100110100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 70 1100110101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 71 1100110110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 72 1100110111101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1000 step 73 1100111000101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 74 1100111001101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 75 1100111010101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 76 1100111011101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 100 step 77 1100111100101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 78 1100111101101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 79 1100111110101101111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 80 1100111111101101011111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 81 1100111111101100111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 82 1100000000101100111111011001000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 step 83 1101000000101100111111011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 84 1100000000101100111111011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 000 step 85 1101000000101100110001011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 86 1100000000101100110001011001000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 93 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 94 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 95 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 96 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111000001011011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 101 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 102 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 103 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 104 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 105 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 106 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 107 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 108 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 109 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 110 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 111 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 112 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 113 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 114 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 115 1101000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 116 1100000000101100110001000111000001011111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 117 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 118 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 119 1101000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 120 1100000000101100110001000111000001011011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 01 step 121 1101000000101000110001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 122 1100000000101000110001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 123 1101000000101000111001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 124 1100000000101000111001000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 125 1101000000101000111101000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 126 1100000000101000111101000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 127 1101000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 128 1101000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 129 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 130 1101000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 131 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 132 1100111111101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 133 1100111111110000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 134 1100111111101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 135 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 136 1100000000111000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 137 1100000000101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 138 1100111111101000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 139 1100111111110000111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111 step 140 1100111111111110111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 141 1100111111111100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 142 1100111111101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 143 1100000000101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 144 1100000000101100111111000111000001010111 fail ^ ^ step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 156 1101000000101100110001101101101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 157 1101000000101100110001100101101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 158 1101000000101100110001100111101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 159 1100000000101100110001100111101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 160 1101000000101100110001100111101010101011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 161 1100000000101100110001100111101010101011 fail ^ step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 174 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 175 1100000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 176 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 177 1100000000101100110001000111101010101111 fail ^ step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 182 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 183 1100000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 184 1101000000101100110001000111101010101111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 185 1100000000101100110001000111101010101111 fail ^ step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 0 0101 step 213 1100000000101100111111000111000001010111 fail ^ ^ step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 225 1101000000101100110001101101000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 226 1101000000101100110001100101000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 227 1101000000101100110001100111000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 228 1100000000101100110001100111000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 229 1101000000101100110001100111000000001011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 230 1100000000101100110001100111000000001011 fail ^ step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 243 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 244 1100000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 245 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 246 1100000000101100110001000111000000001111 fail ^ step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 251 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 252 1100000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 253 1101000000101100110001000111000000001111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 254 1100000000101100110001000111000000001111 fail ^ step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 282 1100000000101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 1 1 step 283 1100000000101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 284 1100111111101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 11 0 step 285 1100111111101101011111110011101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 286 1100111111101101011111111011101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 287 1100111111101101011111111001101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 288 1100111111101100111111111001101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 289 1100000000101100111111111001101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 step 290 1101000000101100111111111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 291 1100000000101100111111111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 000 step 292 1101000000101100110001111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 293 1100000000101100110001111001101011111011 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 300 1101000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 301 1100000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 302 1101000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 303 1100000000101100110001100111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111101011111011 fail ^ ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 308 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 309 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 310 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 311 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 312 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 313 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 314 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 315 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 316 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 317 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 318 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 319 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 320 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 321 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 322 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 323 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 324 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 325 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 326 1101000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 327 1100000000101100110001000111101011111111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 0 step 328 1101000000101000110001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 329 1100000000101000110001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 330 1101000000101000111001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 331 1100000000101000111001000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 332 1101000000101000111101000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 333 1100000000101000111101000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 334 1101000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: step 335 1101000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 336 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 337 1101000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 338 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 339 1100111111101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 340 1100111111110000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 01 step 341 1100111111101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 342 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 343 1100000000111000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 344 1100000000101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111111 step 345 1100111111101000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 10 step 346 1100111111110000111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 111 step 347 1100111111111110111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 348 1100111111111100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 349 1100111111101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 000000 step 350 1100000000101100111111000111101011110111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 0 0 0 step 351 1100000000101100111111000111000001010111 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 352 1100000000101100111111000111000001010110 fail ^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 353 1100000000101100111111000111000001010111 fail ^ ^ test 1: *** FAIL *************************** 235 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O I I O all fails O I I O was hi 11111111111111111111111111111 1 11111111 rising ^^^^^^^^^^^^^^ ^^^^^^^^^ ^ ^ ^^^^^^ ^ falling vvvvvvvvvvvvvvv vvv vvvvv v v vvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails O I I O was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvv vvvvv v v vvvvvv v rising ^^^^^^^^^^^^^^ ^^^^^^^^^ ^ ^ ^^^^^^ ^ was hi 11111111111111111111111111111 1 11111111 total fails 1, total passes 0 Main menu Thu Jun 29 15:10:31 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 15:25:45 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 8: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 8, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 9: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 9, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 10: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 10, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 11: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 11, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high 1 O BJ1 +3V 2 I BF2 CLEAR FLAG 2-N (NORMALLY 3V) 18 I BS2 WAIT-N (PROLONGS STOP BITS) (NORMALLY 3V) 28 I AN2 ENABLE (NORMALLY 3V) 39 O AV2 20MA OUTPUT (PNP TO +) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 12: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 12, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 13: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 13, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 14: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 14, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 38 O AD2 LINE SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI fails LO: 11 1 1 11 11 11 1111111111111 11 fails LO: 00000000 0 00 000 00 0 0 0 0 0 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 15: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 15, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 40 I AB1 ECHO (ORS WITH LINE -> 20MA OUTPUT) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 16: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 16, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 4 I BP2 2 X BAUD CLOCK INPUT 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) 38 O AD2 LINE space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails O was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 16, total passes 0 Main menu Thu Jun 29 15:31:09 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 15:31:11 2017 output is: 37 O AD1 ACTIVE space toggle output N next output Q quit step 1 1110000000101100110000000111000000000111 step 2 1100000000101100110000000111000000000111 step 3 1101000000101100111000000111000000000111 step 4 1100000000101100111000000111000000000111 step 5 1101000000101100111100000111000000000111 step 6 1100000000101100111100000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 output: 1 output is: 37 O AD1 ACTIVE space toggle output N next output Q quit step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 step 87 1101000000101100110001101101010101011011 step 88 1101000000101100110001100101010101011011 step 89 1101000000101100110001100111010101011011 step 90 1100000000101100110001100111010101011011 step 91 1101000000101100110001100111010101011011 step 92 1100000000101100110001100111010101011011 step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 step 97 1101000000101100110001100111010101011011 step 98 1100000000101100110001100111010101011011 step 99 1101000000101100110001100111010101011011 step 100 1100000000101100110001100111010101011011 step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 output: 0 output is: 37 O AD1 ACTIVE space toggle output N next output Q quit step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 output: 1 output is: 37 O AD1 ACTIVE space toggle output N next output Q quit output is: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) space toggle output N next output Q quit output is: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) space toggle output N next output Q quit output is: 38 O AD2 LINE space toggle output N next output Q quit output is: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) space toggle output N next output Q quit output is: 39 O AV2 20MA OUTPUT (PNP TO +) space toggle output N next output Q quit output is: 1 O BJ1 +3V space toggle output N next output Q quit output is: 21 O BN1 STOP 2-N space toggle output N next output Q quit output is: 20 O BP1 STOP 1.5-N space toggle output N next output Q quit output is: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) space toggle output N next output Q quit output is: 14 O BK2 P.I.REQ-N (FLAG-N) space toggle output N next output Q quit output is: 19 O BR2 STOP 1-N space toggle output N next output Q quit output is: 37 O AD1 ACTIVE space toggle output N next output Q quit output is: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) space toggle output N next output Q quit output is: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) space toggle output N next output Q quit output is: 38 O AD2 LINE space toggle output N next output Q quit output is: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) space toggle output N next output Q quit output is: 39 O AV2 20MA OUTPUT (PNP TO +) space toggle output N next output Q quit output is: 1 O BJ1 +3V space toggle output N next output Q quit output is: 21 O BN1 STOP 2-N space toggle output N next output Q quit output is: 20 O BP1 STOP 1.5-N space toggle output N next output Q quit output is: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) space toggle output N next output Q quit output is: 14 O BK2 P.I.REQ-N (FLAG-N) space toggle output N next output Q quit output is: 19 O BR2 STOP 1-N space toggle output N next output Q quit output is: 37 O AD1 ACTIVE space toggle output N next output Q quit output is: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) space toggle output N next output Q quit output is: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) space toggle output N next output Q quit output is: 38 O AD2 LINE space toggle output N next output Q quit output is: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) space toggle output N next output Q quit output is: 39 O AV2 20MA OUTPUT (PNP TO +) space toggle output N next output Q quit output is: 1 O BJ1 +3V space toggle output N next output Q quit output is: 21 O BN1 STOP 2-N space toggle output N next output Q quit output is: 20 O BP1 STOP 1.5-N space toggle output N next output Q quit output is: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) space toggle output N next output Q quit output is: 14 O BK2 P.I.REQ-N (FLAG-N) space toggle output N next output Q quit output is: 19 O BR2 STOP 1-N space toggle output N next output Q quit output is: 37 O AD1 ACTIVE space toggle output N next output Q quit output is: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) space toggle output N next output Q quit output is: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) space toggle output N next output Q quit output is: 38 O AD2 LINE space toggle output N next output Q quit output is: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) space toggle output N next output Q quit output is: 39 O AV2 20MA OUTPUT (PNP TO +) space toggle output N next output Q quit output is: 1 O BJ1 +3V space toggle output N next output Q quit output is: 21 O BN1 STOP 2-N space toggle output N next output Q quit output is: 20 O BP1 STOP 1.5-N space toggle output N next output Q quit output is: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) space toggle output N next output Q quit output is: 14 O BK2 P.I.REQ-N (FLAG-N) space toggle output N next output Q quit output is: 19 O BR2 STOP 1-N space toggle output N next output Q quit output is: 37 O AD1 ACTIVE space toggle output N next output Q quit output is: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) space toggle output N next output Q quit output is: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) space toggle output N next output Q quit output is: 38 O AD2 LINE space toggle output N next output Q quit step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 step 294 1101000000101100110001101101111111111011 step 295 1101000000101100110001100101111111111011 step 296 1101000000101100110001100111111111111011 step 297 1100000000101100110001100111111111111011 step 298 1101000000101100110001100111111111111011 step 299 1100000000101100110001100111111111111011 step 300 1101000000101100110001100111111111111111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 step 304 1101000000101100110001100111111111111011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 305 1100000000101100110001100111111111111011 step 306 1101000000101100110001100111111111111011 step 307 1100000000101100110001100111111111111011 step 308 1101000000101100110001000111111111111111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 step 87 1101000000101100110001101101010101011011 step 88 1101000000101100110001100101010101011011 step 89 1101000000101100110001100111010101011011 step 90 1100000000101100110001100111010101011011 step 91 1101000000101100110001100111010101011011 step 92 1100000000101100110001100111010101011011 step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 step 97 1101000000101100110001100111010101011011 step 98 1100000000101100110001100111010101011011 step 99 1101000000101100110001100111010101011011 step 100 1100000000101100110001100111010101011011 step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 output: 1 output is: 38 O AD2 LINE space toggle output N next output Q quit step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 output: 0 output is: 38 O AD2 LINE space toggle output N next output Q quit Main menu Thu Jun 29 15:32:17 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 15:32:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 8: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 8, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 9: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 9, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 10: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 10, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails O was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 10, total passes 0 Main menu Thu Jun 29 15:32:29 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 15:32:31 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Thu Jun 29 15:32:36 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m707d.tst reading test file: tests\m707d.tst comment: M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER comment: comment: ICs are VERTICAL on PCB REV D. comment: comment: Rev D adds AB1 ECHO input. comment: comment: does not test AV2 20MA OUTPUT, use scope and pulldown comment: comment: or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) comment: pins: PINS pins: 1 O BJ1 +3V pins: 2 I BF2 CLEAR FLAG 2-N (NORMALLY 3V) pins: 3 I BE2 I/O CLEAR (NORMALLY INITIALIZE) pins: 4 I BP2 2 X BAUD CLOCK INPUT pins: 5 I AE1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB04-N) pins: 6 I AE2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB03-N) pins: 7 I AF1 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB06) pins: 8 I AF2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB05-N) pins: 9 I AH2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB08-N) pins: 10 I AJ2 (DEVICE SELECTOR BMB IN) (NAND)->(DEVICE SELECT-N) (NORMALLY MB07-N) pins: 11 I AN1 (FORCE SELECT-N) (NORMALLY HI) NAND(DEVICE SELECT-N)=(SELECTED) pins: 12 I BH2 I/O SKP. STROBE (NORMALLY IOT 1) pins: 13 O BJ2 I/O SKP.-N (NAND OF I/O SKP. STROBE, FLAG, DEV DECODE) pins: 14 O BK2 P.I.REQ-N (FLAG-N) pins: 15 I BD2 CLEAR FLAG 1 (NORMALLY IOT 2) pins: 16 I AS1 LOAD BUFFER (NORMALLY IOT 4) pins: 17 I AR1 LOAD BUFFER STROBE-N (NAND SELECTED, LOAD BUFFER) pins: 18 I BS2 WAIT-N (PROLONGS STOP BITS) (NORMALLY 3V) pins: 19 O BR2 STOP 1-N pins: 20 O BP1 STOP 1.5-N pins: 21 O BN1 STOP 2-N pins: 22 I BN2 (STOP SELECT) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 23 O AJ1 (BIT 6) (CONNECTS TO AK1 FOR 5 BIT OUTPUT) pins: 24 O AK2 (ENABLE) (CONNECTS TO AK1 FOR 8 BIT OUTPUT) pins: 25 I AK1 (CHARACTER LOADED) (MUST BE HI TO SET ACTIVE I.E. TX NEXT CHARACTER) pins: 26 O AL1 (ENABLE-N) (NORMALLY CONNECTS TO DECODE INPUT 8) pins: 27 I AH1 (DECODE INPUT 8) (NORMALLY CONNECTS TO (ENABLE-N) pins: 28 I AN2 ENABLE (NORMALLY 3V) pins: 29 I AP2 BIT 8 (NORMALLY AC4) pins: 30 I AR2 BIT 7 (NORMALLY AC5) pins: 31 I AL2 BIT 6 (NORMALLY AC6) pins: 32 I AM2 BIT 5 (NORMALLY AC7) pins: 33 I AU2 BIT 4 (NORMALLY AC8) pins: 34 I AS2 BIT 3 (NORMALLY AC9) pins: 35 I AT2 BIT 2 (NORMALLY AC10) pins: 36 I AU1 BIT 1 (NORMALLY AC11) pins: 37 O AD1 ACTIVE pins: 38 O AD2 LINE pins: 39 O AV2 20MA OUTPUT (PNP TO +) pins: 40 I AB1 ECHO (ORS WITH LINE -> 20MA OUTPUT) pins: direction: OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI comment: ; set CLEAR FLAG 2-N, I/O CLEAR comment: ; note: STOP FF outputs are unknown. comment: ; note: 20MA output can not test (open emitter) test 1: 111000000010110011XXX00001110000000001X1 comment: ; remove I/O CLEAR test 2: 0 comment: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs test 3: 1 1 test 4: 0 test 5: 1 1 test 6: 0 test 7: 1 1 test 8: 0 comment: ; set (STOP SELECT since all 3 STOP FFs are HI) test 9: 1 comment: ; comment: ; test DEVICE DECODER comment: ; comment: ; turn on LOAD BUFFER (normally IOP4) test 10: 1 comment: ; comment: ; set up to load ENABLE/55h (alternating ones) comment: ; test 11: 101010101 comment: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO comment: ; (ENABLE) will go HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) will go LO test 12: 111111 0 1 0 comment: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 13: 0 comment: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI comment: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) test 14: 000000 1 1 comment: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO test 15: 0 0 test 16: 1 1 comment: ; test all DEVICE ADDRESS combinations test 17: 000000 1 test 18: 000001 1 test 19: 000010 1 test 20: 000011 1 test 21: 000100 1 test 22: 000101 1 test 23: 000110 1 test 24: 000111 1 test 25: 001000 1 test 26: 001001 1 test 27: 001010 1 test 28: 001011 1 test 29: 001100 1 test 30: 001101 1 test 31: 001110 1 test 32: 001111 1 test 33: 010000 1 test 34: 010001 1 test 35: 010010 1 test 36: 010011 1 test 37: 010100 1 test 38: 010101 1 test 39: 010110 1 test 40: 010111 1 test 41: 011000 1 test 42: 011001 1 test 43: 011010 1 test 44: 011011 1 test 45: 011100 1 test 46: 011101 1 test 47: 011110 1 test 48: 011111 1 test 49: 100000 1 test 50: 100001 1 test 51: 100010 1 test 52: 100011 1 test 53: 100100 1 test 54: 100101 1 test 55: 100110 1 test 56: 100111 1 test 57: 101000 1 test 58: 101001 1 test 59: 101010 1 test 60: 101011 1 test 61: 101100 1 test 62: 101101 1 test 63: 101110 1 test 64: 101111 1 test 65: 110000 1 test 66: 110001 1 test 67: 110010 1 test 68: 110011 1 test 69: 110100 1 test 70: 110101 1 test 71: 110110 1 test 72: 110111 1 test 73: 111000 1 test 74: 111001 1 test 75: 111010 1 test 76: 111011 1 test 77: 111100 1 test 78: 111101 1 test 79: 111110 1 test 80: 111111 0 comment: ; remove LOAD BUFFER (normally IOP4) test 81: 01 comment: ; remove DEVICE ADDRESS test 82: 000000 comment: ; comment: ; comment: ; send the 0x55 character comment: ; comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 83: 1 10 test 84: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 85: 1 000 test 86: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 87: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 88: 0 comment: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 89: 1 test 90: 0 test 91: 1 test 92: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 93: 1 0 0 test 94: 0 test 95: 1 test 96: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) shifts test 97: 1 1 1 test 98: 0 test 99: 1 test 100: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE test 101: 1 0 0 test 102: 0 test 103: 1 test 104: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 105: 1 0 1 test 106: 0 test 107: 1 test 108: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 109: 1 0 test 110: 0 test 111: 1 test 112: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 113: 1 1 test 114: 0 test 115: 1 test 116: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 117: 1 0 test 118: 0 test 119: 1 test 120: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 121: 1 0 01 test 122: 0 comment: ; STOP FFs bits start counting... test 123: 1 1 test 124: 0 test 125: 1 1 test 126: 0 test 127: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 128: 1 test 129: 0 test 130: 1 test 131: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 132: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 133: 10 test 134: 01 comment: ; turn off DEVICE ADDRESS bits test 135: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 136: 1 test 137: 0 comment: ; turn on DEVICE ADDRESS bits test 138: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 139: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 140: 111 test 141: 0 comment: ; turn off I/O SKP. STROBE test 142: 0 comment: ; turn off DEVICE ADDRESS bits test 143: 000000 test 144: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xAA comment: ; comment: ; comment: ; set up to load ENABLE/0xAA (alternating ones) test 145: 110101010 comment: ; turn on DEVICE ADDRESS bits test 146: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 147: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 148: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 149: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 150: 01 comment: ; remove DEVICE ADDRESS test 151: 000000 comment: ; comment: ; shift out the 0xAA character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 152: 1 10 test 153: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 154: 1 000 test 155: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 156: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 157: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 158: 1 test 159: 0 test 160: 1 test 161: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 162: 1 1 1 test 163: 0 test 164: 1 test 165: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 166: 1 1 0 test 167: 0 test 168: 1 test 169: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 170: 1 0 1 test 171: 0 test 172: 1 test 173: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 174: 1 0 0 test 175: 0 test 176: 1 test 177: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 178: 1 1 test 179: 0 test 180: 1 test 181: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 182: 1 0 test 183: 0 test 184: 1 test 185: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 186: 1 1 test 187: 0 test 188: 1 test 189: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 190: 1 0 01 test 191: 0 comment: ; STOP FFs bits start counting... test 192: 1 1 test 193: 0 test 194: 1 1 test 195: 0 test 196: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 197: 1 test 198: 0 test 199: 1 test 200: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 201: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 202: 10 test 203: 01 comment: ; turn off DEVICE ADDRESS bits test 204: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 205: 1 test 206: 0 comment: ; turn on DEVICE ADDRESS bits test 207: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 208: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 209: 111 test 210: 0 comment: ; turn off I/O SKP. STROBE test 211: 0 comment: ; turn off DEVICE ADDRESS bits test 212: 000000 test 213: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0x00 comment: ; comment: ; comment: ; set up to load ENABLE/0x00 (all zeroes) test 214: 100000000 comment: ; turn on DEVICE ADDRESS bits test 215: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes LO comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 216: 10 01 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 217: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 218: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 219: 01 comment: ; remove DEVICE ADDRESS test 220: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 221: 1 10 test 222: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 223: 1 000 test 224: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 225: 1 00 1 0 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 226: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 227: 1 test 228: 0 test 229: 1 test 230: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 231: 1 0 0 test 232: 0 test 233: 1 test 234: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 235: 1 1 0 test 236: 0 test 237: 1 test 238: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 239: 1 0 0 test 240: 0 test 241: 1 test 242: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 243: 1 0 0 test 244: 0 test 245: 1 test 246: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 247: 1 0 test 248: 0 test 249: 1 test 250: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 251: 1 0 test 252: 0 test 253: 1 test 254: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 255: 1 0 test 256: 0 test 257: 1 test 258: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 259: 1 0 01 test 260: 0 comment: ; STOP FFs bits start counting... test 261: 1 1 test 262: 0 test 263: 1 1 test 264: 0 test 265: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 266: 1 test 267: 0 test 268: 1 test 269: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 270: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 271: 10 test 272: 01 comment: ; turn off DEVICE ADDRESS bits test 273: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 274: 1 test 275: 0 comment: ; turn on DEVICE ADDRESS bits test 276: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 277: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 278: 111 test 279: 0 comment: ; turn off I/O SKP. STROBE test 280: 0 comment: ; turn off DEVICE ADDRESS bits test 281: 000000 test 282: 11000000001011001111110001110101010101X1 comment: ; comment: ; comment: ; send a 0xFF comment: ; comment: ; comment: ; set up to load ENABLE/0xFF (all ones) test 283: 111111111 comment: ; turn on DEVICE ADDRESS bits test 284: 111111 comment: ; turn on LOAD BUFFER (normally IOP4) comment: ; LOAD BUFFER STROBE-N goes LO comment: ; (BIT 6) goes HI comment: ; (ENABLE) goes HI (note: next CLOCK starts TX...) comment: ; (ENABLE-N) goes LO test 285: 10 11 0 comment: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) test 286: 1 comment: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 287: 0 comment: ; remove LOAD BUFFER (normally IOP4) test 288: 01 comment: ; remove DEVICE ADDRESS test 289: 000000 comment: ; comment: ; shift out the 0x00 character comment: ; comment: ; on first 2 X BAUD CLOCK INPUT comment: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). comment: ; test 290: 1 10 test 291: 0 comment: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET test 292: 1 000 test 293: 0 comment: ; ORGINAL BIT 1 (AC11) goes to LINE comment: ; (BIT 6) shifts comment: ; (ENABLE) goes LO, (ENABLE-N) goes HI test 294: 1 10 1 1 comment: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) test 295: 0 comment: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) test 296: 1 test 297: 0 test 298: 1 test 299: 0 comment: ; ORGINAL BIT 2 (AC10) goes to LINE test 300: 1 1 1 test 301: 0 test 302: 1 test 303: 0 comment: ; ORGINAL BIT 3 (AC9) goes to LINE comment: ; (BIT 6) becomes original ENABLE test 304: 1 1 1 test 305: 0 test 306: 1 test 307: 0 comment: ; ORGINAL BIT 4 (AC8) goes to LINE comment: ; (BIT 6) goes LO test 308: 1 0 1 test 309: 0 test 310: 1 test 311: 0 comment: ; ORGINAL BIT 5 (AC7) goes to LINE comment: ; test 312: 1 1 test 313: 0 test 314: 1 test 315: 0 comment: ; ORGINAL BIT 6 (AC6) goes to LINE test 316: 1 1 test 317: 0 test 318: 1 test 319: 0 comment: ; ORGINAL BIT 7 (AC5) goes to LINE test 320: 1 1 test 321: 0 test 322: 1 test 323: 0 comment: ; ORGINAL BIT 8 (AC4) goes to LINE test 324: 1 1 test 325: 0 test 326: 1 test 327: 0 comment: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) comment: ; (ACTIVE) goes LO comment: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON test 328: 1 0 01 test 329: 0 comment: ; STOP FFs bits start counting... test 330: 1 1 test 331: 0 test 332: 1 1 test 333: 0 test 334: 1 1 comment: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) test 335: 1 test 336: 0 test 337: 1 test 338: 0 comment: ; comment: ; try the I/O SKIP comment: ; comment: ; turn on DEVICE ADDRESS bits test 339: 111111 comment: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) test 340: 10 test 341: 01 comment: ; turn off DEVICE ADDRESS bits test 342: 000000 comment: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) test 343: 11 test 344: 01 comment: ; turn on DEVICE ADDRESS bits test 345: 111111 comment: ; set I/O SKP. STROBE, I/O SKP.-N goes LO test 346: 10 comment: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI comment: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF test 347: 111 test 348: 0 comment: ; turn off I/O SKP. STROBE test 349: 0 comment: ; turn off DEVICE ADDRESS bits test 350: 000000 test 351: 11000000001011001111110001110101010101X1 comment: ; comment: ; test ECHO input (need to scope AV2 20MA OUTPUT) comment: ; comment: ; set ECHO-N lo, 20MA OUTPUT goes LO test 352: X0 test 353: X1 end: END summary column 1: offset 3, mask 0x4000 column 2: offset 2, mask 0x0080 column 3: offset 2, mask 0x0040 column 4: offset 3, mask 0x0040 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 1, mask 0x1000 column 12: offset 3, mask 0x0001 column 13: offset 3, mask 0x0002 column 14: offset 3, mask 0x0004 column 15: offset 2, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0400 column 18: offset 4, mask 0x0001 column 19: offset 3, mask 0x0080 column 20: offset 3, mask 0x0200 column 21: offset 3, mask 0x0400 column 22: offset 3, mask 0x0020 column 23: offset 0, mask 0x0100 column 24: offset 1, mask 0x0001 column 25: offset 1, mask 0x8000 column 26: offset 1, mask 0x4000 column 27: offset 0, mask 0x0200 column 28: offset 1, mask 0x0008 column 29: offset 1, mask 0x0010 column 30: offset 1, mask 0x0020 column 31: offset 1, mask 0x0002 column 32: offset 1, mask 0x0004 column 33: offset 2, mask 0x0001 column 34: offset 1, mask 0x0040 column 35: offset 1, mask 0x0080 column 36: offset 2, mask 0x8000 column 37: offset 0, mask 0x1000 column 38: offset 0, mask 0x0010 column 39: offset 2, mask 0x0002 column 40: offset 0, mask 0x4000 direction bits (1=input) 0xB1F0 0x6901 0x7F1A 0xFF9E 0xF0FE pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4210 0x5408 0x00C0 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 2: 0x4210 0x5408 0x0080 0x4006 0x0001 0x0000 0x0000 0x0002 0x0680 0x0000 3: 0x4210 0x5408 0x0080 0x40C6 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 4: 0x4210 0x5408 0x0080 0x4086 0x0001 0x0000 0x0000 0x0002 0x0600 0x0000 5: 0x4210 0x5408 0x0080 0x42C6 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 6: 0x4210 0x5408 0x0080 0x4286 0x0001 0x0000 0x0000 0x0002 0x0400 0x0000 7: 0x4210 0x5408 0x0080 0x46C6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 8: 0x4210 0x5408 0x0080 0x4686 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 9: 0x4210 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 10: 0x4210 0x5608 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 11: 0x4210 0x566C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 12: 0x4E1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 13: 0x4C1F 0x126D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 14: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 15: 0x4010 0x826D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 16: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 17: 0x4010 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 18: 0x4011 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 19: 0x4012 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 20: 0x4013 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 21: 0x4014 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 22: 0x4015 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 23: 0x4016 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 24: 0x4017 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 25: 0x4410 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 26: 0x4411 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 27: 0x4412 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 28: 0x4413 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 29: 0x4414 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 30: 0x4415 0x966D 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 31: 0x4416 0x966D 0x8080 0x46A6 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0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 246: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 247: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 248: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 249: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 250: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 251: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 252: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 253: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 254: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 255: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 256: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 257: 0x5200 0x5408 0x0080 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 258: 0x5200 0x5408 0x0080 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 259: 0x4210 0x5408 0x0080 0x4062 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 260: 0x4210 0x5408 0x0080 0x4022 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 261: 0x4210 0x5408 0x0080 0x40E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 262: 0x4210 0x5408 0x0080 0x40A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 263: 0x4210 0x5408 0x0080 0x42E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 264: 0x4210 0x5408 0x0080 0x42A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 265: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 266: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 267: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 268: 0x4210 0x5408 0x0080 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 269: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 270: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 271: 0x4E1F 0x5408 0x0080 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 272: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 273: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 274: 0x4210 0x5408 0x0080 0x46A3 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 275: 0x4210 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 276: 0x4E1F 0x5408 0x0080 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 277: 0x4E1F 0x5408 0x0080 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 278: 0x4E1F 0x5408 0x00A0 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 279: 0x4E1F 0x5408 0x0080 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 280: 0x4E1F 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 281: 0x4210 0x5408 0x0080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 282: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 283: 0x4210 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 284: 0x4E1F 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 285: 0x4F1F 0x12FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 286: 0x4F1F 0x92FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 287: 0x4D1F 0x92FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 288: 0x4D1F 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 289: 0x4110 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 290: 0x5100 0x94FF 0x8081 0x46E6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 291: 0x5100 0x94FF 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 292: 0x5100 0x94FF 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 293: 0x5100 0x94FF 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 294: 0x5110 0xD4FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 295: 0x5110 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 296: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 297: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 298: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 299: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 300: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 301: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 302: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 303: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 304: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 305: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 306: 0x5310 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 307: 0x5310 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 308: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 309: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 310: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 311: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 312: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 313: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 314: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 315: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 316: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 317: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 318: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 319: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 320: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 321: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 322: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 323: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 324: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 325: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 326: 0x5210 0x54FE 0x8081 0x4066 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 327: 0x5210 0x54FE 0x8081 0x4026 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 328: 0x4210 0x54FE 0x8081 0x4062 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 329: 0x4210 0x54FE 0x8081 0x4022 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 330: 0x4210 0x54FE 0x8081 0x40E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 331: 0x4210 0x54FE 0x8081 0x40A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 332: 0x4210 0x54FE 0x8081 0x42E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 333: 0x4210 0x54FE 0x8081 0x42A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 334: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 335: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 336: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 337: 0x4210 0x54FE 0x8081 0x46E2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 338: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 339: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 340: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 341: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 342: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 343: 0x4210 0x54FE 0x8081 0x46A3 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 344: 0x4210 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 345: 0x4E1F 0x54FE 0x8081 0x46A2 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 346: 0x4E1F 0x54FE 0x8081 0x46A1 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 347: 0x4E1F 0x54FE 0x80A1 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 348: 0x4E1F 0x54FE 0x8081 0x46A7 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 349: 0x4E1F 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 350: 0x4210 0x54FE 0x8081 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 351: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 352: 0x0210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 353: 0x4210 0x546C 0x8080 0x46A6 0x0001 0x0000 0x0000 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I OIIIOIO I IIGI P GOIIIIOIIIIIIIIO O OO G P GIIIIOO IIOI UUT inputs: 28 UUT outputs: 12 pins used: 40 not used: 26 353 'test steps' 643 lines M707 PCB REV D SCHEMATIC REV c TELETYPE TRANSMITTER ICs are VERTICAL on PCB REV D. Rev D adds AB1 ECHO input. does not test AV2 20MA OUTPUT, use scope and pulldown or use M707D_MA.TST to test 20MA OUTPUT (needs jumper) PINS Main menu Thu Jun 29 15:32:44 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Thu Jun 29 15:32:47 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 15:32:50 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 1110000000101100111000000111000000000111 step 2 1100000000101100111000000111000000000111 step 3 1101000000101100111100000111000000000111 step 4 1100000000101100111100000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 1: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvv vvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1110000000101100111110000111000000000111 step 2 1100000000101100111110000111000000000111 step 3 1101000000101100111110000111000000000111 step 4 1100000000101100111110000111000000000111 step 5 1101000000101100111110000111000000000111 step 6 1100000000101100111110000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011011 source: 0 changed: 0 step 94 1100000000101100110001000111010101011011 source: 1 changed: 1 step 95 1101000000101100110001000111010101011011 source: 0 changed: 0 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 step 101 1101000000101100110001000111010101011011 source: 0 changed: 0 step 102 1100000000101100110001000111010101011011 source: 1 changed: 1 step 103 1101000000101100110001000111010101011011 source: 0 changed: 0 step 104 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 0 step 109 1101000000101100110001000111010101011011 source: 0 changed: 0 step 110 1100000000101100110001000111010101011011 source: 1 changed: 1 step 111 1101000000101100110001000111010101011011 source: 0 changed: 0 step 112 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 2: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 1 0 step 12 1100111111101101011111010011010101010111 source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101011111010001010101010111 source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101111111011001010101010111 source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101011111011001010101010111 source: 1 1 changed: 1 1 step 16 1100000000101101111111011001010101010111 source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101111111011001010101010111 source: 000001 1 changed: 1 step 18 1100000001101101111111011001010101010111 source: 000010 1 changed: 10 step 19 1100000010101101111111011001010101010111 source: 000011 1 changed: 1 step 20 1100000011101101111111011001010101010111 source: 000100 1 changed: 100 step 21 1100000100101101111111011001010101010111 source: 000101 1 changed: 1 step 22 1100000101101101111111011001010101010111 source: 000110 1 changed: 10 step 23 1100000110101101111111011001010101010111 source: 000111 1 changed: 1 step 24 1100000111101101111111011001010101010111 source: 001000 1 changed: 1000 step 25 1100001000101101111111011001010101010111 source: 001001 1 changed: 1 step 26 1100001001101101111111011001010101010111 source: 001010 1 changed: 10 step 27 1100001010101101111111011001010101010111 source: 001011 1 changed: 1 step 28 1100001011101101111111011001010101010111 source: 001100 1 changed: 100 step 29 1100001100101101111111011001010101010111 source: 001101 1 changed: 1 step 30 1100001101101101111111011001010101010111 source: 001110 1 changed: 10 step 31 1100001110101101111111011001010101010111 source: 001111 1 changed: 1 step 32 1100001111101101111111011001010101010111 source: 010000 1 changed: 10000 step 33 1100010000101101111111011001010101010111 source: 010001 1 changed: 1 step 34 1100010001101101111111011001010101010111 source: 010010 1 changed: 10 step 35 1100010010101101111111011001010101010111 source: 010011 1 changed: 1 step 36 1100010011101101111111011001010101010111 source: 010100 1 changed: 100 step 37 1100010100101101111111011001010101010111 source: 010101 1 changed: 1 step 38 1100010101101101111111011001010101010111 source: 010110 1 changed: 10 step 39 1100010110101101111111011001010101010111 source: 010111 1 changed: 1 step 40 1100010111101101111111011001010101010111 source: 011000 1 changed: 1000 step 41 1100011000101101111111011001010101010111 source: 011001 1 changed: 1 step 42 1100011001101101111111011001010101010111 source: 011010 1 changed: 10 step 43 1100011010101101111111011001010101010111 source: 011011 1 changed: 1 step 44 1100011011101101111111011001010101010111 source: 011100 1 changed: 100 step 45 1100011100101101111111011001010101010111 source: 011101 1 changed: 1 step 46 1100011101101101111111011001010101010111 source: 011110 1 changed: 10 step 47 1100011110101101111111011001010101010111 source: 011111 1 changed: 1 step 48 1100011111101101111111011001010101010111 source: 100000 1 changed: 100000 step 49 1100100000101101111111011001010101010111 source: 100001 1 changed: 1 step 50 1100100001101101111111011001010101010111 source: 100010 1 changed: 10 step 51 1100100010101101111111011001010101010111 source: 100011 1 changed: 1 step 52 1100100011101101111111011001010101010111 source: 100100 1 changed: 100 step 53 1100100100101101111111011001010101010111 source: 100101 1 changed: 1 step 54 1100100101101101111111011001010101010111 source: 100110 1 changed: 10 step 55 1100100110101101111111011001010101010111 source: 100111 1 changed: 1 step 56 1100100111101101111111011001010101010111 source: 101000 1 changed: 1000 step 57 1100101000101101111111011001010101010111 source: 101001 1 changed: 1 step 58 1100101001101101111111011001010101010111 source: 101010 1 changed: 10 step 59 1100101010101101111111011001010101010111 source: 101011 1 changed: 1 step 60 1100101011101101111111011001010101010111 source: 101100 1 changed: 100 step 61 1100101100101101111111011001010101010111 source: 101101 1 changed: 1 step 62 1100101101101101111111011001010101010111 source: 101110 1 changed: 10 step 63 1100101110101101111111011001010101010111 source: 101111 1 changed: 1 step 64 1100101111101101111111011001010101010111 source: 110000 1 changed: 10000 step 65 1100110000101101111111011001010101010111 source: 110001 1 changed: 1 step 66 1100110001101101111111011001010101010111 source: 110010 1 changed: 10 step 67 1100110010101101111111011001010101010111 source: 110011 1 changed: 1 step 68 1100110011101101111111011001010101010111 source: 110100 1 changed: 100 step 69 1100110100101101111111011001010101010111 source: 110101 1 changed: 1 step 70 1100110101101101111111011001010101010111 source: 110110 1 changed: 10 step 71 1100110110101101111111011001010101010111 source: 110111 1 changed: 1 step 72 1100110111101101111111011001010101010111 source: 111000 1 changed: 1000 step 73 1100111000101101111111011001010101010111 source: 111001 1 changed: 1 step 74 1100111001101101111111011001010101010111 source: 111010 1 changed: 10 step 75 1100111010101101111111011001010101010111 source: 111011 1 changed: 1 step 76 1100111011101101111111011001010101010111 source: 111100 1 changed: 100 step 77 1100111100101101111111011001010101010111 source: 111101 1 changed: 1 step 78 1100111101101101111111011001010101010111 source: 111110 1 changed: 10 step 79 1100111110101101111111011001010101010111 source: 111111 0 changed: 1 0 step 80 1100111111101101011111011001010101010111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100111111011001010101010111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100111111011001010101010111 source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 83 1101000000101100111111011001010101011011 source: 0 changed: 0 step 84 1100000000101100111111011001010101011011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 85 1101000000101100110001011001010101011011 source: 0 changed: 0 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011011 source: 0 changed: 0 step 94 1100000000101100110001000111010101011011 source: 1 changed: 1 step 95 1101000000101100110001000111010101011011 source: 0 changed: 0 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 step 101 1101000000101100110001000111010101011011 source: 0 changed: 0 step 102 1100000000101100110001000111010101011011 source: 1 changed: 1 step 103 1101000000101100110001000111010101011011 source: 0 changed: 0 step 104 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 0 step 109 1101000000101100110001000111010101011011 source: 0 changed: 0 step 110 1100000000101100110001000111010101011011 source: 1 changed: 1 step 111 1101000000101100110001000111010101011011 source: 0 changed: 0 step 112 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 3: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 1 0 step 12 1100111111101101011111010011010101010111 source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101011111010001010101010111 source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101111111011001010101010111 source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101011111011001010101010111 source: 1 1 changed: 1 1 step 16 1100000000101101111111011001010101010111 source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101111111011001010101010111 source: 000001 1 changed: 1 step 18 1100000001101101111111011001010101010111 source: 000010 1 changed: 10 step 19 1100000010101101111111011001010101010111 source: 000011 1 changed: 1 step 20 1100000011101101111111011001010101010111 source: 000100 1 changed: 100 step 21 1100000100101101111111011001010101010111 source: 000101 1 changed: 1 step 22 1100000101101101111111011001010101010111 source: 000110 1 changed: 10 step 23 1100000110101101111111011001010101010111 source: 000111 1 changed: 1 step 24 1100000111101101111111011001010101010111 source: 001000 1 changed: 1000 step 25 1100001000101101111111011001010101010111 source: 001001 1 changed: 1 step 26 1100001001101101111111011001010101010111 source: 001010 1 changed: 10 step 27 1100001010101101111111011001010101010111 source: 001011 1 changed: 1 step 28 1100001011101101111111011001010101010111 source: 001100 1 changed: 100 step 29 1100001100101101111111011001010101010111 source: 001101 1 changed: 1 step 30 1100001101101101111111011001010101010111 source: 001110 1 changed: 10 step 31 1100001110101101111111011001010101010111 source: 001111 1 changed: 1 step 32 1100001111101101111111011001010101010111 source: 010000 1 changed: 10000 step 33 1100010000101101111111011001010101010111 source: 010001 1 changed: 1 step 34 1100010001101101111111011001010101010111 source: 010010 1 changed: 10 step 35 1100010010101101111111011001010101010111 source: 010011 1 changed: 1 step 36 1100010011101101111111011001010101010111 source: 010100 1 changed: 100 step 37 1100010100101101111111011001010101010111 source: 010101 1 changed: 1 step 38 1100010101101101111111011001010101010111 source: 010110 1 changed: 10 step 39 1100010110101101111111011001010101010111 source: 010111 1 changed: 1 step 40 1100010111101101111111011001010101010111 source: 011000 1 changed: 1000 step 41 1100011000101101111111011001010101010111 source: 011001 1 changed: 1 step 42 1100011001101101111111011001010101010111 source: 011010 1 changed: 10 step 43 1100011010101101111111011001010101010111 source: 011011 1 changed: 1 step 44 1100011011101101111111011001010101010111 source: 011100 1 changed: 100 step 45 1100011100101101111111011001010101010111 source: 011101 1 changed: 1 step 46 1100011101101101111111011001010101010111 source: 011110 1 changed: 10 step 47 1100011110101101111111011001010101010111 source: 011111 1 changed: 1 step 48 1100011111101101111111011001010101010111 source: 100000 1 changed: 100000 step 49 1100100000101101111111011001010101010111 source: 100001 1 changed: 1 step 50 1100100001101101111111011001010101010111 source: 100010 1 changed: 10 step 51 1100100010101101111111011001010101010111 source: 100011 1 changed: 1 step 52 1100100011101101111111011001010101010111 source: 100100 1 changed: 100 step 53 1100100100101101111111011001010101010111 source: 100101 1 changed: 1 step 54 1100100101101101111111011001010101010111 source: 100110 1 changed: 10 step 55 1100100110101101111111011001010101010111 source: 100111 1 changed: 1 step 56 1100100111101101111111011001010101010111 source: 101000 1 changed: 1000 step 57 1100101000101101111111011001010101010111 source: 101001 1 changed: 1 step 58 1100101001101101111111011001010101010111 source: 101010 1 changed: 10 step 59 1100101010101101111111011001010101010111 source: 101011 1 changed: 1 step 60 1100101011101101111111011001010101010111 source: 101100 1 changed: 100 step 61 1100101100101101111111011001010101010111 source: 101101 1 changed: 1 step 62 1100101101101101111111011001010101010111 source: 101110 1 changed: 10 step 63 1100101110101101111111011001010101010111 source: 101111 1 changed: 1 step 64 1100101111101101111111011001010101010111 source: 110000 1 changed: 10000 step 65 1100110000101101111111011001010101010111 source: 110001 1 changed: 1 step 66 1100110001101101111111011001010101010111 source: 110010 1 changed: 10 step 67 1100110010101101111111011001010101010111 source: 110011 1 changed: 1 step 68 1100110011101101111111011001010101010111 source: 110100 1 changed: 100 step 69 1100110100101101111111011001010101010111 source: 110101 1 changed: 1 step 70 1100110101101101111111011001010101010111 source: 110110 1 changed: 10 step 71 1100110110101101111111011001010101010111 source: 110111 1 changed: 1 step 72 1100110111101101111111011001010101010111 source: 111000 1 changed: 1000 step 73 1100111000101101111111011001010101010111 source: 111001 1 changed: 1 step 74 1100111001101101111111011001010101010111 source: 111010 1 changed: 10 step 75 1100111010101101111111011001010101010111 source: 111011 1 changed: 1 step 76 1100111011101101111111011001010101010111 source: 111100 1 changed: 100 step 77 1100111100101101111111011001010101010111 source: 111101 1 changed: 1 step 78 1100111101101101111111011001010101010111 source: 111110 1 changed: 10 step 79 1100111110101101111111011001010101010111 source: 111111 0 changed: 1 0 step 80 1100111111101101011111011001010101010111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100111111011001010101010111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100111111011001010101010111 source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 83 1101000000101100111111011001010101011011 source: 0 changed: 0 step 84 1100000000101100111111011001010101011011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 85 1101000000101100110001011001010101011011 source: 0 changed: 0 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011011 source: 0 changed: 0 step 94 1100000000101100110001000111010101011011 source: 1 changed: 1 step 95 1101000000101100110001000111010101011011 source: 0 changed: 0 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 step 101 1101000000101100110001000111010101011011 source: 0 changed: 0 step 102 1100000000101100110001000111010101011011 source: 1 changed: 1 step 103 1101000000101100110001000111010101011011 source: 0 changed: 0 step 104 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 0 step 109 1101000000101100110001000111010101011011 source: 0 changed: 0 step 110 1100000000101100110001000111010101011011 source: 1 changed: 1 step 111 1101000000101100110001000111010101011011 source: 0 changed: 0 step 112 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 4: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 4, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high 1 O BJ1 +3V 2 I BF2 CLEAR FLAG 2-N (NORMALLY 3V) 18 I BS2 WAIT-N (PROLONGS STOP BITS) (NORMALLY 3V) 28 I AN2 ENABLE (NORMALLY 3V) 39 O AV2 20MA OUTPUT (PNP TO +) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 38 O AD2 LINE SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI fails LO: 11 1 1 11 11 11 1111111111111 11 fails LO: 00000000 0 00 000 00 0 0 0 0 0 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 1 0 step 12 1100111111101101011111010011010101010111 source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101011111010001010101010111 source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101111111011001010101010111 source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101011111011001010101010111 source: 1 1 changed: 1 1 step 16 1100000000101101111111011001010101010111 source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101111111011001010101010111 source: 000001 1 changed: 1 step 18 1100000001101101111111011001010101010111 source: 000010 1 changed: 10 step 19 1100000010101101111111011001010101010111 source: 000011 1 changed: 1 step 20 1100000011101101111111011001010101010111 source: 000100 1 changed: 100 step 21 1100000100101101111111011001010101010111 source: 000101 1 changed: 1 step 22 1100000101101101111111011001010101010111 source: 000110 1 changed: 10 step 23 1100000110101101111111011001010101010111 source: 000111 1 changed: 1 step 24 1100000111101101111111011001010101010111 source: 001000 1 changed: 1000 step 25 1100001000101101111111011001010101010111 source: 001001 1 changed: 1 step 26 1100001001101101111111011001010101010111 source: 001010 1 changed: 10 step 27 1100001010101101111111011001010101010111 source: 001011 1 changed: 1 step 28 1100001011101101111111011001010101010111 source: 001100 1 changed: 100 step 29 1100001100101101111111011001010101010111 source: 001101 1 changed: 1 step 30 1100001101101101111111011001010101010111 source: 001110 1 changed: 10 step 31 1100001110101101111111011001010101010111 source: 001111 1 changed: 1 step 32 1100001111101101111111011001010101010111 source: 010000 1 changed: 10000 step 33 1100010000101101111111011001010101010111 source: 010001 1 changed: 1 step 34 1100010001101101111111011001010101010111 source: 010010 1 changed: 10 step 35 1100010010101101111111011001010101010111 source: 010011 1 changed: 1 step 36 1100010011101101111111011001010101010111 source: 010100 1 changed: 100 step 37 1100010100101101111111011001010101010111 source: 010101 1 changed: 1 step 38 1100010101101101111111011001010101010111 source: 010110 1 changed: 10 step 39 1100010110101101111111011001010101010111 source: 010111 1 changed: 1 step 40 1100010111101101111111011001010101010111 source: 011000 1 changed: 1000 step 41 1100011000101101111111011001010101010111 source: 011001 1 changed: 1 step 42 1100011001101101111111011001010101010111 source: 011010 1 changed: 10 step 43 1100011010101101111111011001010101010111 source: 011011 1 changed: 1 step 44 1100011011101101111111011001010101010111 source: 011100 1 changed: 100 step 45 1100011100101101111111011001010101010111 source: 011101 1 changed: 1 step 46 1100011101101101111111011001010101010111 source: 011110 1 changed: 10 step 47 1100011110101101111111011001010101010111 source: 011111 1 changed: 1 step 48 1100011111101101111111011001010101010111 source: 100000 1 changed: 100000 step 49 1100100000101101111111011001010101010111 source: 100001 1 changed: 1 step 50 1100100001101101111111011001010101010111 source: 100010 1 changed: 10 step 51 1100100010101101111111011001010101010111 source: 100011 1 changed: 1 step 52 1100100011101101111111011001010101010111 source: 100100 1 changed: 100 step 53 1100100100101101111111011001010101010111 source: 100101 1 changed: 1 step 54 1100100101101101111111011001010101010111 source: 100110 1 changed: 10 step 55 1100100110101101111111011001010101010111 source: 100111 1 changed: 1 step 56 1100100111101101111111011001010101010111 source: 101000 1 changed: 1000 step 57 1100101000101101111111011001010101010111 source: 101001 1 changed: 1 step 58 1100101001101101111111011001010101010111 source: 101010 1 changed: 10 step 59 1100101010101101111111011001010101010111 source: 101011 1 changed: 1 step 60 1100101011101101111111011001010101010111 source: 101100 1 changed: 100 step 61 1100101100101101111111011001010101010111 source: 101101 1 changed: 1 step 62 1100101101101101111111011001010101010111 source: 101110 1 changed: 10 step 63 1100101110101101111111011001010101010111 source: 101111 1 changed: 1 step 64 1100101111101101111111011001010101010111 source: 110000 1 changed: 10000 step 65 1100110000101101111111011001010101010111 source: 110001 1 changed: 1 step 66 1100110001101101111111011001010101010111 source: 110010 1 changed: 10 step 67 1100110010101101111111011001010101010111 source: 110011 1 changed: 1 step 68 1100110011101101111111011001010101010111 source: 110100 1 changed: 100 step 69 1100110100101101111111011001010101010111 source: 110101 1 changed: 1 step 70 1100110101101101111111011001010101010111 source: 110110 1 changed: 10 step 71 1100110110101101111111011001010101010111 source: 110111 1 changed: 1 step 72 1100110111101101111111011001010101010111 source: 111000 1 changed: 1000 step 73 1100111000101101111111011001010101010111 source: 111001 1 changed: 1 step 74 1100111001101101111111011001010101010111 source: 111010 1 changed: 10 step 75 1100111010101101111111011001010101010111 source: 111011 1 changed: 1 step 76 1100111011101101111111011001010101010111 source: 111100 1 changed: 100 step 77 1100111100101101111111011001010101010111 source: 111101 1 changed: 1 step 78 1100111101101101111111011001010101010111 source: 111110 1 changed: 10 step 79 1100111110101101111111011001010101010111 source: 111111 0 changed: 1 0 step 80 1100111111101101011111011001010101010111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100111111011001010101010111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100111111011001010101010111 source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 83 1101000000101100111111011001010101011011 source: 0 changed: 0 step 84 1100000000101100111111011001010101011011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 85 1101000000101100110001011001010101011011 source: 0 changed: 0 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011011 source: 0 changed: 0 step 94 1100000000101100110001000111010101011011 source: 1 changed: 1 step 95 1101000000101100110001000111010101011011 source: 0 changed: 0 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 step 101 1101000000101100110001000111010101011011 source: 0 changed: 0 step 102 1100000000101100110001000111010101011011 source: 1 changed: 1 step 103 1101000000101100110001000111010101011011 source: 0 changed: 0 step 104 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 0 step 109 1101000000101100110001000111010101011011 source: 0 changed: 0 step 110 1100000000101100110001000111010101011011 source: 1 changed: 1 step 111 1101000000101100110001000111010101011011 source: 0 changed: 0 step 112 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 5: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 5, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 1 0 step 12 1100111111101101011111010011010101010111 source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101011111010001010101010111 source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101111111011001010101010111 source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101011111011001010101010111 source: 1 1 changed: 1 1 step 16 1100000000101101111111011001010101010111 source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101111111011001010101010111 source: 000001 1 changed: 1 step 18 1100000001101101111111011001010101010111 source: 000010 1 changed: 10 step 19 1100000010101101111111011001010101010111 source: 000011 1 changed: 1 step 20 1100000011101101111111011001010101010111 source: 000100 1 changed: 100 step 21 1100000100101101111111011001010101010111 source: 000101 1 changed: 1 step 22 1100000101101101111111011001010101010111 source: 000110 1 changed: 10 step 23 1100000110101101111111011001010101010111 source: 000111 1 changed: 1 step 24 1100000111101101111111011001010101010111 source: 001000 1 changed: 1000 step 25 1100001000101101111111011001010101010111 source: 001001 1 changed: 1 step 26 1100001001101101111111011001010101010111 source: 001010 1 changed: 10 step 27 1100001010101101111111011001010101010111 source: 001011 1 changed: 1 step 28 1100001011101101111111011001010101010111 source: 001100 1 changed: 100 step 29 1100001100101101111111011001010101010111 source: 001101 1 changed: 1 step 30 1100001101101101111111011001010101010111 source: 001110 1 changed: 10 step 31 1100001110101101111111011001010101010111 source: 001111 1 changed: 1 step 32 1100001111101101111111011001010101010111 source: 010000 1 changed: 10000 step 33 1100010000101101111111011001010101010111 source: 010001 1 changed: 1 step 34 1100010001101101111111011001010101010111 source: 010010 1 changed: 10 step 35 1100010010101101111111011001010101010111 source: 010011 1 changed: 1 step 36 1100010011101101111111011001010101010111 source: 010100 1 changed: 100 step 37 1100010100101101111111011001010101010111 source: 010101 1 changed: 1 step 38 1100010101101101111111011001010101010111 source: 010110 1 changed: 10 step 39 1100010110101101111111011001010101010111 source: 010111 1 changed: 1 step 40 1100010111101101111111011001010101010111 source: 011000 1 changed: 1000 step 41 1100011000101101111111011001010101010111 source: 011001 1 changed: 1 step 42 1100011001101101111111011001010101010111 source: 011010 1 changed: 10 step 43 1100011010101101111111011001010101010111 source: 011011 1 changed: 1 step 44 1100011011101101111111011001010101010111 source: 011100 1 changed: 100 step 45 1100011100101101111111011001010101010111 source: 011101 1 changed: 1 step 46 1100011101101101111111011001010101010111 source: 011110 1 changed: 10 step 47 1100011110101101111111011001010101010111 source: 011111 1 changed: 1 step 48 1100011111101101111111011001010101010111 source: 100000 1 changed: 100000 step 49 1100100000101101111111011001010101010111 source: 100001 1 changed: 1 step 50 1100100001101101111111011001010101010111 source: 100010 1 changed: 10 step 51 1100100010101101111111011001010101010111 source: 100011 1 changed: 1 step 52 1100100011101101111111011001010101010111 source: 100100 1 changed: 100 step 53 1100100100101101111111011001010101010111 source: 100101 1 changed: 1 step 54 1100100101101101111111011001010101010111 source: 100110 1 changed: 10 step 55 1100100110101101111111011001010101010111 source: 100111 1 changed: 1 step 56 1100100111101101111111011001010101010111 source: 101000 1 changed: 1000 step 57 1100101000101101111111011001010101010111 source: 101001 1 changed: 1 step 58 1100101001101101111111011001010101010111 source: 101010 1 changed: 10 step 59 1100101010101101111111011001010101010111 source: 101011 1 changed: 1 step 60 1100101011101101111111011001010101010111 source: 101100 1 changed: 100 step 61 1100101100101101111111011001010101010111 source: 101101 1 changed: 1 step 62 1100101101101101111111011001010101010111 source: 101110 1 changed: 10 step 63 1100101110101101111111011001010101010111 source: 101111 1 changed: 1 step 64 1100101111101101111111011001010101010111 source: 110000 1 changed: 10000 step 65 1100110000101101111111011001010101010111 source: 110001 1 changed: 1 step 66 1100110001101101111111011001010101010111 source: 110010 1 changed: 10 step 67 1100110010101101111111011001010101010111 source: 110011 1 changed: 1 step 68 1100110011101101111111011001010101010111 source: 110100 1 changed: 100 step 69 1100110100101101111111011001010101010111 source: 110101 1 changed: 1 step 70 1100110101101101111111011001010101010111 source: 110110 1 changed: 10 step 71 1100110110101101111111011001010101010111 source: 110111 1 changed: 1 step 72 1100110111101101111111011001010101010111 source: 111000 1 changed: 1000 step 73 1100111000101101111111011001010101010111 source: 111001 1 changed: 1 step 74 1100111001101101111111011001010101010111 source: 111010 1 changed: 10 step 75 1100111010101101111111011001010101010111 source: 111011 1 changed: 1 step 76 1100111011101101111111011001010101010111 source: 111100 1 changed: 100 step 77 1100111100101101111111011001010101010111 source: 111101 1 changed: 1 step 78 1100111101101101111111011001010101010111 source: 111110 1 changed: 10 step 79 1100111110101101111111011001010101010111 source: 111111 0 changed: 1 0 step 80 1100111111101101011111011001010101010111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100111111011001010101010111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100111111011001010101010111 source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 83 1101000000101100111111011001010101011011 source: 0 changed: 0 step 84 1100000000101100111111011001010101011011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 85 1101000000101100110001011001010101011011 source: 0 changed: 0 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011011 source: 0 changed: 0 step 94 1100000000101100110001000111010101011011 source: 1 changed: 1 step 95 1101000000101100110001000111010101011011 source: 0 changed: 0 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 step 101 1101000000101100110001000111010101011011 source: 0 changed: 0 step 102 1100000000101100110001000111010101011011 source: 1 changed: 1 step 103 1101000000101100110001000111010101011011 source: 0 changed: 0 step 104 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 0 step 109 1101000000101100110001000111010101011011 source: 0 changed: 0 step 110 1100000000101100110001000111010101011011 source: 1 changed: 1 step 111 1101000000101100110001000111010101011011 source: 0 changed: 0 step 112 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 6: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 6, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 1 0 step 12 1100111111101101011111010011010101010111 source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101011111010001010101010111 source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101111111011001010101010111 source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101011111011001010101010111 source: 1 1 changed: 1 1 step 16 1100000000101101111111011001010101010111 source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101111111011001010101010111 source: 000001 1 changed: 1 step 18 1100000001101101111111011001010101010111 source: 000010 1 changed: 10 step 19 1100000010101101111111011001010101010111 source: 000011 1 changed: 1 step 20 1100000011101101111111011001010101010111 source: 000100 1 changed: 100 step 21 1100000100101101111111011001010101010111 source: 000101 1 changed: 1 step 22 1100000101101101111111011001010101010111 source: 000110 1 changed: 10 step 23 1100000110101101111111011001010101010111 source: 000111 1 changed: 1 step 24 1100000111101101111111011001010101010111 source: 001000 1 changed: 1000 step 25 1100001000101101111111011001010101010111 source: 001001 1 changed: 1 step 26 1100001001101101111111011001010101010111 source: 001010 1 changed: 10 step 27 1100001010101101111111011001010101010111 source: 001011 1 changed: 1 step 28 1100001011101101111111011001010101010111 source: 001100 1 changed: 100 step 29 1100001100101101111111011001010101010111 source: 001101 1 changed: 1 step 30 1100001101101101111111011001010101010111 source: 001110 1 changed: 10 step 31 1100001110101101111111011001010101010111 source: 001111 1 changed: 1 step 32 1100001111101101111111011001010101010111 source: 010000 1 changed: 10000 step 33 1100010000101101111111011001010101010111 source: 010001 1 changed: 1 step 34 1100010001101101111111011001010101010111 source: 010010 1 changed: 10 step 35 1100010010101101111111011001010101010111 source: 010011 1 changed: 1 step 36 1100010011101101111111011001010101010111 source: 010100 1 changed: 100 step 37 1100010100101101111111011001010101010111 source: 010101 1 changed: 1 step 38 1100010101101101111111011001010101010111 source: 010110 1 changed: 10 step 39 1100010110101101111111011001010101010111 source: 010111 1 changed: 1 step 40 1100010111101101111111011001010101010111 source: 011000 1 changed: 1000 step 41 1100011000101101111111011001010101010111 source: 011001 1 changed: 1 step 42 1100011001101101111111011001010101010111 source: 011010 1 changed: 10 step 43 1100011010101101111111011001010101010111 source: 011011 1 changed: 1 step 44 1100011011101101111111011001010101010111 source: 011100 1 changed: 100 step 45 1100011100101101111111011001010101010111 source: 011101 1 changed: 1 step 46 1100011101101101111111011001010101010111 source: 011110 1 changed: 10 step 47 1100011110101101111111011001010101010111 source: 011111 1 changed: 1 step 48 1100011111101101111111011001010101010111 source: 100000 1 changed: 100000 step 49 1100100000101101111111011001010101010111 source: 100001 1 changed: 1 step 50 1100100001101101111111011001010101010111 source: 100010 1 changed: 10 step 51 1100100010101101111111011001010101010111 source: 100011 1 changed: 1 step 52 1100100011101101111111011001010101010111 source: 100100 1 changed: 100 step 53 1100100100101101111111011001010101010111 source: 100101 1 changed: 1 step 54 1100100101101101111111011001010101010111 source: 100110 1 changed: 10 step 55 1100100110101101111111011001010101010111 source: 100111 1 changed: 1 step 56 1100100111101101111111011001010101010111 source: 101000 1 changed: 1000 step 57 1100101000101101111111011001010101010111 source: 101001 1 changed: 1 step 58 1100101001101101111111011001010101010111 source: 101010 1 changed: 10 step 59 1100101010101101111111011001010101010111 source: 101011 1 changed: 1 step 60 1100101011101101111111011001010101010111 source: 101100 1 changed: 100 step 61 1100101100101101111111011001010101010111 source: 101101 1 changed: 1 step 62 1100101101101101111111011001010101010111 source: 101110 1 changed: 10 step 63 1100101110101101111111011001010101010111 source: 101111 1 changed: 1 step 64 1100101111101101111111011001010101010111 source: 110000 1 changed: 10000 step 65 1100110000101101111111011001010101010111 source: 110001 1 changed: 1 step 66 1100110001101101111111011001010101010111 source: 110010 1 changed: 10 step 67 1100110010101101111111011001010101010111 source: 110011 1 changed: 1 step 68 1100110011101101111111011001010101010111 source: 110100 1 changed: 100 step 69 1100110100101101111111011001010101010111 source: 110101 1 changed: 1 step 70 1100110101101101111111011001010101010111 source: 110110 1 changed: 10 step 71 1100110110101101111111011001010101010111 source: 110111 1 changed: 1 step 72 1100110111101101111111011001010101010111 source: 111000 1 changed: 1000 step 73 1100111000101101111111011001010101010111 source: 111001 1 changed: 1 step 74 1100111001101101111111011001010101010111 source: 111010 1 changed: 10 step 75 1100111010101101111111011001010101010111 source: 111011 1 changed: 1 step 76 1100111011101101111111011001010101010111 source: 111100 1 changed: 100 step 77 1100111100101101111111011001010101010111 source: 111101 1 changed: 1 step 78 1100111101101101111111011001010101010111 source: 111110 1 changed: 10 step 79 1100111110101101111111011001010101010111 source: 111111 0 changed: 1 0 step 80 1100111111101101011111011001010101010111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100111111011001010101010111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100111111011001010101010111 source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 83 1101000000101100111111011001010101011011 source: 0 changed: 0 step 84 1100000000101100111111011001010101011011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 85 1101000000101100110001011001010101011011 source: 0 changed: 0 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011011 source: 0 changed: 0 step 94 1100000000101100110001000111010101011011 source: 1 changed: 1 step 95 1101000000101100110001000111010101011011 source: 0 changed: 0 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 step 101 1101000000101100110001000111010101011011 source: 0 changed: 0 step 102 1100000000101100110001000111010101011011 source: 1 changed: 1 step 103 1101000000101100110001000111010101011011 source: 0 changed: 0 step 104 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 0 step 109 1101000000101100110001000111010101011011 source: 0 changed: 0 step 110 1100000000101100110001000111010101011011 source: 1 changed: 1 step 111 1101000000101100110001000111010101011011 source: 0 changed: 0 step 112 1100000000101100110001000111010101011011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 7: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 7, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 1 0 step 12 1100111111101101011111010011010101010111 source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101011111010001010101010111 source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101111111011001010101010111 source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101011111011001010101010111 source: 1 1 changed: 1 1 step 16 1100000000101101111111011001010101010111 source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101111111011001010101010111 source: 000001 1 changed: 1 step 18 1100000001101101111111011001010101010111 source: 000010 1 changed: 10 step 19 1100000010101101111111011001010101010111 source: 000011 1 changed: 1 step 20 1100000011101101111111011001010101010111 source: 000100 1 changed: 100 step 21 1100000100101101111111011001010101010111 source: 000101 1 changed: 1 step 22 1100000101101101111111011001010101010111 source: 000110 1 changed: 10 step 23 1100000110101101111111011001010101010111 source: 000111 1 changed: 1 step 24 1100000111101101111111011001010101010111 source: 001000 1 changed: 1000 step 25 1100001000101101111111011001010101010111 source: 001001 1 changed: 1 step 26 1100001001101101111111011001010101010111 source: 001010 1 changed: 10 step 27 1100001010101101111111011001010101010111 source: 001011 1 changed: 1 step 28 1100001011101101111111011001010101010111 source: 001100 1 changed: 100 step 29 1100001100101101111111011001010101010111 source: 001101 1 changed: 1 step 30 1100001101101101111111011001010101010111 source: 001110 1 changed: 10 step 31 1100001110101101111111011001010101010111 source: 001111 1 changed: 1 step 32 1100001111101101111111011001010101010111 source: 010000 1 changed: 10000 step 33 1100010000101101111111011001010101010111 source: 010001 1 changed: 1 step 34 1100010001101101111111011001010101010111 source: 010010 1 changed: 10 step 35 1100010010101101111111011001010101010111 source: 010011 1 changed: 1 step 36 1100010011101101111111011001010101010111 source: 010100 1 changed: 100 step 37 1100010100101101111111011001010101010111 source: 010101 1 changed: 1 step 38 1100010101101101111111011001010101010111 source: 010110 1 changed: 10 step 39 1100010110101101111111011001010101010111 source: 010111 1 changed: 1 step 40 1100010111101101111111011001010101010111 source: 011000 1 changed: 1000 step 41 1100011000101101111111011001010101010111 source: 011001 1 changed: 1 step 42 1100011001101101111111011001010101010111 source: 011010 1 changed: 10 step 43 1100011010101101111111011001010101010111 source: 011011 1 changed: 1 step 44 1100011011101101111111011001010101010111 source: 011100 1 changed: 100 step 45 1100011100101101111111011001010101010111 source: 011101 1 changed: 1 step 46 1100011101101101111111011001010101010111 source: 011110 1 changed: 10 step 47 1100011110101101111111011001010101010111 source: 011111 1 changed: 1 step 48 1100011111101101111111011001010101010111 source: 100000 1 changed: 100000 step 49 1100100000101101111111011001010101010111 source: 100001 1 changed: 1 step 50 1100100001101101111111011001010101010111 source: 100010 1 changed: 10 step 51 1100100010101101111111011001010101010111 source: 100011 1 changed: 1 step 52 1100100011101101111111011001010101010111 source: 100100 1 changed: 100 step 53 1100100100101101111111011001010101010111 source: 100101 1 changed: 1 step 54 1100100101101101111111011001010101010111 source: 100110 1 changed: 10 step 55 1100100110101101111111011001010101010111 source: 100111 1 changed: 1 step 56 1100100111101101111111011001010101010111 source: 101000 1 changed: 1000 step 57 1100101000101101111111011001010101010111 source: 101001 1 changed: 1 step 58 1100101001101101111111011001010101010111 source: 101010 1 changed: 10 step 59 1100101010101101111111011001010101010111 source: 101011 1 changed: 1 step 60 1100101011101101111111011001010101010111 source: 101100 1 changed: 100 step 61 1100101100101101111111011001010101010111 source: 101101 1 changed: 1 step 62 1100101101101101111111011001010101010111 source: 101110 1 changed: 10 step 63 1100101110101101111111011001010101010111 source: 101111 1 changed: 1 step 64 1100101111101101111111011001010101010111 source: 110000 1 changed: 10000 step 65 1100110000101101111111011001010101010111 source: 110001 1 changed: 1 step 66 1100110001101101111111011001010101010111 source: 110010 1 changed: 10 step 67 1100110010101101111111011001010101010111 source: 110011 1 changed: 1 step 68 1100110011101101111111011001010101010111 source: 110100 1 changed: 100 step 69 1100110100101101111111011001010101010111 source: 110101 1 changed: 1 step 70 1100110101101101111111011001010101010111 source: 110110 1 changed: 10 step 71 1100110110101101111111011001010101010111 source: 110111 1 changed: 1 step 72 1100110111101101111111011001010101010111 source: 111000 1 changed: 1000 step 73 1100111000101101111111011001010101010111 source: 111001 1 changed: 1 step 74 1100111001101101111111011001010101010111 source: 111010 1 changed: 10 step 75 1100111010101101111111011001010101010111 source: 111011 1 changed: 1 step 76 1100111011101101111111011001010101010111 source: 111100 1 changed: 100 step 77 1100111100101101111111011001010101010111 source: 111101 1 changed: 1 step 78 1100111101101101111111011001010101010111 source: 111110 1 changed: 10 step 79 1100111110101101111111011001010101010111 source: 111111 0 changed: 1 0 step 80 1100111111101101011111011001010101010111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100111111011001010101010111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100111111011001010101010111 source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 83 1101000000101100111111011001010101011011 source: 0 changed: 0 step 84 1100000000101100111111011001010101011011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 85 1101000000101100110001011001010101011011 source: 0 changed: 0 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails O was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 7, total passes 0 Main menu Thu Jun 29 15:58:43 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 15:58:46 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 1110000000101100110000000111000000000111 step 2 1100000000101100110000000111000000000111 step 3 1101000000101100111000000111000000000111 step 4 1100000000101100111000000111000000000111 step 5 1101000000101100111100000111000000000111 step 6 1100000000101100111100000111000000000111 step 7 1101000000101100111110000111000000000111 step 8 1100000000101100111110000111000000000111 step 9 1100000000101100111111000111000000000111 step 10 1100000000101101111111000111000000000111 step 11 1100000000101101111111000111010101010111 step 12 1100111111101101011111010011010101010111 step 13 1100111111101101011111010001010101010111 step 14 1100000000101101111111011001010101010111 step 15 1100000000001101011111011001010101010111 step 16 1100000000101101111111011001010101010111 step 17 1100000000101101111111011001010101010111 step 18 1100000001101101111111011001010101010111 step 19 1100000010101101111111011001010101010111 step 20 1100000011101101111111011001010101010111 step 21 1100000100101101111111011001010101010111 step 22 1100000101101101111111011001010101010111 step 23 1100000110101101111111011001010101010111 step 24 1100000111101101111111011001010101010111 step 25 1100001000101101111111011001010101010111 step 26 1100001001101101111111011001010101010111 step 27 1100001010101101111111011001010101010111 step 28 1100001011101101111111011001010101010111 step 29 1100001100101101111111011001010101010111 step 30 1100001101101101111111011001010101010111 step 31 1100001110101101111111011001010101010111 step 32 1100001111101101111111011001010101010111 step 33 1100010000101101111111011001010101010111 step 34 1100010001101101111111011001010101010111 step 35 1100010010101101111111011001010101010111 step 36 1100010011101101111111011001010101010111 step 37 1100010100101101111111011001010101010111 step 38 1100010101101101111111011001010101010111 step 39 1100010110101101111111011001010101010111 step 40 1100010111101101111111011001010101010111 step 41 1100011000101101111111011001010101010111 step 42 1100011001101101111111011001010101010111 step 43 1100011010101101111111011001010101010111 step 44 1100011011101101111111011001010101010111 step 45 1100011100101101111111011001010101010111 step 46 1100011101101101111111011001010101010111 step 47 1100011110101101111111011001010101010111 step 48 1100011111101101111111011001010101010111 step 49 1100100000101101111111011001010101010111 step 50 1100100001101101111111011001010101010111 step 51 1100100010101101111111011001010101010111 step 52 1100100011101101111111011001010101010111 step 53 1100100100101101111111011001010101010111 step 54 1100100101101101111111011001010101010111 step 55 1100100110101101111111011001010101010111 step 56 1100100111101101111111011001010101010111 step 57 1100101000101101111111011001010101010111 step 58 1100101001101101111111011001010101010111 step 59 1100101010101101111111011001010101010111 step 60 1100101011101101111111011001010101010111 step 61 1100101100101101111111011001010101010111 step 62 1100101101101101111111011001010101010111 step 63 1100101110101101111111011001010101010111 step 64 1100101111101101111111011001010101010111 step 65 1100110000101101111111011001010101010111 step 66 1100110001101101111111011001010101010111 step 67 1100110010101101111111011001010101010111 step 68 1100110011101101111111011001010101010111 step 69 1100110100101101111111011001010101010111 step 70 1100110101101101111111011001010101010111 step 71 1100110110101101111111011001010101010111 step 72 1100110111101101111111011001010101010111 step 73 1100111000101101111111011001010101010111 step 74 1100111001101101111111011001010101010111 step 75 1100111010101101111111011001010101010111 step 76 1100111011101101111111011001010101010111 step 77 1100111100101101111111011001010101010111 step 78 1100111101101101111111011001010101010111 step 79 1100111110101101111111011001010101010111 step 80 1100111111101101011111011001010101010111 step 81 1100111111101100111111011001010101010111 step 82 1100000000101100111111011001010101010111 step 83 1101000000101100111111011001010101011011 step 84 1100000000101100111111011001010101011011 step 85 1101000000101100110001011001010101011011 step 86 1100000000101100110001011001010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 10 1 step 87 1101000000101100110001101101010101011011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 88 1101000000101100110001100101010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 89 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 90 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 91 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 92 1100000000101100110001100111010101011011 fail ^ step 93 1101000000101100110001000111010101011011 step 94 1100000000101100110001000111010101011011 step 95 1101000000101100110001000111010101011011 step 96 1100000000101100110001000111010101011011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 1 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ step 101 1101000000101100110001000111010101011011 step 102 1100000000101100110001000111010101011011 step 103 1101000000101100110001000111010101011011 step 104 1100000000101100110001000111010101011011 step 105 1101000000101100110001000111010101011111 step 106 1100000000101100110001000111010101011111 step 107 1101000000101100110001000111010101011111 step 108 1100000000101100110001000111010101011111 step 109 1101000000101100110001000111010101011011 step 110 1100000000101100110001000111010101011011 step 111 1101000000101100110001000111010101011011 step 112 1100000000101100110001000111010101011011 step 113 1101000000101100110001000111010101011111 step 114 1100000000101100110001000111010101011111 step 115 1101000000101100110001000111010101011111 step 116 1100000000101100110001000111010101011111 step 117 1101000000101100110001000111010101011011 step 118 1100000000101100110001000111010101011011 step 119 1101000000101100110001000111010101011011 step 120 1100000000101100110001000111010101011011 step 121 1101000000101000110001000111010101010111 step 122 1100000000101000110001000111010101010111 step 123 1101000000101000111001000111010101010111 step 124 1100000000101000111001000111010101010111 step 125 1101000000101000111101000111010101010111 step 126 1100000000101000111101000111010101010111 step 127 1101000000101000111111000111010101010111 step 128 1101000000101000111111000111010101010111 step 129 1100000000101000111111000111010101010111 step 130 1101000000101000111111000111010101010111 step 131 1100000000101000111111000111010101010111 step 132 1100111111101000111111000111010101010111 step 133 1100111111110000111111000111010101010111 step 134 1100111111101000111111000111010101010111 step 135 1100000000101000111111000111010101010111 step 136 1100000000111000111111000111010101010111 step 137 1100000000101000111111000111010101010111 step 138 1100111111101000111111000111010101010111 step 139 1100111111110000111111000111010101010111 step 140 1100111111111110111111000111010101010111 step 141 1100111111111100111111000111010101010111 step 142 1100111111101100111111000111010101010111 step 143 1100000000101100111111000111010101010111 step 144 1100000000101100111111000111010101010111 step 145 1100000000101100111111000111101010100111 step 146 1100111111101100111111000111101010100111 step 147 1100111111101101011111110011101010100111 step 148 1100111111101101011111111011101010100111 step 149 1100111111101101011111111001101010100111 step 150 1100111111101100111111111001101010100111 step 151 1100000000101100111111111001101010100111 step 152 1101000000101100111111111001101010101011 step 153 1100000000101100111111111001101010101011 step 154 1101000000101100110001111001101010101011 step 155 1100000000101100110001111001101010101011 step 156 1101000000101100110001001101101010101011 step 157 1101000000101100110001000101101010101011 step 158 1101000000101100110001000111101010101011 step 159 1100000000101100110001000111101010101011 step 160 1101000000101100110001000111101010101011 step 161 1100000000101100110001000111101010101011 step 162 1101000000101100110001100111101010101111 step 163 1100000000101100110001100111101010101111 step 164 1101000000101100110001100111101010101111 step 165 1100000000101100110001100111101010101111 step 166 1101000000101100110001100111101010101011 step 167 1100000000101100110001100111101010101011 step 168 1101000000101100110001100111101010101011 step 169 1100000000101100110001100111101010101011 step 170 1101000000101100110001000111101010101111 step 171 1100000000101100110001000111101010101111 step 172 1101000000101100110001000111101010101111 step 173 1100000000101100110001000111101010101111 step 174 1101000000101100110001000111101010101011 step 175 1100000000101100110001000111101010101011 step 176 1101000000101100110001000111101010101011 step 177 1100000000101100110001000111101010101011 step 178 1101000000101100110001000111101010101111 step 179 1100000000101100110001000111101010101111 step 180 1101000000101100110001000111101010101111 step 181 1100000000101100110001000111101010101111 step 182 1101000000101100110001000111101010101011 step 183 1100000000101100110001000111101010101011 step 184 1101000000101100110001000111101010101011 step 185 1100000000101100110001000111101010101011 step 186 1101000000101100110001000111101010101111 step 187 1100000000101100110001000111101010101111 step 188 1101000000101100110001000111101010101111 step 189 1100000000101100110001000111101010101111 step 190 1101000000101000110001000111101010100111 step 191 1100000000101000110001000111101010100111 step 192 1101000000101000111001000111101010100111 step 193 1100000000101000111001000111101010100111 step 194 1101000000101000111101000111101010100111 step 195 1100000000101000111101000111101010100111 step 196 1101000000101000111111000111101010100111 step 197 1101000000101000111111000111101010100111 step 198 1100000000101000111111000111101010100111 step 199 1101000000101000111111000111101010100111 step 200 1100000000101000111111000111101010100111 step 201 1100111111101000111111000111101010100111 step 202 1100111111110000111111000111101010100111 step 203 1100111111101000111111000111101010100111 step 204 1100000000101000111111000111101010100111 step 205 1100000000111000111111000111101010100111 step 206 1100000000101000111111000111101010100111 step 207 1100111111101000111111000111101010100111 step 208 1100111111110000111111000111101010100111 step 209 1100111111111110111111000111101010100111 step 210 1100111111111100111111000111101010100111 step 211 1100111111101100111111000111101010100111 step 212 1100000000101100111111000111101010100111 step 213 1100000000101100111111000111010101010111 step 214 1100000000101100111111000111000000000111 step 215 1100111111101100111111000111000000000111 step 216 1100111111101101011111010011000000000111 step 217 1100111111101101011111011011000000000111 step 218 1100111111101101011111011001000000000111 step 219 1100111111101100111111011001000000000111 step 220 1100000000101100111111011001000000000111 step 221 1101000000101100111111011001000000001011 step 222 1100000000101100111111011001000000001011 step 223 1101000000101100110001011001000000001011 step 224 1100000000101100110001011001000000001011 step 225 1101000000101100110001001101000000001011 step 226 1101000000101100110001000101000000001011 step 227 1101000000101100110001000111000000001011 step 228 1100000000101100110001000111000000001011 step 229 1101000000101100110001000111000000001011 step 230 1100000000101100110001000111000000001011 step 231 1101000000101100110001000111000000001011 step 232 1100000000101100110001000111000000001011 step 233 1101000000101100110001000111000000001011 step 234 1100000000101100110001000111000000001011 step 235 1101000000101100110001100111000000001011 step 236 1100000000101100110001100111000000001011 step 237 1101000000101100110001100111000000001011 step 238 1100000000101100110001100111000000001011 step 239 1101000000101100110001000111000000001011 step 240 1100000000101100110001000111000000001011 step 241 1101000000101100110001000111000000001011 step 242 1100000000101100110001000111000000001011 step 243 1101000000101100110001000111000000001011 step 244 1100000000101100110001000111000000001011 step 245 1101000000101100110001000111000000001011 step 246 1100000000101100110001000111000000001011 step 247 1101000000101100110001000111000000001011 step 248 1100000000101100110001000111000000001011 step 249 1101000000101100110001000111000000001011 step 250 1100000000101100110001000111000000001011 step 251 1101000000101100110001000111000000001011 step 252 1100000000101100110001000111000000001011 step 253 1101000000101100110001000111000000001011 step 254 1100000000101100110001000111000000001011 step 255 1101000000101100110001000111000000001011 step 256 1100000000101100110001000111000000001011 step 257 1101000000101100110001000111000000001011 step 258 1100000000101100110001000111000000001011 step 259 1101000000101000110001000111000000000111 step 260 1100000000101000110001000111000000000111 step 261 1101000000101000111001000111000000000111 step 262 1100000000101000111001000111000000000111 step 263 1101000000101000111101000111000000000111 step 264 1100000000101000111101000111000000000111 step 265 1101000000101000111111000111000000000111 step 266 1101000000101000111111000111000000000111 step 267 1100000000101000111111000111000000000111 step 268 1101000000101000111111000111000000000111 step 269 1100000000101000111111000111000000000111 step 270 1100111111101000111111000111000000000111 step 271 1100111111110000111111000111000000000111 step 272 1100111111101000111111000111000000000111 step 273 1100000000101000111111000111000000000111 step 274 1100000000111000111111000111000000000111 step 275 1100000000101000111111000111000000000111 step 276 1100111111101000111111000111000000000111 step 277 1100111111110000111111000111000000000111 step 278 1100111111111110111111000111000000000111 step 279 1100111111111100111111000111000000000111 step 280 1100111111101100111111000111000000000111 step 281 1100000000101100111111000111000000000111 step 282 1100000000101100111111000111010101010111 step 283 1100000000101100111111000111111111110111 step 284 1100111111101100111111000111111111110111 step 285 1100111111101101011111110011111111110111 step 286 1100111111101101011111111011111111110111 step 287 1100111111101101011111111001111111110111 step 288 1100111111101100111111111001111111110111 step 289 1100000000101100111111111001111111110111 step 290 1101000000101100111111111001111111111011 step 291 1100000000101100111111111001111111111011 step 292 1101000000101100110001111001111111111011 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ step 300 1101000000101100110001100111111111111111 step 301 1100000000101100110001100111111111111111 step 302 1101000000101100110001100111111111111111 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ step 308 1101000000101100110001000111111111111111 step 309 1100000000101100110001000111111111111111 step 310 1101000000101100110001000111111111111111 step 311 1100000000101100110001000111111111111111 step 312 1101000000101100110001000111111111111111 step 313 1100000000101100110001000111111111111111 step 314 1101000000101100110001000111111111111111 step 315 1100000000101100110001000111111111111111 step 316 1101000000101100110001000111111111111111 step 317 1100000000101100110001000111111111111111 step 318 1101000000101100110001000111111111111111 step 319 1100000000101100110001000111111111111111 step 320 1101000000101100110001000111111111111111 step 321 1100000000101100110001000111111111111111 step 322 1101000000101100110001000111111111111111 step 323 1100000000101100110001000111111111111111 step 324 1101000000101100110001000111111111111111 step 325 1100000000101100110001000111111111111111 step 326 1101000000101100110001000111111111111111 step 327 1100000000101100110001000111111111111111 step 328 1101000000101000110001000111111111110111 step 329 1100000000101000110001000111111111110111 step 330 1101000000101000111001000111111111110111 step 331 1100000000101000111001000111111111110111 step 332 1101000000101000111101000111111111110111 step 333 1100000000101000111101000111111111110111 step 334 1101000000101000111111000111111111110111 step 335 1101000000101000111111000111111111110111 step 336 1100000000101000111111000111111111110111 step 337 1101000000101000111111000111111111110111 step 338 1100000000101000111111000111111111110111 step 339 1100111111101000111111000111111111110111 step 340 1100111111110000111111000111111111110111 step 341 1100111111101000111111000111111111110111 step 342 1100000000101000111111000111111111110111 step 343 1100000000111000111111000111111111110111 step 344 1100000000101000111111000111111111110111 step 345 1100111111101000111111000111111111110111 step 346 1100111111110000111111000111111111110111 step 347 1100111111111110111111000111111111110111 step 348 1100111111111100111111000111111111110111 step 349 1100111111101100111111000111111111110111 step 350 1100000000101100111111000111111111110111 step 351 1100000000101100111111000111010101010111 step 352 1100000000101100111111000111010101010110 step 353 1100000000101100111111000111010101010111 test 1: *** FAIL *************************** 20 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail O all fails O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvv vvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 000 11 0 step 12 1100111111101101010001110011010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101010001110001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101010001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 1 step 16 1100000000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000001 1 changed: 1 step 18 1100000001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000010 1 changed: 10 step 19 1100000010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000011 1 changed: 1 step 20 1100000011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000100 1 changed: 100 step 21 1100000100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000101 1 changed: 1 step 22 1100000101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000110 1 changed: 10 step 23 1100000110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000111 1 changed: 1 step 24 1100000111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001000 1 changed: 1000 step 25 1100001000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001001 1 changed: 1 step 26 1100001001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001010 1 changed: 10 step 27 1100001010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001011 1 changed: 1 step 28 1100001011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001100 1 changed: 100 step 29 1100001100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001101 1 changed: 1 step 30 1100001101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001110 1 changed: 10 step 31 1100001110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001111 1 changed: 1 step 32 1100001111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010000 1 changed: 10000 step 33 1100010000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010001 1 changed: 1 step 34 1100010001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010010 1 changed: 10 step 35 1100010010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010011 1 changed: 1 step 36 1100010011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010100 1 changed: 100 step 37 1100010100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010101 1 changed: 1 step 38 1100010101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010110 1 changed: 10 step 39 1100010110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010111 1 changed: 1 step 40 1100010111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011000 1 changed: 1000 step 41 1100011000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011001 1 changed: 1 step 42 1100011001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011010 1 changed: 10 step 43 1100011010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011011 1 changed: 1 step 44 1100011011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011100 1 changed: 100 step 45 1100011100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011101 1 changed: 1 step 46 1100011101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011110 1 changed: 10 step 47 1100011110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011111 1 changed: 1 step 48 1100011111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100000 1 changed: 100000 step 49 1100100000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100001 1 changed: 1 step 50 1100100001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100010 1 changed: 10 step 51 1100100010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100011 1 changed: 1 step 52 1100100011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100100 1 changed: 100 step 53 1100100100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100101 1 changed: 1 step 54 1100100101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100110 1 changed: 10 step 55 1100100110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100111 1 changed: 1 step 56 1100100111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101000 1 changed: 1000 step 57 1100101000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101001 1 changed: 1 step 58 1100101001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101010 1 changed: 10 step 59 1100101010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101011 1 changed: 1 step 60 1100101011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101100 1 changed: 100 step 61 1100101100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101101 1 changed: 1 step 62 1100101101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101110 1 changed: 10 step 63 1100101110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101111 1 changed: 1 step 64 1100101111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110000 1 changed: 10000 step 65 1100110000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110001 1 changed: 1 step 66 1100110001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110010 1 changed: 10 step 67 1100110010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110011 1 changed: 1 step 68 1100110011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110100 1 changed: 100 step 69 1100110100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110101 1 changed: 1 step 70 1100110101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110110 1 changed: 10 step 71 1100110110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110111 1 changed: 1 step 72 1100110111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111000 1 changed: 1000 step 73 1100111000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111001 1 changed: 1 step 74 1100111001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111010 1 changed: 10 step 75 1100111010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111011 1 changed: 1 step 76 1100111011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111100 1 changed: 100 step 77 1100111100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111101 1 changed: 1 step 78 1100111101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111110 1 changed: 10 step 79 1100111110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111111 0 changed: 1 0 step 80 1100111111101101010001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 1 10 step 83 1101000000101100111001111001010101011011 fail ^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 84 1100000000101100111001111001010101011011 fail ^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 0 step 85 1101000000101100110001111001010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 86 1100000000101100110001111001010101011011 fail ^ source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 1 step 87 1101000000101100110001101101010101011111 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011111 source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011111 source: 0 changed: 0 step 90 1100000000101100110001100111010101011111 source: 1 changed: 1 step 91 1101000000101100110001100111010101011111 source: 0 changed: 0 step 92 1100000000101100110001100111010101011111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 94 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 95 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 96 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 0 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 1 step 101 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 102 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 103 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 104 1100000000101100110001000111010101011111 fail ^ source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 109 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 110 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 111 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 112 1100000000101100110001000111010101011111 fail ^ source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 2: *** FAIL *************************** 101 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail OOO O O all fails OOO O O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 000 11 0 step 12 1100111111101101010001110011010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; (ENABLE-N) is LO so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 13 1100111111101101010001110001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove DEVICE ADDRESS, LOAD BUFFER STROBE-N goes HI source: ; since (ENABLE) is HI, set (CHARACTER LOADED) (normal 8 BIT TX) source: 000000 1 1 changed: 000000 1 1 step 14 1100000000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; toggle (FORCE SELECT-N), LOAD BUFFER STROBE-N goes LO source: 0 0 changed: 0 0 step 15 1100000000001101010001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 1 step 16 1100000000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; test all DEVICE ADDRESS combinations source: 000000 1 changed: step 17 1100000000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000001 1 changed: 1 step 18 1100000001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000010 1 changed: 10 step 19 1100000010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000011 1 changed: 1 step 20 1100000011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000100 1 changed: 100 step 21 1100000100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000101 1 changed: 1 step 22 1100000101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000110 1 changed: 10 step 23 1100000110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 000111 1 changed: 1 step 24 1100000111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001000 1 changed: 1000 step 25 1100001000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001001 1 changed: 1 step 26 1100001001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001010 1 changed: 10 step 27 1100001010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001011 1 changed: 1 step 28 1100001011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001100 1 changed: 100 step 29 1100001100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001101 1 changed: 1 step 30 1100001101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001110 1 changed: 10 step 31 1100001110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 001111 1 changed: 1 step 32 1100001111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010000 1 changed: 10000 step 33 1100010000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010001 1 changed: 1 step 34 1100010001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010010 1 changed: 10 step 35 1100010010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010011 1 changed: 1 step 36 1100010011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010100 1 changed: 100 step 37 1100010100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010101 1 changed: 1 step 38 1100010101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010110 1 changed: 10 step 39 1100010110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 010111 1 changed: 1 step 40 1100010111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011000 1 changed: 1000 step 41 1100011000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011001 1 changed: 1 step 42 1100011001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011010 1 changed: 10 step 43 1100011010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011011 1 changed: 1 step 44 1100011011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011100 1 changed: 100 step 45 1100011100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011101 1 changed: 1 step 46 1100011101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011110 1 changed: 10 step 47 1100011110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 011111 1 changed: 1 step 48 1100011111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100000 1 changed: 100000 step 49 1100100000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100001 1 changed: 1 step 50 1100100001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100010 1 changed: 10 step 51 1100100010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100011 1 changed: 1 step 52 1100100011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100100 1 changed: 100 step 53 1100100100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100101 1 changed: 1 step 54 1100100101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100110 1 changed: 10 step 55 1100100110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 100111 1 changed: 1 step 56 1100100111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101000 1 changed: 1000 step 57 1100101000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101001 1 changed: 1 step 58 1100101001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101010 1 changed: 10 step 59 1100101010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101011 1 changed: 1 step 60 1100101011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101100 1 changed: 100 step 61 1100101100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101101 1 changed: 1 step 62 1100101101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101110 1 changed: 10 step 63 1100101110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 101111 1 changed: 1 step 64 1100101111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110000 1 changed: 10000 step 65 1100110000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110001 1 changed: 1 step 66 1100110001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110010 1 changed: 10 step 67 1100110010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110011 1 changed: 1 step 68 1100110011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110100 1 changed: 100 step 69 1100110100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110101 1 changed: 1 step 70 1100110101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110110 1 changed: 10 step 71 1100110110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 110111 1 changed: 1 step 72 1100110111101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111000 1 changed: 1000 step 73 1100111000101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111001 1 changed: 1 step 74 1100111001101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111010 1 changed: 10 step 75 1100111010101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111011 1 changed: 1 step 76 1100111011101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111100 1 changed: 100 step 77 1100111100101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111101 1 changed: 1 step 78 1100111101101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111110 1 changed: 10 step 79 1100111110101101110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 111111 0 changed: 1 0 step 80 1100111111101101010001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 81 1100111111101100110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 82 1100000000101100110001111001010101010111 fail ^^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; source: ; send the 0x55 character source: ; source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 1 10 step 83 1101000000101100111001111001010101011011 fail ^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 84 1100000000101100111001111001010101011011 fail ^^ ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 0 step 85 1101000000101100110001111001010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 86 1100000000101100110001111001010101011011 fail ^ source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 1 step 87 1101000000101100110001101101010101011111 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 88 1101000000101100110001100101010101011111 source: ; (ENABLE-N) is HI so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 89 1101000000101100110001100111010101011111 source: 0 changed: 0 step 90 1100000000101100110001100111010101011111 source: 1 changed: 1 step 91 1101000000101100110001100111010101011111 source: 0 changed: 0 step 92 1100000000101100110001100111010101011111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 0 step 93 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 94 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 95 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 96 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) shifts source: 1 1 1 changed: 1 1 0 step 97 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 98 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 99 1101000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 100 1100000000101100110001100111010101011011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 4 (AC8) goes to LINE source: 1 0 0 changed: 1 0 1 step 101 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 102 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 103 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 104 1100000000101100110001000111010101011111 fail ^ source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 1 changed: 1 step 105 1101000000101100110001000111010101011111 source: 0 changed: 0 step 106 1100000000101100110001000111010101011111 source: 1 changed: 1 step 107 1101000000101100110001000111010101011111 source: 0 changed: 0 step 108 1100000000101100110001000111010101011111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 109 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 110 1100000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 111 1101000000101100110001000111010101011111 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 112 1100000000101100110001000111010101011111 fail ^ source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 113 1101000000101100110001000111010101011111 source: 0 changed: 0 step 114 1100000000101100110001000111010101011111 source: 1 changed: 1 step 115 1101000000101100110001000111010101011111 source: 0 changed: 0 step 116 1100000000101100110001000111010101011111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 0 step 117 1101000000101100110001000111010101011011 source: 0 changed: 0 step 118 1100000000101100110001000111010101011011 source: 1 changed: 1 step 119 1101000000101100110001000111010101011011 source: 0 changed: 0 step 120 1100000000101100110001000111010101011011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 121 1101000000101000110001000111010101010111 source: 0 changed: 0 step 122 1100000000101000110001000111010101010111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 123 1101000000101000111001000111010101010111 source: 0 changed: 0 step 124 1100000000101000111001000111010101010111 source: 1 1 changed: 1 1 step 125 1101000000101000111101000111010101010111 source: 0 changed: 0 step 126 1100000000101000111101000111010101010111 source: 1 1 changed: 1 1 step 127 1101000000101000111111000111010101010111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 128 1101000000101000111111000111010101010111 source: 0 changed: 0 step 129 1100000000101000111111000111010101010111 source: 1 changed: 1 step 130 1101000000101000111111000111010101010111 source: 0 changed: 0 step 131 1100000000101000111111000111010101010111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 132 1100111111101000111111000111010101010111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 133 1100111111110000111111000111010101010111 source: 01 changed: 01 step 134 1100111111101000111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 135 1100000000101000111111000111010101010111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 136 1100000000111000111111000111010101010111 source: 0 changed: 0 step 137 1100000000101000111111000111010101010111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 138 1100111111101000111111000111010101010111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 139 1100111111110000111111000111010101010111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 140 1100111111111110111111000111010101010111 source: 0 changed: 0 step 141 1100111111111100111111000111010101010111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 142 1100111111101100111111000111010101010111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 143 1100000000101100111111000111010101010111 source: 11000000001011001111110001110101010101X1 changed: step 144 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xAA source: ; source: ; source: ; set up to load ENABLE/0xAA (alternating ones) source: 110101010 changed: 10101010 step 145 1100000000101100111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 146 1100111111101100111111000111101010100111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 147 1100111111101101011111110011101010100111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 148 1100111111101101011111111011101010100111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 149 1100111111101101011111111001101010100111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 150 1100111111101100111111111001101010100111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 151 1100000000101100111111111001101010100111 source: ; source: ; shift out the 0xAA character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 152 1101000000101100111111111001101010101011 source: 0 changed: 0 step 153 1100000000101100111111111001101010101011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 154 1101000000101100110001111001101010101011 source: 0 changed: 0 step 155 1100000000101100110001111001101010101011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 00 1 step 156 1101000000101100110001001101101010101011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 157 1101000000101100110001000101101010101011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 158 1101000000101100110001000111101010101011 source: 0 changed: 0 step 159 1100000000101100110001000111101010101011 source: 1 changed: 1 step 160 1101000000101100110001000111101010101011 source: 0 changed: 0 step 161 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 1 step 162 1101000000101100110001100111101010101111 source: 0 changed: 0 step 163 1100000000101100110001100111101010101111 source: 1 changed: 1 step 164 1101000000101100110001100111101010101111 source: 0 changed: 0 step 165 1100000000101100110001100111101010101111 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 0 step 166 1101000000101100110001100111101010101011 source: 0 changed: 0 step 167 1100000000101100110001100111101010101011 source: 1 changed: 1 step 168 1101000000101100110001100111101010101011 source: 0 changed: 0 step 169 1100000000101100110001100111101010101011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 170 1101000000101100110001000111101010101111 source: 0 changed: 0 step 171 1100000000101100110001000111101010101111 source: 1 changed: 1 step 172 1101000000101100110001000111101010101111 source: 0 changed: 0 step 173 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 0 step 174 1101000000101100110001000111101010101011 source: 0 changed: 0 step 175 1100000000101100110001000111101010101011 source: 1 changed: 1 step 176 1101000000101100110001000111101010101011 source: 0 changed: 0 step 177 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 1 step 178 1101000000101100110001000111101010101111 source: 0 changed: 0 step 179 1100000000101100110001000111101010101111 source: 1 changed: 1 step 180 1101000000101100110001000111101010101111 source: 0 changed: 0 step 181 1100000000101100110001000111101010101111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 0 step 182 1101000000101100110001000111101010101011 source: 0 changed: 0 step 183 1100000000101100110001000111101010101011 source: 1 changed: 1 step 184 1101000000101100110001000111101010101011 source: 0 changed: 0 step 185 1100000000101100110001000111101010101011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 1 step 186 1101000000101100110001000111101010101111 source: 0 changed: 0 step 187 1100000000101100110001000111101010101111 source: 1 changed: 1 step 188 1101000000101100110001000111101010101111 source: 0 changed: 0 step 189 1100000000101100110001000111101010101111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 190 1101000000101000110001000111101010100111 source: 0 changed: 0 step 191 1100000000101000110001000111101010100111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 192 1101000000101000111001000111101010100111 source: 0 changed: 0 step 193 1100000000101000111001000111101010100111 source: 1 1 changed: 1 1 step 194 1101000000101000111101000111101010100111 source: 0 changed: 0 step 195 1100000000101000111101000111101010100111 source: 1 1 changed: 1 1 step 196 1101000000101000111111000111101010100111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 197 1101000000101000111111000111101010100111 source: 0 changed: 0 step 198 1100000000101000111111000111101010100111 source: 1 changed: 1 step 199 1101000000101000111111000111101010100111 source: 0 changed: 0 step 200 1100000000101000111111000111101010100111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 201 1100111111101000111111000111101010100111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 202 1100111111110000111111000111101010100111 source: 01 changed: 01 step 203 1100111111101000111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 204 1100000000101000111111000111101010100111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 205 1100000000111000111111000111101010100111 source: 0 changed: 0 step 206 1100000000101000111111000111101010100111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 207 1100111111101000111111000111101010100111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 208 1100111111110000111111000111101010100111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 209 1100111111111110111111000111101010100111 source: 0 changed: 0 step 210 1100111111111100111111000111101010100111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 211 1100111111101100111111000111101010100111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 212 1100000000101100111111000111101010100111 source: 11000000001011001111110001110101010101X1 changed: 01010101 step 213 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0x00 source: ; source: ; source: ; set up to load ENABLE/0x00 (all zeroes) source: 100000000 changed: 0 0 0 0 step 214 1100000000101100111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 215 1100111111101100111111000111000000000111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes LO source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 01 0 changed: 10 1 0 step 216 1100111111101101011111010011000000000111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 217 1100111111101101011111011011000000000111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 218 1100111111101101011111011001000000000111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 219 1100111111101100111111011001000000000111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 220 1100000000101100111111011001000000000111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 221 1101000000101100111111011001000000001011 source: 0 changed: 0 step 222 1100000000101100111111011001000000001011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 223 1101000000101100110001011001000000001011 source: 0 changed: 0 step 224 1100000000101100110001011001000000001011 source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 00 1 0 changed: 1 0 1 step 225 1101000000101100110001001101000000001011 source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 226 1101000000101100110001000101000000001011 source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 227 1101000000101100110001000111000000001011 source: 0 changed: 0 step 228 1100000000101100110001000111000000001011 source: 1 changed: 1 step 229 1101000000101100110001000111000000001011 source: 0 changed: 0 step 230 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 0 0 changed: 1 step 231 1101000000101100110001000111000000001011 source: 0 changed: 0 step 232 1100000000101100110001000111000000001011 source: 1 changed: 1 step 233 1101000000101100110001000111000000001011 source: 0 changed: 0 step 234 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 0 changed: 1 1 step 235 1101000000101100110001100111000000001011 source: 0 changed: 0 step 236 1100000000101100110001100111000000001011 source: 1 changed: 1 step 237 1101000000101100110001100111000000001011 source: 0 changed: 0 step 238 1100000000101100110001100111000000001011 source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 0 changed: 1 0 step 239 1101000000101100110001000111000000001011 source: 0 changed: 0 step 240 1100000000101100110001000111000000001011 source: 1 changed: 1 step 241 1101000000101100110001000111000000001011 source: 0 changed: 0 step 242 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 0 0 changed: 1 step 243 1101000000101100110001000111000000001011 source: 0 changed: 0 step 244 1100000000101100110001000111000000001011 source: 1 changed: 1 step 245 1101000000101100110001000111000000001011 source: 0 changed: 0 step 246 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 0 changed: 1 step 247 1101000000101100110001000111000000001011 source: 0 changed: 0 step 248 1100000000101100110001000111000000001011 source: 1 changed: 1 step 249 1101000000101100110001000111000000001011 source: 0 changed: 0 step 250 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 0 changed: 1 step 251 1101000000101100110001000111000000001011 source: 0 changed: 0 step 252 1100000000101100110001000111000000001011 source: 1 changed: 1 step 253 1101000000101100110001000111000000001011 source: 0 changed: 0 step 254 1100000000101100110001000111000000001011 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 0 changed: 1 step 255 1101000000101100110001000111000000001011 source: 0 changed: 0 step 256 1100000000101100110001000111000000001011 source: 1 changed: 1 step 257 1101000000101100110001000111000000001011 source: 0 changed: 0 step 258 1100000000101100110001000111000000001011 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 01 step 259 1101000000101000110001000111000000000111 source: 0 changed: 0 step 260 1100000000101000110001000111000000000111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 261 1101000000101000111001000111000000000111 source: 0 changed: 0 step 262 1100000000101000111001000111000000000111 source: 1 1 changed: 1 1 step 263 1101000000101000111101000111000000000111 source: 0 changed: 0 step 264 1100000000101000111101000111000000000111 source: 1 1 changed: 1 1 step 265 1101000000101000111111000111000000000111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 266 1101000000101000111111000111000000000111 source: 0 changed: 0 step 267 1100000000101000111111000111000000000111 source: 1 changed: 1 step 268 1101000000101000111111000111000000000111 source: 0 changed: 0 step 269 1100000000101000111111000111000000000111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 270 1100111111101000111111000111000000000111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 271 1100111111110000111111000111000000000111 source: 01 changed: 01 step 272 1100111111101000111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 273 1100000000101000111111000111000000000111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 1 changed: 1 step 274 1100000000111000111111000111000000000111 source: 0 changed: 0 step 275 1100000000101000111111000111000000000111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 276 1100111111101000111111000111000000000111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 277 1100111111110000111111000111000000000111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 278 1100111111111110111111000111000000000111 source: 0 changed: 0 step 279 1100111111111100111111000111000000000111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 280 1100111111101100111111000111000000000111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 281 1100000000101100111111000111000000000111 source: 11000000001011001111110001110101010101X1 changed: 1 1 1 1 step 282 1100000000101100111111000111010101010111 source: ; source: ; source: ; send a 0xFF source: ; source: ; source: ; set up to load ENABLE/0xFF (all ones) source: 111111111 changed: 1 1 1 1 step 283 1100000000101100111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 284 1100111111101100111111000111111111110111 source: ; turn on LOAD BUFFER (normally IOP4) source: ; LOAD BUFFER STROBE-N goes LO source: ; (BIT 6) goes HI source: ; (ENABLE) goes HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) goes LO source: 10 11 0 changed: 10 11 0 step 285 1100111111101101011111110011111111110111 source: ; (ENABLE) is HI, so set (CHARACTER LOADED) (normal 8 BIT TX) source: 1 changed: 1 step 286 1100111111101101011111111011111111110111 source: ; (ENABLE-N) is LO, so change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 0 changed: 0 step 287 1100111111101101011111111001111111110111 source: ; remove LOAD BUFFER (normally IOP4) source: 01 changed: 01 step 288 1100111111101100111111111001111111110111 source: ; remove DEVICE ADDRESS source: 000000 changed: 000000 step 289 1100000000101100111111111001111111110111 source: ; source: ; shift out the 0x00 character source: ; source: ; on first 2 X BAUD CLOCK INPUT source: ; ACTIVE is SET, causes LINE to CLEAR (i.e. START BIT). source: ; source: 1 10 changed: 1 10 step 290 1101000000101100111111111001111111111011 source: 0 changed: 0 step 291 1100000000101100111111111001111111111011 source: ; the 2nd 2 X BAUD CLOCK INPUT causes the STOP FFs to PRESET source: 1 000 changed: 1 000 step 292 1101000000101100110001111001111111111011 source: 0 changed: 0 step 293 1100000000101100110001111001111111111011 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 1 (AC11) goes to LINE source: ; (BIT 6) shifts source: ; (ENABLE) goes LO, (ENABLE-N) goes HI source: 1 10 1 1 changed: 1 0 1 step 294 1101000000101100110001101101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE) is LO, change (CHARACTER LOADED) (i.e. 8 not 5) source: 0 changed: 0 step 295 1101000000101100110001100101111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; since (ENABLE-N) is HI, change (DECODE INPUT 8) (normally connects to (ENABLE-N) source: 1 changed: 1 step 296 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 297 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 298 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 299 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 2 (AC10) goes to LINE source: 1 1 1 changed: 1 1 step 300 1101000000101100110001100111111111111111 source: 0 changed: 0 step 301 1100000000101100110001100111111111111111 source: 1 changed: 1 step 302 1101000000101100110001100111111111111111 source: 0 changed: 0 step 303 1100000000101100110001100111111111111111 SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; ORGINAL BIT 3 (AC9) goes to LINE source: ; (BIT 6) becomes original ENABLE source: 1 1 1 changed: 1 0 step 304 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 305 1100000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 changed: 1 step 306 1101000000101100110001100111111111111011 fail ^ SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 307 1100000000101100110001100111111111111011 fail ^ source: ; ORGINAL BIT 4 (AC8) goes to LINE source: ; (BIT 6) goes LO source: 1 0 1 changed: 1 0 1 step 308 1101000000101100110001000111111111111111 source: 0 changed: 0 step 309 1100000000101100110001000111111111111111 source: 1 changed: 1 step 310 1101000000101100110001000111111111111111 source: 0 changed: 0 step 311 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 5 (AC7) goes to LINE source: ; source: 1 1 changed: 1 step 312 1101000000101100110001000111111111111111 source: 0 changed: 0 step 313 1100000000101100110001000111111111111111 source: 1 changed: 1 step 314 1101000000101100110001000111111111111111 source: 0 changed: 0 step 315 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 6 (AC6) goes to LINE source: 1 1 changed: 1 step 316 1101000000101100110001000111111111111111 source: 0 changed: 0 step 317 1100000000101100110001000111111111111111 source: 1 changed: 1 step 318 1101000000101100110001000111111111111111 source: 0 changed: 0 step 319 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 7 (AC5) goes to LINE source: 1 1 changed: 1 step 320 1101000000101100110001000111111111111111 source: 0 changed: 0 step 321 1100000000101100110001000111111111111111 source: 1 changed: 1 step 322 1101000000101100110001000111111111111111 source: 0 changed: 0 step 323 1100000000101100110001000111111111111111 source: ; ORGINAL BIT 8 (AC4) goes to LINE source: 1 1 changed: 1 step 324 1101000000101100110001000111111111111111 source: 0 changed: 0 step 325 1100000000101100110001000111111111111111 source: 1 changed: 1 step 326 1101000000101100110001000111111111111111 source: 0 changed: 0 step 327 1100000000101100110001000111111111111111 source: ; ORGINAL (ENABLE) goes to LINE (STOP BITS) source: ; (ACTIVE) goes LO source: ; P.I.REQ-N (FLAG-N) goes LO...FLAG is ON source: 1 0 01 changed: 1 0 0 step 328 1101000000101000110001000111111111110111 source: 0 changed: 0 step 329 1100000000101000110001000111111111110111 source: ; STOP FFs bits start counting... source: 1 1 changed: 1 1 step 330 1101000000101000111001000111111111110111 source: 0 changed: 0 step 331 1100000000101000111001000111111111110111 source: 1 1 changed: 1 1 step 332 1101000000101000111101000111111111110111 source: 0 changed: 0 step 333 1100000000101000111101000111111111110111 source: 1 1 changed: 1 1 step 334 1101000000101000111111000111111111110111 source: ; since STOP 2-N went HI, set (STOP SELECT) (i.e. 2 STOP BITS) source: 1 changed: step 335 1101000000101000111111000111111111110111 source: 0 changed: 0 step 336 1100000000101000111111000111111111110111 source: 1 changed: 1 step 337 1101000000101000111111000111111111110111 source: 0 changed: 0 step 338 1100000000101000111111000111111111110111 source: ; source: ; try the I/O SKIP source: ; source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 339 1100111111101000111111000111111111110111 source: ; toggle I/O SKP.STROBE I/O SKP.-N pulses LO (active) source: 10 changed: 10 step 340 1100111111110000111111000111111111110111 source: 01 changed: 01 step 341 1100111111101000111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 342 1100000000101000111111000111111111110111 source: ; toggle I/O SKP.STROBE- I/O SKP.-N stays HI (inactive) source: 11 changed: 1 step 343 1100000000111000111111000111111111110111 source: 01 changed: 0 step 344 1100000000101000111111000111111111110111 source: ; turn on DEVICE ADDRESS bits source: 111111 changed: 111111 step 345 1100111111101000111111000111111111110111 source: ; set I/O SKP. STROBE, I/O SKP.-N goes LO source: 10 changed: 10 step 346 1100111111110000111111000111111111110111 source: ; clear the FLAG- pulse CLEAR FLAG 1, I/O SKP.-n goes HI source: ; P.I.REQ-N (FLAG-N) goes HI...FLAG is OFF source: 111 changed: 111 step 347 1100111111111110111111000111111111110111 source: 0 changed: 0 step 348 1100111111111100111111000111111111110111 source: ; turn off I/O SKP. STROBE source: 0 changed: 0 step 349 1100111111101100111111000111111111110111 source: ; turn off DEVICE ADDRESS bits source: 000000 changed: 000000 step 350 1100000000101100111111000111111111110111 source: 11000000001011001111110001110101010101X1 changed: 0 0 0 0 step 351 1100000000101100111111000111010101010111 source: ; source: ; test ECHO input (need to scope AV2 20MA OUTPUT) source: ; source: ; set ECHO-N lo, 20MA OUTPUT goes LO source: X0 changed: 0 step 352 1100000000101100111111000111010101010110 source: X1 changed: 1 step 353 1100000000101100111111000111010101010111 test 3: *** FAIL *************************** 101 steps failed SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI this fail OOO O O all fails OOO O O was hi 1111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v was lo 000000000000000 000000000 0000000000 0 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; set CLEAR FLAG 2-N, I/O CLEAR source: ; note: STOP FF outputs are unknown. source: ; note: 20MA output can not test (open emitter) source: 111000000010110011XXX00001110000000001X1 changed: 1 0 0 0 0 0 step 1 1110000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; remove I/O CLEAR source: 0 changed: 0 step 2 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; clock 2 X BAUD CLOCK INPUT to set STOP FFs source: 1 1 changed: 1 step 3 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 4 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 step 5 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 6 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 1 1 changed: 1 step 7 1101000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: 0 changed: 0 step 8 1100000000101100111110000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; set (STOP SELECT since all 3 STOP FFs are HI) source: 1 changed: 1 step 9 1100000000101100111111000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; test DEVICE DECODER source: ; source: ; turn on LOAD BUFFER (normally IOP4) source: 1 changed: 1 step 10 1100000000101101111111000111000000000111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; source: ; set up to load ENABLE/55h (alternating ones) source: ; source: 101010101 changed: 1 1 1 1 step 11 1100000000101101111111000111010101010111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI source: ; turn on DEVICE ADDRESS bits, LOAD BUFFER STROBE-N goes LO source: ; (ENABLE) will go HI (note: next CLOCK starts TX...) source: ; (ENABLE-N) will go LO source: 111111 0 1 0 changed: 111111 0 1 0 step 12 1100111111101101011111010011010101010111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails OOO O O was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 3, total passes 0 Main menu Thu Jun 29 16:30:54 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 16:30:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBAAAAAAABBBBAABBBBBAAAAAAAAAAAAAAAAAA LETTER JFEPEEFFHJNHJKDSRSRPNNJKKLHNPRLMUSTUDDVB SIDE 1222121222122221122112121112222222211221 DIRECTION OIIIIIIIIIIIOOIIIIOOOIOOIOIIIIIIIIIIOOOI all fails was lo 000000000000000 000000000 0000000000 0 falling vvvvvvvvvvvvvvv vvvvvvvvv vvvvvvvvvv v rising ^^^^^^^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^^ ^ was hi 1111111111111111111111111111111111111111 total fails 0, total passes 36 Main menu Thu Jun 29 16:31:05 2017 test file is: tests\m707d.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Thu Jun 29 16:38:30 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 16:38:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 52 00001100011000111000101011000010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 53 00001100011000111000101111000010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 54 00001100011000111000100111000010 fail ^^ step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 23: *** FAIL *************************** 3 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 23, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00001100011000110000110001100011 step 2 10001000010000100000110001100011 step 3 10011000010000100000110001100011 step 4 11010100010000100000110001100011 step 5 11110100010000100000110001100011 step 6 10110100010000100000110001100011 step 7 11111000010000100000110001100011 step 8 11011000010000100000110001100011 step 9 10011000010000100000110001100011 step 10 00010100011000110000110001100011 step 11 10010100010000100000110001100011 step 12 10001000010000100000110001100011 step 13 00001100011000110000110001100011 step 14 10001000010000100000110001100011 step 15 10001000110000100000110001100011 step 16 10001010101000100000110001100011 step 17 10001011101000100000110001100011 step 18 10001001101000100000110001100011 step 19 10001011110000100000110001100011 step 20 10001010110000100000110001100011 step 21 10001000110000100000110001100011 step 22 00001100101000110000110001100011 step 23 10001000101000100000110001100011 step 24 10001000010000100000110001100011 step 25 00001100011000110000110001100011 step 26 10001000010000100000110001100011 step 27 10001000010001100000110001100011 step 28 10001000010101010000110001100011 step 29 10001000010111010000110001100011 step 30 10001000010011010000110001100011 step 31 10001000010111100000110001100011 step 32 10001000010101100000110001100011 step 33 10001000010001100000110001100011 step 34 00001100011001010000110001100011 step 35 10001000010001010000110001100011 step 36 10001000010000100000110001100011 step 37 00001100011000110000110001100011 step 38 00001100011000111000100001000010 step 39 00001100011000111001100001000010 step 40 00001100011000111101010001000010 step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 52 00001100011000111000101011000010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 53 00001100011000111000101111000010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 54 00001100011000111000100111000010 fail ^^ step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 24: *** FAIL *************************** 3 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 24, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00001100011000110000110001100011 step 2 10001000010000100000110001100011 step 3 10011000010000100000110001100011 step 4 11010100010000100000110001100011 step 5 11110100010000100000110001100011 step 6 10110100010000100000110001100011 step 7 11111000010000100000110001100011 step 8 11011000010000100000110001100011 step 9 10011000010000100000110001100011 step 10 00010100011000110000110001100011 step 11 10010100010000100000110001100011 step 12 10001000010000100000110001100011 step 13 00001100011000110000110001100011 step 14 10001000010000100000110001100011 step 15 10001000110000100000110001100011 step 16 10001010101000100000110001100011 step 17 10001011101000100000110001100011 step 18 10001001101000100000110001100011 step 19 10001011110000100000110001100011 step 20 10001010110000100000110001100011 step 21 10001000110000100000110001100011 step 22 00001100101000110000110001100011 step 23 10001000101000100000110001100011 step 24 10001000010000100000110001100011 step 25 00001100011000110000110001100011 step 26 10001000010000100000110001100011 step 27 10001000010001100000110001100011 step 28 10001000010101010000110001100011 step 29 10001000010111010000110001100011 step 30 10001000010011010000110001100011 step 31 10001000010111100000110001100011 step 32 10001000010101100000110001100011 step 33 10001000010001100000110001100011 step 34 00001100011001010000110001100011 step 35 10001000010001010000110001100011 step 36 10001000010000100000110001100011 step 37 00001100011000110000110001100011 step 38 00001100011000111000100001000010 step 39 00001100011000111001100001000010 step 40 00001100011000111101010001000010 step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 52 00001100011000111000101011000010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 53 00001100011000111000101111000010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 54 00001100011000111000100111000010 fail ^^ step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 25: *** FAIL *************************** 3 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 25, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 25, total passes 0 Main menu Thu Jun 29 16:45:07 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Thu Jun 29 16:45:11 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x000D Main menu Thu Jun 29 16:57:33 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 16:57:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 108 Main menu Thu Jun 29 16:59:48 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:00:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 39 Main menu Thu Jun 29 17:00:48 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Thu Jun 29 17:01:06 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Thu Jun 29 17:02:33 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:02:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 44 Main menu Thu Jun 29 17:02:48 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Thu Jun 29 17:03:14 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:03:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 step 109 011011111011110111101111011110 step 110 011101111011110111101111011110 step 111 010111111011110111101111011110 step 112 010011111011110111101111011110 step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 step 119 111101001111110111101111011110 step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 step 122 111100001111110111101111011110 step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 step 127 111100101111110111101111011110 step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 22: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 22 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 step 5 011010000100001000010000100001 step 6 011100000100001000010000100001 step 7 010110000100001000010000100001 step 8 010010000100001000010000100001 step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 step 18 000010001100001000010000100001 step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 step 23 000010101100001000010000100001 step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 step 31 000011001100001000010000100001 step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 step 85 000010000100001000010000101101 step 86 000010000100001000010000101110 step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 step 109 011011111011110111101111011110 step 110 011101111011110111101111011110 step 111 010111111011110111101111011110 step 112 010011111011110111101111011110 step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 step 119 111101001111110111101111011110 step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 step 122 111100001111110111101111011110 step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 step 127 111100101111110111101111011110 step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 23: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 23 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 1 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 2 000110000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 3 001100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 4 001010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 011010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 6 011100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 7 010110000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 9 110000000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 10 110100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 111100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 12 111000000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 13 101010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 14 101100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 15 100110000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 16 100010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 17 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 18 000010001100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 19 000010011000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 20 000010010100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 21 000010110100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 22 000010111000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 23 000010101100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 24 000010100100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 25 000011100000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000011101000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 27 000011111000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 28 000011110000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 29 000011010100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 30 000011011000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 31 000011001100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 32 000011000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 33 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000010000100011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 35 000010000100110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 36 000010000100101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000010000101101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000010000101110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 39 000010000101011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 40 000010000101001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 41 000010000111000000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 42 000010000111010000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000010000111110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 44 000010000111100000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 45 000010000110101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 23 Main menu Thu Jun 29 17:03:38 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:03:39 2017 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 output: 0 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 4 001010000100001000010000100001 output: 1 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 5 011010000100001000010000100001 step 6 011100000100001000010000100001 output: 0 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit output is: 25 O AS1 E3-8 OUTPUT E space toggle output N next output Q quit output is: 10 O AJ2 E1-6 OUTPUT B space toggle output N next output Q quit output is: 20 O AP2 E2-6 OUTPUT D space toggle output N next output Q quit output is: 30 O AV2 E3-6 OUTPUT F space toggle output N next output Q quit output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 7 010110000100001000010000100001 step 8 010010000100001000010000100001 step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 step 18 000010001100001000010000100001 step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 step 23 000010101100001000010000100001 step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 step 31 000011001100001000010000100001 step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 36 000010000100101000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 39 000010000101011000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 46 000010000110110000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 47 000010000110011000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 step 85 000010000100001000010000101101 step 86 000010000100001000010000101110 step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 step 109 011011111011110111101111011110 step 110 011101111011110111101111011110 step 111 010111111011110111101111011110 step 112 010011111011110111101111011110 step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 step 119 111101001111110111101111011110 step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 step 122 111100001111110111101111011110 step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 step 127 111100101111110111101111011110 step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 134 111101111010110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 135 111101111010011111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 140 111101111000101111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 143 111101111001011111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit Main menu Thu Jun 29 17:05:05 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:05:06 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 114 Main menu Thu Jun 29 17:05:20 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Thu Jun 29 17:08:15 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:08:31 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Thu Jun 29 17:08:35 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:08:37 2017 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 output: 0 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 4 001010000100001000010000100001 output: 1 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 5 011010000100001000010000100001 step 6 011100000100001000010000100001 output: 0 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 7 010110000100001000010000100001 output: 1 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit step 8 010010000100001000010000100001 step 9 110000000100001000010000100001 output: 0 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit output is: 25 O AS1 E3-8 OUTPUT E space toggle output N next output Q quit Main menu Thu Jun 29 17:08:45 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:08:46 2017 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit output is: 25 O AS1 E3-8 OUTPUT E space toggle output N next output Q quit Main menu Thu Jun 29 17:08:52 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:08:53 2017 output is: 5 O AE1 E1-8 OUTPUT A space toggle output N next output Q quit output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 step 5 011010000100001000010000100001 step 6 011100000100001000010000100001 step 7 010110000100001000010000100001 step 8 010010000100001000010000100001 step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 step 18 000010001100001000010000100001 step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 step 23 000010101100001000010000100001 step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 step 31 000011001100001000010000100001 step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 36 000010000100101000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 39 000010000101011000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 46 000010000110110000010000100001 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 47 000010000110011000010000100001 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 step 85 000010000100001000010000101101 step 86 000010000100001000010000101110 step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 step 109 011011111011110111101111011110 step 110 011101111011110111101111011110 step 111 010111111011110111101111011110 step 112 010011111011110111101111011110 step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 step 119 111101001111110111101111011110 step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 step 122 111100001111110111101111011110 step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 step 127 111100101111110111101111011110 step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 134 111101111010110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 135 111101111010011111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 140 111101111000101111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 output: 0 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit step 143 111101111001011111101111011110 output: 1 output is: 15 O AL1 E2-8 OUTPUT C space toggle output N next output Q quit Main menu Thu Jun 29 17:14:54 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.tst reading test file: tests\m222.tst comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: +5v AA2, BA2 comment: GROUND AC2, AT1, BC2, BT1 comment: (ALL PINS ARE USED). comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: ; walk a 0, TAC 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 74: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 75: 1 0 1 comment: ; load TAC from tape bus (01) test 76: 10110 test 77: 0 comment: ; restore TAC 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 78: 1 0 1 comment: ; load TAC from tape bus (11) test 79: 11010 test 80: 0 comment: comment: comment: ; walk a 0, TAC 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 81: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 82: 0 1 0 comment: ; load TAC from tape bus (10) test 83: 11001 test 84: 0 comment: ; restore TAC 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 85: 1 0 1 comment: ; load TAC from tape bus (11) test 86: 11010 test 87: 0 comment: comment: comment: ; walk a 0, TB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 88: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 89: 1 0 1 comment: ; load TB from tape bus (01) test 90: 101 test 91: 0 comment: ; restore TB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 92: 1 0 1 comment: ; load TB from tape bus (11) test 93: 111 test 94: 0 comment: comment: comment: ; walk a 0, TB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 95: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 96: 0 1 0 comment: ; load TB from tape bus (10) test 97: 110 test 98: 0 comment: ; restore TB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 99: 1 0 1 comment: ; load TB from tape bus (11) test 100: 111 test 101: 0 comment: comment: comment: ; walk a 0, RWB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 102: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 103: 1 0 1 comment: ; load TB from tape bus (01) test 104: 101 test 105: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 106: 1 01 test 107: 0 comment: ; restore TB 2 and RWB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 108: 1 0 1 comment: ; load TB from tape bus (11) test 109: 111 test 110: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 111: 1 11 test 112: 0 comment: comment: comment: ; walk a 0, RWB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 113: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 114: 0 1 0 comment: ; load TB from tape bus (10) test 115: 110 test 116: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 117: 1 10 test 118: 0 comment: ; restore TB 3 and RWB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 119: 1 0 1 comment: ; load TB from tape bus (11) test 120: 111 test 121: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 122: 1 11 test 123: 0 comment: comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 124: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 125: 0 1 0 comment: ; (no change) test 126: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;********************* need to walk a one ********************** comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 127: 1 comment: ; set pin AM1 HIGH test 128: 1 comment: ; set pin AE1 HIGH test 129: 1 comment: ; set pin AM2 HIGH test 130: 1 comment: ; set pin AB2 HIGH test 131: 1 comment: ; set pin AS1 HIGH test 132: 1 comment: ; set pin BE1 HIGH test 133: 1 comment: ; set pin BM1 HIGH test 134: 1 comment: ; set pin BH1 HIGH test 135: 1 comment: ; set pin BR1 HIGH test 136: 1 comment: ; set pin BC1 HIGH test 137: 1 comment: ; set pin BJ2 HIGH test 138: 1 comment: ; set pin BJ1 HIGH test 139: 1 comment: ; set pin BK2 HIGH test 140: 1 comment: ; set pin BH2 HIGH test 141: 1 comment: ; set pin BP2 HIGH test 142: 1 comment: ; set pin BN2 HIGH test 143: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 144: 1 0 0 11 test 145: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 146: 1 0 0 11 test 147: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 148: 1 0 0 11 test 149: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 150: 1 0 0 11 test 151: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 152: 1 0 0 11 test 153: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 154: 1 0 0 11 test 155: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 156: 1 0 1 test 157: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 158: 1 0 1 test 159: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 160: 1 0 1 test 161: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 162: 1 0 1 test 163: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 164: 1 00 11 test 165: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 166: 1 00 11 test 167: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 168: 1 00 11 test 169: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 170: 1 00 11 test 171: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 172: 1 00 11 test 173: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 174: 1 00 11 test 175: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 176: 1 0 1 test 177: 0 1 0 comment: ; no change test 178: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 179: 0 test 180: 110 test 181: 0 comment: ; toggle phase should toggle RWB 2 test 182: 0 0 test 183: 1 1 comment: comment: ; shift in 0, expect 00 test 184: 0 test 185: 100 test 186: 0 comment: ; toggle phase should toggle RWB 2 test 187: 0 1 test 188: 1 0 comment: comment: ; shift in 0, expect 00 test 189: 0 test 190: 100 test 191: 0 comment: ; shift in 1, expect 01 test 192: 1 test 193: 101 test 194: 0 comment: ; shift in 1, expect 11 test 195: 1 test 196: 111 test 197: 0 comment: ; shift in 1, expect 11 test 198: 1 test 199: 111 test 200: 0 comment: ; shift in 0, expect 10 test 201: 0 test 202: 110 test 203: 0 comment: ; shift in 1, expect 01 test 204: 1 test 205: 101 test 206: 0 comment: ; shift in 0, expect 10 test 207: 0 test 208: 110 test 209: 0 comment: ; shift in 1, expect 01 test 210: 1 test 211: 101 test 212: 0 comment: ; shift in 1, expect 11 test 213: 1 test 214: 111 test 215: 0 comment: ; no change test 216: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0x1602 0x1489 0xF422 0x0680 0x1005 75: 0x1602 0x1489 0xF422 0x0680 0x1005 76: 0x9603 0x0489 0xF422 0x0680 0x1005 77: 0x1603 0x0489 0xF422 0x0680 0x1005 78: 0x1603 0x0491 0xF422 0x0680 0x100D 79: 0x9602 0x1491 0xF422 0x0680 0x100D 80: 0x1602 0x1491 0xF422 0x0680 0x100D 81: 0x1602 0x1491 0xF422 0x0680 0x100D 82: 0x1202 0x1491 0xF42A 0x0600 0x100D 83: 0xD200 0x1491 0xF42A 0x0600 0x100D 84: 0x5200 0x1491 0xF42A 0x0600 0x100D 85: 0x5600 0x1491 0xF422 0x0680 0x100D 86: 0x9602 0x1491 0xF422 0x0680 0x100D 87: 0x1602 0x1491 0xF422 0x0680 0x100D 88: 0x1602 0x1489 0xF422 0x0680 0x1005 89: 0x1602 0x1489 0xF422 0x0680 0x1005 90: 0x1602 0x1489 0xF422 0x0480 0x1007 91: 0x1602 0x1489 0xF422 0x0480 0x1005 92: 0x1602 0x1491 0xF422 0x0480 0x100D 93: 0x1602 0x1491 0xF422 0x0680 0x100F 94: 0x1602 0x1491 0xF422 0x0680 0x100D 95: 0x1602 0x1491 0xF422 0x0680 0x100D 96: 0x1202 0x1491 0xF42A 0x0600 0x100D 97: 0x1202 0x1491 0xF02A 0x0600 0x100F 98: 0x1202 0x1491 0xF02A 0x0600 0x100D 99: 0x1602 0x1491 0xF022 0x0680 0x100D 100: 0x1602 0x1491 0xF422 0x0680 0x100F 101: 0x1602 0x1491 0xF422 0x0680 0x100D 102: 0x1602 0x1489 0xF422 0x0680 0x1005 103: 0x1602 0x1489 0xF422 0x0680 0x1005 104: 0x1602 0x1489 0xF422 0x0480 0x1007 105: 0x1602 0x1489 0xF422 0x0480 0x1005 106: 0x1602 0x1489 0xF4A2 0x0480 0x0005 107: 0x1602 0x1489 0xF422 0x0480 0x0005 108: 0x1602 0x1491 0xF422 0x0480 0x000D 109: 0x1602 0x1491 0xF422 0x0680 0x000F 110: 0x1602 0x1491 0xF422 0x0680 0x000D 111: 0x1602 0x1491 0xF4A2 0x0680 0x100D 112: 0x1602 0x1491 0xF422 0x0680 0x100D 113: 0x1602 0x1491 0xF422 0x0680 0x100D 114: 0x1202 0x1491 0xF42A 0x0600 0x100D 115: 0x1202 0x1491 0xF02A 0x0600 0x100F 116: 0x1202 0x1491 0xF02A 0x0600 0x100D 117: 0x1202 0x1491 0xF08A 0x0600 0x100D 118: 0x1202 0x1491 0xF00A 0x0600 0x100D 119: 0x1602 0x1491 0xF002 0x0680 0x100D 120: 0x1602 0x1491 0xF402 0x0680 0x100F 121: 0x1602 0x1491 0xF402 0x0680 0x100D 122: 0x1602 0x1491 0xF4A2 0x0680 0x100D 123: 0x1602 0x1491 0xF422 0x0680 0x100D 124: 0x1202 0x1491 0xF42A 0x0600 0x100D 125: 0x1202 0x1489 0xF42A 0x0600 0x1005 126: 0x1202 0x1489 0xF42A 0x0600 0x1005 127: 0x1206 0x1489 0xF42A 0x0600 0x1005 128: 0x1206 0x3489 0xF42A 0x0600 0x1005 129: 0x1A06 0x3489 0xF42A 0x0600 0x1005 130: 0x1A06 0x348D 0xF42A 0x0600 0x1005 131: 0x1A46 0x348D 0xF42A 0x0600 0x1005 132: 0x1A46 0x368D 0xF42A 0x0600 0x1005 133: 0x1A46 0x368D 0xF62A 0x0600 0x1005 134: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 135: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 136: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 137: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 138: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 139: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 140: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 141: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 142: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 143: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 144: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 145: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 146: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 147: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 148: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 149: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 150: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 151: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 152: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 153: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 154: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 155: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 156: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 157: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 158: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 159: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 160: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 161: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 162: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 163: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 164: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 165: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 166: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 167: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 168: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 169: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 170: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 171: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 172: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 173: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 174: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 175: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 176: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 177: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 178: 0x1202 0x1489 0xF42A 0x0600 0x1005 179: 0x1202 0x1489 0xB42A 0x0600 0x1005 180: 0x1202 0x1489 0xB44A 0x0600 0x1005 181: 0x1202 0x1489 0xB40A 0x0600 0x1005 182: 0x1202 0x1489 0xB40A 0x0600 0x0004 183: 0x1202 0x1489 0xB40A 0x0600 0x1005 184: 0x1202 0x1489 0xB40A 0x0600 0x1005 185: 0x1202 0x1489 0xB44A 0x0600 0x0005 186: 0x1202 0x1489 0xB40A 0x0600 0x0005 187: 0x1202 0x1489 0xB40A 0x0600 0x1004 188: 0x1202 0x1489 0xB40A 0x0600 0x0005 189: 0x1202 0x1489 0xB40A 0x0600 0x0005 190: 0x1202 0x1489 0xB44A 0x0600 0x0005 191: 0x1202 0x1489 0xB40A 0x0600 0x0005 192: 0x1202 0x1489 0xF40A 0x0600 0x0005 193: 0x1202 0x1489 0xF46A 0x0600 0x0005 194: 0x1202 0x1489 0xF42A 0x0600 0x0005 195: 0x1202 0x1489 0xF42A 0x0600 0x0005 196: 0x1202 0x1489 0xF46A 0x0600 0x1005 197: 0x1202 0x1489 0xF42A 0x0600 0x1005 198: 0x1202 0x1489 0xF42A 0x0600 0x1005 199: 0x1202 0x1489 0xF46A 0x0600 0x1005 200: 0x1202 0x1489 0xF42A 0x0600 0x1005 201: 0x1202 0x1489 0xB42A 0x0600 0x1005 202: 0x1202 0x1489 0xB44A 0x0600 0x1005 203: 0x1202 0x1489 0xB40A 0x0600 0x1005 204: 0x1202 0x1489 0xF40A 0x0600 0x1005 205: 0x1202 0x1489 0xF46A 0x0600 0x0005 206: 0x1202 0x1489 0xF42A 0x0600 0x0005 207: 0x1202 0x1489 0xB42A 0x0600 0x0005 208: 0x1202 0x1489 0xB44A 0x0600 0x1005 209: 0x1202 0x1489 0xB40A 0x0600 0x1005 210: 0x1202 0x1489 0xF40A 0x0600 0x1005 211: 0x1202 0x1489 0xF46A 0x0600 0x0005 212: 0x1202 0x1489 0xF42A 0x0600 0x0005 213: 0x1202 0x1489 0xF42A 0x0600 0x0005 214: 0x1202 0x1489 0xF46A 0x0600 0x1005 215: 0x1202 0x1489 0xF42A 0x0600 0x1005 216: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT inputs: 44 UUT outputs: 22 pins used: 66 not used: 0 216 'test steps' 584 lines M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: +5v AA2, BA2 GROUND AC2, AT1, BC2, BT1 (ALL PINS ARE USED). PINS Main menu Thu Jun 29 17:15:53 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 17:16:04 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 80 100000000000010010000000000000000000110111011011011010100110110111 step 81 100000000000010010000000000000000000110111011011011010100110110111 step 82 100000000000000010000000000000000001110110011011011010100110110111 step 83 100000000000000010000000000000000001110110011011011110010110110111 step 84 100000000000000010000000000000000001110110011011011010010110110111 step 85 100000000000010010000000000000000000110111011011011010010110110111 step 86 100000000000010010000000000000000000110111011011011110100110110111 step 87 100000000000010010000000000000000000110111011011011010100110110111 step 88 100000000000010000000000000000000000111101011011011010100110110111 step 89 100000000000010000000000000000000000111101011011011010100110110111 step 90 100000000000010000000000000000000000111101011011011010101010110111 step 91 100000000000010000000000000000000000111101011011011010100010110111 step 92 100000000000010010000000000000000000110111011011011010100010110111 step 93 100000000000010010000000000000000000110111011011011010101110110111 step 94 100000000000010010000000000000000000110111011011011010100110110111 step 95 100000000000010010000000000000000000110111011011011010100110110111 step 96 100000000000000010000000000000000001110110011011011010100110110111 step 97 100000000000000010000000000000000001110110011011011010101100110111 step 98 100000000000000010000000000000000001110110011011011010100100110111 step 99 100000000000010010000000000000000000110111011011011010100100110111 step 100 100000000000010010000000000000000000110111011011011010101110110111 step 101 100000000000010010000000000000000000110111011011011010100110110111 step 102 100000000000010000000000000000000000111101011011011010100110110111 step 103 100000000000010000000000000000000000111101011011011010100110110111 step 104 100000000000010000000000000000000000111101011011011010101010110111 step 105 100000000000010000000000000000000000111101011011011010100010110111 step 106 100000000000010000000000000000000000111101011011011010100011110011 step 107 100000000000010000000000000000000000111101011011011010100010110011 step 108 100000000000010010000000000000000000110111011011011010100010110011 step 109 100000000000010010000000000000000000110111011011011010101110110011 step 110 100000000000010010000000000000000000110111011011011010100110110011 step 111 100000000000010010000000000000000000110111011011011010100111110111 step 112 100000000000010010000000000000000000110111011011011010100110110111 step 113 100000000000010010000000000000000000110111011011011010100110110111 step 114 100000000000000010000000000000000001110110011011011010100110110111 step 115 100000000000000010000000000000000001110110011011011010101100110111 step 116 100000000000000010000000000000000001110110011011011010100100110111 step 117 100000000000000010000000000000000001110110011011011010100101110101 step 118 100000000000000010000000000000000001110110011011011010100100110101 step 119 100000000000010010000000000000000000110111011011011010100100110101 step 120 100000000000010010000000000000000000110111011011011010101110110101 step 121 100000000000010010000000000000000000110111011011011010100110110101 step 122 100000000000010010000000000000000000110111011011011010100111110111 step 123 100000000000010010000000000000000000110111011011011010100110110111 step 124 100000000000000010000000000000000001110110011011011010100110110111 step 125 100000000000000000000000000000000001111100011011011010100110110111 step 126 100000000000000000000000000000000001111100011011011010100110110111 step 127 100001000000000000000000000000000001111100011011011010100110110111 step 128 100001100000000000000000000000000001111100011011011010100110110111 step 129 100001100100000000000000000000000001111100011011011010100110110111 step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ step 183 100000000000000000000000000000000001111100011011011010100110100101 step 184 100000000000000000000000000000000001111100011011011010100110100101 step 185 100000000000000000000000000000000001111100011011011010100110101001 step 186 100000000000000000000000000000000001111100011011011010100110100001 step 187 100000000000000000000000000000000001111100011011011010100110000101 step 188 100000000000000000000000000000000001111100011011011010100110100001 step 189 100000000000000000000000000000000001111100011011011010100110100001 step 190 100000000000000000000000000000000001111100011011011010100110101001 step 191 100000000000000000000000000000000001111100011011011010100110100001 step 192 100000000000000000000000000000000001111100011011011010100110110001 step 193 100000000000000000000000000000000001111100011011011010100110111011 step 194 100000000000000000000000000000000001111100011011011010100110110011 step 195 100000000000000000000000000000000001111100011011011010100110110011 step 196 100000000000000000000000000000000001111100011011011010100110111111 step 197 100000000000000000000000000000000001111100011011011010100110110111 step 198 100000000000000000000000000000000001111100011011011010100110110111 step 199 100000000000000000000000000000000001111100011011011010100110111111 step 200 100000000000000000000000000000000001111100011011011010100110110111 step 201 100000000000000000000000000000000001111100011011011010100110100111 step 202 100000000000000000000000000000000001111100011011011010100110101101 step 203 100000000000000000000000000000000001111100011011011010100110100101 step 204 100000000000000000000000000000000001111100011011011010100110110101 step 205 100000000000000000000000000000000001111100011011011010100110111011 step 206 100000000000000000000000000000000001111100011011011010100110110011 step 207 100000000000000000000000000000000001111100011011011010100110100011 step 208 100000000000000000000000000000000001111100011011011010100110101101 step 209 100000000000000000000000000000000001111100011011011010100110100101 step 210 100000000000000000000000000000000001111100011011011010100110110101 step 211 100000000000000000000000000000000001111100011011011010100110111011 step 212 100000000000000000000000000000000001111100011011011010100110110011 step 213 100000000000000000000000000000000001111100011011011010100110110011 step 214 100000000000000000000000000000000001111100011011011010100110111111 step 215 100000000000000000000000000000000001111100011011011010100110110111 step 216 100000000000000000000000000000000001111100011011011010100110110111 test 10: *** FAIL *************************** 1 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 10, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 step 40 100000000000000010000000000000000001110110011011011010100110110111 step 41 100000000000000010000000000000000001110110110011011010100110110111 step 42 100000000000000010000000000000000001110110010011011010100110110111 step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010000000000000000000000111101011011011010100110110111 step 47 100000000000010000000000000000000000111101011011011010100110110111 step 48 100000000000010000000000000000000000111101011101011010100110110111 step 49 100000000000010000000000000000000000111101011001011010100110110111 step 50 100000000000010010000000000000000000110111011001011010100110110111 step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 step 54 100000000000000010000000000000000001110110011011011010100110110111 step 55 100000000000000010000000000000000001110110011110011010100110110111 step 56 100000000000000010000000000000000001110110011010011010100110110111 step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 step 60 100000000000010000000000000000000000111101011011011010100110110111 step 61 100000000000010000000000000000000000111101011011011010100110110111 step 62 100000000000010000000000000000000000111101011011101010100110110111 step 63 100000000000010000000000000000000000111101011011001010100110110111 step 64 100000000000010010000000000000000000110111011011001010100110110111 step 65 100000000000010010000000000000000000110111011011111010100110110111 step 66 100000000000010010000000000000000000110111011011011010100110110111 step 67 100000000000010010000000000000000000110111011011011010100110110111 step 68 100000000000000010000000000000000001110110011011011010100110110111 step 69 100000000000000010000000000000000001110110011011110010100110110111 step 70 100000000000000010000000000000000001110110011011010010100110110111 step 71 100000000000010010000000000000000000110111011011010010100110110111 step 72 100000000000010010000000000000000000110111011011111010100110110111 step 73 100000000000010010000000000000000000110111011011011010100110110111 step 74 100000000000010000000000000000000000111101011011011010100110110111 step 75 100000000000010000000000000000000000111101011011011010100110110111 step 76 100000000000010000000000000000000000111101011011011101100110110111 step 77 100000000000010000000000000000000000111101011011011001100110110111 step 78 100000000000010010000000000000000000110111011011011001100110110111 step 79 100000000000010010000000000000000000110111011011011110100110110111 step 80 100000000000010010000000000000000000110111011011011010100110110111 step 81 100000000000010010000000000000000000110111011011011010100110110111 step 82 100000000000000010000000000000000001110110011011011010100110110111 step 83 100000000000000010000000000000000001110110011011011110010110110111 step 84 100000000000000010000000000000000001110110011011011010010110110111 step 85 100000000000010010000000000000000000110111011011011010010110110111 step 86 100000000000010010000000000000000000110111011011011110100110110111 step 87 100000000000010010000000000000000000110111011011011010100110110111 step 88 100000000000010000000000000000000000111101011011011010100110110111 step 89 100000000000010000000000000000000000111101011011011010100110110111 step 90 100000000000010000000000000000000000111101011011011010101010110111 step 91 100000000000010000000000000000000000111101011011011010100010110111 step 92 100000000000010010000000000000000000110111011011011010100010110111 step 93 100000000000010010000000000000000000110111011011011010101110110111 step 94 100000000000010010000000000000000000110111011011011010100110110111 step 95 100000000000010010000000000000000000110111011011011010100110110111 step 96 100000000000000010000000000000000001110110011011011010100110110111 step 97 100000000000000010000000000000000001110110011011011010101100110111 step 98 100000000000000010000000000000000001110110011011011010100100110111 step 99 100000000000010010000000000000000000110111011011011010100100110111 step 100 100000000000010010000000000000000000110111011011011010101110110111 step 101 100000000000010010000000000000000000110111011011011010100110110111 step 102 100000000000010000000000000000000000111101011011011010100110110111 step 103 100000000000010000000000000000000000111101011011011010100110110111 step 104 100000000000010000000000000000000000111101011011011010101010110111 step 105 100000000000010000000000000000000000111101011011011010100010110111 step 106 100000000000010000000000000000000000111101011011011010100011110011 step 107 100000000000010000000000000000000000111101011011011010100010110011 step 108 100000000000010010000000000000000000110111011011011010100010110011 step 109 100000000000010010000000000000000000110111011011011010101110110011 step 110 100000000000010010000000000000000000110111011011011010100110110011 step 111 100000000000010010000000000000000000110111011011011010100111110111 step 112 100000000000010010000000000000000000110111011011011010100110110111 step 113 100000000000010010000000000000000000110111011011011010100110110111 step 114 100000000000000010000000000000000001110110011011011010100110110111 step 115 100000000000000010000000000000000001110110011011011010101100110111 step 116 100000000000000010000000000000000001110110011011011010100100110111 step 117 100000000000000010000000000000000001110110011011011010100101110101 step 118 100000000000000010000000000000000001110110011011011010100100110101 step 119 100000000000010010000000000000000000110111011011011010100100110101 step 120 100000000000010010000000000000000000110111011011011010101110110101 step 121 100000000000010010000000000000000000110111011011011010100110110101 step 122 100000000000010010000000000000000000110111011011011010100111110111 step 123 100000000000010010000000000000000000110111011011011010100110110111 step 124 100000000000000010000000000000000001110110011011011010100110110111 step 125 100000000000000000000000000000000001111100011011011010100110110111 step 126 100000000000000000000000000000000001111100011011011010100110110111 step 127 100001000000000000000000000000000001111100011011011010100110110111 step 128 100001100000000000000000000000000001111100011011011010100110110111 step 129 100001100100000000000000000000000001111100011011011010100110110111 step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ step 183 100000000000000000000000000000000001111100011011011010100110100101 step 184 100000000000000000000000000000000001111100011011011010100110100101 step 185 100000000000000000000000000000000001111100011011011010100110101001 step 186 100000000000000000000000000000000001111100011011011010100110100001 step 187 100000000000000000000000000000000001111100011011011010100110000101 step 188 100000000000000000000000000000000001111100011011011010100110100001 step 189 100000000000000000000000000000000001111100011011011010100110100001 step 190 100000000000000000000000000000000001111100011011011010100110101001 step 191 100000000000000000000000000000000001111100011011011010100110100001 step 192 100000000000000000000000000000000001111100011011011010100110110001 step 193 100000000000000000000000000000000001111100011011011010100110111011 step 194 100000000000000000000000000000000001111100011011011010100110110011 step 195 100000000000000000000000000000000001111100011011011010100110110011 step 196 100000000000000000000000000000000001111100011011011010100110111111 step 197 100000000000000000000000000000000001111100011011011010100110110111 step 198 100000000000000000000000000000000001111100011011011010100110110111 step 199 100000000000000000000000000000000001111100011011011010100110111111 step 200 100000000000000000000000000000000001111100011011011010100110110111 step 201 100000000000000000000000000000000001111100011011011010100110100111 step 202 100000000000000000000000000000000001111100011011011010100110101101 step 203 100000000000000000000000000000000001111100011011011010100110100101 step 204 100000000000000000000000000000000001111100011011011010100110110101 step 205 100000000000000000000000000000000001111100011011011010100110111011 step 206 100000000000000000000000000000000001111100011011011010100110110011 step 207 100000000000000000000000000000000001111100011011011010100110100011 step 208 100000000000000000000000000000000001111100011011011010100110101101 step 209 100000000000000000000000000000000001111100011011011010100110100101 step 210 100000000000000000000000000000000001111100011011011010100110110101 step 211 100000000000000000000000000000000001111100011011011010100110111011 step 212 100000000000000000000000000000000001111100011011011010100110110011 step 213 100000000000000000000000000000000001111100011011011010100110110011 step 214 100000000000000000000000000000000001111100011011011010100110111111 step 215 100000000000000000000000000000000001111100011011011010100110110111 step 216 100000000000000000000000000000000001111100011011011010100110110111 test 11: *** FAIL *************************** 1 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 11, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 11, total passes 0 Main menu Thu Jun 29 17:16:14 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 18:55:06 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000001111100000000000001010000110001 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 1 step 2 100000000000000000000000000000000001111100100000000001010000110001 source: 0 changed: 0 step 3 100000000000000000000000000000000001111100000000000001010000110001 source: ; load TMA from tape bus (00) source: 100 changed: 1 step 4 100000000000000000000000000000000001111100000100000001010000110001 source: 0 changed: 0 step 5 100000000000000000000000000000000001111100000000000001010000110001 source: ; load TBN from tape bus (00) source: 100 changed: 1 step 6 100000000000000000000000000000000001111100000000100001010000110001 source: 0 changed: 0 step 7 100000000000000000000000000000000001111100000000000001010000110001 source: ; load TAC from tape bus (00) source: 10101 changed: 1 step 8 100000000000000000000000000000000001111100000000000101010000110001 source: 0 changed: 0 step 9 100000000000000000000000000000000001111100000000000001010000110001 source: ; load TB from tape bus (00) source: 100 changed: 1 step 10 100000000000000000000000000000000001111100000000000001011000110001 source: 0 changed: 0 step 11 100000000000000000000000000000000001111100000000000001010000110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 step 12 100000000000000000000000000000000001111100000000000001010001110001 source: 0 changed: 0 step 13 100000000000000000000000000000000001111100000000000001010000110001 source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000001111100000000000001010000110001 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000001010000110001 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000001010000110001 source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 111 step 17 100000000000010010000000000000000000110111111000000001010000110001 source: 0 changed: 0 step 18 100000000000010010000000000000000000110111011000000001010000110001 source: ; load TMA from tape bus (11) source: 111 changed: 111 step 19 100000000000010010000000000000000000110111011111000001010000110001 source: 0 changed: 0 step 20 100000000000010010000000000000000000110111011011000001010000110001 source: ; load TBN from tape bus (11) source: 111 changed: 111 step 21 100000000000010010000000000000000000110111011011111001010000110001 source: 0 changed: 0 step 22 100000000000010010000000000000000000110111011011011001010000110001 source: ; load TAC from tape bus (11) source: 11010 changed: 11010 step 23 100000000000010010000000000000000000110111011011011110100000110001 source: 0 changed: 0 step 24 100000000000010010000000000000000000110111011011011010100000110001 source: ; load TB from tape bus (11) source: 111 changed: 111 step 25 100000000000010010000000000000000000110111011011011010101110110001 source: 0 changed: 0 step 26 100000000000010010000000000000000000110111011011011010100110110001 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 11 step 27 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 28 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 29 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 30 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000001111100011011011010100110110111 source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000001111100011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 33 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA SETUP from tape bus (01) source: 101 changed: 10 step 34 100000000000010000000000000000000000111101101011011010100110110111 source: 0 changed: 0 step 35 100000000000010000000000000000000000111101001011011010100110110111 source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 36 100000000000010010000000000000000000110111001011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 11 step 37 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 38 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 40 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 0 step 41 100000000000000010000000000000000001110110110011011010100110110111 source: 0 changed: 0 step 42 100000000000000010000000000000000001110110010011011010100110110111 source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 43 100000000000010010000000000000000000110111010011011010100110110111 source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 1 step 44 100000000000010010000000000000000000110111111011011010100110110111 source: 0 changed: 0 step 45 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 46 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TMA from tape bus (01) source: 101 changed: 10 step 48 100000000000010000000000000000000000111101011101011010100110110111 source: 0 changed: 0 step 49 100000000000010000000000000000000000111101011001011010100110110111 source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 11 step 51 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 52 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 54 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TMA from tape bus (10) source: 110 changed: 1 0 step 55 100000000000000010000000000000000001110110011110011010100110110111 source: 0 changed: 0 step 56 100000000000000010000000000000000001110110011010011010100110110111 source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 57 100000000000010010000000000000000000110111011010011010100110110111 source: ; load TMA from tape bus (11) source: 111 changed: 1 1 step 58 100000000000010010000000000000000000110111011111011010100110110111 source: 0 changed: 0 step 59 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 60 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TBN from tape bus (01) source: 101 changed: 10 step 62 100000000000010000000000000000000000111101011011101010100110110111 source: 0 changed: 0 step 63 100000000000010000000000000000000000111101011011001010100110110111 source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 64 100000000000010010000000000000000000110111011011001010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 11 step 65 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 66 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 68 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TBN from tape bus (10) source: 110 changed: 1 0 step 69 100000000000000010000000000000000001110110011011110010100110110111 source: 0 changed: 0 step 70 100000000000000010000000000000000001110110011011010010100110110111 source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 71 100000000000010010000000000000000000110111011011010010100110110111 source: ; load TBN from tape bus (11) source: 111 changed: 1 1 step 72 100000000000010010000000000000000000110111011011111010100110110111 source: 0 changed: 0 step 73 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 74 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TAC from tape bus (01) source: 10110 changed: 101 step 76 100000000000010000000000000000000000111101011011011101100110110111 source: 0 changed: 0 step 77 100000000000010000000000000000000000111101011011011001100110110111 source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 78 100000000000010010000000000000000000110111011011011001100110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 110 step 79 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 80 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 82 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TAC from tape bus (10) source: 11001 changed: 1 01 step 83 100000000000000010000000000000000001110110011011011110010110110111 source: 0 changed: 0 step 84 100000000000000010000000000000000001110110011011011010010110110111 source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 85 100000000000010010000000000000000000110111011011011010010110110111 source: ; load TAC from tape bus (11) source: 11010 changed: 1 10 step 86 100000000000010010000000000000000000110111011011011110100110110111 source: 0 changed: 0 step 87 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 88 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 90 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 91 100000000000010000000000000000000000111101011011011010100010110111 source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 92 100000000000010010000000000000000000110111011011011010100010110111 source: ; load TB from tape bus (11) source: 111 changed: 11 step 93 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 94 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 96 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 97 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 98 100000000000000010000000000000000001110110011011011010100100110111 source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 99 100000000000010010000000000000000000110111011011011010100100110111 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 100 100000000000010010000000000000000000110111011011011010101110110111 source: 0 changed: 0 step 101 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 102 100000000000010000000000000000000000111101011011011010100110110111 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000111101011011011010100110110111 source: ; load TB from tape bus (01) source: 101 changed: 10 step 104 100000000000010000000000000000000000111101011011011010101010110111 source: 0 changed: 0 step 105 100000000000010000000000000000000000111101011011011010100010110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 0 step 106 100000000000010000000000000000000000111101011011011010100011110011 source: 0 changed: 0 step 107 100000000000010000000000000000000000111101011011011010100010110011 source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 108 100000000000010010000000000000000000110111011011011010100010110011 source: ; load TB from tape bus (11) source: 111 changed: 11 step 109 100000000000010010000000000000000000110111011011011010101110110011 source: 0 changed: 0 step 110 100000000000010010000000000000000000110111011011011010100110110011 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 111 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 112 100000000000010010000000000000000000110111011011011010100110110111 source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000110111011011011010100110110111 source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 114 100000000000000010000000000000000001110110011011011010100110110111 source: ; load TB from tape bus (10) source: 110 changed: 1 0 step 115 100000000000000010000000000000000001110110011011011010101100110111 source: 0 changed: 0 step 116 100000000000000010000000000000000001110110011011011010100100110111 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 0 step 117 100000000000000010000000000000000001110110011011011010100101110101 source: 0 changed: 0 step 118 100000000000000010000000000000000001110110011011011010100100110101 source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 119 100000000000010010000000000000000000110111011011011010100100110101 source: ; load TB from tape bus (11) source: 111 changed: 1 1 step 120 100000000000010010000000000000000000110111011011011010101110110101 source: 0 changed: 0 step 121 100000000000010010000000000000000000110111011011011010100110110101 source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 1 step 122 100000000000010010000000000000000000110111011011011010100111110111 source: 0 changed: 0 step 123 100000000000010010000000000000000000110111011011011010100110110111 source: source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 1 0 step 124 100000000000000010000000000000000001110110011011011010100110110111 source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 1 0 step 125 100000000000000000000000000000000001111100011011011010100110110111 source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 126 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 127 100001000000000000000000000000000001111100011011011010100110110111 source: ; set pin AM1 HIGH source: 1 changed: 1 step 128 100001100000000000000000000000000001111100011011011010100110110111 source: ; set pin AE1 HIGH source: 1 changed: 1 step 129 100001100100000000000000000000000001111100011011011010100110110111 source: ; set pin AM2 HIGH source: 1 changed: 1 step 130 100001100110000000000000000000000001111100011011011010100110110111 source: ; set pin AB2 HIGH source: 1 changed: 1 step 131 100001100110100000000000000000000001111100011011011010100110110111 source: ; set pin AS1 HIGH source: 1 changed: 1 step 132 100001100110100100000000000000000001111100011011011010100110110111 source: ; set pin BE1 HIGH source: 1 changed: 1 step 133 100001100110100100010000000000000001111100011011011010100110110111 source: ; set pin BM1 HIGH source: 1 changed: 1 step 134 100001100110100100011000000000000001111100011011011010100110110111 source: ; set pin BH1 HIGH source: 1 changed: 1 step 135 100001100110100100011010000000000001111100011011011010100110110111 source: ; set pin BR1 HIGH source: 1 changed: 1 step 136 100001100110100100011011000000000001111100011011011010100110110111 source: ; set pin BC1 HIGH source: 1 changed: 1 step 137 100001100110100100011011010000000001111100011011011010100110110111 source: ; set pin BJ2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011000000001111100011011011010100110110111 source: ; set pin BJ1 HIGH source: 1 changed: 1 step 139 100001100110100100011011011010000001111100011011011010100110110111 source: ; set pin BK2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011000001111100011011011010100110110111 source: ; set pin BH2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011010001111100011011011010100110110111 source: ; set pin BP2 HIGH source: 1 changed: 1 step 142 100001100110100100011011011011011001111100011011011010100110110111 source: ; set pin BN2 HIGH source: 1 changed: 1 step 143 100001100110100100011011011011011101111100011011011010100110110111 source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 144 110001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 145 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 146 101001100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 147 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 148 100101100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 149 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 150 100011100110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 151 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 152 100001110110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 153 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 154 100001101110100100011011011011011100110111011011011010100110110111 source: 0 1 1 00 changed: 0 1 1 00 step 155 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100111100100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110110100011011011011011100111101011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110101100011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 162 100001100110100110011011011011011101110110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 163 100001100110100100011011011011011101111100011011011010100110110111 source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 164 100001100110100101011011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 165 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100111011011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011111011011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011111011011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011111011101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 174 100001100110100100011011011011111101001111011011011010100110110111 source: 0 11 00 changed: 0 11 00 step 175 100001100110100100011011011011011101111100011011011010100110110111 source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 176 100001100110100100011011011011011111101110011011011010100110110111 source: 0 1 0 changed: 0 1 0 step 177 100001100110100100011011011011011101111100011011011010100110110111 source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 178 100000000000000000000000000000000001111100011011011010100110110111 source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011011011010100110100111 source: 110 changed: 1 0 step 180 100000000000000000000000000000000001111100011011011010100110101101 source: 0 changed: 0 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 1 1 changed: 00000 00 00 00 0 0 00 1 0 0 step 183 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; shift in 0, expect 00 source: 0 changed: step 184 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 100 changed: 1 step 185 100000000000000000000000000000000000000000000000000000000000101000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 186 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 step 187 100000000000000000000000000000000000000000000000000000000000000000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 1 0 changed: 1 step 188 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; shift in 0, expect 00 source: 0 changed: step 189 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 100 changed: 1 step 190 100000000000000000000000000000000000000000000000000000000000101000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 191 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 01 source: 1 changed: 1 step 192 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 101 changed: 1 step 193 100000000000000000000000000000000000000000000000000000000000111000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 194 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 195 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 111 changed: 1 step 196 100000000000000000000000000000000000000000000000000000000000111000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 197 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 198 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 111 changed: 1 step 199 100000000000000000000000000000000000000000000000000000000000111000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 200 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 0, expect 10 source: 0 changed: 0 step 201 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 1 step 202 100000000000000000000000000000000000000000000000000000000000101000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 203 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 01 source: 1 changed: 1 step 204 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 101 changed: 1 step 205 100000000000000000000000000000000000000000000000000000000000111000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 206 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 0, expect 10 source: 0 changed: 0 step 207 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 1 step 208 100000000000000000000000000000000000000000000000000000000000101000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 209 100000000000000000000000000000000000000000000000000000000000100000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 01 source: 1 changed: 1 step 210 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 101 changed: 1 step 211 100000000000000000000000000000000000000000000000000000000000111000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 212 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 213 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 111 changed: 1 step 214 100000000000000000000000000000000000000000000000000000000000111000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 215 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 216 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ test 1: *** FAIL *************************** 35 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail OOOOO OO OO OO O O OO OOO all fails OOOOO OO OO OO O O OO OOO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; all registers are unknown source: ; turn on C0, PHASE source: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 source: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 changed: step 1 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers LOW source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; load TMA SETUP from tape bus (00) source: 100 changed: 1 step 2 100000000000000000000000000000000000000000100000000000000000110000 fail ^^^^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 3 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (00) source: 100 changed: 1 step 4 100000000000000000000000000000000000000000000100000000000000110000 fail ^^^^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 5 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TBN from tape bus (00) source: 100 changed: 1 step 6 100000000000000000000000000000000000000000000000100000000000110000 fail ^^^^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 7 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (00) source: 10101 changed: 1 step 8 100000000000000000000000000000000000000000000000000100000000110000 fail ^^^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 9 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (00) source: 100 changed: 1 step 10 100000000000000000000000000000000000000000000000000000001000110000 fail ^^^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 11 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 00 changed: 1 step 12 100000000000000000000000000000000000000000000000000000000001110000 fail ^^^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 13 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; (no change) source: 100000000000000000000000000000000001111100000000000001010000110001 changed: step 14 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; set all registers HIGH source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 15 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 16 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 step 17 100000000000010010000000000000000000000000100000000000000000110000 fail ^^ ^^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 18 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (11) source: 111 changed: 1 step 19 100000000000010010000000000000000000000000000100000000000000110000 fail ^^ ^^^ ^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 20 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TBN from tape bus (11) source: 111 changed: 1 step 21 100000000000010010000000000000000000000000000000100000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 22 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (11) source: 11010 changed: 1 step 23 100000000000010010000000000000000000000000000000000100000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 24 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (11) source: 111 changed: 1 step 25 100000000000010010000000000000000000000000000000000000001000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 26 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 step 27 100000000000010010000000000000000000000000000000000000000001110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 28 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 29 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 step 30 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 31 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; will all registers high, walk a 0 source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: source: ; walk a 0, TMA SETUP 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: step 32 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 33 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (01) source: 101 changed: 1 step 34 100000000000010000000000000000000000000000100000000000000000110000 fail ^^^^ ^ ^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 35 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TMA SETUP 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 36 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 step 37 100000000000010010000000000000000000000000100000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 38 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TMA SETUP 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 39 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 40 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (10) source: 110 changed: 1 step 41 100000000000000010000000000000000000000000100000000000000000110000 fail ^^^ ^^ ^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 42 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TMA SETUP 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 43 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA SETUP from tape bus (11) source: 111 changed: 1 step 44 100000000000010010000000000000000000000000100000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 45 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TMA 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 step 46 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 47 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (01) source: 101 changed: 1 step 48 100000000000010000000000000000000000000000000100000000000000110000 fail ^^^^ ^ ^^ ^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 49 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TMA 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 50 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (11) source: 111 changed: 1 step 51 100000000000010010000000000000000000000000000100000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 52 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TMA 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 53 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 54 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (10) source: 110 changed: 1 step 55 100000000000000010000000000000000000000000000100000000000000110000 fail ^^^ ^^ ^^ ^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 56 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TMA 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 57 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TMA from tape bus (11) source: 111 changed: 1 step 58 100000000000010010000000000000000000000000000100000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 59 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TBN 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 step 60 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 61 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TBN from tape bus (01) source: 101 changed: 1 step 62 100000000000010000000000000000000000000000000000100000000000110000 fail ^^^^ ^ ^^ ^^ ^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 63 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TBN 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 64 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TBN from tape bus (11) source: 111 changed: 1 step 65 100000000000010010000000000000000000000000000000100000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 66 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TBN 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 67 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 68 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TBN from tape bus (10) source: 110 changed: 1 step 69 100000000000000010000000000000000000000000000000100000000000110000 fail ^^^ ^^ ^^ ^^ ^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 70 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TBN 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 71 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TBN from tape bus (11) source: 111 changed: 1 step 72 100000000000010010000000000000000000000000000000100000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 73 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TAC 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 step 74 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 75 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (01) source: 10110 changed: 1 step 76 100000000000010000000000000000000000000000000000000100000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 77 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TAC 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 78 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (11) source: 11010 changed: 1 step 79 100000000000010010000000000000000000000000000000000100000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 80 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TAC 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 81 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 82 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (10) source: 11001 changed: 1 step 83 100000000000000010000000000000000000000000000000000100000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 84 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TAC 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 85 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TAC from tape bus (11) source: 11010 changed: 1 step 86 100000000000010010000000000000000000000000000000000100000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 87 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 step 88 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 89 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (01) source: 101 changed: 1 step 90 100000000000010000000000000000000000000000000000000000001000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 91 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 92 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (11) source: 111 changed: 1 step 93 100000000000010010000000000000000000000000000000000000001000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 94 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, TB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 95 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 96 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (10) source: 110 changed: 1 step 97 100000000000000010000000000000000000000000000000000000001000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 98 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 99 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (11) source: 111 changed: 1 step 100 100000000000010010000000000000000000000000000000000000001000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 101 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, RWB 2 source: source: source: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 step 102 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: step 103 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (01) source: 101 changed: 1 step 104 100000000000010000000000000000000000000000000000000000001000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 105 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 01 changed: 1 step 106 100000000000010000000000000000000000000000000000000000000001110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 107 100000000000010000000000000000000000000000000000000000000000110000 fail ^^^^ ^ ^^ ^^ ^^ ^ ^ ^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TB 2 and RWB 2 source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 step 108 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (11) source: 111 changed: 1 step 109 100000000000010010000000000000000000000000000000000000001000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 110 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 step 111 100000000000010010000000000000000000000000000000000000000001110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 112 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ; walk a 0, RWB 3 source: source: source: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT source: 1 0 1 changed: step 113 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 114 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (10) source: 110 changed: 1 step 115 100000000000000010000000000000000000000000000000000000001000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 116 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 10 changed: 1 step 117 100000000000000010000000000000000000000000000000000000000001110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 118 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; restore TB 3 and RWB 3 source: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 step 119 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load TB from tape bus (11) source: 111 changed: 1 step 120 100000000000010010000000000000000000000000000000000000001000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 121 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; load RWB from TB (JAMS CLEAR AND PRESET) source: 1 11 changed: 1 step 122 100000000000010010000000000000000000000000000000000000000001110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 123 100000000000010010000000000000000000000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT source: 0 1 0 changed: 0 step 124 100000000000000010000000000000000000000000000000000000000000110000 fail ^^^ ^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT source: 0 1 0 changed: 0 step 125 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; (no change) source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 126 100000000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;********************* need to walk a one ********************** source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; source: ; test AND-NOR logic source: ; source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; (all registers are HIGH) source: ; set all pins HIGH except ENABLES source: source: ; set pin AF2 HIGH source: 1 changed: 1 step 127 100001000000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM1 HIGH source: 1 changed: 1 step 128 100001100000000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE1 HIGH source: 1 changed: 1 step 129 100001100100000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AM2 HIGH source: 1 changed: 1 step 130 100001100110000000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AB2 HIGH source: 1 changed: 1 step 131 100001100110100000000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS1 HIGH source: 1 changed: 1 step 132 100001100110100100000000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BE1 HIGH source: 1 changed: 1 step 133 100001100110100100010000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM1 HIGH source: 1 changed: 1 step 134 100001100110100100011000000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH1 HIGH source: 1 changed: 1 step 135 100001100110100100011010000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BR1 HIGH source: 1 changed: 1 step 136 100001100110100100011011000000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BC1 HIGH source: 1 changed: 1 step 137 100001100110100100011011010000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ2 HIGH source: 1 changed: 1 step 138 100001100110100100011011011000000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BJ1 HIGH source: 1 changed: 1 step 139 100001100110100100011011011010000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BK2 HIGH source: 1 changed: 1 step 140 100001100110100100011011011011000000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BH2 HIGH source: 1 changed: 1 step 141 100001100110100100011011011011010000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BP2 HIGH source: 1 changed: 1 step 142 100001100110100100011011011011011000000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BN2 HIGH source: 1 changed: 1 step 143 100001100110100100011011011011011100000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle each ENABLE source: source: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 144 110001100110100100011011011011011100000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 145 100001100110100100011011011011011100000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 146 101001100110100100011011011011011100000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 147 100001100110100100011011011011011100000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 148 100101100110100100011011011011011100000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 149 100001100110100100011011011011011100000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 step 150 100011100110100100011011011011011100000000000000000000000000110000 fail ^^ ^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 step 151 100001100110100100011011011011011100000000000000000000000000110000 fail ^^^^^ ^^ ^^ ^^ ^ ^ ^^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 1111 1 11 1 11 1 11 step 152 100001110110100100011011011011011100111101011010000001100010110011 fail ^ ^ ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 1 0 step 153 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 0 0 11 changed: 1 0 0 11 step 154 100001101110100100011011011011011100110111011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 1 00 changed: 0 1 1 00 step 155 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 156 100001100111100100011011011011011100111101011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 157 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 158 100001100110110100011011011011011100111101011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 159 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 160 100001100110101100011011011011011101110110011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 161 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT source: 1 0 1 changed: 1 0 1 step 162 100001100110100110011011011011011101110110011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 163 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 0 1 step 164 100001100110100101011011011011011101011101011010000001100010110011 fail ^ ^ ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 1 0 step 165 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 166 100001100110100100111011011011011101001111011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 167 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 168 100001100110100100011111011011011101001111011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 169 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 170 100001100110100100011011111011011101001111011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 171 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 172 100001100110100100011011011111011101001111011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 173 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT source: 1 00 11 changed: 1 00 11 step 174 100001100110100100011011011011111101001111011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 11 00 changed: 0 11 00 step 175 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT source: 1 0 1 changed: 1 0 1 step 176 100001100110100100011011011011011111101110011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 1 0 changed: 0 1 0 step 177 100001100110100100011011011011011101111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: 00 00 0 0 00 00 00 00 000 step 178 100000000000000000000000000000000001111100011010000001100010110011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: ; test shifting the RWB source: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; source: source: ; shift in 0, expect 10 source: 0 changed: 0 step 179 100000000000000000000000000000000001111100011010000001100010100011 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 110 step 180 100000000000000000000000000000000001111100011010000001100010101101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 181 100000000000000000000000000000000001111100011010000001100010100101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle phase should toggle RWB 2 source: 0 0 changed: 0 step 182 100000000000000000000000000000000001111100011010000001100010000101 fail ^ ^^ ^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 1 1 changed: 1 step 183 100000000000000000000000000000000001111100011010000001100010100101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; shift in 0, expect 00 source: 0 changed: step 184 100000000000000000000000000000000001111100011010000001100010100101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 100 changed: 10 step 185 100000000000000000000000000000000001111100011010000001100010101001 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 186 100000000000000000000000000000000001111100011010000001100010100001 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; toggle phase should toggle RWB 2 source: 0 1 changed: 0 1 step 187 100000000000000000000000000000000001111100011010000001100010000101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 1 0 changed: 1 0 step 188 100000000000000000000000000000000001111100011010000001100010100001 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: source: ; shift in 0, expect 00 source: 0 changed: step 189 100000000000000000000000000000000001111100011010000001100010100001 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 100 changed: 1 step 190 100000000000000000000000000000000001111100011010000001100010101001 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 191 100000000000000000000000000000000001111100011010000001100010100001 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 01 source: 1 changed: 1 step 192 100000000000000000000000000000000001111100011010000001100010110001 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 101 changed: 1 1 step 193 100000000000000000000000000000000001111100011010000001100010111011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 194 100000000000000000000000000000000001111100011010000001100010110011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 195 100000000000000000000000000000000001111100011010000001100010110011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 111 changed: 11 step 196 100000000000000000000000000000000001111100011010000001100010111111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 197 100000000000000000000000000000000001111100011010000001100010110111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 198 100000000000000000000000000000000001111100011010000001100010110111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 111 changed: 1 step 199 100000000000000000000000000000000001111100011010000001100010111111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 200 100000000000000000000000000000000001111100011010000001100010110111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 0, expect 10 source: 0 changed: 0 step 201 100000000000000000000000000000000001111100011010000001100010100111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 1 0 step 202 100000000000000000000000000000000001111100011010000001100010101101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 203 100000000000000000000000000000000001111100011010000001100010100101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 01 source: 1 changed: 1 step 204 100000000000000000000000000000000001111100011010000001100010110101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 101 changed: 101 step 205 100000000000000000000000000000000001111100011010000001100010111011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 206 100000000000000000000000000000000001111100011010000001100010110011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 0, expect 10 source: 0 changed: 0 step 207 100000000000000000000000000000000001111100011010000001100010100011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 110 changed: 110 step 208 100000000000000000000000000000000001111100011010000001100010101101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 209 100000000000000000000000000000000001111100011010000001100010100101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 01 source: 1 changed: 1 step 210 100000000000000000000000000000000001111100011010000001100010110101 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 101 changed: 101 step 211 100000000000000000000000000000000001111100011010000001100010111011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 212 100000000000000000000000000000000001111100011010000001100010110011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; shift in 1, expect 11 source: 1 changed: step 213 100000000000000000000000000000000001111100011010000001100010110011 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 111 changed: 11 step 214 100000000000000000000000000000000001111100011010000001100010111111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: 0 changed: 0 step 215 100000000000000000000000000000000001111100011010000001100010110111 fail ^ ^^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO source: ; no change source: 100000000000000000000000000000000001111100011011011010100110110111 changed: step 216 100000000000000000000000000000000001111100011010000001100010110111 fail ^ ^^ ^^ ^ test 2: *** FAIL *************************** 216 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail OOOOOOO OO OO OO OOOO OO OOO all fails OOOOOOO OO OO OO OOOO OO OOO was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000000000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails OOOOOOO OO OO OO OOOO OO OOO was lo 00000000000000000000000000000000000000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 2, total passes 0 Main menu Thu Jun 29 19:04:15 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:04:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ step 183 100000000000000000000000000000000001111100011011011010100110100101 step 184 100000000000000000000000000000000001111100011011011010100110100101 step 185 100000000000000000000000000000000001111100011011011010100110101001 step 186 100000000000000000000000000000000001111100011011011010100110100001 step 187 100000000000000000000000000000000001111100011011011010100110000101 step 188 100000000000000000000000000000000001111100011011011010100110100001 step 189 100000000000000000000000000000000001111100011011011010100110100001 step 190 100000000000000000000000000000000001111100011011011010100110101001 step 191 100000000000000000000000000000000001111100011011011010100110100001 step 192 100000000000000000000000000000000001111100011011011010100110110001 step 193 100000000000000000000000000000000001111100011011011010100110111011 step 194 100000000000000000000000000000000001111100011011011010100110110011 step 195 100000000000000000000000000000000001111100011011011010100110110011 step 196 100000000000000000000000000000000001111100011011011010100110111111 step 197 100000000000000000000000000000000001111100011011011010100110110111 step 198 100000000000000000000000000000000001111100011011011010100110110111 step 199 100000000000000000000000000000000001111100011011011010100110111111 step 200 100000000000000000000000000000000001111100011011011010100110110111 step 201 100000000000000000000000000000000001111100011011011010100110100111 step 202 100000000000000000000000000000000001111100011011011010100110101101 step 203 100000000000000000000000000000000001111100011011011010100110100101 step 204 100000000000000000000000000000000001111100011011011010100110110101 step 205 100000000000000000000000000000000001111100011011011010100110111011 step 206 100000000000000000000000000000000001111100011011011010100110110011 step 207 100000000000000000000000000000000001111100011011011010100110100011 step 208 100000000000000000000000000000000001111100011011011010100110101101 step 209 100000000000000000000000000000000001111100011011011010100110100101 step 210 100000000000000000000000000000000001111100011011011010100110110101 step 211 100000000000000000000000000000000001111100011011011010100110111011 step 212 100000000000000000000000000000000001111100011011011010100110110011 step 213 100000000000000000000000000000000001111100011011011010100110110011 step 214 100000000000000000000000000000000001111100011011011010100110111111 step 215 100000000000000000000000000000000001111100011011011010100110110111 step 216 100000000000000000000000000000000001111100011011011010100110110111 test 13: *** FAIL *************************** 1 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 13, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 13, total passes 0 Main menu Thu Jun 29 19:04:21 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:04:22 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100000010000001010000110001 step 2 100000000000000000000000000000000001111100100010000001010000110001 step 3 100000000000000000000000000000000001111100000010000001010000110001 step 4 100000000000000000000000000000000001111100000100000001010000110001 step 5 100000000000000000000000000000000001111100000000000001010000110001 step 6 100000000000000000000000000000000001111100000000100001010000110001 step 7 100000000000000000000000000000000001111100000000000001010000110001 step 8 100000000000000000000000000000000001111100000000000101010000110001 step 9 100000000000000000000000000000000001111100000000000001010000110001 step 10 100000000000000000000000000000000001111100000000000001011000110001 step 11 100000000000000000000000000000000001111100000000000001010000110001 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 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100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 step 40 100000000000000010000000000000000001110110011011011010100110110111 step 41 100000000000000010000000000000000001110110110011011010100110110111 step 42 100000000000000010000000000000000001110110010011011010100110110111 step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010000000000000000000000111101011011011010100110110111 step 47 100000000000010000000000000000000000111101011011011010100110110111 step 48 100000000000010000000000000000000000111101011101011010100110110111 step 49 100000000000010000000000000000000000111101011001011010100110110111 step 50 100000000000010010000000000000000000110111011001011010100110110111 step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 step 54 100000000000000010000000000000000001110110011011011010100110110111 step 55 100000000000000010000000000000000001110110011110011010100110110111 step 56 100000000000000010000000000000000001110110011010011010100110110111 step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 step 60 100000000000010000000000000000000000111101011011011010100110110111 step 61 100000000000010000000000000000000000111101011011011010100110110111 step 62 100000000000010000000000000000000000111101011011101010100110110111 step 63 100000000000010000000000000000000000111101011011001010100110110111 step 64 100000000000010010000000000000000000110111011011001010100110110111 step 65 100000000000010010000000000000000000110111011011111010100110110111 step 66 100000000000010010000000000000000000110111011011011010100110110111 step 67 100000000000010010000000000000000000110111011011011010100110110111 step 68 100000000000000010000000000000000001110110011011011010100110110111 step 69 100000000000000010000000000000000001110110011011110010100110110111 step 70 100000000000000010000000000000000001110110011011010010100110110111 step 71 100000000000010010000000000000000000110111011011010010100110110111 step 72 100000000000010010000000000000000000110111011011111010100110110111 step 73 100000000000010010000000000000000000110111011011011010100110110111 step 74 100000000000010000000000000000000000111101011011011010100110110111 step 75 100000000000010000000000000000000000111101011011011010100110110111 step 76 100000000000010000000000000000000000111101011011011101100110110111 step 77 100000000000010000000000000000000000111101011011011001100110110111 step 78 100000000000010010000000000000000000110111011011011001100110110111 step 79 100000000000010010000000000000000000110111011011011110100110110111 step 80 100000000000010010000000000000000000110111011011011010100110110111 step 81 100000000000010010000000000000000000110111011011011010100110110111 step 82 100000000000000010000000000000000001110110011011011010100110110111 step 83 100000000000000010000000000000000001110110011011011110010110110111 step 84 100000000000000010000000000000000001110110011011011010010110110111 step 85 100000000000010010000000000000000000110111011011011010010110110111 step 86 100000000000010010000000000000000000110111011011011110100110110111 step 87 100000000000010010000000000000000000110111011011011010100110110111 step 88 100000000000010000000000000000000000111101011011011010100110110111 step 89 100000000000010000000000000000000000111101011011011010100110110111 step 90 100000000000010000000000000000000000111101011011011010101010110111 step 91 100000000000010000000000000000000000111101011011011010100010110111 step 92 100000000000010010000000000000000000110111011011011010100010110111 step 93 100000000000010010000000000000000000110111011011011010101110110111 step 94 100000000000010010000000000000000000110111011011011010100110110111 step 95 100000000000010010000000000000000000110111011011011010100110110111 step 96 100000000000000010000000000000000001110110011011011010100110110111 step 97 100000000000000010000000000000000001110110011011011010101100110111 step 98 100000000000000010000000000000000001110110011011011010100100110111 step 99 100000000000010010000000000000000000110111011011011010100100110111 step 100 100000000000010010000000000000000000110111011011011010101110110111 step 101 100000000000010010000000000000000000110111011011011010100110110111 step 102 100000000000010000000000000000000000111101011011011010100110110111 step 103 100000000000010000000000000000000000111101011011011010100110110111 step 104 100000000000010000000000000000000000111101011011011010101010110111 step 105 100000000000010000000000000000000000111101011011011010100010110111 step 106 100000000000010000000000000000000000111101011011011010100011110011 step 107 100000000000010000000000000000000000111101011011011010100010110011 step 108 100000000000010010000000000000000000110111011011011010100010110011 step 109 100000000000010010000000000000000000110111011011011010101110110011 step 110 100000000000010010000000000000000000110111011011011010100110110011 step 111 100000000000010010000000000000000000110111011011011010100111110111 step 112 100000000000010010000000000000000000110111011011011010100110110111 step 113 100000000000010010000000000000000000110111011011011010100110110111 step 114 100000000000000010000000000000000001110110011011011010100110110111 step 115 100000000000000010000000000000000001110110011011011010101100110111 step 116 100000000000000010000000000000000001110110011011011010100100110111 step 117 100000000000000010000000000000000001110110011011011010100101110101 step 118 100000000000000010000000000000000001110110011011011010100100110101 step 119 100000000000010010000000000000000000110111011011011010100100110101 step 120 100000000000010010000000000000000000110111011011011010101110110101 step 121 100000000000010010000000000000000000110111011011011010100110110101 step 122 100000000000010010000000000000000000110111011011011010100111110111 step 123 100000000000010010000000000000000000110111011011011010100110110111 step 124 100000000000000010000000000000000001110110011011011010100110110111 step 125 100000000000000000000000000000000001111100011011011010100110110111 step 126 100000000000000000000000000000000001111100011011011010100110110111 step 127 100001000000000000000000000000000001111100011011011010100110110111 step 128 100001100000000000000000000000000001111100011011011010100110110111 step 129 100001100100000000000000000000000001111100011011011010100110110111 step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ step 183 100000000000000000000000000000000001111100011011011010100110100101 step 184 100000000000000000000000000000000001111100011011011010100110100101 step 185 100000000000000000000000000000000001111100011011011010100110101001 step 186 100000000000000000000000000000000001111100011011011010100110100001 step 187 100000000000000000000000000000000001111100011011011010100110000101 step 188 100000000000000000000000000000000001111100011011011010100110100001 step 189 100000000000000000000000000000000001111100011011011010100110100001 step 190 100000000000000000000000000000000001111100011011011010100110101001 step 191 100000000000000000000000000000000001111100011011011010100110100001 step 192 100000000000000000000000000000000001111100011011011010100110110001 step 193 100000000000000000000000000000000001111100011011011010100110111011 step 194 100000000000000000000000000000000001111100011011011010100110110011 step 195 100000000000000000000000000000000001111100011011011010100110110011 step 196 100000000000000000000000000000000001111100011011011010100110111111 step 197 100000000000000000000000000000000001111100011011011010100110110111 step 198 100000000000000000000000000000000001111100011011011010100110110111 step 199 100000000000000000000000000000000001111100011011011010100110111111 step 200 100000000000000000000000000000000001111100011011011010100110110111 step 201 100000000000000000000000000000000001111100011011011010100110100111 step 202 100000000000000000000000000000000001111100011011011010100110101101 step 203 100000000000000000000000000000000001111100011011011010100110100101 step 204 100000000000000000000000000000000001111100011011011010100110110101 step 205 100000000000000000000000000000000001111100011011011010100110111011 step 206 100000000000000000000000000000000001111100011011011010100110110011 step 207 100000000000000000000000000000000001111100011011011010100110100011 step 208 100000000000000000000000000000000001111100011011011010100110101101 step 209 100000000000000000000000000000000001111100011011011010100110100101 step 210 100000000000000000000000000000000001111100011011011010100110110101 step 211 100000000000000000000000000000000001111100011011011010100110111011 step 212 100000000000000000000000000000000001111100011011011010100110110011 step 213 100000000000000000000000000000000001111100011011011010100110110011 step 214 100000000000000000000000000000000001111100011011011010100110111111 step 215 100000000000000000000000000000000001111100011011011010100110110111 step 216 100000000000000000000000000000000001111100011011011010100110110111 test 1: *** FAIL *************************** 1 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 66 O BU2 +3.5V space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO fails LO: fails LO: fails HI: 1 11111 11 11 11 1 1 11 1 fails HI: 0000000000000000000000000000000000 000 0 0 0 0 00 0000 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 0 Main menu Thu Jun 29 19:05:05 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:05:06 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100000010000001010000110001 step 2 100000000000000000000000000000000001111100100010000001010000110001 step 3 100000000000000000000000000000000001111100000010000001010000110001 step 4 100000000000000000000000000000000001111100000100000001010000110001 step 5 100000000000000000000000000000000001111100000000000001010000110001 step 6 100000000000000000000000000000000001111100000000100001010000110001 step 7 100000000000000000000000000000000001111100000000000001010000110001 step 8 100000000000000000000000000000000001111100000000000101010000110001 step 9 100000000000000000000000000000000001111100000000000001010000110001 step 10 100000000000000000000000000000000001111100000000000001011000110001 step 11 100000000000000000000000000000000001111100000000000001010000110001 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 step 40 100000000000000010000000000000000001110110011011011010100110110111 step 41 100000000000000010000000000000000001110110110011011010100110110111 step 42 100000000000000010000000000000000001110110010011011010100110110111 step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 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100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ step 183 100000000000000000000000000000000001111100011011011010100110100101 step 184 100000000000000000000000000000000001111100011011011010100110100101 step 185 100000000000000000000000000000000001111100011011011010100110101001 step 186 100000000000000000000000000000000001111100011011011010100110100001 step 187 100000000000000000000000000000000001111100011011011010100110000101 step 188 100000000000000000000000000000000001111100011011011010100110100001 step 189 100000000000000000000000000000000001111100011011011010100110100001 step 190 100000000000000000000000000000000001111100011011011010100110101001 step 191 100000000000000000000000000000000001111100011011011010100110100001 step 192 100000000000000000000000000000000001111100011011011010100110110001 step 193 100000000000000000000000000000000001111100011011011010100110111011 step 194 100000000000000000000000000000000001111100011011011010100110110011 step 195 100000000000000000000000000000000001111100011011011010100110110011 step 196 100000000000000000000000000000000001111100011011011010100110111111 step 197 100000000000000000000000000000000001111100011011011010100110110111 step 198 100000000000000000000000000000000001111100011011011010100110110111 step 199 100000000000000000000000000000000001111100011011011010100110111111 step 200 100000000000000000000000000000000001111100011011011010100110110111 step 201 100000000000000000000000000000000001111100011011011010100110100111 step 202 100000000000000000000000000000000001111100011011011010100110101101 step 203 100000000000000000000000000000000001111100011011011010100110100101 step 204 100000000000000000000000000000000001111100011011011010100110110101 step 205 100000000000000000000000000000000001111100011011011010100110111011 step 206 100000000000000000000000000000000001111100011011011010100110110011 step 207 100000000000000000000000000000000001111100011011011010100110100011 step 208 100000000000000000000000000000000001111100011011011010100110101101 step 209 100000000000000000000000000000000001111100011011011010100110100101 step 210 100000000000000000000000000000000001111100011011011010100110110101 step 211 100000000000000000000000000000000001111100011011011010100110111011 step 212 100000000000000000000000000000000001111100011011011010100110110011 step 213 100000000000000000000000000000000001111100011011011010100110110011 step 214 100000000000000000000000000000000001111100011011011010100110111111 step 215 100000000000000000000000000000000001111100011011011010100110110111 step 216 100000000000000000000000000000000001111100011011011010100110110111 test 1: *** FAIL *************************** 1 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 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100000000000000010000000000000000001110110011011011010100110110111 step 97 100000000000000010000000000000000001110110011011011010101100110111 step 98 100000000000000010000000000000000001110110011011011010100100110111 step 99 100000000000010010000000000000000000110111011011011010100100110111 step 100 100000000000010010000000000000000000110111011011011010101110110111 step 101 100000000000010010000000000000000000110111011011011010100110110111 step 102 100000000000010000000000000000000000111101011011011010100110110111 step 103 100000000000010000000000000000000000111101011011011010100110110111 step 104 100000000000010000000000000000000000111101011011011010101010110111 step 105 100000000000010000000000000000000000111101011011011010100010110111 step 106 100000000000010000000000000000000000111101011011011010100011110011 step 107 100000000000010000000000000000000000111101011011011010100010110011 step 108 100000000000010010000000000000000000110111011011011010100010110011 step 109 100000000000010010000000000000000000110111011011011010101110110011 step 110 100000000000010010000000000000000000110111011011011010100110110011 step 111 100000000000010010000000000000000000110111011011011010100111110111 step 112 100000000000010010000000000000000000110111011011011010100110110111 step 113 100000000000010010000000000000000000110111011011011010100110110111 step 114 100000000000000010000000000000000001110110011011011010100110110111 step 115 100000000000000010000000000000000001110110011011011010101100110111 step 116 100000000000000010000000000000000001110110011011011010100100110111 step 117 100000000000000010000000000000000001110110011011011010100101110101 step 118 100000000000000010000000000000000001110110011011011010100100110101 step 119 100000000000010010000000000000000000110111011011011010100100110101 step 120 100000000000010010000000000000000000110111011011011010101110110101 step 121 100000000000010010000000000000000000110111011011011010100110110101 step 122 100000000000010010000000000000000000110111011011011010100111110111 step 123 100000000000010010000000000000000000110111011011011010100110110111 step 124 100000000000000010000000000000000001110110011011011010100110110111 step 125 100000000000000000000000000000000001111100011011011010100110110111 step 126 100000000000000000000000000000000001111100011011011010100110110111 step 127 100001000000000000000000000000000001111100011011011010100110110111 step 128 100001100000000000000000000000000001111100011011011010100110110111 step 129 100001100100000000000000000000000001111100011011011010100110110111 step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 0 Main menu Thu Jun 29 19:09:01 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:12:33 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100000000000001010000110001 step 2 100000000000000000000000000000000001111100100000000001010000110001 step 3 100000000000000000000000000000000001111100000000000001010000110001 step 4 100000000000000000000000000000000001111100000100000001010000110001 step 5 100000000000000000000000000000000001111100000000000001010000110001 step 6 100000000000000000000000000000000001111100000000100001010000110001 step 7 100000000000000000000000000000000001111100000000000001010000110001 step 8 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100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ step 183 100000000000000000000000000000000001111100011011011010100110100101 step 184 100000000000000000000000000000000001111100011011011010100110100101 step 185 100000000000000000000000000000000001111100011011011010100110101001 step 186 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100000000000000000000000000000000001111100011011011010100110110011 step 213 100000000000000000000000000000000001111100011011011010100110110011 step 214 100000000000000000000000000000000001111100011011011010100110111111 step 215 100000000000000000000000000000000001111100011011011010100110110111 step 216 100000000000000000000000000000000001111100011011011010100110110111 test 1: *** FAIL *************************** 1 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011011011010100110110111 step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 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100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 0 Main menu Thu Jun 29 19:13:48 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:13:50 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100010000000001010100110101 step 2 100000000000000000000000000000000001111100100000000001010100110101 step 3 100000000000000000000000000000000001111100000000000001010100110101 step 4 100000000000000000000000000000000001111100000100000001010100110101 step 5 100000000000000000000000000000000001111100000000000001010100110101 step 6 100000000000000000000000000000000001111100000000100001010100110101 step 7 100000000000000000000000000000000001111100000000000001010100110101 step 8 100000000000000000000000000000000001111100000000000101010100110101 step 9 100000000000000000000000000000000001111100000000000001010100110101 step 10 100000000000000000000000000000000001111100000000000001011000110101 step 11 100000000000000000000000000000000001111100000000000001010000110101 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 step 40 100000000000000010000000000000000001110110011011011010100110110111 step 41 100000000000000010000000000000000001110110110011011010100110110111 step 42 100000000000000010000000000000000001110110010011011010100110110111 step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010000000000000000000000111101011011011010100110110111 step 47 100000000000010000000000000000000000111101011011011010100110110111 step 48 100000000000010000000000000000000000111101011101011010100110110111 step 49 100000000000010000000000000000000000111101011001011010100110110111 step 50 100000000000010010000000000000000000110111011001011010100110110111 step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 step 54 100000000000000010000000000000000001110110011011011010100110110111 step 55 100000000000000010000000000000000001110110011110011010100110110111 step 56 100000000000000010000000000000000001110110011010011010100110110111 step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 step 60 100000000000010000000000000000000000111101011011011010100110110111 step 61 100000000000010000000000000000000000111101011011011010100110110111 step 62 100000000000010000000000000000000000111101011011101010100110110111 step 63 100000000000010000000000000000000000111101011011001010100110110111 step 64 100000000000010010000000000000000000110111011011001010100110110111 step 65 100000000000010010000000000000000000110111011011111010100110110111 step 66 100000000000010010000000000000000000110111011011011010100110110111 step 67 100000000000010010000000000000000000110111011011011010100110110111 step 68 100000000000000010000000000000000001110110011011011010100110110111 step 69 100000000000000010000000000000000001110110011011110010100110110111 step 70 100000000000000010000000000000000001110110011011010010100110110111 step 71 100000000000010010000000000000000000110111011011010010100110110111 step 72 100000000000010010000000000000000000110111011011111010100110110111 step 73 100000000000010010000000000000000000110111011011011010100110110111 step 74 100000000000010000000000000000000000111101011011011010100110110111 step 75 100000000000010000000000000000000000111101011011011010100110110111 step 76 100000000000010000000000000000000000111101011011011101100110110111 step 77 100000000000010000000000000000000000111101011011011001100110110111 step 78 100000000000010010000000000000000000110111011011011001100110110111 step 79 100000000000010010000000000000000000110111011011011110100110110111 step 80 100000000000010010000000000000000000110111011011011010100110110111 step 81 100000000000010010000000000000000000110111011011011010100110110111 step 82 100000000000000010000000000000000001110110011011011010100110110111 step 83 100000000000000010000000000000000001110110011011011110010110110111 step 84 100000000000000010000000000000000001110110011011011010010110110111 step 85 100000000000010010000000000000000000110111011011011010010110110111 step 86 100000000000010010000000000000000000110111011011011110100110110111 step 87 100000000000010010000000000000000000110111011011011010100110110111 step 88 100000000000010000000000000000000000111101011011011010100110110111 step 89 100000000000010000000000000000000000111101011011011010100110110111 step 90 100000000000010000000000000000000000111101011011011010101010110111 step 91 100000000000010000000000000000000000111101011011011010100010110111 step 92 100000000000010010000000000000000000110111011011011010100010110111 step 93 100000000000010010000000000000000000110111011011011010101110110111 step 94 100000000000010010000000000000000000110111011011011010100110110111 step 95 100000000000010010000000000000000000110111011011011010100110110111 step 96 100000000000000010000000000000000001110110011011011010100110110111 step 97 100000000000000010000000000000000001110110011011011010101100110111 step 98 100000000000000010000000000000000001110110011011011010100100110111 step 99 100000000000010010000000000000000000110111011011011010100100110111 step 100 100000000000010010000000000000000000110111011011011010101110110111 step 101 100000000000010010000000000000000000110111011011011010100110110111 step 102 100000000000010000000000000000000000111101011011011010100110110111 step 103 100000000000010000000000000000000000111101011011011010100110110111 step 104 100000000000010000000000000000000000111101011011011010101010110111 step 105 100000000000010000000000000000000000111101011011011010100010110111 step 106 100000000000010000000000000000000000111101011011011010100011110011 step 107 100000000000010000000000000000000000111101011011011010100010110011 step 108 100000000000010010000000000000000000110111011011011010100010110011 step 109 100000000000010010000000000000000000110111011011011010101110110011 step 110 100000000000010010000000000000000000110111011011011010100110110011 step 111 100000000000010010000000000000000000110111011011011010100111110111 step 112 100000000000010010000000000000000000110111011011011010100110110111 step 113 100000000000010010000000000000000000110111011011011010100110110111 step 114 100000000000000010000000000000000001110110011011011010100110110111 step 115 100000000000000010000000000000000001110110011011011010101100110111 step 116 100000000000000010000000000000000001110110011011011010100100110111 step 117 100000000000000010000000000000000001110110011011011010100101110101 step 118 100000000000000010000000000000000001110110011011011010100100110101 step 119 100000000000010010000000000000000000110111011011011010100100110101 step 120 100000000000010010000000000000000000110111011011011010101110110101 step 121 100000000000010010000000000000000000110111011011011010100110110101 step 122 100000000000010010000000000000000000110111011011011010100111110111 step 123 100000000000010010000000000000000000110111011011011010100110110111 step 124 100000000000000010000000000000000001110110011011011010100110110111 step 125 100000000000000000000000000000000001111100011011011010100110110111 step 126 100000000000000000000000000000000001111100011011011010100110110111 step 127 100001000000000000000000000000000001111100011011011010100110110111 step 128 100001100000000000000000000000000001111100011011011010100110110111 step 129 100001100100000000000000000000000001111100011011011010100110110111 step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 183 100000000000000000000000000000000001111100011011011010100110100101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 184 100000000000000000000000000000000001111100011011011010100110100101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 185 100000000000000000000000000000000001111100011011011010100110101001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 186 100000000000000000000000000000000001111100011011011010100110100001 step 187 100000000000000000000000000000000001111100011011011010100110000101 step 188 100000000000000000000000000000000001111100011011011010100110100001 step 189 100000000000000000000000000000000001111100011011011010100110100001 step 190 100000000000000000000000000000000001111100011011011010100110101001 step 191 100000000000000000000000000000000001111100011011011010100110100001 step 192 100000000000000000000000000000000001111100011011011010100110110001 step 193 100000000000000000000000000000000001111100011011011010100110111011 step 194 100000000000000000000000000000000001111100011011011010100110110011 step 195 100000000000000000000000000000000001111100011011011010100110110011 step 196 100000000000000000000000000000000001111100011011011010100110111111 step 197 100000000000000000000000000000000001111100011011011010100110110111 step 198 100000000000000000000000000000000001111100011011011010100110110111 step 199 100000000000000000000000000000000001111100011011011010100110111111 step 200 100000000000000000000000000000000001111100011011011010100110110111 step 201 100000000000000000000000000000000001111100011011011010100110100111 step 202 100000000000000000000000000000000001111100011011011010100110101101 step 203 100000000000000000000000000000000001111100011011011010100110100101 step 204 100000000000000000000000000000000001111100011011011010100110110101 step 205 100000000000000000000000000000000001111100011011011010100110111011 step 206 100000000000000000000000000000000001111100011011011010100110110011 step 207 100000000000000000000000000000000001111100011011011010100110100011 step 208 100000000000000000000000000000000001111100011011011010100110101101 step 209 100000000000000000000000000000000001111100011011011010100110100101 step 210 100000000000000000000000000000000001111100011011011010100110110101 step 211 100000000000000000000000000000000001111100011011011010100110111011 step 212 100000000000000000000000000000000001111100011011011010100110110011 step 213 100000000000000000000000000000000001111100011011011010100110110011 step 214 100000000000000000000000000000000001111100011011011010100110111111 step 215 100000000000000000000000000000000001111100011011011010100110110111 step 216 100000000000000000000000000000000001111100011011011010100110110111 test 1: *** FAIL *************************** 1 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O all fails O was hi 111111111111111111111111111111111111111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000000000 0000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 1 100000000000000000000000000000000001111100011011011010100110110111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 2 100000000000000000000000000000000001111100100011011010100110110111 step 3 100000000000000000000000000000000001111100000011011010100110110111 step 4 100000000000000000000000000000000001111100000100011010100110110111 step 5 100000000000000000000000000000000001111100000000011010100110110111 step 6 100000000000000000000000000000000001111100000000100010100110110111 step 7 100000000000000000000000000000000001111100000000000010100110110111 step 8 100000000000000000000000000000000001111100000000000101010110110111 step 9 100000000000000000000000000000000001111100000000000001010110110111 step 10 100000000000000000000000000000000001111100000000000001011000110111 step 11 100000000000000000000000000000000001111100000000000001010000110111 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 step 40 100000000000000010000000000000000001110110011011011010100110110111 step 41 100000000000000010000000000000000001110110110011011010100110110111 step 42 100000000000000010000000000000000001110110010011011010100110110111 step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010000000000000000000000111101011011011010100110110111 step 47 100000000000010000000000000000000000111101011011011010100110110111 step 48 100000000000010000000000000000000000111101011101011010100110110111 step 49 100000000000010000000000000000000000111101011001011010100110110111 step 50 100000000000010010000000000000000000110111011001011010100110110111 step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 step 54 100000000000000010000000000000000001110110011011011010100110110111 step 55 100000000000000010000000000000000001110110011110011010100110110111 step 56 100000000000000010000000000000000001110110011010011010100110110111 step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 step 60 100000000000010000000000000000000000111101011011011010100110110111 step 61 100000000000010000000000000000000000111101011011011010100110110111 step 62 100000000000010000000000000000000000111101011011101010100110110111 step 63 100000000000010000000000000000000000111101011011001010100110110111 step 64 100000000000010010000000000000000000110111011011001010100110110111 step 65 100000000000010010000000000000000000110111011011111010100110110111 step 66 100000000000010010000000000000000000110111011011011010100110110111 step 67 100000000000010010000000000000000000110111011011011010100110110111 step 68 100000000000000010000000000000000001110110011011011010100110110111 step 69 100000000000000010000000000000000001110110011011110010100110110111 step 70 100000000000000010000000000000000001110110011011010010100110110111 step 71 100000000000010010000000000000000000110111011011010010100110110111 step 72 100000000000010010000000000000000000110111011011111010100110110111 step 73 100000000000010010000000000000000000110111011011011010100110110111 step 74 100000000000010000000000000000000000111101011011011010100110110111 step 75 100000000000010000000000000000000000111101011011011010100110110111 step 76 100000000000010000000000000000000000111101011011011101100110110111 step 77 100000000000010000000000000000000000111101011011011001100110110111 step 78 100000000000010010000000000000000000110111011011011001100110110111 step 79 100000000000010010000000000000000000110111011011011110100110110111 step 80 100000000000010010000000000000000000110111011011011010100110110111 step 81 100000000000010010000000000000000000110111011011011010100110110111 step 82 100000000000000010000000000000000001110110011011011010100110110111 step 83 100000000000000010000000000000000001110110011011011110010110110111 step 84 100000000000000010000000000000000001110110011011011010010110110111 step 85 100000000000010010000000000000000000110111011011011010010110110111 step 86 100000000000010010000000000000000000110111011011011110100110110111 step 87 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100000000000010010000000000000000000110111011011011010100110110111 step 114 100000000000000010000000000000000001110110011011011010100110110111 step 115 100000000000000010000000000000000001110110011011011010101100110111 step 116 100000000000000010000000000000000001110110011011011010100100110111 step 117 100000000000000010000000000000000001110110011011011010100101110101 step 118 100000000000000010000000000000000001110110011011011010100100110101 step 119 100000000000010010000000000000000000110111011011011010100100110101 step 120 100000000000010010000000000000000000110111011011011010101110110101 step 121 100000000000010010000000000000000000110111011011011010100110110101 step 122 100000000000010010000000000000000000110111011011011010100111110111 step 123 100000000000010010000000000000000000110111011011011010100110110111 step 124 100000000000000010000000000000000001110110011011011010100110110111 step 125 100000000000000000000000000000000001111100011011011010100110110111 step 126 100000000000000000000000000000000001111100011011011010100110110111 step 127 100001000000000000000000000000000001111100011011011010100110110111 step 128 100001100000000000000000000000000001111100011011011010100110110111 step 129 100001100100000000000000000000000001111100011011011010100110110111 step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 1, total passes 0 Main menu Thu Jun 29 19:27:58 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:27:59 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100000000000000000000000000000000001111100000000000001010000110001 step 2 100000000000000000000000000000000001111100100000000001010000110001 step 3 100000000000000000000000000000000001111100000000000001010000110001 step 4 100000000000000000000000000000000001111100000100000001010000110001 step 5 100000000000000000000000000000000001111100000000000001010000110001 step 6 100000000000000000000000000000000001111100000000100001010000110001 step 7 100000000000000000000000000000000001111100000000000001010000110001 step 8 100000000000000000000000000000000001111100000000000101010000110001 step 9 100000000000000000000000000000000001111100000000000001010000110001 step 10 100000000000000000000000000000000001111100000000000001011000110001 step 11 100000000000000000000000000000000001111100000000000001010000110001 step 12 100000000000000000000000000000000001111100000000000001010001110001 step 13 100000000000000000000000000000000001111100000000000001010000110001 step 14 100000000000000000000000000000000001111100000000000001010000110001 step 15 100000000000010000000000000000000000111101000000000001010000110001 step 16 100000000000010010000000000000000000110111000000000001010000110001 step 17 100000000000010010000000000000000000110111111000000001010000110001 step 18 100000000000010010000000000000000000110111011000000001010000110001 step 19 100000000000010010000000000000000000110111011111000001010000110001 step 20 100000000000010010000000000000000000110111011011000001010000110001 step 21 100000000000010010000000000000000000110111011011111001010000110001 step 22 100000000000010010000000000000000000110111011011011001010000110001 step 23 100000000000010010000000000000000000110111011011011110100000110001 step 24 100000000000010010000000000000000000110111011011011010100000110001 step 25 100000000000010010000000000000000000110111011011011010101110110001 step 26 100000000000010010000000000000000000110111011011011010100110110001 step 27 100000000000010010000000000000000000110111011011011010100111110111 step 28 100000000000010010000000000000000000110111011011011010100110110111 step 29 100000000000000010000000000000000001110110011011011010100110110111 step 30 100000000000000000000000000000000001111100011011011010100110110111 step 31 100000000000000000000000000000000001111100011011011010100110110111 step 32 100000000000000000000000000000000001111100011011011010100110110111 step 33 100000000000010000000000000000000000111101011011011010100110110111 step 34 100000000000010000000000000000000000111101101011011010100110110111 step 35 100000000000010000000000000000000000111101001011011010100110110111 step 36 100000000000010010000000000000000000110111001011011010100110110111 step 37 100000000000010010000000000000000000110111111011011010100110110111 step 38 100000000000010010000000000000000000110111011011011010100110110111 step 39 100000000000010010000000000000000000110111011011011010100110110111 step 40 100000000000000010000000000000000001110110011011011010100110110111 step 41 100000000000000010000000000000000001110110110011011010100110110111 step 42 100000000000000010000000000000000001110110010011011010100110110111 step 43 100000000000010010000000000000000000110111010011011010100110110111 step 44 100000000000010010000000000000000000110111111011011010100110110111 step 45 100000000000010010000000000000000000110111011011011010100110110111 step 46 100000000000010000000000000000000000111101011011011010100110110111 step 47 100000000000010000000000000000000000111101011011011010100110110111 step 48 100000000000010000000000000000000000111101011101011010100110110111 step 49 100000000000010000000000000000000000111101011001011010100110110111 step 50 100000000000010010000000000000000000110111011001011010100110110111 step 51 100000000000010010000000000000000000110111011111011010100110110111 step 52 100000000000010010000000000000000000110111011011011010100110110111 step 53 100000000000010010000000000000000000110111011011011010100110110111 step 54 100000000000000010000000000000000001110110011011011010100110110111 step 55 100000000000000010000000000000000001110110011110011010100110110111 step 56 100000000000000010000000000000000001110110011010011010100110110111 step 57 100000000000010010000000000000000000110111011010011010100110110111 step 58 100000000000010010000000000000000000110111011111011010100110110111 step 59 100000000000010010000000000000000000110111011011011010100110110111 step 60 100000000000010000000000000000000000111101011011011010100110110111 step 61 100000000000010000000000000000000000111101011011011010100110110111 step 62 100000000000010000000000000000000000111101011011101010100110110111 step 63 100000000000010000000000000000000000111101011011001010100110110111 step 64 100000000000010010000000000000000000110111011011001010100110110111 step 65 100000000000010010000000000000000000110111011011111010100110110111 step 66 100000000000010010000000000000000000110111011011011010100110110111 step 67 100000000000010010000000000000000000110111011011011010100110110111 step 68 100000000000000010000000000000000001110110011011011010100110110111 step 69 100000000000000010000000000000000001110110011011110010100110110111 step 70 100000000000000010000000000000000001110110011011010010100110110111 step 71 100000000000010010000000000000000000110111011011010010100110110111 step 72 100000000000010010000000000000000000110111011011111010100110110111 step 73 100000000000010010000000000000000000110111011011011010100110110111 step 74 100000000000010000000000000000000000111101011011011010100110110111 step 75 100000000000010000000000000000000000111101011011011010100110110111 step 76 100000000000010000000000000000000000111101011011011101100110110111 step 77 100000000000010000000000000000000000111101011011011001100110110111 step 78 100000000000010010000000000000000000110111011011011001100110110111 step 79 100000000000010010000000000000000000110111011011011110100110110111 step 80 100000000000010010000000000000000000110111011011011010100110110111 step 81 100000000000010010000000000000000000110111011011011010100110110111 step 82 100000000000000010000000000000000001110110011011011010100110110111 step 83 100000000000000010000000000000000001110110011011011110010110110111 step 84 100000000000000010000000000000000001110110011011011010010110110111 step 85 100000000000010010000000000000000000110111011011011010010110110111 step 86 100000000000010010000000000000000000110111011011011110100110110111 step 87 100000000000010010000000000000000000110111011011011010100110110111 step 88 100000000000010000000000000000000000111101011011011010100110110111 step 89 100000000000010000000000000000000000111101011011011010100110110111 step 90 100000000000010000000000000000000000111101011011011010101010110111 step 91 100000000000010000000000000000000000111101011011011010100010110111 step 92 100000000000010010000000000000000000110111011011011010100010110111 step 93 100000000000010010000000000000000000110111011011011010101110110111 step 94 100000000000010010000000000000000000110111011011011010100110110111 step 95 100000000000010010000000000000000000110111011011011010100110110111 step 96 100000000000000010000000000000000001110110011011011010100110110111 step 97 100000000000000010000000000000000001110110011011011010101100110111 step 98 100000000000000010000000000000000001110110011011011010100100110111 step 99 100000000000010010000000000000000000110111011011011010100100110111 step 100 100000000000010010000000000000000000110111011011011010101110110111 step 101 100000000000010010000000000000000000110111011011011010100110110111 step 102 100000000000010000000000000000000000111101011011011010100110110111 step 103 100000000000010000000000000000000000111101011011011010100110110111 step 104 100000000000010000000000000000000000111101011011011010101010110111 step 105 100000000000010000000000000000000000111101011011011010100010110111 step 106 100000000000010000000000000000000000111101011011011010100011110011 step 107 100000000000010000000000000000000000111101011011011010100010110011 step 108 100000000000010010000000000000000000110111011011011010100010110011 step 109 100000000000010010000000000000000000110111011011011010101110110011 step 110 100000000000010010000000000000000000110111011011011010100110110011 step 111 100000000000010010000000000000000000110111011011011010100111110111 step 112 100000000000010010000000000000000000110111011011011010100110110111 step 113 100000000000010010000000000000000000110111011011011010100110110111 step 114 100000000000000010000000000000000001110110011011011010100110110111 step 115 100000000000000010000000000000000001110110011011011010101100110111 step 116 100000000000000010000000000000000001110110011011011010100100110111 step 117 100000000000000010000000000000000001110110011011011010100101110101 step 118 100000000000000010000000000000000001110110011011011010100100110101 step 119 100000000000010010000000000000000000110111011011011010100100110101 step 120 100000000000010010000000000000000000110111011011011010101110110101 step 121 100000000000010010000000000000000000110111011011011010100110110101 step 122 100000000000010010000000000000000000110111011011011010100111110111 step 123 100000000000010010000000000000000000110111011011011010100110110111 step 124 100000000000000010000000000000000001110110011011011010100110110111 step 125 100000000000000000000000000000000001111100011011011010100110110111 step 126 100000000000000000000000000000000001111100011011011010100110110111 step 127 100001000000000000000000000000000001111100011011011010100110110111 step 128 100001100000000000000000000000000001111100011011011010100110110111 step 129 100001100100000000000000000000000001111100011011011010100110110111 step 130 100001100110000000000000000000000001111100011011011010100110110111 step 131 100001100110100000000000000000000001111100011011011010100110110111 step 132 100001100110100100000000000000000001111100011011011010100110110111 step 133 100001100110100100010000000000000001111100011011011010100110110111 step 134 100001100110100100011000000000000001111100011011011010100110110111 step 135 100001100110100100011010000000000001111100011011011010100110110111 step 136 100001100110100100011011000000000001111100011011011010100110110111 step 137 100001100110100100011011010000000001111100011011011010100110110111 step 138 100001100110100100011011011000000001111100011011011010100110110111 step 139 100001100110100100011011011010000001111100011011011010100110110111 step 140 100001100110100100011011011011000001111100011011011010100110110111 step 141 100001100110100100011011011011010001111100011011011010100110110111 step 142 100001100110100100011011011011011001111100011011011010100110110111 step 143 100001100110100100011011011011011101111100011011011010100110110111 step 144 110001100110100100011011011011011100110111011011011010100110110111 step 145 100001100110100100011011011011011101111100011011011010100110110111 step 146 101001100110100100011011011011011100110111011011011010100110110111 step 147 100001100110100100011011011011011101111100011011011010100110110111 step 148 100101100110100100011011011011011100110111011011011010100110110111 step 149 100001100110100100011011011011011101111100011011011010100110110111 step 150 100011100110100100011011011011011100110111011011011010100110110111 step 151 100001100110100100011011011011011101111100011011011010100110110111 step 152 100001110110100100011011011011011100110111011011011010100110110111 step 153 100001100110100100011011011011011101111100011011011010100110110111 step 154 100001101110100100011011011011011100110111011011011010100110110111 step 155 100001100110100100011011011011011101111100011011011010100110110111 step 156 100001100111100100011011011011011100111101011011011010100110110111 step 157 100001100110100100011011011011011101111100011011011010100110110111 step 158 100001100110110100011011011011011100111101011011011010100110110111 step 159 100001100110100100011011011011011101111100011011011010100110110111 step 160 100001100110101100011011011011011101110110011011011010100110110111 step 161 100001100110100100011011011011011101111100011011011010100110110111 step 162 100001100110100110011011011011011101110110011011011010100110110111 step 163 100001100110100100011011011011011101111100011011011010100110110111 step 164 100001100110100101011011011011011101001111011011011010100110110111 step 165 100001100110100100011011011011011101111100011011011010100110110111 step 166 100001100110100100111011011011011101001111011011011010100110110111 step 167 100001100110100100011011011011011101111100011011011010100110110111 step 168 100001100110100100011111011011011101001111011011011010100110110111 step 169 100001100110100100011011011011011101111100011011011010100110110111 step 170 100001100110100100011011111011011101001111011011011010100110110111 step 171 100001100110100100011011011011011101111100011011011010100110110111 step 172 100001100110100100011011011111011101001111011011011010100110110111 step 173 100001100110100100011011011011011101111100011011011010100110110111 step 174 100001100110100100011011011011111101001111011011011010100110110111 step 175 100001100110100100011011011011011101111100011011011010100110110111 step 176 100001100110100100011011011011011111101110011011011010100110110111 step 177 100001100110100100011011011011011101111100011011011010100110110111 step 178 100000000000000000000000000000000001111100011011011010100110110111 step 179 100000000000000000000000000000000001111100011011011010100110100111 step 180 100000000000000000000000000000000001111100011011011010100110101101 step 181 100000000000000000000000000000000001111100011011011010100110100101 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 182 100000000000000000000000000000000001111100011011011010100110000101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 183 100000000000000000000000000000000001111100011011011010100110100101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 184 100000000000000000000000000000000001111100011011011010100110100101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 185 100000000000000000000000000000000001111100011011011010100110101001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 186 100000000000000000000000000000000001111100011011011010100110100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 step 187 100000000000000000000000000000000001111100011011011010100110000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^ ^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 0 Main menu Thu Jun 29 19:29:59 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.TST reading test file: tests\7450.TST comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7410 PIN 1 1A pins: 2 I AS2 E1-15 7410 PIN 13 1B pins: 3 I AM2 E1-11 7410 PIN 9 1C pins: 4 I AN2 E1-12 7410 PIN 10 1D pins: 5 O AP2 E1-13 7410 PIN 11 X (EXPANDER) pins: 6 O AR2 E1-14 7410 PIN 12 X-N (EXPANDER) pins: 7 O AL2 E1-10 7410 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 8 I AB2 E1-2 7410 PIN 2 2A pins: 9 I AC1 E1-3 7410 PIN 3 2B pins: 10 I AD2 E1-4 7410 PIN 4 2C pins: 11 I AE2 E1-5 7410 PIN 5 2D pins: 12 O AF2 E1-6 7410 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 13 I AH2 E1-7 7410 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7410 PIN 14 VCC pins: direction: IIIIOOOIIIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: ; ALL INPUTS HI test 1: 11110 11110 error: the first 'test step' is too short error: it must set EVERY column expected 'test step' (16 columns of '0','1','X', or ' ') bad test file Main menu Thu Jun 29 19:51:33 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.TST reading test file: tests\7450.TST comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7410 PIN 1 1A pins: 2 I AS2 E1-15 7410 PIN 13 1B pins: 3 I AM2 E1-11 7410 PIN 9 1C pins: 4 I AN2 E1-12 7410 PIN 10 1D pins: 5 O AP2 E1-13 7410 PIN 11 X (EXPANDER) pins: 6 O AR2 E1-14 7410 PIN 12 X-N (EXPANDER) pins: 7 O AL2 E1-10 7410 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 8 I AB2 E1-2 7410 PIN 2 2A pins: 9 I AC1 E1-3 7410 PIN 3 2B pins: 10 I AD2 E1-4 7410 PIN 4 2C pins: 11 I AE2 E1-5 7410 PIN 5 2D pins: 12 O AF2 E1-6 7410 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 13 I AH2 E1-7 7410 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7410 PIN 14 VCC pins: direction: IIIIOOOIIIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 00001XX00001XXXX comment: comment: ; ALL INPUTS HI test 2: 11110 11110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 01 1 test 4: 00 1 test 5: 10 1 test 6: 11 0 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 01 1 test 12: 00 1 test 13: 10 1 test 14: 11 0 test 15: 011 test 16: 001 test 17: 101 test 18: 110 'test step' is too long expected 'test step' (16 columns of '0','1','X', or ' ') bad test file Main menu Thu Jun 29 19:52:27 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.TST reading test file: tests\7450.TST comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7410 PIN 1 1A pins: 2 I AS2 E1-15 7410 PIN 13 1B pins: 3 I AM2 E1-11 7410 PIN 9 1C pins: 4 I AN2 E1-12 7410 PIN 10 1D pins: 5 O AP2 E1-13 7410 PIN 11 X (EXPANDER) pins: 6 O AR2 E1-14 7410 PIN 12 X-N (EXPANDER) pins: 7 O AL2 E1-10 7410 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 8 I AB2 E1-2 7410 PIN 2 2A pins: 9 I AC1 E1-3 7410 PIN 3 2B pins: 10 I AD2 E1-4 7410 PIN 4 2C pins: 11 I AE2 E1-5 7410 PIN 5 2D pins: 12 O AF2 E1-6 7410 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 13 I AH2 E1-7 7410 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7410 PIN 14 VCC pins: direction: IIIIOOOIIIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 00001XX00001XXXX comment: comment: ; ALL INPUTS HI test 2: 11110 11110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 01 1 test 4: 00 1 test 5: 10 1 test 6: 11 0 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 01 1 test 12: 00 1 test 13: 10 1 test 14: 11 0 test 15: 011 test 16: 001 test 17: 101 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 00001 00001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 011 test 25: 110 test 26: 101 test 27: 001 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 test 32: 011 test 33: 110 test 34: 101 test 35: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 1, mask 0x0002 column 8: offset 0, mask 0x0040 column 9: offset 0, mask 0x2000 column 10: offset 0, mask 0x0010 column 11: offset 0, mask 0x0008 column 12: offset 0, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 3: 0x2058 0x005C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 4: 0x2058 0x001C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 5: 0xA058 0x001C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 7: 0xA058 0x0058 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 8: 0xA058 0x0050 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 9: 0xA058 0x0054 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 11: 0xA01C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 12: 0x801C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 13: 0x805C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 15: 0xA04C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 16: 0xA044 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 17: 0xA054 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 19: 0x0004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 20: 0x0004 0x0050 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 21: 0x8004 0x0040 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 22: 0x8004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 23: 0x0004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 24: 0x0004 0x0018 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 25: 0x0004 0x000C 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 26: 0x0004 0x0014 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 27: 0x0004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 28: 0x2004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 29: 0x2040 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 30: 0x0044 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 31: 0x0004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 32: 0x000C 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 33: 0x0018 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 34: 0x0014 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 35: 0x0004 0x0010 0x0000 0x0000 0x0000 0x0003 0x00A3 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 82 lines 7450 TRIPLE 3-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Thu Jun 29 19:53:25 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:53:32 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 32 0000011000110000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 0 step 33 0000011001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 01 step 34 0000011001010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 35 0000011000010000 fail ^ test 56: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 56, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: step 1 0000011000010000 fail ^ step 2 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 3 0111000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 4 0011000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 5 1011000111100000 fail ^ step 6 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 7 1101000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 8 1100000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 9 1110000111100000 fail ^ step 10 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 11 1111000011100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 12 1111000001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 13 1111000101100000 fail ^ step 14 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 15 1111000110100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 16 1111000110000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 17 1111000111000000 fail ^ step 18 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0000 1100001 step 19 0000011000010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 20 0100011000010000 fail ^ step 21 1100000000010000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 11 step 22 1000011000010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 23 0000011000010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 24 0001011000010000 fail ^ step 25 0011000000010000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 11 step 26 0010011000010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 27 0000011000010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 28 0000011010010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 0 step 29 0000011110000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 1 step 30 0000011100010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 31 0000011000010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 32 0000011000110000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 0 step 33 0000011001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 01 step 34 0000011001010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 35 0000011000010000 fail ^ test 57: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 57, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: step 1 0000011000010000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails O O was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 57, total passes 0 Main menu Thu Jun 29 19:53:49 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.TST reading test file: tests\7450.TST comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7410 PIN 1 1A pins: 2 I AS2 E1-15 7410 PIN 13 1B pins: 3 I AM2 E1-11 7410 PIN 9 1C pins: 4 I AN2 E1-12 7410 PIN 10 1D pins: 5 O AP2 E1-13 7410 PIN 11 X (EXPANDER) pins: 6 O AR2 E1-14 7410 PIN 12 X-N (EXPANDER) pins: 7 O AL2 E1-10 7410 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 8 I AB2 E1-2 7410 PIN 2 2A pins: 9 I AC1 E1-3 7410 PIN 3 2B pins: 10 I AD2 E1-4 7410 PIN 4 2C pins: 11 I AE2 E1-5 7410 PIN 5 2D pins: 12 O AF2 E1-6 7410 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 13 I AH2 E1-7 7410 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7410 PIN 14 VCC pins: direction: IIIIOOOIIIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000XX100001XXXX comment: comment: ; ALL INPUTS HI test 2: 1111 011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 01 1 test 4: 00 1 test 5: 10 1 test 6: 11 0 test 7: 01 1 test 8: 00 1 test 9: 10 1 test 10: 11 0 test 11: 01 1 test 12: 00 1 test 13: 10 1 test 14: 11 0 test 15: 011 test 16: 001 test 17: 101 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 0000 100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 test 32: 011 test 33: 110 test 34: 101 test 35: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 1, mask 0x0002 column 8: offset 0, mask 0x0040 column 9: offset 0, mask 0x2000 column 10: offset 0, mask 0x0010 column 11: offset 0, mask 0x0008 column 12: offset 0, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 3: 0x2058 0x004E 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 4: 0x2058 0x000E 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 5: 0xA058 0x000E 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 7: 0xA058 0x004A 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 8: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 9: 0xA058 0x0046 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 11: 0xA01C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 12: 0x801C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 13: 0x805C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 15: 0xA04C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 16: 0xA044 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 17: 0xA054 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 19: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 20: 0x0004 0x0042 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 21: 0x8004 0x0040 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 22: 0x8004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 23: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 24: 0x0004 0x000A 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 25: 0x0004 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 26: 0x0004 0x0006 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 27: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 28: 0x2004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 29: 0x2040 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 30: 0x0044 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 31: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 32: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 33: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 34: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 82 lines 7450 TRIPLE 3-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Thu Jun 29 19:55:34 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0053 Main menu Thu Jun 29 19:55:35 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 19:55:41 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 16 1111000110000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 17 1111000111000000 fail ^ step 18 1111000111100000 step 19 0000011000010000 step 20 0100011000010000 step 21 1100000000010000 step 22 1000011000010000 step 23 0000011000010000 step 24 0001011000010000 step 25 0011000000010000 step 26 0010011000010000 step 27 0000011000010000 step 28 0000011010010000 step 29 0000011110000000 step 30 0000011100010000 step 31 0000011000010000 step 32 0000011000110000 step 33 0000011001100000 step 34 0000011001010000 step 35 0000011000010000 test 48: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 48, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000011000010000 step 2 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 3 0111000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 4 0011000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 5 1011000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 6 1111000111100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 7 1101000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 8 1100000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 9 1110000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 10 1111000111100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 11 1111000011100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 12 1111000001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 13 1111000101100000 fail ^ step 14 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 15 1111000110100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 16 1111000110000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 17 1111000111000000 fail ^ step 18 1111000111100000 step 19 0000011000010000 step 20 0100011000010000 step 21 1100000000010000 step 22 1000011000010000 step 23 0000011000010000 step 24 0001011000010000 step 25 0011000000010000 step 26 0010011000010000 step 27 0000011000010000 step 28 0000011010010000 step 29 0000011110000000 step 30 0000011100010000 step 31 0000011000010000 step 32 0000011000110000 step 33 0000011001100000 step 34 0000011001010000 step 35 0000011000010000 test 49: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 49, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000011000010000 step 2 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 3 0111000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 4 0011000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 5 1011000111100000 fail ^ step 6 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 7 1101000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 8 1100000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 9 1110000111100000 fail ^ step 10 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 11 1111000011100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 12 1111000001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 13 1111000101100000 fail ^ step 14 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 15 1111000110100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 16 1111000110000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 17 1111000111000000 fail ^ step 18 1111000111100000 step 19 0000011000010000 step 20 0100011000010000 step 21 1100000000010000 step 22 1000011000010000 step 23 0000011000010000 step 24 0001011000010000 step 25 0011000000010000 step 26 0010011000010000 step 27 0000011000010000 step 28 0000011010010000 step 29 0000011110000000 step 30 0000011100010000 step 31 0000011000010000 step 32 0000011000110000 step 33 0000011001100000 step 34 0000011001010000 step 35 0000011000010000 test 50: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 50, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000011000010000 step 2 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 3 0111000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails O O was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 50, total passes 0 Main menu Thu Jun 29 20:04:44 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.TST reading test file: tests\7450.TST comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7410 PIN 1 1A pins: 2 I AS2 E1-15 7410 PIN 13 1B pins: 3 I AM2 E1-11 7410 PIN 9 1C pins: 4 I AN2 E1-12 7410 PIN 10 1D pins: 5 O AP2 E1-13 7410 PIN 11 X (EXPANDER) pins: 6 O AR2 E1-14 7410 PIN 12 X-N (EXPANDER) pins: 7 O AL2 E1-10 7410 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 8 I AB2 E1-2 7410 PIN 2 2A pins: 9 I AC1 E1-3 7410 PIN 3 2B pins: 10 I AD2 E1-4 7410 PIN 4 2C pins: 11 I AE2 E1-5 7410 PIN 5 2D pins: 12 O AF2 E1-6 7410 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 13 I AH2 E1-7 7410 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7410 PIN 14 VCC pins: direction: IIIIOOOIIIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000XX100001XXXX comment: comment: ; ALL INPUTS HI test 2: 1111 011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 01 1 test 4: 00 1 test 5: 10 1 test 6: 11 0 test 7: 01 1 test 8: 00 1 test 9: 10 1 test 10: 11 0 test 11: 01 1 test 12: 00 1 test 13: 10 1 test 14: 11 0 test 15: 011 test 16: 001 test 17: 101 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 0000 100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 test 32: 011 test 33: 110 test 34: 101 test 35: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 1, mask 0x0002 column 8: offset 0, mask 0x0040 column 9: offset 0, mask 0x2000 column 10: offset 0, mask 0x0010 column 11: offset 0, mask 0x0008 column 12: offset 0, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 3: 0x2058 0x004E 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 4: 0x2058 0x000E 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 5: 0xA058 0x000E 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 7: 0xA058 0x004A 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 8: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 9: 0xA058 0x0046 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 11: 0xA01C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 12: 0x801C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 13: 0x805C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 15: 0xA04C 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 16: 0xA044 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 17: 0xA054 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 19: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 20: 0x0004 0x0042 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 21: 0x8004 0x0040 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 22: 0x8004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 23: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 24: 0x0004 0x000A 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 25: 0x0004 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 26: 0x0004 0x0006 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 27: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 28: 0x2004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 29: 0x2040 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 30: 0x0044 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 31: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 32: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 33: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 34: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 82 lines 7450 TRIPLE 3-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Thu Jun 29 20:04:50 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:04:51 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 35 0000011000010000 test 69: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 69, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000011000010000 step 2 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 3 0111000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 4 0011000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 5 1011000111100000 fail ^ step 6 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 7 1101000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 8 1100000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 9 1110000111100000 fail ^ step 10 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 11 1111000011100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 12 1111000001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 13 1111000101100000 fail ^ step 14 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 15 1111000110100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 16 1111000110000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 17 1111000111000000 fail ^ step 18 1111000111100000 step 19 0000011000010000 step 20 0100011000010000 step 21 1100000000010000 step 22 1000011000010000 step 23 0000011000010000 step 24 0001011000010000 step 25 0011000000010000 step 26 0010011000010000 step 27 0000011000010000 step 28 0000011010010000 step 29 0000011110000000 step 30 0000011100010000 step 31 0000011000010000 step 32 0000011000110000 step 33 0000011001100000 step 34 0000011001010000 step 35 0000011000010000 test 70: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 70, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000011000010000 step 2 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 3 0111000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 4 0011000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 5 1011000111100000 fail ^ step 6 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 7 1101000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 8 1100000111100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 9 1110000111100000 fail ^ step 10 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 11 1111000011100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 12 1111000001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 13 1111000101100000 fail ^ step 14 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 15 1111000110100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 16 1111000110000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 1 step 17 1111000111000000 fail ^ step 18 1111000111100000 step 19 0000011000010000 step 20 0100011000010000 step 21 1100000000010000 step 22 1000011000010000 step 23 0000011000010000 step 24 0001011000010000 step 25 0011000000010000 step 26 0010011000010000 step 27 0000011000010000 step 28 0000011010010000 step 29 0000011110000000 step 30 0000011100010000 step 31 0000011000010000 step 32 0000011000110000 step 33 0000011001100000 step 34 0000011001010000 step 35 0000011000010000 test 71: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII this fail O O all fails O O was hi 1111 1111111 rising ^^^^ ^^^^^^^ falling vvvv vvvvvvv was lo 0000000000000000 total fails 71, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000011000010000 step 2 1111000111100000 SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII changed: 0 step 3 0111000111100000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails O O was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 71, total passes 0 Main menu Thu Jun 29 20:06:08 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.TST reading test file: tests\7450.TST comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7410 PIN 1 1A pins: 2 I AS2 E1-15 7410 PIN 13 1B pins: 3 I AM2 E1-11 7410 PIN 9 1C pins: 4 I AN2 E1-12 7410 PIN 10 1D pins: 5 O AP2 E1-13 7410 PIN 11 X (EXPANDER) pins: 6 O AR2 E1-14 7410 PIN 12 X-N (EXPANDER) pins: 7 O AL2 E1-10 7410 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 8 I AB2 E1-2 7410 PIN 2 2A pins: 9 I AC1 E1-3 7410 PIN 3 2B pins: 10 I AD2 E1-4 7410 PIN 4 2C pins: 11 I AE2 E1-5 7410 PIN 5 2D pins: 12 O AF2 E1-6 7410 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 13 I AH2 E1-7 7410 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7410 PIN 14 VCC pins: direction: IIIIOOOIIIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000XX100001XXXX comment: comment: ; ALL INPUTS HI test 2: 1111 011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 01 0 test 4: 00 0 test 5: 10 0 test 6: 11 0 test 7: 01 0 test 8: 00 0 test 9: 10 0 test 10: 11 0 test 11: 01 0 test 12: 00 0 test 13: 10 0 test 14: 11 0 test 15: 010 test 16: 000 test 17: 100 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 0000 100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 test 32: 011 test 33: 110 test 34: 101 test 35: 001 comment: comment: ;**************************** comment: ; SHOULD TEST ALL 16 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 1, mask 0x0002 column 8: offset 0, mask 0x0040 column 9: offset 0, mask 0x2000 column 10: offset 0, mask 0x0010 column 11: offset 0, mask 0x0008 column 12: offset 0, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 3: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 5: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 7: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 8: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 9: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 11: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 12: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 13: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 15: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 16: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 17: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 19: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 20: 0x0004 0x0042 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 21: 0x8004 0x0040 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 22: 0x8004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 23: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 24: 0x0004 0x000A 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 25: 0x0004 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 26: 0x0004 0x0006 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 27: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 28: 0x2004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 29: 0x2040 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 30: 0x0044 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 31: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 32: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 33: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 34: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 88 lines 7450 TRIPLE 3-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Thu Jun 29 20:06:12 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:06:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 0, total passes 219 Main menu Thu Jun 29 20:06:19 2017 test file is: tests\7450.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m222.tst reading test file: tests\m222.tst comment: M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS comment: comment: TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. comment: comment: BUT... comment: comment: DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... comment: DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). comment: (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). comment: comment: SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. comment: WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; comment: THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). comment: AND THERE IS NO CARRY (C1-N IS HI). comment: comment: THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). comment: THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). comment: comment: POWER PINS: comment: +5v AA2, BA2 comment: GROUND AC2, AT1, BC2, BT1 comment: (ALL PINS ARE USED). comment: pins: PINS pins: 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 pins: 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) pins: 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) pins: 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) pins: 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) pins: 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). pins: 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) pins: 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) pins: 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) pins: 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). pins: 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) pins: 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) pins: 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) pins: 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) pins: 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) pins: 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) pins: 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) pins: 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) pins: 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) pins: 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). pins: 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) pins: 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) pins: 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) pins: 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) pins: 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), pins: 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) pins: 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) pins: 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), pins: 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) pins: 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) pins: 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT pins: 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT pins: 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT pins: 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT pins: 40 O AV2 CARRY OUT-N (E9-10 7482 C2) pins: 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) pins: 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) pins: 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 44 O AR1 TMA SETUP 2 pins: 45 O AH1 TMA SETUP 3 pins: 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 47 O AT2 TMA 2 pins: 48 O AD1 TMA 3 pins: 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 50 O AU1 TBN 2 pins: 51 O AK2 TBN 3 pins: 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 53 O AN1 TAC 2 pins: 54 O AJ2 TAC 2-N pins: 55 O AH2 TAC 3 pins: 56 O AB1 TAC 3-N pins: 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) pins: 58 O BP1 TB 2 pins: 59 O BD1 TB 3 pins: 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) pins: 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) pins: 62 I AV1 RWB IN (SHIFTED INTO RWB 3) pins: 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) pins: 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) pins: 65 O BD2 RWB 3 pins: 66 O BU2 +3.5V pins: direction: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO comment: ; all registers are unknown comment: ; turn on C0, PHASE comment: ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 test 1: 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers LOW comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; load TMA SETUP from tape bus (00) test 2: 100 test 3: 0 comment: ; load TMA from tape bus (00) test 4: 100 test 5: 0 comment: ; load TBN from tape bus (00) test 6: 100 test 7: 0 comment: ; load TAC from tape bus (00) test 8: 10101 test 9: 0 comment: ; load TB from tape bus (00) test 10: 100 test 11: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 12: 1 00 test 13: 0 comment: ; (no change) test 14: 100000000000000000000000000000000001111100000000000001010000110001 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; set all registers HIGH comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 15: 1 0 1 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 16: 1 0 1 comment: comment: comment: ; load TMA SETUP from tape bus (11) test 17: 111 test 18: 0 comment: ; load TMA from tape bus (11) test 19: 111 test 20: 0 comment: ; load TBN from tape bus (11) test 21: 111 test 22: 0 comment: ; load TAC from tape bus (11) test 23: 11010 test 24: 0 comment: ; load TB from tape bus (11) test 25: 111 test 26: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 27: 1 11 test 28: 0 comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 29: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 30: 0 1 0 comment: ; (no change) test 31: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; will all registers high, walk a 0 comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: comment: ; walk a 0, TMA SETUP 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 32: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 33: 1 0 1 comment: ; load TMA SETUP from tape bus (01) test 34: 101 test 35: 0 comment: ; restore TMA SETUP 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 36: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 37: 111 test 38: 0 comment: comment: comment: ; walk a 0, TMA SETUP 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 39: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 40: 0 1 0 comment: ; load TMA SETUP from tape bus (10) test 41: 110 test 42: 0 comment: ; restore TMA SETUP 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 43: 1 0 1 comment: ; load TMA SETUP from tape bus (11) test 44: 111 test 45: 0 comment: comment: comment: ; walk a 0, TMA 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 46: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 47: 1 0 1 comment: ; load TMA from tape bus (01) test 48: 101 test 49: 0 comment: ; restore TMA 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 50: 1 0 1 comment: ; load TMA from tape bus (11) test 51: 111 test 52: 0 comment: comment: comment: ; walk a 0, TMA 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 53: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 54: 0 1 0 comment: ; load TMA from tape bus (10) test 55: 110 test 56: 0 comment: ; restore TMA 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 57: 1 0 1 comment: ; load TMA from tape bus (11) test 58: 111 test 59: 0 comment: comment: comment: ; walk a 0, TBN 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 60: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 61: 1 0 1 comment: ; load TBN from tape bus (01) test 62: 101 test 63: 0 comment: ; restore TBN 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 64: 1 0 1 comment: ; load TBN from tape bus (11) test 65: 111 test 66: 0 comment: comment: comment: ; walk a 0, TBN 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 67: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 68: 0 1 0 comment: ; load TBN from tape bus (10) test 69: 110 test 70: 0 comment: ; restore TBN 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 71: 1 0 1 comment: ; load TBN from tape bus (11) test 72: 111 test 73: 0 comment: comment: comment: ; walk a 0, TAC 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 74: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 75: 1 0 1 comment: ; load TAC from tape bus (01) test 76: 10110 test 77: 0 comment: ; restore TAC 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 78: 1 0 1 comment: ; load TAC from tape bus (11) test 79: 11010 test 80: 0 comment: comment: comment: ; walk a 0, TAC 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 81: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 82: 0 1 0 comment: ; load TAC from tape bus (10) test 83: 11001 test 84: 0 comment: ; restore TAC 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 85: 1 0 1 comment: ; load TAC from tape bus (11) test 86: 11010 test 87: 0 comment: comment: comment: ; walk a 0, TB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 88: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 89: 1 0 1 comment: ; load TB from tape bus (01) test 90: 101 test 91: 0 comment: ; restore TB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 92: 1 0 1 comment: ; load TB from tape bus (11) test 93: 111 test 94: 0 comment: comment: comment: ; walk a 0, TB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 95: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 96: 0 1 0 comment: ; load TB from tape bus (10) test 97: 110 test 98: 0 comment: ; restore TB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 99: 1 0 1 comment: ; load TB from tape bus (11) test 100: 111 test 101: 0 comment: comment: comment: ; walk a 0, RWB 2 comment: comment: comment: ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT test 102: 0 1 0 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 103: 1 0 1 comment: ; load TB from tape bus (01) test 104: 101 test 105: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 106: 1 01 test 107: 0 comment: ; restore TB 2 and RWB 2 comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 108: 1 0 1 comment: ; load TB from tape bus (11) test 109: 111 test 110: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 111: 1 11 test 112: 0 comment: comment: comment: ; walk a 0, RWB 3 comment: comment: comment: ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT test 113: 1 0 1 comment: ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT test 114: 0 1 0 comment: ; load TB from tape bus (10) test 115: 110 test 116: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 117: 1 10 test 118: 0 comment: ; restore TB 3 and RWB 3 comment: ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT test 119: 1 0 1 comment: ; load TB from tape bus (11) test 120: 111 test 121: 0 comment: ; load RWB from TB (JAMS CLEAR AND PRESET) test 122: 1 11 test 123: 0 comment: comment: ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT test 124: 0 1 0 comment: ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT test 125: 0 1 0 comment: ; (no change) test 126: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;********************* need to walk a one ********************** comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; comment: ; test AND-NOR logic comment: ; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; (all registers are HIGH) comment: ; set all pins HIGH except ENABLES comment: comment: ; set pin AF2 HIGH test 127: 1 comment: ; set pin AM1 HIGH test 128: 1 comment: ; set pin AE1 HIGH test 129: 1 comment: ; set pin AM2 HIGH test 130: 1 comment: ; set pin AB2 HIGH test 131: 1 comment: ; set pin AS1 HIGH test 132: 1 comment: ; set pin BE1 HIGH test 133: 1 comment: ; set pin BM1 HIGH test 134: 1 comment: ; set pin BH1 HIGH test 135: 1 comment: ; set pin BR1 HIGH test 136: 1 comment: ; set pin BC1 HIGH test 137: 1 comment: ; set pin BJ2 HIGH test 138: 1 comment: ; set pin BJ1 HIGH test 139: 1 comment: ; set pin BK2 HIGH test 140: 1 comment: ; set pin BH2 HIGH test 141: 1 comment: ; set pin BP2 HIGH test 142: 1 comment: ; set pin BN2 HIGH test 143: 1 comment: ; toggle each ENABLE comment: comment: ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 144: 1 0 0 11 test 145: 0 1 1 00 comment: ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 146: 1 0 0 11 test 147: 0 1 1 00 comment: ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 148: 1 0 0 11 test 149: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 150: 1 0 0 11 test 151: 0 1 1 00 comment: ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 152: 1 0 0 11 test 153: 0 1 1 00 comment: ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 154: 1 0 0 11 test 155: 0 1 1 00 comment: ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 156: 1 0 1 test 157: 0 1 0 comment: ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT test 158: 1 0 1 test 159: 0 1 0 comment: ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 160: 1 0 1 test 161: 0 1 0 comment: ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT test 162: 1 0 1 test 163: 0 1 0 comment: comment: ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 164: 1 00 11 test 165: 0 11 00 comment: ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 166: 1 00 11 test 167: 0 11 00 comment: ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 168: 1 00 11 test 169: 0 11 00 comment: ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 170: 1 00 11 test 171: 0 11 00 comment: ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 172: 1 00 11 test 173: 0 11 00 comment: ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT test 174: 1 00 11 test 175: 0 11 00 comment: ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT test 176: 1 0 1 test 177: 0 1 0 comment: ; no change test 178: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; test shifting the RWB comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: comment: ; shift in 0, expect 10 test 179: 0 test 180: 110 test 181: 0 comment: ; toggle phase should toggle RWB 2 test 182: 0 0 test 183: 1 1 comment: comment: ; shift in 0, expect 00 test 184: 0 test 185: 100 test 186: 0 comment: ; toggle phase should toggle RWB 2 test 187: 0 1 test 188: 1 0 comment: comment: ; shift in 0, expect 00 test 189: 0 test 190: 100 test 191: 0 comment: ; shift in 1, expect 01 test 192: 1 test 193: 101 test 194: 0 comment: ; shift in 1, expect 11 test 195: 1 test 196: 111 test 197: 0 comment: ; shift in 1, expect 11 test 198: 1 test 199: 111 test 200: 0 comment: ; shift in 0, expect 10 test 201: 0 test 202: 110 test 203: 0 comment: ; shift in 1, expect 01 test 204: 1 test 205: 101 test 206: 0 comment: ; shift in 0, expect 10 test 207: 0 test 208: 110 test 209: 0 comment: ; shift in 1, expect 01 test 210: 1 test 211: 101 test 212: 0 comment: ; shift in 1, expect 11 test 213: 1 test 214: 111 test 215: 0 comment: ; no change test 216: 100000000000000000000000000000000001111100011011011010100110110111 comment: comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ; needs work (more adder tests, more register tests) comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; comment: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end: END summary column 1: offset 2, mask 0x2000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0800 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x4000 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0800 column 11: offset 1, mask 0x0004 column 12: offset 0, mask 0x2000 column 13: offset 0, mask 0x0040 column 14: offset 0, mask 0x0400 column 15: offset 1, mask 0x0020 column 16: offset 1, mask 0x0200 column 17: offset 1, mask 0x0010 column 18: offset 3, mask 0x2000 column 19: offset 3, mask 0x1000 column 20: offset 2, mask 0x0200 column 21: offset 3, mask 0x0800 column 22: offset 2, mask 0x0100 column 23: offset 3, mask 0x8000 column 24: offset 3, mask 0x0100 column 25: offset 4, mask 0x8000 column 26: offset 2, mask 0x0800 column 27: offset 3, mask 0x0002 column 28: offset 3, mask 0x0008 column 29: offset 3, mask 0x4000 column 30: offset 3, mask 0x0004 column 31: offset 4, mask 0x2000 column 32: offset 3, mask 0x0001 column 33: offset 3, mask 0x0040 column 34: offset 3, mask 0x0020 column 35: offset 3, mask 0x0010 column 36: offset 2, mask 0x0008 column 37: offset 2, mask 0x1000 column 38: offset 3, mask 0x0400 column 39: offset 1, mask 0x0008 column 40: offset 2, mask 0x0002 column 41: offset 4, mask 0x0008 column 42: offset 3, mask 0x0080 column 43: offset 1, mask 0x8000 column 44: offset 1, mask 0x0400 column 45: offset 0, mask 0x0200 column 46: offset 2, mask 0x0001 column 47: offset 1, mask 0x0080 column 48: offset 0, mask 0x1000 column 49: offset 0, mask 0x0100 column 50: offset 2, mask 0x8000 column 51: offset 1, mask 0x0001 column 52: offset 0, mask 0x8000 column 53: offset 1, mask 0x1000 column 54: offset 0, mask 0x0001 column 55: offset 0, mask 0x0002 column 56: offset 0, mask 0x4000 column 57: offset 4, mask 0x0002 column 58: offset 3, mask 0x0200 column 59: offset 2, mask 0x0400 column 60: offset 2, mask 0x0080 column 61: offset 4, mask 0x0001 column 62: offset 2, mask 0x4000 column 63: offset 2, mask 0x0040 column 64: offset 4, mask 0x1000 column 65: offset 2, mask 0x0020 column 66: offset 4, mask 0x0004 direction bits (1=input) 0x52A3 0x1589 0x943A 0x0680 0x50FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5203 0x1481 0x8420 0x0200 0x1000 2: 0x0000 0x8008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 3: 0x0000 0x0008 0x700A 0x0400 0x0005 0x5003 0x1081 0x8420 0x0200 0x1000 4: 0x0000 0x0008 0x700B 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 5: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1001 0x8420 0x0200 0x1000 6: 0x0100 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 7: 0x0000 0x0008 0x700A 0x0400 0x0005 0x4003 0x1000 0x0420 0x0200 0x1000 8: 0xC001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 9: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0420 0x0200 0x1000 10: 0x4001 0x0008 0x700A 0x0400 0x0007 0x0000 0x0000 0x0020 0x0000 0x1000 11: 0x4001 0x0008 0x700A 0x0400 0x0005 0x0000 0x0000 0x0020 0x0000 0x1000 12: 0x4001 0x0008 0x708A 0x0400 0x0005 13: 0x4001 0x0008 0x700A 0x0400 0x0005 14: 0x4001 0x0008 0x700A 0x0400 0x0005 15: 0x4401 0x0008 0x7002 0x0480 0x0005 16: 0x4401 0x0010 0x7002 0x0480 0x000D 17: 0x4601 0x8410 0x7002 0x0480 0x000D 18: 0x4601 0x0410 0x7002 0x0480 0x000D 19: 0x5601 0x0490 0x7003 0x0480 0x000D 20: 0x5601 0x0490 0x7002 0x0480 0x000D 21: 0x5701 0x0491 0xF002 0x0480 0x000D 22: 0x5601 0x0491 0xF002 0x0480 0x000D 23: 0x9602 0x1491 0xF002 0x0480 0x000D 24: 0x1602 0x1491 0xF002 0x0480 0x000D 25: 0x1602 0x1491 0xF402 0x0680 0x000F 26: 0x1602 0x1491 0xF402 0x0680 0x000D 27: 0x1602 0x1491 0xF4A2 0x0680 0x100D 28: 0x1602 0x1491 0xF422 0x0680 0x100D 29: 0x1202 0x1491 0xF42A 0x0600 0x100D 30: 0x1202 0x1489 0xF42A 0x0600 0x1005 31: 0x1202 0x1489 0xF42A 0x0600 0x1005 32: 0x1202 0x1489 0xF42A 0x0600 0x1005 33: 0x1602 0x1489 0xF422 0x0680 0x1005 34: 0x1602 0x9089 0xF422 0x0680 0x1005 35: 0x1602 0x1089 0xF422 0x0680 0x1005 36: 0x1602 0x1091 0xF422 0x0680 0x100D 37: 0x1602 0x9491 0xF422 0x0680 0x100D 38: 0x1602 0x1491 0xF422 0x0680 0x100D 39: 0x1602 0x1491 0xF422 0x0680 0x100D 40: 0x1202 0x1491 0xF42A 0x0600 0x100D 41: 0x1002 0x9491 0xF42A 0x0600 0x100D 42: 0x1002 0x1491 0xF42A 0x0600 0x100D 43: 0x1402 0x1491 0xF422 0x0680 0x100D 44: 0x1602 0x9491 0xF422 0x0680 0x100D 45: 0x1602 0x1491 0xF422 0x0680 0x100D 46: 0x1602 0x1489 0xF422 0x0680 0x1005 47: 0x1602 0x1489 0xF422 0x0680 0x1005 48: 0x1602 0x1409 0xF423 0x0680 0x1005 49: 0x1602 0x1409 0xF422 0x0680 0x1005 50: 0x1602 0x1411 0xF422 0x0680 0x100D 51: 0x1602 0x1491 0xF423 0x0680 0x100D 52: 0x1602 0x1491 0xF422 0x0680 0x100D 53: 0x1602 0x1491 0xF422 0x0680 0x100D 54: 0x1202 0x1491 0xF42A 0x0600 0x100D 55: 0x0202 0x1491 0xF42B 0x0600 0x100D 56: 0x0202 0x1491 0xF42A 0x0600 0x100D 57: 0x0602 0x1491 0xF422 0x0680 0x100D 58: 0x1602 0x1491 0xF423 0x0680 0x100D 59: 0x1602 0x1491 0xF422 0x0680 0x100D 60: 0x1602 0x1489 0xF422 0x0680 0x1005 61: 0x1602 0x1489 0xF422 0x0680 0x1005 62: 0x1702 0x1489 0x7422 0x0680 0x1005 63: 0x1602 0x1489 0x7422 0x0680 0x1005 64: 0x1602 0x1491 0x7422 0x0680 0x100D 65: 0x1702 0x1491 0xF422 0x0680 0x100D 66: 0x1602 0x1491 0xF422 0x0680 0x100D 67: 0x1602 0x1491 0xF422 0x0680 0x100D 68: 0x1202 0x1491 0xF42A 0x0600 0x100D 69: 0x1302 0x1490 0xF42A 0x0600 0x100D 70: 0x1202 0x1490 0xF42A 0x0600 0x100D 71: 0x1602 0x1490 0xF422 0x0680 0x100D 72: 0x1702 0x1491 0xF422 0x0680 0x100D 73: 0x1602 0x1491 0xF422 0x0680 0x100D 74: 0x1602 0x1489 0xF422 0x0680 0x1005 75: 0x1602 0x1489 0xF422 0x0680 0x1005 76: 0x9603 0x0489 0xF422 0x0680 0x1005 77: 0x1603 0x0489 0xF422 0x0680 0x1005 78: 0x1603 0x0491 0xF422 0x0680 0x100D 79: 0x9602 0x1491 0xF422 0x0680 0x100D 80: 0x1602 0x1491 0xF422 0x0680 0x100D 81: 0x1602 0x1491 0xF422 0x0680 0x100D 82: 0x1202 0x1491 0xF42A 0x0600 0x100D 83: 0xD200 0x1491 0xF42A 0x0600 0x100D 84: 0x5200 0x1491 0xF42A 0x0600 0x100D 85: 0x5600 0x1491 0xF422 0x0680 0x100D 86: 0x9602 0x1491 0xF422 0x0680 0x100D 87: 0x1602 0x1491 0xF422 0x0680 0x100D 88: 0x1602 0x1489 0xF422 0x0680 0x1005 89: 0x1602 0x1489 0xF422 0x0680 0x1005 90: 0x1602 0x1489 0xF422 0x0480 0x1007 91: 0x1602 0x1489 0xF422 0x0480 0x1005 92: 0x1602 0x1491 0xF422 0x0480 0x100D 93: 0x1602 0x1491 0xF422 0x0680 0x100F 94: 0x1602 0x1491 0xF422 0x0680 0x100D 95: 0x1602 0x1491 0xF422 0x0680 0x100D 96: 0x1202 0x1491 0xF42A 0x0600 0x100D 97: 0x1202 0x1491 0xF02A 0x0600 0x100F 98: 0x1202 0x1491 0xF02A 0x0600 0x100D 99: 0x1602 0x1491 0xF022 0x0680 0x100D 100: 0x1602 0x1491 0xF422 0x0680 0x100F 101: 0x1602 0x1491 0xF422 0x0680 0x100D 102: 0x1602 0x1489 0xF422 0x0680 0x1005 103: 0x1602 0x1489 0xF422 0x0680 0x1005 104: 0x1602 0x1489 0xF422 0x0480 0x1007 105: 0x1602 0x1489 0xF422 0x0480 0x1005 106: 0x1602 0x1489 0xF4A2 0x0480 0x0005 107: 0x1602 0x1489 0xF422 0x0480 0x0005 108: 0x1602 0x1491 0xF422 0x0480 0x000D 109: 0x1602 0x1491 0xF422 0x0680 0x000F 110: 0x1602 0x1491 0xF422 0x0680 0x000D 111: 0x1602 0x1491 0xF4A2 0x0680 0x100D 112: 0x1602 0x1491 0xF422 0x0680 0x100D 113: 0x1602 0x1491 0xF422 0x0680 0x100D 114: 0x1202 0x1491 0xF42A 0x0600 0x100D 115: 0x1202 0x1491 0xF02A 0x0600 0x100F 116: 0x1202 0x1491 0xF02A 0x0600 0x100D 117: 0x1202 0x1491 0xF08A 0x0600 0x100D 118: 0x1202 0x1491 0xF00A 0x0600 0x100D 119: 0x1602 0x1491 0xF002 0x0680 0x100D 120: 0x1602 0x1491 0xF402 0x0680 0x100F 121: 0x1602 0x1491 0xF402 0x0680 0x100D 122: 0x1602 0x1491 0xF4A2 0x0680 0x100D 123: 0x1602 0x1491 0xF422 0x0680 0x100D 124: 0x1202 0x1491 0xF42A 0x0600 0x100D 125: 0x1202 0x1489 0xF42A 0x0600 0x1005 126: 0x1202 0x1489 0xF42A 0x0600 0x1005 127: 0x1206 0x1489 0xF42A 0x0600 0x1005 128: 0x1206 0x3489 0xF42A 0x0600 0x1005 129: 0x1A06 0x3489 0xF42A 0x0600 0x1005 130: 0x1A06 0x348D 0xF42A 0x0600 0x1005 131: 0x1A46 0x348D 0xF42A 0x0600 0x1005 132: 0x1A46 0x368D 0xF42A 0x0600 0x1005 133: 0x1A46 0x368D 0xF62A 0x0600 0x1005 134: 0x1A46 0x368D 0xF62A 0x0E00 0x1005 135: 0x1A46 0x368D 0xF62A 0x8E00 0x1005 136: 0x1A46 0x368D 0xF62A 0x8F00 0x1005 137: 0x1A46 0x368D 0xFE2A 0x8F00 0x1005 138: 0x1A46 0x368D 0xFE2A 0x8F02 0x1005 139: 0x1A46 0x368D 0xFE2A 0xCF02 0x1005 140: 0x1A46 0x368D 0xFE2A 0xCF06 0x1005 141: 0x1A46 0x368D 0xFE2A 0xCF07 0x1005 142: 0x1A46 0x368D 0xFE2A 0xCF47 0x1005 143: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 144: 0x1A46 0x3687 0xFE22 0xCFE7 0x100D 145: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 146: 0x1A46 0x3E85 0xFE22 0xCFE7 0x100D 147: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 148: 0x1A46 0x36C5 0xFE22 0xCFE7 0x100D 149: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 150: 0x1A46 0x7685 0xFE22 0xCFE7 0x100D 151: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 152: 0x1A56 0x3685 0xFE22 0xCFE7 0x100D 153: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 154: 0x1A4E 0x3685 0xFE22 0xCFE7 0x100D 155: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 156: 0x3A46 0x368D 0xFE22 0xCFE7 0x1005 157: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 158: 0x1E46 0x368D 0xFE22 0xCFE7 0x1005 159: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 160: 0x1A46 0x36A5 0xFE2A 0xCF67 0x100D 161: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 162: 0x1A46 0x3695 0xFE2A 0xCF67 0x100D 163: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 164: 0x1A46 0x368D 0xEE2A 0xEBE7 0x100D 165: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 166: 0x1A46 0x368D 0xEE2A 0xDBE7 0x100D 167: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 168: 0x1A46 0x368D 0xEF2A 0xCBE7 0x100D 169: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 170: 0x1A46 0x368D 0xEE2A 0xCBE7 0x900D 171: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 172: 0x1A46 0x368D 0xEE2A 0xCBEF 0x100D 173: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 174: 0x1A46 0x368D 0xEE2A 0xCBE7 0x300D 175: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 176: 0x1A46 0x368D 0xFE2A 0xCB77 0x100D 177: 0x1A46 0x368D 0xFE2A 0xCF67 0x1005 178: 0x1202 0x1489 0xF42A 0x0600 0x1005 179: 0x1202 0x1489 0xB42A 0x0600 0x1005 180: 0x1202 0x1489 0xB44A 0x0600 0x1005 181: 0x1202 0x1489 0xB40A 0x0600 0x1005 182: 0x1202 0x1489 0xB40A 0x0600 0x0004 183: 0x1202 0x1489 0xB40A 0x0600 0x1005 184: 0x1202 0x1489 0xB40A 0x0600 0x1005 185: 0x1202 0x1489 0xB44A 0x0600 0x0005 186: 0x1202 0x1489 0xB40A 0x0600 0x0005 187: 0x1202 0x1489 0xB40A 0x0600 0x1004 188: 0x1202 0x1489 0xB40A 0x0600 0x0005 189: 0x1202 0x1489 0xB40A 0x0600 0x0005 190: 0x1202 0x1489 0xB44A 0x0600 0x0005 191: 0x1202 0x1489 0xB40A 0x0600 0x0005 192: 0x1202 0x1489 0xF40A 0x0600 0x0005 193: 0x1202 0x1489 0xF46A 0x0600 0x0005 194: 0x1202 0x1489 0xF42A 0x0600 0x0005 195: 0x1202 0x1489 0xF42A 0x0600 0x0005 196: 0x1202 0x1489 0xF46A 0x0600 0x1005 197: 0x1202 0x1489 0xF42A 0x0600 0x1005 198: 0x1202 0x1489 0xF42A 0x0600 0x1005 199: 0x1202 0x1489 0xF46A 0x0600 0x1005 200: 0x1202 0x1489 0xF42A 0x0600 0x1005 201: 0x1202 0x1489 0xB42A 0x0600 0x1005 202: 0x1202 0x1489 0xB44A 0x0600 0x1005 203: 0x1202 0x1489 0xB40A 0x0600 0x1005 204: 0x1202 0x1489 0xF40A 0x0600 0x1005 205: 0x1202 0x1489 0xF46A 0x0600 0x0005 206: 0x1202 0x1489 0xF42A 0x0600 0x0005 207: 0x1202 0x1489 0xB42A 0x0600 0x0005 208: 0x1202 0x1489 0xB44A 0x0600 0x1005 209: 0x1202 0x1489 0xB40A 0x0600 0x1005 210: 0x1202 0x1489 0xF40A 0x0600 0x1005 211: 0x1202 0x1489 0xF46A 0x0600 0x0005 212: 0x1202 0x1489 0xF42A 0x0600 0x0005 213: 0x1202 0x1489 0xF42A 0x0600 0x0005 214: 0x1202 0x1489 0xF46A 0x0600 0x1005 215: 0x1202 0x1489 0xF42A 0x0600 0x1005 216: 0x1202 0x1489 0xF42A 0x0600 0x1005 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIOIIOIIIIOIOIGOIPIGIIIOOOIIOIIIOIOIOIOIIIIIIIOOIIGIOPOGOIIIIIIIIIOIIOO UUT inputs: 44 UUT outputs: 22 pins used: 66 not used: 0 216 'test steps' 584 lines M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: +5v AA2, BA2 GROUND AC2, AT1, BC2, BT1 (ALL PINS ARE USED). PINS Main menu Thu Jun 29 20:20:00 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:20:02 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 4 100000000000000000000000000000000001111100000100011010000110110111 step 5 100000000000000000000000000000000001111100000000011010000110110111 step 6 100000000000000000000000000000000001111100000000100010000110110111 step 7 100000000000000000000000000000000001111100000000000010000110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 8 100000000000000000000000000000000001111100000000000110000110110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 9 100000000000000000000000000000000001111100000000000010000110110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 100 step 10 100000000000000000000000000000000001111100000000000010001000110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 11 100000000000000000000000000000000001111100000000000010000000110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 step 12 100000000000000000000000000000000001111100000000000010000001110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 13 100000000000000000000000000000000001111100000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 14 100000000000000000000000000000000001111100000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 111 step 17 100000000000010010000000000000000000110111111000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 18 100000000000010010000000000000000000110111011000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 19 100000000000010010000000000000000000110111011101000010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 20 100000000000010010000000000000000000110111011001000010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 111 step 21 100000000000010010000000000000000000110111011001111010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 22 100000000000010010000000000000000000110111011001011010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 23 100000000000010010000000000000000000110111011001011110000000110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 24 100000000000010010000000000000000000110111011001011010000000110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 111 step 25 100000000000010010000000000000000000110111011001011010001110110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 26 100000000000010010000000000000000000110111011001011010000110110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 11 step 27 100000000000010010000000000000000000110111011001011010000111110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 28 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 29 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 30 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 31 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 32 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 33 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 34 100000000000010000000000000000000000111101101001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 35 100000000000010000000000000000000000111101001001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 36 100000000000010010000000000000000000110111001001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 37 100000000000010010000000000000000000110111111001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 38 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 39 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 40 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 41 100000000000000010000000000000000001110110110001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 42 100000000000000010000000000000000001110110010001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 43 100000000000010010000000000000000000110111010001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 44 100000000000010010000000000000000000110111111001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 45 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 46 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 47 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 48 100000000000010000000000000000000000111101011101011010000110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 49 100000000000010000000000000000000000111101011001011010000110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010000110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 51 100000000000010010000000000000000000110111011101011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 52 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 53 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 54 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 55 100000000000000010000000000000000001110110011100011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 56 100000000000000010000000000000000001110110011000011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 57 100000000000010010000000000000000000110111011000011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 58 100000000000010010000000000000000000110111011101011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 59 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 60 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 61 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 62 100000000000010000000000000000000000111101011001101010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 63 100000000000010000000000000000000000111101011001001010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 64 100000000000010010000000000000000000110111011001001010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 65 100000000000010010000000000000000000110111011001111010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 66 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 67 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 68 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 69 100000000000000010000000000000000001110110011001110010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 70 100000000000000010000000000000000001110110011001010010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 71 100000000000010010000000000000000000110111011001010010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 72 100000000000010010000000000000000000110111011001111010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 73 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 74 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 75 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 76 100000000000010000000000000000000000111101011001011110000110110111 fail ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 77 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 78 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 79 100000000000010010000000000000000000110111011001011110000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 80 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 81 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 82 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 83 100000000000000010000000000000000001110110011001011110000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 84 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 85 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 86 100000000000010010000000000000000000110111011001011110000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 87 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 88 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 89 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 90 100000000000010000000000000000000000111101011001011010001010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 91 100000000000010000000000000000000000111101011001011010000010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 92 100000000000010010000000000000000000110111011001011010000010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 93 100000000000010010000000000000000000110111011001011010001110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 94 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 95 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 96 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 97 100000000000000010000000000000000001110110011001011010001100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 98 100000000000000010000000000000000001110110011001011010000100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 99 100000000000010010000000000000000000110111011001011010000100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 100 100000000000010010000000000000000000110111011001011010001110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 101 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 102 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 103 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 104 100000000000010000000000000000000000111101011001011010001010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 105 100000000000010000000000000000000000111101011001011010000010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 106 100000000000010000000000000000000000111101011001011010000011110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 107 100000000000010000000000000000000000111101011001011010000010110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 108 100000000000010010000000000000000000110111011001011010000010110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 109 100000000000010010000000000000000000110111011001011010001110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 110 100000000000010010000000000000000000110111011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 111 100000000000010010000000000000000000110111011001011010000111110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 112 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 113 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 114 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 115 100000000000000010000000000000000001110110011001011010001100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 116 100000000000000010000000000000000001110110011001011010000100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 117 100000000000000010000000000000000001110110011001011010000101110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 118 100000000000000010000000000000000001110110011001011010000100110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 119 100000000000010010000000000000000000110111011001011010000100110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 120 100000000000010010000000000000000000110111011001011010001110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 121 100000000000010010000000000000000000110111011001011010000110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 122 100000000000010010000000000000000000110111011001011010000111110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 123 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 124 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 125 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 126 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 127 100001000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 128 100001100000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 129 100001100100000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 130 100001100110000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 131 100001100110100000000000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 132 100001100110100100000000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 133 100001100110100100010000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 134 100001100110100100011000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 135 100001100110100100011010000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 136 100001100110100100011011000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 137 100001100110100100011011010000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 138 100001100110100100011011011000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 139 100001100110100100011011011010000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 140 100001100110100100011011011011000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 141 100001100110100100011011011011010000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 142 100001100110100100011011011011011000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 143 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 144 110001100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 145 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 146 101001100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 147 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 148 100101100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 149 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 150 100011100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 151 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 152 100001110110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 153 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 154 100001101110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 155 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 156 100001100111100100011011011011011100111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 157 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 158 100001100110110100011011011011011100111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 159 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 160 100001100110101100011011011011011100110111011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 161 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 162 100001100110100110011011011011011100110111011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 163 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 164 100001100110100101011011011011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 165 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 166 100001100110100100111011011011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 167 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 168 100001100110100100011111011011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 169 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 170 100001100110100100011011111011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 171 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 172 100001100110100100011011011111011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 173 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 174 100001100110100100011011011011111100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 175 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 176 100001100110100100011011011011011110101111011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 177 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 00 00 0 0 00 00 00 00 000 1 0 step 178 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 179 100000000000000000000000000000000001111100011001011010000110100111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 180 100000000000000000000000000000000001111100011001011010000110101101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 181 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 0 step 182 100000000000000000000000000000000001111100011001011010000110000001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 183 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 184 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 185 100000000000000000000000000000000001111100011001011010000110101001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 186 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 step 187 100000000000000000000000000000000001111100011001011010000110000101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 188 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 189 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 190 100000000000000000000000000000000001111100011001011010000110101001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 191 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 192 100000000000000000000000000000000001111100011001011010000110110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 193 100000000000000000000000000000000001111100011001011010000110111011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 194 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 195 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 196 100000000000000000000000000000000001111100011001011010000110111111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 197 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 198 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 199 100000000000000000000000000000000001111100011001011010000110111111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 200 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 201 100000000000000000000000000000000001111100011001011010000110100111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 202 100000000000000000000000000000000001111100011001011010000110101101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 203 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 204 100000000000000000000000000000000001111100011001011010000110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 101 step 205 100000000000000000000000000000000001111100011001011010000110111011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 206 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 207 100000000000000000000000000000000001111100011001011010000110100011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 110 step 208 100000000000000000000000000000000001111100011001011010000110101101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 209 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 210 100000000000000000000000000000000001111100011001011010000110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 101 step 211 100000000000000000000000000000000001111100011001011010000110111011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 212 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 213 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 214 100000000000000000000000000000000001111100011001011010000110111111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 215 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 216 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ test 12: *** FAIL *************************** 209 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O OOO O OOOO all fails O OOO O OOOO was hi 1111111111111111111111111111111111111111111111 111111 1111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvv vvvvvvvvv was lo 000000000000000000000000000000000000000000000000000 000000000000 total fails 12, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100000000000000000000000000000000001111100011001011010000110110111 step 2 100000000000000000000000000000000001111100100001011010000110110111 step 3 100000000000000000000000000000000001111100000001011010000110110111 step 4 100000000000000000000000000000000001111100000100011010000110110111 step 5 100000000000000000000000000000000001111100000000011010000110110111 step 6 100000000000000000000000000000000001111100000000100010000110110111 step 7 100000000000000000000000000000000001111100000000000010000110110111 SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 8 100000000000000000000000000000000001111100000000000110000110110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 9 100000000000000000000000000000000001111100000000000010000110110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 100 step 10 100000000000000000000000000000000001111100000000000010001000110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 11 100000000000000000000000000000000001111100000000000010000000110111 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 step 12 100000000000000000000000000000000001111100000000000010000001110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 13 100000000000000000000000000000000001111100000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 14 100000000000000000000000000000000001111100000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 15 100000000000010000000000000000000000111101000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 16 100000000000010010000000000000000000110111000000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 111 step 17 100000000000010010000000000000000000110111111000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 18 100000000000010010000000000000000000110111011000000010000000110001 fail ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 19 100000000000010010000000000000000000110111011101000010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 20 100000000000010010000000000000000000110111011001000010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 111 step 21 100000000000010010000000000000000000110111011001111010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 22 100000000000010010000000000000000000110111011001011010000000110001 fail ^ ^^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 23 100000000000010010000000000000000000110111011001011110000000110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 24 100000000000010010000000000000000000110111011001011010000000110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 111 step 25 100000000000010010000000000000000000110111011001011010001110110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 26 100000000000010010000000000000000000110111011001011010000110110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 11 step 27 100000000000010010000000000000000000110111011001011010000111110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 28 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 29 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 30 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 31 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 32 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 33 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 34 100000000000010000000000000000000000111101101001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 35 100000000000010000000000000000000000111101001001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 36 100000000000010010000000000000000000110111001001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 37 100000000000010010000000000000000000110111111001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 38 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 39 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 40 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 41 100000000000000010000000000000000001110110110001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 42 100000000000000010000000000000000001110110010001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 43 100000000000010010000000000000000000110111010001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 44 100000000000010010000000000000000000110111111001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 45 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 46 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 47 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 48 100000000000010000000000000000000000111101011101011010000110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 49 100000000000010000000000000000000000111101011001011010000110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 50 100000000000010010000000000000000000110111011001011010000110110111 fail ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 51 100000000000010010000000000000000000110111011101011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 52 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 53 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 54 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 55 100000000000000010000000000000000001110110011100011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 56 100000000000000010000000000000000001110110011000011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 57 100000000000010010000000000000000000110111011000011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 58 100000000000010010000000000000000000110111011101011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 59 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 60 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 61 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 62 100000000000010000000000000000000000111101011001101010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 63 100000000000010000000000000000000000111101011001001010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 64 100000000000010010000000000000000000110111011001001010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 65 100000000000010010000000000000000000110111011001111010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 66 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 67 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 68 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 69 100000000000000010000000000000000001110110011001110010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 70 100000000000000010000000000000000001110110011001010010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 71 100000000000010010000000000000000000110111011001010010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 72 100000000000010010000000000000000000110111011001111010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 73 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 74 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 75 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 76 100000000000010000000000000000000000111101011001011110000110110111 fail ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 77 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 78 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^^^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 79 100000000000010010000000000000000000110111011001011110000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 80 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 81 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 82 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 83 100000000000000010000000000000000001110110011001011110000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 84 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 85 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 86 100000000000010010000000000000000000110111011001011110000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 87 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 88 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 89 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 90 100000000000010000000000000000000000111101011001011010001010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 91 100000000000010000000000000000000000111101011001011010000010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 92 100000000000010010000000000000000000110111011001011010000010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 93 100000000000010010000000000000000000110111011001011010001110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 94 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 95 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 96 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 97 100000000000000010000000000000000001110110011001011010001100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 98 100000000000000010000000000000000001110110011001011010000100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 99 100000000000010010000000000000000000110111011001011010000100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 100 100000000000010010000000000000000000110111011001011010001110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 101 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 102 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 103 100000000000010000000000000000000000111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 104 100000000000010000000000000000000000111101011001011010001010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 105 100000000000010000000000000000000000111101011001011010000010110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 106 100000000000010000000000000000000000111101011001011010000011110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 107 100000000000010000000000000000000000111101011001011010000010110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 108 100000000000010010000000000000000000110111011001011010000010110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 109 100000000000010010000000000000000000110111011001011010001110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 110 100000000000010010000000000000000000110111011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 111 100000000000010010000000000000000000110111011001011010000111110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 112 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 113 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 114 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 115 100000000000000010000000000000000001110110011001011010001100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 116 100000000000000010000000000000000001110110011001011010000100110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 117 100000000000000010000000000000000001110110011001011010000101110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 118 100000000000000010000000000000000001110110011001011010000100110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 119 100000000000010010000000000000000000110111011001011010000100110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 120 100000000000010010000000000000000000110111011001011010001110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 121 100000000000010010000000000000000000110111011001011010000110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 122 100000000000010010000000000000000000110111011001011010000111110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 123 100000000000010010000000000000000000110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 124 100000000000000010000000000000000001110110011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 125 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 126 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 127 100001000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 128 100001100000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 129 100001100100000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 130 100001100110000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 131 100001100110100000000000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 132 100001100110100100000000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 133 100001100110100100010000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 134 100001100110100100011000000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 135 100001100110100100011010000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 136 100001100110100100011011000000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 137 100001100110100100011011010000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 138 100001100110100100011011011000000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 139 100001100110100100011011011010000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 140 100001100110100100011011011011000000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 141 100001100110100100011011011011010000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 142 100001100110100100011011011011011000111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 143 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 144 110001100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 145 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 146 101001100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 147 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 148 100101100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 149 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 150 100011100110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 151 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 152 100001110110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 153 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 154 100001101110100100011011011011011100110111011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 155 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 156 100001100111100100011011011011011100111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 157 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 158 100001100110110100011011011011011100111101011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 159 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 160 100001100110101100011011011011011100110111011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 161 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 162 100001100110100110011011011011011100110111011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 163 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 164 100001100110100101011011011011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 165 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 166 100001100110100100111011011011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 167 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 168 100001100110100100011111011011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 169 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 170 100001100110100100011011111011011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 171 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 172 100001100110100100011011011111011100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 173 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 00 0 0 step 174 100001100110100100011011011011111100001000011001011010000110110111 fail ^ ^^^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 11 1 1 step 175 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 1 step 176 100001100110100100011011011011011110101111011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 0 step 177 100001100110100100011011011011011100111101011001011010000110110111 fail ^ ^ ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 00 00 0 0 00 00 00 00 000 1 0 step 178 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 179 100000000000000000000000000000000001111100011001011010000110100111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 180 100000000000000000000000000000000001111100011001011010000110101101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 181 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 0 step 182 100000000000000000000000000000000001111100011001011010000110000001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 183 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 184 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 10 step 185 100000000000000000000000000000000001111100011001011010000110101001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 186 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 1 step 187 100000000000000000000000000000000001111100011001011010000110000101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 188 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 189 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 190 100000000000000000000000000000000001111100011001011010000110101001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 191 100000000000000000000000000000000001111100011001011010000110100001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 192 100000000000000000000000000000000001111100011001011010000110110001 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 1 step 193 100000000000000000000000000000000001111100011001011010000110111011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 194 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 195 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 196 100000000000000000000000000000000001111100011001011010000110111111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 197 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 198 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 199 100000000000000000000000000000000001111100011001011010000110111111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 200 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 201 100000000000000000000000000000000001111100011001011010000110100111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 0 step 202 100000000000000000000000000000000001111100011001011010000110101101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 203 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 204 100000000000000000000000000000000001111100011001011010000110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 101 step 205 100000000000000000000000000000000001111100011001011010000110111011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 206 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 207 100000000000000000000000000000000001111100011001011010000110100011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 110 step 208 100000000000000000000000000000000001111100011001011010000110101101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 209 100000000000000000000000000000000001111100011001011010000110100101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 1 step 210 100000000000000000000000000000000001111100011001011010000110110101 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 101 step 211 100000000000000000000000000000000001111100011001011010000110111011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 212 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 213 100000000000000000000000000000000001111100011001011010000110110011 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 11 step 214 100000000000000000000000000000000001111100011001011010000110111111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: 0 step 215 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO changed: step 216 100000000000000000000000000000000001111100011001011010000110110111 fail ^ ^ test 13: *** FAIL *************************** 209 steps failed SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO this fail O OOO O OOOO all fails O OOO O OOOO was hi 1111111111111111111111111111111111111111111111 111111 1111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^ ^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvv vvvvvvvvv was lo 000000000000000000000000000000000000000000000000000 000000000000 total fails 13, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails O OOO O OOOO was lo 000000000000000000000000000000000000000000000000000 000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvv vvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^ ^^^^^^^^^ was hi 1111111111111111111111111111111111111111111111 111111 1111111111 total fails 13, total passes 0 Main menu Thu Jun 29 20:21:06 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:21:07 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBAABBAAAAAAAAAAAAAABBBBBABBBB LETTER ALPSLFMDEEMCBFRSPKLEMFHRSCJLJKUHPNMBBNNVVRKRHUTDJUKANJHBTPDFSVEVDU SIDE 121212122121212121111111112212122222112222111221112112212112212122 DIRECTION IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO all fails was lo 00000000000000000000000000000000000000 0000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111111111111111111111111111111111111111 total fails 0, total passes 49 Main menu Thu Jun 29 20:21:17 2017 test file is: tests\m222.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m217.tst reading test file: tests\m217.tst comment: ; M217 PCB REV A SCHEMATIC REV (BLANK) 4-BIT CLOCK REGISTER WITH BUFFER REGISTER comment: ; comment: ; comment: ; 8 FLIP-FLOPS: CNT0 (MSB) THRU CNT3 (LSB), BUF0 (MSB) THRU BUF3 (LSB) comment: ; CNT CAN BE INCREMENTED, CLEARED, JAMMED FROM BUF comment: ; BUF CAN BE CLEARED, LOAD FROM CNT, JAMS FROM PINS (AC) comment: ; BUF OUTPUTS CAN BE GATED TO PINS (INTERNAL BUS, OC OUTPUTS) comment: comment: pins: PINS pins: 1 I AS2 E5-13,E5-1,E6-13,E6-1 CLR_BUF-N CLEARS BUF3 THRU BUF0 pins: 2 I AE1 E1-10,E1-13,E1-1,E1-4 AC_TO_BUF JAMS PINS (AC3 THRU AC0) TO BUF3 THRU BUF0 pins: 3 I AD2 E1-9 AC3 pins: 4 I AD1 E1-12 AC2 pins: 5 I AF1 E1-2 AC1 pins: 6 I AH1 E1-5 AC0 pins: 7 I AN2 E5-11,E5-3,E6-11,E6-3 CNT_TO_BUF CNT3 THRU CNT0 -> BUF3 THRU BUF0 (RISING) pins: 8 O AJ2 E5-9 BUF3 pins: 9 O AH2 E5-8 BUF3-N pins: 10 O AK1 E5-5 BUF2 pins: 11 O AA1 E5-6 BUF2-N pins: 12 O AM2 E6-9 BUF1 pins: 13 O AP1 E6-8 BUF1-N pins: 14 O AR1 E6-5 BUF0 pins: 15 O AS1 E6-6 BUF0-N pins: 16 I AM1 E3-9 BUF_TO_AC ENABLE OUTPUT PINS INT_BUS3 THRU INT_BUS0 (AC) pins: 17 P AK2 E3-10 INT_BUS3-N (AC3-N) (7401 OPEN COLLECTOR OUTPUT) pins: 18 P AJ1 E3-13 INT_BUS2-N (AC2-N) (7401 OPEN COLLECTOR OUTPUT) pins: 19 P AL1 E3-4 INT_BUS1-N (AC1-N) (7401 OPEN COLLECTOR OUTPUT) pins: 20 P AN1 E3-1 INT_BUS0-N (AC0-N) (7401 OPEN COLLECTOR OUTPUT) pins: 21 I AV2 E2-13,E2-1,E7-13,E7-1 CLR_CNT-N CLEARS CNT3 THRU CNT0 pins: 22 I AL2 E4-10,E4-12,E4-5,E4-2 BUF_TO_CNT JAMS BUF3 THRU BUF0 TO CNT3 THRU CNT0 pins: 23 I AV1 E7-3 CLOCK_CNT INCREMENTS CNT3 THRU CNT0 (RISING EDGE) pins: 24 O AB1 E2-9 CNT3 pins: 25 O AC1 E2-8 CNT3-N pins: 26 O AF2 E2-5 CNT2 pins: 27 O AE2 E2-6 CNT2-N pins: 28 O AP2 E7-9 CNT1 pins: 29 O AR2 E7-8 CNT1-N pins: 30 O AT2 E7-5 CNT0 pins: 31 O AU2 E7-6 CNT0-N pins: direction: IIIIIIIOOOOOOOOIPPPPIIIOOOOOOOO test 1: 1000000XXXXXXXX01111100XXXXXXXX comment: ; CLEAR BUF test 2: 0 01010101 test 3: 1 comment: ; CLEAR CNT test 4: 0 01010101 test 5: 1 comment: test 6: 1000000010101010111110001010101 comment: comment: ; LOAD ALL 16 VALUES (GRAY CODE) INTO BUF comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 7: 0 01010101 test 8: 1 test 9: 0001 test 10: 1 01010110 test 11: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 12: 0 01010101 test 13: 1 test 14: 0011 test 15: 1 01011010 test 16: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 17: 0 01010101 test 18: 1 test 19: 0010 test 20: 1 01011001 test 21: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 22: 0 01010101 test 23: 1 test 24: 0110 test 25: 1 01101001 test 26: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 27: 0 01010101 test 28: 1 test 29: 0111 test 30: 1 01101010 test 31: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 32: 0 01010101 test 33: 1 test 34: 0101 test 35: 1 01100110 test 36: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 37: 0 01010101 test 38: 1 test 39: 0100 test 40: 1 01100101 test 41: 0 comment: test 42: 0 01010101 test 43: 1 test 44: 1100 test 45: 1 10100101 test 46: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 47: 0 01010101 test 48: 1 test 49: 1101 test 50: 1 10100110 test 51: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 52: 0 01010101 test 53: 1 test 54: 1111 test 55: 1 10101010 test 56: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 57: 0 01010101 test 58: 1 test 59: 1110 test 60: 1 10101001 test 61: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 62: 0 01010101 test 63: 1 test 64: 1010 test 65: 1 10011001 test 66: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 67: 0 01010101 test 68: 1 test 69: 1011 test 70: 1 10011010 test 71: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 72: 0 01010101 test 73: 1 test 74: 1001 test 75: 1 10010110 test 76: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 77: 0 01010101 test 78: 1 test 79: 1000 test 80: 1 10010101 test 81: 0 comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 82: 0 01010101 test 83: 1 test 84: 0000 test 85: 1 01010101 test 86: 0 comment: test 87: 1000000010101010111110001010101 comment: comment: comment: ; LOAD ALL 16 VALUES (GRAY CODE) INTO BUF, CLEAR CNT, JAM BUF INTO CNT comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 88: 0 01010101 test 89: 1 test 90: 0001 test 91: 1 01010110 test 92: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 93: 0 01010101 test 94: 1 test 95: 1 01010110 test 96: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 97: 0 01010101 test 98: 1 test 99: 0011 test 100: 1 01011010 test 101: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 102: 0 01010101 test 103: 1 test 104: 1 01011010 test 105: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 106: 0 01010101 test 107: 1 test 108: 0010 test 109: 1 01011001 test 110: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 111: 0 01010101 test 112: 1 test 113: 1 01011001 test 114: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 115: 0 01010101 test 116: 1 test 117: 0110 test 118: 1 01101001 test 119: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 120: 0 01010101 test 121: 1 test 122: 1 01101001 test 123: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 124: 0 01010101 test 125: 1 test 126: 0111 test 127: 1 01101010 test 128: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 129: 0 01010101 test 130: 1 test 131: 1 01101010 test 132: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 133: 0 01010101 test 134: 1 test 135: 0101 test 136: 1 01100110 test 137: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 138: 0 01010101 test 139: 1 test 140: 1 01100110 test 141: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 142: 0 01010101 test 143: 1 test 144: 0100 test 145: 1 01100101 test 146: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 147: 0 01010101 test 148: 1 test 149: 1 01100101 test 150: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 151: 0 01010101 test 152: 1 test 153: 1100 test 154: 1 10100101 test 155: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 156: 0 01010101 test 157: 1 test 158: 1 10100101 test 159: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 160: 0 01010101 test 161: 1 test 162: 1101 test 163: 1 10100110 test 164: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 165: 0 01010101 test 166: 1 test 167: 1 10100110 test 168: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 169: 0 01010101 test 170: 1 test 171: 1111 test 172: 1 10101010 test 173: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 174: 0 01010101 test 175: 1 test 176: 1 10101010 test 177: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 178: 0 01010101 test 179: 1 test 180: 1110 test 181: 1 10101001 test 182: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 183: 0 01010101 test 184: 1 test 185: 1 10101001 test 186: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 187: 0 01010101 test 188: 1 test 189: 1010 test 190: 1 10011001 test 191: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 192: 0 01010101 test 193: 1 test 194: 1 10011001 test 195: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 196: 0 01010101 test 197: 1 test 198: 1011 test 199: 1 10011010 test 200: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 201: 0 01010101 test 202: 1 test 203: 1 10011010 test 204: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 205: 0 01010101 test 206: 1 test 207: 1001 test 208: 1 10010110 test 209: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 210: 0 01010101 test 211: 1 test 212: 1 10010110 test 213: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 214: 0 01010101 test 215: 1 test 216: 1000 test 217: 1 10010101 test 218: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 219: 0 01010101 test 220: 1 test 221: 1 10010101 test 222: 0 comment: comment: comment: ; CLEAR BUF, JAM BUF FROM PINS (AC) comment: test 223: 0 01010101 test 224: 1 test 225: 0000 test 226: 1 01010101 test 227: 0 comment: comment: ; CLEAR CNT, JAM BUF INTO CNT test 228: 0 01010101 test 229: 1 test 230: 1 01010101 test 231: 0 comment: test 232: 1000000010101010111110001010101 comment: comment: comment: ; CLEAR CNT test 233: 0 01010101 test 234: 1 test 235: 1000000010101010111110001010101 comment: comment: ; INCREMENT CNT 0000 TO 1111 TO 0000 comment: test 236: 101010110 test 237: 0 test 238: 101011001 test 239: 0 test 240: 101011010 test 241: 0 test 242: 101100101 test 243: 0 test 244: 101100110 test 245: 0 test 246: 101101001 test 247: 0 test 248: 101101010 test 249: 0 test 250: 110010101 test 251: 0 test 252: 110010110 test 253: 0 test 254: 110011001 test 255: 0 test 256: 110011010 test 257: 0 test 258: 110100101 test 259: 0 test 260: 110100110 test 261: 0 test 262: 110101001 test 263: 0 test 264: 110101010 test 265: 0 test 266: 101010101 test 267: 0 comment: test 268: 1000000010101010111110001010101 comment: comment: ; CLEAR CNT test 269: 0 01010101 test 270: 1 test 271: 1000000010101010111110001010101 comment: comment: ; INCREMENT CNT 0000 TO 1111 TO 0000, LOAD INTO BUF comment: comment: comment: test 272: 101010110 test 273: 0 test 274: 101010110 test 275: 0 test 276: 101011001 test 277: 0 test 278: 101011001 test 279: 0 test 280: 101011010 test 281: 0 test 282: 101011010 test 283: 0 test 284: 101100101 test 285: 0 test 286: 101100101 test 287: 0 test 288: 101100110 test 289: 0 test 290: 101100110 test 291: 0 test 292: 101101001 test 293: 0 test 294: 101101001 test 295: 0 test 296: 101101010 test 297: 0 test 298: 101101010 test 299: 0 test 300: 110010101 test 301: 0 test 302: 110010101 test 303: 0 test 304: 110010110 test 305: 0 test 306: 110010110 test 307: 0 test 308: 110011001 test 309: 0 test 310: 110011001 test 311: 0 test 312: 110011010 test 313: 0 test 314: 110011010 test 315: 0 test 316: 110100101 test 317: 0 test 318: 110100101 test 319: 0 test 320: 110100110 test 321: 0 test 322: 110100110 test 323: 0 test 324: 110101001 test 325: 0 test 326: 110101001 test 327: 0 test 328: 110101010 test 329: 0 test 330: 110101010 test 331: 0 test 332: 101010101 test 333: 0 test 334: 101010101 test 335: 0 comment: test 336: 1000000010101010111110001010101 comment: comment: ; CLEAR CNT test 337: 0 01010101 test 338: 1 test 339: 1000000010101010111110001010101 comment: comment: ; INCREMENT CNT 0000 TO 1111 TO 0000, LOAD INTO BUF, ENABLE INT_BUS-N PINS comment: comment: comment: ; INCREMENT TO 0001 test 340: 101010110 test 341: 0 comment: ; LOAD INTO BUF test 342: 101010110 test 343: 0 comment: ; ENABLE INT_BUS-N PINS test 344: 11110 test 345: 01111 comment: comment: comment: ; INCREMENT TO 0010 test 346: 101011001 test 347: 0 comment: ; LOAD INTO BUF test 348: 101011001 test 349: 0 comment: ; ENABLE INT_BUS-N PINS test 350: 11101 test 351: 01111 comment: comment: comment: ; INCREMENT TO 0011 test 352: 101011010 test 353: 0 comment: ; LOAD INTO BUF test 354: 101011010 test 355: 0 comment: ; ENABLE INT_BUS-N PINS test 356: 11100 test 357: 01111 comment: comment: comment: ; INCREMENT TO 0100 test 358: 101100101 test 359: 0 comment: ; LOAD INTO BUF test 360: 101100101 test 361: 0 comment: ; ENABLE INT_BUS-N PINS test 362: 11011 test 363: 01111 comment: comment: comment: ; INCREMENT TO 0101 test 364: 101100110 test 365: 0 comment: ; LOAD INTO BUF test 366: 101100110 test 367: 0 comment: ; ENABLE INT_BUS-N PINS test 368: 11010 test 369: 01111 comment: comment: comment: ; INCREMENT TO 0110 test 370: 101101001 test 371: 0 comment: ; LOAD INTO BUF test 372: 101101001 test 373: 0 comment: ; ENABLE INT_BUS-N PINS test 374: 11001 test 375: 01111 comment: comment: comment: ; INCREMENT TO 0111 test 376: 101101010 test 377: 0 comment: ; LOAD INTO BUF test 378: 101101010 test 379: 0 comment: ; ENABLE INT_BUS-N PINS test 380: 11000 test 381: 01111 comment: comment: comment: ; INCREMENT TO 1000 test 382: 110010101 test 383: 0 comment: ; LOAD INTO BUF test 384: 110010101 test 385: 0 comment: ; ENABLE INT_BUS-N PINS test 386: 10111 test 387: 01111 comment: comment: comment: ; INCREMENT TO 1001 test 388: 110010110 test 389: 0 comment: ; LOAD INTO BUF test 390: 110010110 test 391: 0 comment: comment: ; INCREMENT TO 1010 test 392: 110011001 test 393: 0 comment: ; LOAD INTO BUF test 394: 110011001 test 395: 0 comment: ; ENABLE INT_BUS-N PINS test 396: 10101 test 397: 01111 comment: comment: comment: ; INCREMENT TO 1011 test 398: 110011010 test 399: 0 comment: ; LOAD INTO BUF test 400: 110011010 test 401: 0 comment: ; ENABLE INT_BUS-N PINS test 402: 10100 test 403: 01111 comment: comment: comment: ; INCREMENT TO 1100 test 404: 110100101 test 405: 0 comment: ; LOAD INTO BUF test 406: 110100101 test 407: 0 comment: ; ENABLE INT_BUS-N PINS test 408: 10011 test 409: 01111 comment: comment: comment: ; INCREMENT TO 1101 test 410: 110100110 test 411: 0 comment: ; LOAD INTO BUF test 412: 110100110 test 413: 0 comment: ; ENABLE INT_BUS-N PINS test 414: 10010 test 415: 01111 comment: comment: comment: ; INCREMENT TO 1110 test 416: 110101001 test 417: 0 comment: ; LOAD INTO BUF test 418: 110101001 test 419: 0 comment: ; ENABLE INT_BUS-N PINS test 420: 10001 test 421: 01111 comment: comment: comment: ; INCREMENT TO 1111 test 422: 110101010 test 423: 0 comment: ; LOAD INTO BUF test 424: 110101010 test 425: 0 comment: ; ENABLE INT_BUS-N PINS test 426: 10000 test 427: 01111 comment: comment: comment: ; INCREMENT TO 0000 test 428: 101010101 test 429: 0 comment: ; LOAD INTO BUF test 430: 101010101 test 431: 0 comment: ; ENABLE INT_BUS-N PINS test 432: 11111 test 433: 01111 comment: comment: test 434: 1000000010101010111110001010101 comment: end: END summary column 1: offset 1, mask 0x0040 column 2: offset 0, mask 0x0800 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0400 column 6: offset 0, mask 0x0200 column 7: offset 1, mask 0x0008 column 8: offset 0, mask 0x0001 column 9: offset 0, mask 0x0002 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x8000 column 12: offset 1, mask 0x0004 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 0, mask 0x0100 column 19: offset 1, mask 0x4000 column 20: offset 1, mask 0x1000 column 21: offset 2, mask 0x0002 column 22: offset 1, mask 0x0002 column 23: offset 2, mask 0x4000 column 24: offset 0, mask 0x4000 column 25: offset 0, mask 0x2000 column 26: offset 0, mask 0x0004 column 27: offset 0, mask 0x0008 column 28: offset 1, mask 0x0010 column 29: offset 1, mask 0x0020 column 30: offset 1, mask 0x0080 column 31: offset 2, mask 0x0001 direction bits (1=input) 0xE1EF 0xDFB5 0xBFF9 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0100 0x5001 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0100 0x5041 0x0002 0x0000 0x0000 0xE00F 0x8EB4 0x0001 0x0000 0x0000 2: 0x8102 0x5A01 0x0002 0x0000 0x0000 0x600C 0x00B0 0x0001 0x0000 0x0000 3: 0x8102 0x5A41 0x0002 0x0000 0x0000 0x600C 0x00B0 0x0001 0x0000 0x0000 4: 0xA10A 0x5A61 0x0001 0x0000 0x0000 5: 0xA10A 0x5A61 0x0003 0x0000 0x0000 6: 0xA10A 0x5A61 0x0003 0x0000 0x0000 7: 0xA10A 0x5A21 0x0003 0x0000 0x0000 8: 0xA10A 0x5A61 0x0003 0x0000 0x0000 9: 0xA30A 0x5A61 0x0003 0x0000 0x0000 10: 0xAB0A 0x5C61 0x0003 0x0000 0x0000 11: 0xA30A 0x5C61 0x0003 0x0000 0x0000 12: 0xA30A 0x5A21 0x0003 0x0000 0x0000 13: 0xA30A 0x5A61 0x0003 0x0000 0x0000 14: 0xA70A 0x5A61 0x0003 0x0000 0x0000 15: 0xAF0A 0x5465 0x0003 0x0000 0x0000 16: 0xA70A 0x5465 0x0003 0x0000 0x0000 17: 0xA70A 0x5A21 0x0003 0x0000 0x0000 18: 0xA70A 0x5A61 0x0003 0x0000 0x0000 19: 0xA50A 0x5A61 0x0003 0x0000 0x0000 20: 0xAD0A 0x5265 0x0003 0x0000 0x0000 21: 0xA50A 0x5265 0x0003 0x0000 0x0000 22: 0xA50A 0x5A21 0x0003 0x0000 0x0000 23: 0xA50A 0x5A61 0x0003 0x0000 0x0000 24: 0xB50A 0x5A61 0x0003 0x0000 0x0000 25: 0x3D0A 0xD265 0x0003 0x0000 0x0000 26: 0x350A 0xD265 0x0003 0x0000 0x0000 27: 0xB50A 0x5A21 0x0003 0x0000 0x0000 28: 0xB50A 0x5A61 0x0003 0x0000 0x0000 29: 0xB70A 0x5A61 0x0003 0x0000 0x0000 30: 0x3F0A 0xD465 0x0003 0x0000 0x0000 31: 0x370A 0xD465 0x0003 0x0000 0x0000 32: 0xB70A 0x5A21 0x0003 0x0000 0x0000 33: 0xB70A 0x5A61 0x0003 0x0000 0x0000 34: 0xB30A 0x5A61 0x0003 0x0000 0x0000 35: 0x3B0A 0xDC61 0x0003 0x0000 0x0000 36: 0x330A 0xDC61 0x0003 0x0000 0x0000 37: 0xB30A 0x5A21 0x0003 0x0000 0x0000 38: 0xB30A 0x5A61 0x0003 0x0000 0x0000 39: 0xB10A 0x5A61 0x0003 0x0000 0x0000 40: 0x390A 0xDA61 0x0003 0x0000 0x0000 41: 0x310A 0xDA61 0x0003 0x0000 0x0000 42: 0xB10A 0x5A21 0x0003 0x0000 0x0000 43: 0xB10A 0x5A61 0x0003 0x0000 0x0000 44: 0xB11A 0x5A61 0x0003 0x0000 0x0000 45: 0x3919 0xDA61 0x0003 0x0000 0x0000 46: 0x3119 0xDA61 0x0003 0x0000 0x0000 47: 0xB11A 0x5A21 0x0003 0x0000 0x0000 48: 0xB11A 0x5A61 0x0003 0x0000 0x0000 49: 0xB31A 0x5A61 0x0003 0x0000 0x0000 50: 0x3B19 0xDC61 0x0003 0x0000 0x0000 51: 0x3319 0xDC61 0x0003 0x0000 0x0000 52: 0xB31A 0x5A21 0x0003 0x0000 0x0000 53: 0xB31A 0x5A61 0x0003 0x0000 0x0000 54: 0xB71A 0x5A61 0x0003 0x0000 0x0000 55: 0x3F19 0xD465 0x0003 0x0000 0x0000 56: 0x3719 0xD465 0x0003 0x0000 0x0000 57: 0xB71A 0x5A21 0x0003 0x0000 0x0000 58: 0xB71A 0x5A61 0x0003 0x0000 0x0000 59: 0xB51A 0x5A61 0x0003 0x0000 0x0000 60: 0x3D19 0xD265 0x0003 0x0000 0x0000 61: 0x3519 0xD265 0x0003 0x0000 0x0000 62: 0xB51A 0x5A21 0x0003 0x0000 0x0000 63: 0xB51A 0x5A61 0x0003 0x0000 0x0000 64: 0xA51A 0x5A61 0x0003 0x0000 0x0000 65: 0xAD19 0x5265 0x0003 0x0000 0x0000 66: 0xA519 0x5265 0x0003 0x0000 0x0000 67: 0xA51A 0x5A21 0x0003 0x0000 0x0000 68: 0xA51A 0x5A61 0x0003 0x0000 0x0000 69: 0xA71A 0x5A61 0x0003 0x0000 0x0000 70: 0xAF19 0x5465 0x0003 0x0000 0x0000 71: 0xA719 0x5465 0x0003 0x0000 0x0000 72: 0xA71A 0x5A21 0x0003 0x0000 0x0000 73: 0xA71A 0x5A61 0x0003 0x0000 0x0000 74: 0xA31A 0x5A61 0x0003 0x0000 0x0000 75: 0xAB19 0x5C61 0x0003 0x0000 0x0000 76: 0xA319 0x5C61 0x0003 0x0000 0x0000 77: 0xA31A 0x5A21 0x0003 0x0000 0x0000 78: 0xA31A 0x5A61 0x0003 0x0000 0x0000 79: 0xA11A 0x5A61 0x0003 0x0000 0x0000 80: 0xA919 0x5A61 0x0003 0x0000 0x0000 81: 0xA119 0x5A61 0x0003 0x0000 0x0000 82: 0xA11A 0x5A21 0x0003 0x0000 0x0000 83: 0xA11A 0x5A61 0x0003 0x0000 0x0000 84: 0xA10A 0x5A61 0x0003 0x0000 0x0000 85: 0xA90A 0x5A61 0x0003 0x0000 0x0000 86: 0xA10A 0x5A61 0x0003 0x0000 0x0000 87: 0xA10A 0x5A61 0x0003 0x0000 0x0000 88: 0xA10A 0x5A21 0x0003 0x0000 0x0000 89: 0xA10A 0x5A61 0x0003 0x0000 0x0000 90: 0xA30A 0x5A61 0x0003 0x0000 0x0000 91: 0xAB0A 0x5C61 0x0003 0x0000 0x0000 92: 0xA30A 0x5C61 0x0003 0x0000 0x0000 93: 0xA30A 0x5C61 0x0001 0x0000 0x0000 94: 0xA30A 0x5C61 0x0003 0x0000 0x0000 95: 0xA30A 0x5CE3 0x0002 0x0000 0x0000 96: 0xA30A 0x5CE1 0x0002 0x0000 0x0000 97: 0xA30A 0x5AA1 0x0002 0x0000 0x0000 98: 0xA30A 0x5AE1 0x0002 0x0000 0x0000 99: 0xA70A 0x5AE1 0x0002 0x0000 0x0000 100: 0xAF0A 0x54E5 0x0002 0x0000 0x0000 101: 0xA70A 0x54E5 0x0002 0x0000 0x0000 102: 0xA70A 0x5465 0x0001 0x0000 0x0000 103: 0xA70A 0x5465 0x0003 0x0000 0x0000 104: 0xA70A 0x54D7 0x0002 0x0000 0x0000 105: 0xA70A 0x54D5 0x0002 0x0000 0x0000 106: 0xA70A 0x5A91 0x0002 0x0000 0x0000 107: 0xA70A 0x5AD1 0x0002 0x0000 0x0000 108: 0xA50A 0x5AD1 0x0002 0x0000 0x0000 109: 0xAD0A 0x52D5 0x0002 0x0000 0x0000 110: 0xA50A 0x52D5 0x0002 0x0000 0x0000 111: 0xA50A 0x5265 0x0001 0x0000 0x0000 112: 0xA50A 0x5265 0x0003 0x0000 0x0000 113: 0xA50A 0x5257 0x0003 0x0000 0x0000 114: 0xA50A 0x5255 0x0003 0x0000 0x0000 115: 0xA50A 0x5A11 0x0003 0x0000 0x0000 116: 0xA50A 0x5A51 0x0003 0x0000 0x0000 117: 0xB50A 0x5A51 0x0003 0x0000 0x0000 118: 0x3D0A 0xD255 0x0003 0x0000 0x0000 119: 0x350A 0xD255 0x0003 0x0000 0x0000 120: 0x350A 0xD265 0x0001 0x0000 0x0000 121: 0x350A 0xD265 0x0003 0x0000 0x0000 122: 0x3506 0xD257 0x0003 0x0000 0x0000 123: 0x3506 0xD255 0x0003 0x0000 0x0000 124: 0xB506 0x5A11 0x0003 0x0000 0x0000 125: 0xB506 0x5A51 0x0003 0x0000 0x0000 126: 0xB706 0x5A51 0x0003 0x0000 0x0000 127: 0x3F06 0xD455 0x0003 0x0000 0x0000 128: 0x3706 0xD455 0x0003 0x0000 0x0000 129: 0x370A 0xD465 0x0001 0x0000 0x0000 130: 0x370A 0xD465 0x0003 0x0000 0x0000 131: 0x3706 0xD4D7 0x0002 0x0000 0x0000 132: 0x3706 0xD4D5 0x0002 0x0000 0x0000 133: 0xB706 0x5A91 0x0002 0x0000 0x0000 134: 0xB706 0x5AD1 0x0002 0x0000 0x0000 135: 0xB306 0x5AD1 0x0002 0x0000 0x0000 136: 0x3B06 0xDCD1 0x0002 0x0000 0x0000 137: 0x3306 0xDCD1 0x0002 0x0000 0x0000 138: 0x330A 0xDC61 0x0001 0x0000 0x0000 139: 0x330A 0xDC61 0x0003 0x0000 0x0000 140: 0x3306 0xDCE3 0x0002 0x0000 0x0000 141: 0x3306 0xDCE1 0x0002 0x0000 0x0000 142: 0xB306 0x5AA1 0x0002 0x0000 0x0000 143: 0xB306 0x5AE1 0x0002 0x0000 0x0000 144: 0xB106 0x5AE1 0x0002 0x0000 0x0000 145: 0x3906 0xDAE1 0x0002 0x0000 0x0000 146: 0x3106 0xDAE1 0x0002 0x0000 0x0000 147: 0x310A 0xDA61 0x0001 0x0000 0x0000 148: 0x310A 0xDA61 0x0003 0x0000 0x0000 149: 0x3106 0xDA63 0x0003 0x0000 0x0000 150: 0x3106 0xDA61 0x0003 0x0000 0x0000 151: 0xB106 0x5A21 0x0003 0x0000 0x0000 152: 0xB106 0x5A61 0x0003 0x0000 0x0000 153: 0xB116 0x5A61 0x0003 0x0000 0x0000 154: 0x3915 0xDA61 0x0003 0x0000 0x0000 155: 0x3115 0xDA61 0x0003 0x0000 0x0000 156: 0x3119 0xDA61 0x0001 0x0000 0x0000 157: 0x3119 0xDA61 0x0003 0x0000 0x0000 158: 0x5115 0xDA63 0x0003 0x0000 0x0000 159: 0x5115 0xDA61 0x0003 0x0000 0x0000 160: 0xD116 0x5A21 0x0003 0x0000 0x0000 161: 0xD116 0x5A61 0x0003 0x0000 0x0000 162: 0xD316 0x5A61 0x0003 0x0000 0x0000 163: 0x5B15 0xDC61 0x0003 0x0000 0x0000 164: 0x5315 0xDC61 0x0003 0x0000 0x0000 165: 0x3319 0xDC61 0x0001 0x0000 0x0000 166: 0x3319 0xDC61 0x0003 0x0000 0x0000 167: 0x5315 0xDCE3 0x0002 0x0000 0x0000 168: 0x5315 0xDCE1 0x0002 0x0000 0x0000 169: 0xD316 0x5AA1 0x0002 0x0000 0x0000 170: 0xD316 0x5AE1 0x0002 0x0000 0x0000 171: 0xD716 0x5AE1 0x0002 0x0000 0x0000 172: 0x5F15 0xD4E5 0x0002 0x0000 0x0000 173: 0x5715 0xD4E5 0x0002 0x0000 0x0000 174: 0x3719 0xD465 0x0001 0x0000 0x0000 175: 0x3719 0xD465 0x0003 0x0000 0x0000 176: 0x5715 0xD4D7 0x0002 0x0000 0x0000 177: 0x5715 0xD4D5 0x0002 0x0000 0x0000 178: 0xD716 0x5A91 0x0002 0x0000 0x0000 179: 0xD716 0x5AD1 0x0002 0x0000 0x0000 180: 0xD516 0x5AD1 0x0002 0x0000 0x0000 181: 0x5D15 0xD2D5 0x0002 0x0000 0x0000 182: 0x5515 0xD2D5 0x0002 0x0000 0x0000 183: 0x3519 0xD265 0x0001 0x0000 0x0000 184: 0x3519 0xD265 0x0003 0x0000 0x0000 185: 0x5515 0xD257 0x0003 0x0000 0x0000 186: 0x5515 0xD255 0x0003 0x0000 0x0000 187: 0xD516 0x5A11 0x0003 0x0000 0x0000 188: 0xD516 0x5A51 0x0003 0x0000 0x0000 189: 0xC516 0x5A51 0x0003 0x0000 0x0000 190: 0xCD15 0x5255 0x0003 0x0000 0x0000 191: 0xC515 0x5255 0x0003 0x0000 0x0000 192: 0xA519 0x5265 0x0001 0x0000 0x0000 193: 0xA519 0x5265 0x0003 0x0000 0x0000 194: 0xC519 0x5257 0x0003 0x0000 0x0000 195: 0xC519 0x5255 0x0003 0x0000 0x0000 196: 0xC51A 0x5A11 0x0003 0x0000 0x0000 197: 0xC51A 0x5A51 0x0003 0x0000 0x0000 198: 0xC71A 0x5A51 0x0003 0x0000 0x0000 199: 0xCF19 0x5455 0x0003 0x0000 0x0000 200: 0xC719 0x5455 0x0003 0x0000 0x0000 201: 0xA719 0x5465 0x0001 0x0000 0x0000 202: 0xA719 0x5465 0x0003 0x0000 0x0000 203: 0xC719 0x54D7 0x0002 0x0000 0x0000 204: 0xC719 0x54D5 0x0002 0x0000 0x0000 205: 0xC71A 0x5A91 0x0002 0x0000 0x0000 206: 0xC71A 0x5AD1 0x0002 0x0000 0x0000 207: 0xC31A 0x5AD1 0x0002 0x0000 0x0000 208: 0xCB19 0x5CD1 0x0002 0x0000 0x0000 209: 0xC319 0x5CD1 0x0002 0x0000 0x0000 210: 0xA319 0x5C61 0x0001 0x0000 0x0000 211: 0xA319 0x5C61 0x0003 0x0000 0x0000 212: 0xC319 0x5CE3 0x0002 0x0000 0x0000 213: 0xC319 0x5CE1 0x0002 0x0000 0x0000 214: 0xC31A 0x5AA1 0x0002 0x0000 0x0000 215: 0xC31A 0x5AE1 0x0002 0x0000 0x0000 216: 0xC11A 0x5AE1 0x0002 0x0000 0x0000 217: 0xC919 0x5AE1 0x0002 0x0000 0x0000 218: 0xC119 0x5AE1 0x0002 0x0000 0x0000 219: 0xA119 0x5A61 0x0001 0x0000 0x0000 220: 0xA119 0x5A61 0x0003 0x0000 0x0000 221: 0xC119 0x5A63 0x0003 0x0000 0x0000 222: 0xC119 0x5A61 0x0003 0x0000 0x0000 223: 0xC11A 0x5A21 0x0003 0x0000 0x0000 224: 0xC11A 0x5A61 0x0003 0x0000 0x0000 225: 0xC10A 0x5A61 0x0003 0x0000 0x0000 226: 0xC90A 0x5A61 0x0003 0x0000 0x0000 227: 0xC10A 0x5A61 0x0003 0x0000 0x0000 228: 0xA10A 0x5A61 0x0001 0x0000 0x0000 229: 0xA10A 0x5A61 0x0003 0x0000 0x0000 230: 0xA10A 0x5A63 0x0003 0x0000 0x0000 231: 0xA10A 0x5A61 0x0003 0x0000 0x0000 232: 0xA10A 0x5A61 0x0003 0x0000 0x0000 233: 0xA10A 0x5A61 0x0001 0x0000 0x0000 234: 0xA10A 0x5A61 0x0003 0x0000 0x0000 235: 0xA10A 0x5A61 0x0003 0x0000 0x0000 236: 0xA10A 0x5AE1 0x4002 0x0000 0x0000 237: 0xA10A 0x5AE1 0x0002 0x0000 0x0000 238: 0xA10A 0x5A51 0x4003 0x0000 0x0000 239: 0xA10A 0x5A51 0x0003 0x0000 0x0000 240: 0xA10A 0x5AD1 0x4002 0x0000 0x0000 241: 0xA10A 0x5AD1 0x0002 0x0000 0x0000 242: 0xA106 0x5A61 0x4003 0x0000 0x0000 243: 0xA106 0x5A61 0x0003 0x0000 0x0000 244: 0xA106 0x5AE1 0x4002 0x0000 0x0000 245: 0xA106 0x5AE1 0x0002 0x0000 0x0000 246: 0xA106 0x5A51 0x4003 0x0000 0x0000 247: 0xA106 0x5A51 0x0003 0x0000 0x0000 248: 0xA106 0x5AD1 0x4002 0x0000 0x0000 249: 0xA106 0x5AD1 0x0002 0x0000 0x0000 250: 0xC10A 0x5A61 0x4003 0x0000 0x0000 251: 0xC10A 0x5A61 0x0003 0x0000 0x0000 252: 0xC10A 0x5AE1 0x4002 0x0000 0x0000 253: 0xC10A 0x5AE1 0x0002 0x0000 0x0000 254: 0xC10A 0x5A51 0x4003 0x0000 0x0000 255: 0xC10A 0x5A51 0x0003 0x0000 0x0000 256: 0xC10A 0x5AD1 0x4002 0x0000 0x0000 257: 0xC10A 0x5AD1 0x0002 0x0000 0x0000 258: 0xC106 0x5A61 0x4003 0x0000 0x0000 259: 0xC106 0x5A61 0x0003 0x0000 0x0000 260: 0xC106 0x5AE1 0x4002 0x0000 0x0000 261: 0xC106 0x5AE1 0x0002 0x0000 0x0000 262: 0xC106 0x5A51 0x4003 0x0000 0x0000 263: 0xC106 0x5A51 0x0003 0x0000 0x0000 264: 0xC106 0x5AD1 0x4002 0x0000 0x0000 265: 0xC106 0x5AD1 0x0002 0x0000 0x0000 266: 0xA10A 0x5A61 0x4003 0x0000 0x0000 267: 0xA10A 0x5A61 0x0003 0x0000 0x0000 268: 0xA10A 0x5A61 0x0003 0x0000 0x0000 269: 0xA10A 0x5A61 0x0001 0x0000 0x0000 270: 0xA10A 0x5A61 0x0003 0x0000 0x0000 271: 0xA10A 0x5A61 0x0003 0x0000 0x0000 272: 0xA10A 0x5AE1 0x4002 0x0000 0x0000 273: 0xA10A 0x5AE1 0x0002 0x0000 0x0000 274: 0xA10A 0x5CE9 0x0002 0x0000 0x0000 275: 0xA10A 0x5CE1 0x0002 0x0000 0x0000 276: 0xA10A 0x5C51 0x4003 0x0000 0x0000 277: 0xA10A 0x5C51 0x0003 0x0000 0x0000 278: 0xA10A 0x525D 0x0003 0x0000 0x0000 279: 0xA10A 0x5255 0x0003 0x0000 0x0000 280: 0xA10A 0x52D5 0x4002 0x0000 0x0000 281: 0xA10A 0x52D5 0x0002 0x0000 0x0000 282: 0xA10A 0x54DD 0x0002 0x0000 0x0000 283: 0xA10A 0x54D5 0x0002 0x0000 0x0000 284: 0xA106 0x5465 0x4003 0x0000 0x0000 285: 0xA106 0x5465 0x0003 0x0000 0x0000 286: 0x2106 0xDA69 0x0003 0x0000 0x0000 287: 0x2106 0xDA61 0x0003 0x0000 0x0000 288: 0x2106 0xDAE1 0x4002 0x0000 0x0000 289: 0x2106 0xDAE1 0x0002 0x0000 0x0000 290: 0x2106 0xDCE9 0x0002 0x0000 0x0000 291: 0x2106 0xDCE1 0x0002 0x0000 0x0000 292: 0x2106 0xDC51 0x4003 0x0000 0x0000 293: 0x2106 0xDC51 0x0003 0x0000 0x0000 294: 0x2106 0xD25D 0x0003 0x0000 0x0000 295: 0x2106 0xD255 0x0003 0x0000 0x0000 296: 0x2106 0xD2D5 0x4002 0x0000 0x0000 297: 0x2106 0xD2D5 0x0002 0x0000 0x0000 298: 0x2106 0xD4DD 0x0002 0x0000 0x0000 299: 0x2106 0xD4D5 0x0002 0x0000 0x0000 300: 0x410A 0xD465 0x4003 0x0000 0x0000 301: 0x410A 0xD465 0x0003 0x0000 0x0000 302: 0xC109 0x5A69 0x0003 0x0000 0x0000 303: 0xC109 0x5A61 0x0003 0x0000 0x0000 304: 0xC109 0x5AE1 0x4002 0x0000 0x0000 305: 0xC109 0x5AE1 0x0002 0x0000 0x0000 306: 0xC109 0x5CE9 0x0002 0x0000 0x0000 307: 0xC109 0x5CE1 0x0002 0x0000 0x0000 308: 0xC109 0x5C51 0x4003 0x0000 0x0000 309: 0xC109 0x5C51 0x0003 0x0000 0x0000 310: 0xC109 0x525D 0x0003 0x0000 0x0000 311: 0xC109 0x5255 0x0003 0x0000 0x0000 312: 0xC109 0x52D5 0x4002 0x0000 0x0000 313: 0xC109 0x52D5 0x0002 0x0000 0x0000 314: 0xC109 0x54DD 0x0002 0x0000 0x0000 315: 0xC109 0x54D5 0x0002 0x0000 0x0000 316: 0xC105 0x5465 0x4003 0x0000 0x0000 317: 0xC105 0x5465 0x0003 0x0000 0x0000 318: 0x4105 0xDA69 0x0003 0x0000 0x0000 319: 0x4105 0xDA61 0x0003 0x0000 0x0000 320: 0x4105 0xDAE1 0x4002 0x0000 0x0000 321: 0x4105 0xDAE1 0x0002 0x0000 0x0000 322: 0x4105 0xDCE9 0x0002 0x0000 0x0000 323: 0x4105 0xDCE1 0x0002 0x0000 0x0000 324: 0x4105 0xDC51 0x4003 0x0000 0x0000 325: 0x4105 0xDC51 0x0003 0x0000 0x0000 326: 0x4105 0xD25D 0x0003 0x0000 0x0000 327: 0x4105 0xD255 0x0003 0x0000 0x0000 328: 0x4105 0xD2D5 0x4002 0x0000 0x0000 329: 0x4105 0xD2D5 0x0002 0x0000 0x0000 330: 0x4105 0xD4DD 0x0002 0x0000 0x0000 331: 0x4105 0xD4D5 0x0002 0x0000 0x0000 332: 0x2109 0xD465 0x4003 0x0000 0x0000 333: 0x2109 0xD465 0x0003 0x0000 0x0000 334: 0xA10A 0x5A69 0x0003 0x0000 0x0000 335: 0xA10A 0x5A61 0x0003 0x0000 0x0000 336: 0xA10A 0x5A61 0x0003 0x0000 0x0000 337: 0xA10A 0x5A61 0x0001 0x0000 0x0000 338: 0xA10A 0x5A61 0x0003 0x0000 0x0000 339: 0xA10A 0x5A61 0x0003 0x0000 0x0000 340: 0xA10A 0x5AE1 0x4002 0x0000 0x0000 341: 0xA10A 0x5AE1 0x0002 0x0000 0x0000 342: 0xA10A 0x5CE9 0x0002 0x0000 0x0000 343: 0xA10A 0x5CE1 0x0002 0x0000 0x0000 344: 0xA10A 0x6CE1 0x0002 0x0000 0x0000 345: 0xA10A 0x5CE1 0x0002 0x0000 0x0000 346: 0xA10A 0x5C51 0x4003 0x0000 0x0000 347: 0xA10A 0x5C51 0x0003 0x0000 0x0000 348: 0xA10A 0x525D 0x0003 0x0000 0x0000 349: 0xA10A 0x5255 0x0003 0x0000 0x0000 350: 0xA10A 0x3255 0x0003 0x0000 0x0000 351: 0xA10A 0x5255 0x0003 0x0000 0x0000 352: 0xA10A 0x52D5 0x4002 0x0000 0x0000 353: 0xA10A 0x52D5 0x0002 0x0000 0x0000 354: 0xA10A 0x54DD 0x0002 0x0000 0x0000 355: 0xA10A 0x54D5 0x0002 0x0000 0x0000 356: 0xA10A 0x24D5 0x0002 0x0000 0x0000 357: 0xA10A 0x54D5 0x0002 0x0000 0x0000 358: 0xA106 0x5465 0x4003 0x0000 0x0000 359: 0xA106 0x5465 0x0003 0x0000 0x0000 360: 0x2106 0xDA69 0x0003 0x0000 0x0000 361: 0x2106 0xDA61 0x0003 0x0000 0x0000 362: 0x2006 0xFA61 0x0003 0x0000 0x0000 363: 0x2106 0xDA61 0x0003 0x0000 0x0000 364: 0x2106 0xDAE1 0x4002 0x0000 0x0000 365: 0x2106 0xDAE1 0x0002 0x0000 0x0000 366: 0x2106 0xDCE9 0x0002 0x0000 0x0000 367: 0x2106 0xDCE1 0x0002 0x0000 0x0000 368: 0x2006 0xECE1 0x0002 0x0000 0x0000 369: 0x2106 0xDCE1 0x0002 0x0000 0x0000 370: 0x2106 0xDC51 0x4003 0x0000 0x0000 371: 0x2106 0xDC51 0x0003 0x0000 0x0000 372: 0x2106 0xD25D 0x0003 0x0000 0x0000 373: 0x2106 0xD255 0x0003 0x0000 0x0000 374: 0x2006 0xB255 0x0003 0x0000 0x0000 375: 0x2106 0xD255 0x0003 0x0000 0x0000 376: 0x2106 0xD2D5 0x4002 0x0000 0x0000 377: 0x2106 0xD2D5 0x0002 0x0000 0x0000 378: 0x2106 0xD4DD 0x0002 0x0000 0x0000 379: 0x2106 0xD4D5 0x0002 0x0000 0x0000 380: 0x2006 0xA4D5 0x0002 0x0000 0x0000 381: 0x2106 0xD4D5 0x0002 0x0000 0x0000 382: 0x410A 0xD465 0x4003 0x0000 0x0000 383: 0x410A 0xD465 0x0003 0x0000 0x0000 384: 0xC109 0x5A69 0x0003 0x0000 0x0000 385: 0xC109 0x5A61 0x0003 0x0000 0x0000 386: 0xC109 0x7A60 0x0003 0x0000 0x0000 387: 0xC109 0x5A61 0x0003 0x0000 0x0000 388: 0xC109 0x5AE1 0x4002 0x0000 0x0000 389: 0xC109 0x5AE1 0x0002 0x0000 0x0000 390: 0xC109 0x5CE9 0x0002 0x0000 0x0000 391: 0xC109 0x5CE1 0x0002 0x0000 0x0000 392: 0xC109 0x5C51 0x4003 0x0000 0x0000 393: 0xC109 0x5C51 0x0003 0x0000 0x0000 394: 0xC109 0x525D 0x0003 0x0000 0x0000 395: 0xC109 0x5255 0x0003 0x0000 0x0000 396: 0xC109 0x3254 0x0003 0x0000 0x0000 397: 0xC109 0x5255 0x0003 0x0000 0x0000 398: 0xC109 0x52D5 0x4002 0x0000 0x0000 399: 0xC109 0x52D5 0x0002 0x0000 0x0000 400: 0xC109 0x54DD 0x0002 0x0000 0x0000 401: 0xC109 0x54D5 0x0002 0x0000 0x0000 402: 0xC109 0x24D4 0x0002 0x0000 0x0000 403: 0xC109 0x54D5 0x0002 0x0000 0x0000 404: 0xC105 0x5465 0x4003 0x0000 0x0000 405: 0xC105 0x5465 0x0003 0x0000 0x0000 406: 0x4105 0xDA69 0x0003 0x0000 0x0000 407: 0x4105 0xDA61 0x0003 0x0000 0x0000 408: 0x4005 0xFA60 0x0003 0x0000 0x0000 409: 0x4105 0xDA61 0x0003 0x0000 0x0000 410: 0x4105 0xDAE1 0x4002 0x0000 0x0000 411: 0x4105 0xDAE1 0x0002 0x0000 0x0000 412: 0x4105 0xDCE9 0x0002 0x0000 0x0000 413: 0x4105 0xDCE1 0x0002 0x0000 0x0000 414: 0x4005 0xECE0 0x0002 0x0000 0x0000 415: 0x4105 0xDCE1 0x0002 0x0000 0x0000 416: 0x4105 0xDC51 0x4003 0x0000 0x0000 417: 0x4105 0xDC51 0x0003 0x0000 0x0000 418: 0x4105 0xD25D 0x0003 0x0000 0x0000 419: 0x4105 0xD255 0x0003 0x0000 0x0000 420: 0x4005 0xB254 0x0003 0x0000 0x0000 421: 0x4105 0xD255 0x0003 0x0000 0x0000 422: 0x4105 0xD2D5 0x4002 0x0000 0x0000 423: 0x4105 0xD2D5 0x0002 0x0000 0x0000 424: 0x4105 0xD4DD 0x0002 0x0000 0x0000 425: 0x4105 0xD4D5 0x0002 0x0000 0x0000 426: 0x4005 0xA4D4 0x0002 0x0000 0x0000 427: 0x4105 0xD4D5 0x0002 0x0000 0x0000 428: 0x2109 0xD465 0x4003 0x0000 0x0000 429: 0x2109 0xD465 0x0003 0x0000 0x0000 430: 0xA10A 0x5A69 0x0003 0x0000 0x0000 431: 0xA10A 0x5A61 0x0003 0x0000 0x0000 432: 0xA10A 0x7A61 0x0003 0x0000 0x0000 433: 0xA10A 0x5A61 0x0003 0x0000 0x0000 434: 0xA10A 0x5A61 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OOOIIIIPOPIPOOOG IP GIOOOOPIOIOOIOOI G P G UUT inputs: 11 UUT outputs: 20 pins used: 31 not used: 35 434 'test steps' 730 lines ; M217 PCB REV A SCHEMATIC REV (BLANK) 4-BIT CLOCK REGISTER WITH BUFFER REGISTER ; ; ; 8 FLIP-FLOPS: CNT0 (MSB) THRU CNT3 (LSB), BUF0 (MSB) THRU BUF3 (LSB) ; CNT CAN BE INCREMENTED, CLEARED, JAMMED FROM BUF ; BUF CAN BE CLEARED, LOAD FROM CNT, JAMS FROM PINS (AC) ; BUF OUTPUTS CAN BE GATED TO PINS (INTERNAL BUS, OC OUTPUTS) PINS Main menu Thu Jun 29 20:23:25 2017 test file is: tests\m217.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:23:40 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SEDDFHNJHKAMPRSMKJLNVLVBCFEPRTU SIDE 2121112221121111211122111222222 DIRECTION IIIIIIIOOOOOOOOIPPPPIIIOOOOOOOO all fails was lo 0000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111111 total fails 0, total passes 43 Main menu Thu Jun 29 20:24:07 2017 test file is: tests\m217.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:24:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SEDDFHNJHKAMPRSMKJLNVLVBCFEPRTU SIDE 2121112221121111211122111222222 DIRECTION IIIIIIIOOOOOOOOIPPPPIIIOOOOOOOO all fails was lo 0000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111111 total fails 0, total passes 20 Main menu Thu Jun 29 20:24:15 2017 test file is: tests\m217.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst could not open test file. valid test files are: reverting back to test file: tests\m217.tst Main menu Thu Jun 29 20:24:36 2017 test file is: tests\m217.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:24:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SEDDFHNJHKAMPRSMKJLNVLVBCFEPRTU SIDE 2121112221121111211122111222222 DIRECTION IIIIIIIOOOOOOOOIPPPPIIIOOOOOOOO all fails I I IOOOOOOOO PPPPII OOOOOOOO was lo 000000000000 00000 00000000000 falling vvv v v v v v vvv rising ^^^ ^ ^ ^ ^ ^ ^^^ was hi 111 1 1 1 11 1 11 111 total fails 9, total passes 0 Main menu Thu Jun 29 20:24:44 2017 test file is: tests\m217.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst could not open test file. valid test files are: reverting back to test file: tests\m217.tst Main menu Thu Jun 29 20:24:51 2017 test file is: tests\m217.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Thu Jun 29 20:25:22 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst reading test file: tests\m310.tst comment: M310 REV D DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AH2 PULSE INPUT (EDGE?) pins: 2 O AJ2 0 NS DELAY TAP pins: 3 O AK2 50 NS DELAY TAP pins: 4 O AL2 100 NS DELAY TAP pins: 5 O AM2 150 NS DELAY TAP pins: 6 O AN2 200 NS DELAY TAP pins: 7 O AP2 250 NS DELAY TAP pins: 8 O AR2 300 NS DELAY TAP pins: 9 O AS2 350 NS DELAY TAP pins: 10 O AT2 400 NS DELAY TAP pins: 11 O AU2 450 NS DELAY TAP pins: 12 O AV2 500 NS DELAY TAP pins: 13 I AE1 INPUT 1 (NORMALLY CONNECTED TO A DELAY TAP) pins: 14 O AF1 OUTPUT 1 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: 15 I AH1 INPUT 2 (NORMALLY CONNECTED TO A DELAY TAP) pins: 16 O AJ1 OUTPUT 2 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: direction: IOOOOOOOOOOOIOIO test 1: 0111111111110000 test 2: 100000000000 test 3: 011111111111001X test 4: 100000000000 test 5: 0111111111111X00 test 6: 100000000000 test 7: 0111111111110X0X test 8: 100000000000 end: END summary column 1: offset 0, mask 0x0002 column 2: offset 0, mask 0x0001 column 3: offset 1, mask 0x0001 column 4: offset 1, mask 0x0002 column 5: offset 1, mask 0x0004 column 6: offset 1, mask 0x0008 column 7: offset 1, mask 0x0010 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0080 column 11: offset 2, mask 0x0001 column 12: offset 2, mask 0x0002 column 13: offset 0, mask 0x0800 column 14: offset 0, mask 0x0400 column 15: offset 0, mask 0x0200 column 16: offset 0, mask 0x0100 direction bits (1=input) 0xF5FD 0xFFFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x00FF 0x0003 0x0000 0x0000 2: 0x0002 0x0000 0x0000 0x0000 0x0000 3: 0x0201 0x00FF 0x0003 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 4: 0x0202 0x0000 0x0000 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 5: 0x0801 0x00FF 0x0003 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 6: 0x0802 0x0000 0x0000 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 7: 0x0001 0x00FF 0x0003 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 8: 0x0002 0x0000 0x0000 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIO G P G IOOOOOOOOOOO G P G UUT inputs: 3 UUT outputs: 13 pins used: 16 not used: 50 8 'test steps' 37 lines M310 REV D DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. AE1 IS THE INPUT FOR THE AF1 OUTPUT. AH1 IS THE INPUT FOR THE AJ1 OUTPUT. CONNECT AE1 TO EACH TAP: PINS Main menu Thu Jun 29 20:25:26 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:25:36 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^ was hi 111111111111111 total fails 0, total passes 346 Main menu Thu Jun 29 20:25:53 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Thu Jun 29 20:25:55 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Thu Jun 29 20:25:55 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:25:58 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 587 Main menu Thu Jun 29 20:26:13 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:26:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 1227 Main menu Thu Jun 29 20:26:23 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Thu Jun 29 20:26:39 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst reading test file: tests\m310.tst comment: M310 REV D DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AH2 PULSE INPUT (EDGE?) pins: 2 O AJ2 0 NS DELAY TAP pins: 3 O AK2 50 NS DELAY TAP pins: 4 O AL2 100 NS DELAY TAP pins: 5 O AM2 150 NS DELAY TAP pins: 6 O AN2 200 NS DELAY TAP pins: 7 O AP2 250 NS DELAY TAP pins: 8 O AR2 300 NS DELAY TAP pins: 9 O AS2 350 NS DELAY TAP pins: 10 O AT2 400 NS DELAY TAP pins: 11 O AU2 450 NS DELAY TAP pins: 12 O AV2 500 NS DELAY TAP pins: 13 I AE1 INPUT 1 (NORMALLY CONNECTED TO A DELAY TAP) pins: 14 O AF1 OUTPUT 1 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: 15 I AH1 INPUT 2 (NORMALLY CONNECTED TO A DELAY TAP) pins: 16 O AJ1 OUTPUT 2 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: direction: IOOOOOOOOOOOIOIO test 1: 0111111111110000 test 2: 100000000000 test 3: 011111111111001X test 4: 100000000000 test 5: 0111111111111X00 test 6: 100000000000 test 7: 0111111111110X0X test 8: 100000000000 end: END summary column 1: offset 0, mask 0x0002 column 2: offset 0, mask 0x0001 column 3: offset 1, mask 0x0001 column 4: offset 1, mask 0x0002 column 5: offset 1, mask 0x0004 column 6: offset 1, mask 0x0008 column 7: offset 1, mask 0x0010 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0080 column 11: offset 2, mask 0x0001 column 12: offset 2, mask 0x0002 column 13: offset 0, mask 0x0800 column 14: offset 0, mask 0x0400 column 15: offset 0, mask 0x0200 column 16: offset 0, mask 0x0100 direction bits (1=input) 0xF5FD 0xFFFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x00FF 0x0003 0x0000 0x0000 2: 0x0002 0x0000 0x0000 0x0000 0x0000 3: 0x0201 0x00FF 0x0003 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 4: 0x0202 0x0000 0x0000 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 5: 0x0801 0x00FF 0x0003 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 6: 0x0802 0x0000 0x0000 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 7: 0x0001 0x00FF 0x0003 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 8: 0x0002 0x0000 0x0000 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIO G P G IOOOOOOOOOOO G P G UUT inputs: 3 UUT outputs: 13 pins used: 16 not used: 50 8 'test steps' 37 lines M310 REV D DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. AE1 IS THE INPUT FOR THE AF1 OUTPUT. AH1 IS THE INPUT FOR THE AJ1 OUTPUT. CONNECT AE1 TO EACH TAP: PINS Main menu Thu Jun 29 20:26:44 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:26:46 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^ was hi 111111111111111 total fails 0, total passes 443 Main menu Thu Jun 29 20:26:49 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:27:04 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails OOOOOOOOOOO O O was lo 000000 00 00000 falling vv vvvv rising ^^ ^^^^ was hi 11 11 1 1111 total fails 279, total passes 0 Main menu Thu Jun 29 20:27:14 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m360.tst reading test file: tests\m360.tst comment: M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE comment: MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. comment: pins: PINS pins: 1 I AP2 INPUT 1 pins: 2 I AR2 INPUT 2 pins: 3 O AS2 POSITIVE 100 NS PULSE OUTPUT WHEN (INPUT 1 AND INPUT 2) RISING EDGE pins: 4 P AT2 NEGATIVE OF AS2, NEGATIVE 5 US PULSE OUTPUT (FAST DOWN, RC UP) (OPEN DRAIN) pins: 5 I AU2 INVERTER INPUT pins: 6 P AV2 INVERTER OUTPUT (OPEN DRAIN) pins: direction: IIOPIP comment: ; INITAL OFF test 1: 000101 comment: ; NO PULSES test 2: 01 test 3: 00 test 4: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 5: 1101 comment: ;AGAIN WITH INVERTER ON comment: ; INITAL OFF test 6: 000110 comment: ; NO PULSES test 7: 01 test 8: 00 test 9: 10 comment: ; PULSE (SO FAST, IT WLL BE OVER BEFORE TESTED) test 10: 1101 comment: ; BACK TO INITAL CONDITIONS test 11: 000101 end: END summary column 1: offset 1, mask 0x0010 column 2: offset 1, mask 0x0020 column 3: offset 1, mask 0x0040 column 4: offset 1, mask 0x0080 column 5: offset 2, mask 0x0001 column 6: offset 2, mask 0x0002 direction bits (1=input) 0xFFFF 0xFFCF 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0080 0x0002 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0080 0x0002 0x0000 0x0000 2: 0x0000 0x00A0 0x0002 0x0000 0x0000 3: 0x0000 0x0080 0x0002 0x0000 0x0000 4: 0x0000 0x0090 0x0002 0x0000 0x0000 5: 0x0000 0x00B0 0x0002 0x0000 0x0000 6: 0x0000 0x0080 0x0001 0x0000 0x0000 7: 0x0000 0x00A0 0x0001 0x0000 0x0000 8: 0x0000 0x0080 0x0001 0x0000 0x0000 9: 0x0000 0x0090 0x0001 0x0000 0x0000 10: 0x0000 0x00B0 0x0001 0x0000 0x0000 11: 0x0000 0x0080 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G IIOPIP G P G UUT inputs: 3 UUT outputs: 3 pins used: 6 not used: 60 11 'test steps' 37 lines M360 SCHEMATIC REV B, PCB REV B VARIABLE DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. TRIGGER ON STEP 5, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE TRIGGER ON STEP 10, OBSERVE AS2 POSITIVE PULSE, AT2 NEGATIVE PULSE MANUALLY CHANGE DELAY ADJUSTMENT, OBSERVE WITH OSCILLOSCOPE. PINS Main menu Thu Jun 29 20:27:18 2017 test file is: tests\m360.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:27:27 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 342 Main menu Thu Jun 29 20:27:30 2017 test file is: tests\m360.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:27:43 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAA LETTER PRSTUV SIDE 222222 DIRECTION IIOPIP all fails was lo 000 00 falling vv vv rising ^^ ^^ was hi 11 111 total fails 0, total passes 340 Main menu Thu Jun 29 20:27:46 2017 test file is: tests\m360.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Thu Jun 29 20:28:07 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:28:08 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 23 Main menu Thu Jun 29 20:28:12 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:28:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 16 Main menu Thu Jun 29 20:28:25 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Thu Jun 29 20:28:44 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:28:47 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 121 Main menu Thu Jun 29 20:28:53 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Thu Jun 29 20:29:21 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Thu Jun 29 20:29:38 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:29:40 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 19 Main menu Thu Jun 29 20:29:43 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:29:55 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Thu Jun 29 20:29:57 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Thu Jun 29 20:30:01 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:30:03 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 60 Main menu Thu Jun 29 20:30:06 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Thu Jun 29 20:30:20 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:30:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 83 Main menu Thu Jun 29 20:30:26 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:30:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 55 Main menu Thu Jun 29 20:30:41 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:31:02 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 68 Main menu Thu Jun 29 20:31:09 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Thu Jun 29 20:31:36 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:32:31 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails I OO OO OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 37, total passes 0 Main menu Thu Jun 29 20:32:47 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Thu Jun 29 20:32:55 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 65: *** FAIL *************************** 24 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail I OO OO OO all fails I OO OO OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 65, total passes 0 step 1 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 2 00001000010000100000110001100011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 3 00011000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 4 01011000010000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 step 5 11111000010000100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 6 10111000010000100000110001100011 fail ^^ step 7 11111000010000100000110001100011 step 8 11011000010000100000110001100011 step 9 10011000010000100000110001100011 step 10 00010100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 11 00010100010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 12 00001000010000100000110001100011 fail ^ step 13 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 14 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 15 00001000110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 16 00001010110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 17 00001011110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 18 00001001110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 19 00001011110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 20 00001010110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 21 00001000110000100000110001100011 fail ^ step 22 00001100101000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 23 00001000101000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 24 00001000010000100000110001100011 fail ^ step 25 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 26 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 27 00001000010001100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 01 step 28 00001000010101010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 10 step 29 10001000010111100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 30 10001000010011100000110001100011 fail ^^ step 31 10001000010111100000110001100011 step 32 10001000010101100000110001100011 step 33 10001000010001100000110001100011 step 34 00001100011001010000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 35 00001000010001010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 36 00001000010000100000110001100011 fail ^ step 37 00001100011000110000110001100011 step 38 00001100011000111000100001000010 step 39 00001100011000111001100001000010 step 40 00001100011000111101010001000010 step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 step 52 00001100011000111000101010100010 step 53 00001100011000111000101110100010 step 54 00001100011000111000100110100010 step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 66: *** FAIL *************************** 24 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail I OO OO OO all fails I OO OO OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 66, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 2 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 3 00011000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 4 01011000010000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 step 5 11111000010000100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 6 10111000010000100000110001100011 fail ^^ step 7 11111000010000100000110001100011 step 8 11011000010000100000110001100011 step 9 10011000010000100000110001100011 step 10 00010100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 11 00010100010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 12 00001000010000100000110001100011 fail ^ step 13 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 14 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 15 00001000110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 16 00001010110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 17 00001011110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 18 00001001110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 19 00001011110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 20 00001010110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 21 00001000110000100000110001100011 fail ^ step 22 00001100101000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 23 00001000101000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 24 00001000010000100000110001100011 fail ^ step 25 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 26 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 27 00001000010001100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 01 step 28 00001000010101010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 10 step 29 10001000010111100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 30 10001000010011100000110001100011 fail ^^ step 31 10001000010111100000110001100011 step 32 10001000010101100000110001100011 step 33 10001000010001100000110001100011 step 34 00001100011001010000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 35 00001000010001010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 36 00001000010000100000110001100011 fail ^ step 37 00001100011000110000110001100011 step 38 00001100011000111000100001000010 step 39 00001100011000111001100001000010 step 40 00001100011000111101010001000010 step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 step 52 00001100011000111000101010100010 step 53 00001100011000111000101110100010 step 54 00001100011000111000100110100010 step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 67: *** FAIL *************************** 24 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail I OO OO OO all fails I OO OO OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 67, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 2 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 3 00011000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 4 01011000010000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 step 5 11111000010000100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 6 10111000010000100000110001100011 fail ^^ step 7 11111000010000100000110001100011 step 8 11011000010000100000110001100011 step 9 10011000010000100000110001100011 step 10 00010100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 11 00010100010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 12 00001000010000100000110001100011 fail ^ step 13 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 14 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 15 00001000110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 16 00001010110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 17 00001011110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 18 00001001110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 19 00001011110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 20 00001010110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 21 00001000110000100000110001100011 fail ^ step 22 00001100101000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 23 00001000101000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 24 00001000010000100000110001100011 fail ^ step 25 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 26 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 27 00001000010001100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 01 step 28 00001000010101010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 10 step 29 10001000010111100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 30 10001000010011100000110001100011 fail ^^ step 31 10001000010111100000110001100011 step 32 10001000010101100000110001100011 step 33 10001000010001100000110001100011 step 34 00001100011001010000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 35 00001000010001010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 36 00001000010000100000110001100011 fail ^ step 37 00001100011000110000110001100011 step 38 00001100011000111000100001000010 step 39 00001100011000111001100001000010 step 40 00001100011000111101010001000010 step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 step 52 00001100011000111000101010100010 step 53 00001100011000111000101110100010 step 54 00001100011000111000100110100010 step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 68: *** FAIL *************************** 24 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail I OO OO OO all fails I OO OO OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 68, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails I OO OO OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 68, total passes 0 Main menu Thu Jun 29 20:33:59 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m179.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Thu Jun 29 20:34:04 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 08:36:07 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 08:36:12 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit *************************************************************************** * did not verify registers after initialize (chip reset). * * check that the tester is cabled to LPT port and that the power is on. * *************************************************************************** Main menu Fri Jun 30 08:36:25 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 08:36:25 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 08:36:41 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 7 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 9 00011001010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 10 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 12 00010110010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 13 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 00010101100101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 18 00010101011001010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 19 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 21 00010101010110010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 22 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 24 00010101010101100101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 25 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 27 00010101010101011001010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 28 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 30 00010101010101010110010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 31 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 33 00010101010101010101100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 34 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 36 00010101010101010101011001010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 37 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 00010101010101010101010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 42 00010101010101010101010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 43 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 45 00010101010101010101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 46 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 00010101010101010101010101010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 00010101010101010101010101010101 fail ^ step 51 10101010101010101010101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 00101010101010101010101010101010 fail ^ step 53 10101010101010101010101010101010 step 54 10011010101010101010101010101010 step 55 10101010101010101010101010101010 step 56 10100110101010101010101010101010 step 57 10101010101010101010101010101010 step 58 10101001101010101010101010101010 step 59 10101010101010101010101010101010 step 60 10101010011010101010101010101010 step 61 10101010101010101010101010101010 step 62 10101010100110101010101010101010 step 63 10101010101010101010101010101010 step 64 10101010101001101010101010101010 step 65 10101010101010101010101010101010 step 66 10101010101010011010101010101010 step 67 10101010101010101010101010101010 step 68 10101010101010100110101010101010 step 69 10101010101010101010101010101010 step 70 10101010101010101001101010101010 step 71 10101010101010101010101010101010 step 72 10101010101010101010011010101010 step 73 10101010101010101010101010101010 step 74 10101010101010101010100110101010 step 75 10101010101010101010101010101010 step 76 10101010101010101010101001101010 step 77 10101010101010101010101010101010 step 78 10101010101010101010101010011010 step 79 10101010101010101010101010101010 step 80 10101010101010101010101010100110 step 81 10101010101010101010101010101010 step 82 10101010101010101010101010101001 step 83 10101010101010101010101010101010 step 84 10101010101010101010101010101010 test 24: *** FAIL *************************** 50 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O all fails O was hi 1 111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 24, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 010101010101010101010101010101 step 1 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 2 00010101010101010101010101010101 fail ^ step 3 10010101010101010101010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 4 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 6 00100101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 7 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 9 00011001010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 10 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 12 00010110010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 13 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 00010101100101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 18 00010101011001010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 19 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 21 00010101010110010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 22 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 24 00010101010101100101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 25 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 27 00010101010101011001010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 28 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 30 00010101010101010110010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 31 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 33 00010101010101010101100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 34 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 36 00010101010101010101011001010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 37 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 00010101010101010101010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 42 00010101010101010101010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 43 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 45 00010101010101010101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 46 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 00010101010101010101010101010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 00010101010101010101010101010101 fail ^ step 51 10101010101010101010101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 00101010101010101010101010101010 fail ^ step 53 10101010101010101010101010101010 step 54 10011010101010101010101010101010 step 55 10101010101010101010101010101010 step 56 10100110101010101010101010101010 step 57 10101010101010101010101010101010 step 58 10101001101010101010101010101010 step 59 10101010101010101010101010101010 step 60 10101010011010101010101010101010 step 61 10101010101010101010101010101010 step 62 10101010100110101010101010101010 step 63 10101010101010101010101010101010 step 64 10101010101001101010101010101010 step 65 10101010101010101010101010101010 step 66 10101010101010011010101010101010 step 67 10101010101010101010101010101010 step 68 10101010101010100110101010101010 step 69 10101010101010101010101010101010 step 70 10101010101010101001101010101010 step 71 10101010101010101010101010101010 step 72 10101010101010101010011010101010 step 73 10101010101010101010101010101010 step 74 10101010101010101010100110101010 step 75 10101010101010101010101010101010 step 76 10101010101010101010101001101010 step 77 10101010101010101010101010101010 step 78 10101010101010101010101010011010 step 79 10101010101010101010101010101010 step 80 10101010101010101010101010100110 step 81 10101010101010101010101010101010 step 82 10101010101010101010101010101001 step 83 10101010101010101010101010101010 step 84 10101010101010101010101010101010 test 25: *** FAIL *************************** 50 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O all fails O was hi 1 111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 25, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 010101010101010101010101010101 step 1 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 2 00010101010101010101010101010101 fail ^ step 3 10010101010101010101010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 4 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 6 00100101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 7 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 9 00011001010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 10 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 12 00010110010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 13 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 00010101100101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 18 00010101011001010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 19 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 21 00010101010110010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 22 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 24 00010101010101100101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 25 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 27 00010101010101011001010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 28 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 30 00010101010101010110010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 31 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 33 00010101010101010101100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 34 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 36 00010101010101010101011001010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 37 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 00010101010101010101010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 42 00010101010101010101010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 43 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 45 00010101010101010101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 46 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 00010101010101010101010101010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 00010101010101010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 00010101010101010101010101010101 fail ^ step 51 10101010101010101010101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 00101010101010101010101010101010 fail ^ step 53 10101010101010101010101010101010 step 54 10011010101010101010101010101010 step 55 10101010101010101010101010101010 step 56 10100110101010101010101010101010 step 57 10101010101010101010101010101010 step 58 10101001101010101010101010101010 step 59 10101010101010101010101010101010 step 60 10101010011010101010101010101010 step 61 10101010101010101010101010101010 step 62 10101010100110101010101010101010 step 63 10101010101010101010101010101010 step 64 10101010101001101010101010101010 step 65 10101010101010101010101010101010 step 66 10101010101010011010101010101010 step 67 10101010101010101010101010101010 step 68 10101010101010100110101010101010 step 69 10101010101010101010101010101010 step 70 10101010101010101001101010101010 step 71 10101010101010101010101010101010 step 72 10101010101010101010011010101010 step 73 10101010101010101010101010101010 step 74 10101010101010101010100110101010 step 75 10101010101010101010101010101010 step 76 10101010101010101010101001101010 step 77 10101010101010101010101010101010 step 78 10101010101010101010101010011010 step 79 10101010101010101010101010101010 step 80 10101010101010101010101010100110 step 81 10101010101010101010101010101010 step 82 10101010101010101010101010101001 step 83 10101010101010101010101010101010 step 84 10101010101010101010101010101010 test 26: *** FAIL *************************** 50 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O all fails O was hi 1 111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 26, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O was lo 00000000000000000000000000000000 falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1 111111111111111111111111111111 total fails 26, total passes 0 Main menu Fri Jun 30 08:43:28 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 08:43:30 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 08:43:33 2017 output is: 18 O AB1 E2-11 space toggle output N next output Q quit output is: 14 O AE1 E2-8 space toggle output N next output Q quit output is: 12 O AH1 E1-11 space toggle output N next output Q quit output is: 10 O AK1 E1-8 space toggle output N next output Q quit output is: 8 O AM1 E3-11 space toggle output N next output Q quit output is: 6 O AP1 E3-8 space toggle output N next output Q quit output is: 4 O AS1 E4-11 space toggle output N next output Q quit output is: 2 O AU1 E4-8 space toggle output N next output Q quit step 1 00010101010101010101010101010101 step 2 00010101010101010101010101010101 step 3 10010101010101010101010101010101 step 4 00010101010101010101010101010101 step 5 00010101010101010101010101010101 step 6 00100101010101010101010101010101 step 7 00010101010101010101010101010101 step 8 00010101010101010101010101010101 step 9 00011001010101010101010101010101 step 10 00010101010101010101010101010101 step 11 00010101010101010101010101010101 step 12 00010110010101010101010101010101 step 13 00010101010101010101010101010101 step 14 00010101010101010101010101010101 step 15 00010101100101010101010101010101 step 16 00010101010101010101010101010101 step 17 00010101010101010101010101010101 step 18 00010101011001010101010101010101 step 19 00010101010101010101010101010101 step 20 00010101010101010101010101010101 step 21 00010101010110010101010101010101 step 22 00010101010101010101010101010101 step 23 00010101010101010101010101010101 step 24 00010101010101100101010101010101 step 25 00010101010101010101010101010101 step 26 00010101010101010101010101010101 step 27 00010101010101011001010101010101 step 28 00010101010101010101010101010101 step 29 00010101010101010101010101010101 step 30 00010101010101010110010101010101 step 31 00010101010101010101010101010101 step 32 00010101010101010101010101010101 step 33 00010101010101010101100101010101 step 34 00010101010101010101010101010101 step 35 00010101010101010101010101010101 step 36 00010101010101010101011001010101 step 37 00010101010101010101010101010101 step 38 00010101010101010101010101010101 step 39 00010101010101010101010110010101 step 40 00010101010101010101010101010101 step 41 00010101010101010101010101010101 step 42 00010101010101010101010101100101 step 43 00010101010101010101010101010101 step 44 00010101010101010101010101010101 step 45 00010101010101010101010101011001 step 46 00010101010101010101010101010101 step 47 00010101010101010101010101010101 step 48 00010101010101010101010101010110 step 49 00010101010101010101010101010101 step 50 00010101010101010101010101010101 step 51 10101010101010101010101010101010 step 52 00101010101010101010101010101010 step 53 10101010101010101010101010101010 step 54 10011010101010101010101010101010 step 55 10101010101010101010101010101010 step 56 10100110101010101010101010101010 step 57 10101010101010101010101010101010 step 58 10101001101010101010101010101010 step 59 10101010101010101010101010101010 step 60 10101010011010101010101010101010 step 61 10101010101010101010101010101010 step 62 10101010100110101010101010101010 step 63 10101010101010101010101010101010 step 64 10101010101001101010101010101010 step 65 10101010101010101010101010101010 step 66 10101010101010011010101010101010 step 67 10101010101010101010101010101010 step 68 10101010101010100110101010101010 step 69 10101010101010101010101010101010 step 70 10101010101010101001101010101010 step 71 10101010101010101010101010101010 step 72 10101010101010101010011010101010 step 73 10101010101010101010101010101010 step 74 10101010101010101010100110101010 step 75 10101010101010101010101010101010 step 76 10101010101010101010101001101010 step 77 10101010101010101010101010101010 step 78 10101010101010101010101010011010 step 79 10101010101010101010101010101010 step 80 10101010101010101010101010100110 step 81 10101010101010101010101010101010 step 82 10101010101010101010101010101001 step 83 10101010101010101010101010101010 step 84 10101010101010101010101010101010 step 1 00010101010101010101010101010101 step 2 00010101010101010101010101010101 step 3 10010101010101010101010101010101 step 4 00010101010101010101010101010101 step 5 00010101010101010101010101010101 step 6 00100101010101010101010101010101 step 7 00010101010101010101010101010101 step 8 00010101010101010101010101010101 step 9 00011001010101010101010101010101 step 10 00010101010101010101010101010101 step 11 00010101010101010101010101010101 step 12 00010110010101010101010101010101 step 13 00010101010101010101010101010101 step 14 00010101010101010101010101010101 step 15 00010101100101010101010101010101 step 16 00010101010101010101010101010101 step 17 00010101010101010101010101010101 step 18 00010101011001010101010101010101 step 19 00010101010101010101010101010101 step 20 00010101010101010101010101010101 step 21 00010101010110010101010101010101 step 22 00010101010101010101010101010101 step 23 00010101010101010101010101010101 step 24 00010101010101100101010101010101 step 25 00010101010101010101010101010101 step 26 00010101010101010101010101010101 step 27 00010101010101011001010101010101 step 28 00010101010101010101010101010101 step 29 00010101010101010101010101010101 step 30 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00010101010101010110010101010101 step 31 00010101010101010101010101010101 step 32 00010101010101010101010101010101 step 33 00010101010101010101100101010101 step 34 00010101010101010101010101010101 step 35 00010101010101010101010101010101 step 36 00010101010101010101011001010101 step 37 00010101010101010101010101010101 step 38 00010101010101010101010101010101 step 39 00010101010101010101010110010101 step 40 00010101010101010101010101010101 step 41 00010101010101010101010101010101 step 42 00010101010101010101010101100101 step 43 00010101010101010101010101010101 step 44 00010101010101010101010101010101 step 45 00010101010101010101010101011001 step 46 00010101010101010101010101010101 step 47 00010101010101010101010101010101 step 48 00010101010101010101010101010110 step 49 00010101010101010101010101010101 step 50 00010101010101010101010101010101 step 51 10101010101010101010101010101010 step 52 00101010101010101010101010101010 step 53 10101010101010101010101010101010 step 54 10011010101010101010101010101010 step 55 10101010101010101010101010101010 step 56 10100110101010101010101010101010 step 57 10101010101010101010101010101010 step 58 10101001101010101010101010101010 step 59 10101010101010101010101010101010 step 60 10101010011010101010101010101010 step 61 10101010101010101010101010101010 step 62 10101010100110101010101010101010 step 63 10101010101010101010101010101010 step 64 10101010101001101010101010101010 step 65 10101010101010101010101010101010 step 66 10101010101010011010101010101010 step 67 10101010101010101010101010101010 step 68 10101010101010100110101010101010 step 69 10101010101010101010101010101010 step 70 10101010101010101001101010101010 step 71 10101010101010101010101010101010 step 72 10101010101010101010011010101010 step 73 10101010101010101010101010101010 step 74 10101010101010101010100110101010 step 75 10101010101010101010101010101010 step 76 10101010101010101010101001101010 step 77 10101010101010101010101010101010 step 78 10101010101010101010101010011010 step 79 10101010101010101010101010101010 step 80 10101010101010101010101010100110 step 81 10101010101010101010101010101010 step 82 10101010101010101010101010101001 step 83 10101010101010101010101010101010 step 84 10101010101010101010101010101010 step 1 00010101010101010101010101010101 step 2 00010101010101010101010101010101 step 3 10010101010101010101010101010101 step 4 00010101010101010101010101010101 step 5 00010101010101010101010101010101 step 6 00100101010101010101010101010101 step 7 00010101010101010101010101010101 step 8 00010101010101010101010101010101 step 9 00011001010101010101010101010101 step 10 00010101010101010101010101010101 step 11 00010101010101010101010101010101 step 12 00010110010101010101010101010101 step 13 00010101010101010101010101010101 step 14 00010101010101010101010101010101 step 15 00010101100101010101010101010101 step 16 00010101010101010101010101010101 step 17 00010101010101010101010101010101 step 18 00010101011001010101010101010101 step 19 00010101010101010101010101010101 step 20 00010101010101010101010101010101 step 21 00010101010110010101010101010101 step 22 00010101010101010101010101010101 step 23 00010101010101010101010101010101 step 24 00010101010101100101010101010101 step 25 00010101010101010101010101010101 step 26 00010101010101010101010101010101 step 27 00010101010101011001010101010101 step 28 00010101010101010101010101010101 step 29 00010101010101010101010101010101 step 30 00010101010101010110010101010101 step 31 00010101010101010101010101010101 step 32 00010101010101010101010101010101 step 33 00010101010101010101100101010101 step 34 00010101010101010101010101010101 step 35 00010101010101010101010101010101 step 36 00010101010101010101011001010101 step 37 00010101010101010101010101010101 step 38 00010101010101010101010101010101 step 39 00010101010101010101010110010101 step 40 00010101010101010101010101010101 step 41 00010101010101010101010101010101 step 42 00010101010101010101010101100101 step 43 00010101010101010101010101010101 step 44 00010101010101010101010101010101 step 45 00010101010101010101010101011001 step 46 00010101010101010101010101010101 step 47 00010101010101010101010101010101 step 48 00010101010101010101010101010110 step 49 00010101010101010101010101010101 step 50 00010101010101010101010101010101 step 51 10101010101010101010101010101010 step 52 00101010101010101010101010101010 step 53 10101010101010101010101010101010 step 54 10011010101010101010101010101010 step 55 10101010101010101010101010101010 step 56 10100110101010101010101010101010 step 57 10101010101010101010101010101010 step 58 10101001101010101010101010101010 step 59 10101010101010101010101010101010 step 60 10101010011010101010101010101010 step 61 10101010101010101010101010101010 step 62 10101010100110101010101010101010 step 63 10101010101010101010101010101010 step 64 10101010101001101010101010101010 step 65 10101010101010101010101010101010 step 66 10101010101010011010101010101010 step 67 10101010101010101010101010101010 step 68 10101010101010100110101010101010 step 69 10101010101010101010101010101010 step 70 10101010101010101001101010101010 step 71 10101010101010101010101010101010 step 72 10101010101010101010011010101010 step 73 10101010101010101010101010101010 step 74 10101010101010101010100110101010 step 75 10101010101010101010101010101010 step 76 10101010101010101010101001101010 step 77 10101010101010101010101010101010 step 78 10101010101010101010101010011010 step 79 10101010101010101010101010101010 step 80 10101010101010101010101010100110 step 81 10101010101010101010101010101010 step 82 10101010101010101010101010101001 step 83 10101010101010101010101010101010 step 84 10101010101010101010101010101010 step 1 00010101010101010101010101010101 step 2 00010101010101010101010101010101 step 3 10010101010101010101010101010101 step 4 00010101010101010101010101010101 step 5 00010101010101010101010101010101 step 6 00100101010101010101010101010101 step 7 00010101010101010101010101010101 step 8 00010101010101010101010101010101 step 9 00011001010101010101010101010101 step 10 00010101010101010101010101010101 step 11 00010101010101010101010101010101 step 12 00010110010101010101010101010101 step 13 00010101010101010101010101010101 step 14 00010101010101010101010101010101 step 15 00010101100101010101010101010101 step 16 00010101010101010101010101010101 step 17 00010101010101010101010101010101 step 18 00010101011001010101010101010101 step 19 00010101010101010101010101010101 step 20 00010101010101010101010101010101 step 21 00010101010110010101010101010101 step 22 00010101010101010101010101010101 step 23 00010101010101010101010101010101 step 24 00010101010101100101010101010101 step 25 00010101010101010101010101010101 step 26 00010101010101010101010101010101 step 27 00010101010101011001010101010101 step 28 00010101010101010101010101010101 step 29 00010101010101010101010101010101 step 30 00010101010101010110010101010101 step 31 00010101010101010101010101010101 step 32 00010101010101010101010101010101 step 33 00010101010101010101100101010101 step 34 00010101010101010101010101010101 step 35 00010101010101010101010101010101 step 36 00010101010101010101011001010101 step 37 00010101010101010101010101010101 step 38 00010101010101010101010101010101 step 39 00010101010101010101010110010101 step 40 00010101010101010101010101010101 step 41 00010101010101010101010101010101 step 42 00010101010101010101010101100101 step 43 00010101010101010101010101010101 step 44 00010101010101010101010101010101 step 45 00010101010101010101010101011001 step 46 00010101010101010101010101010101 step 47 00010101010101010101010101010101 step 48 00010101010101010101010101010110 step 49 00010101010101010101010101010101 step 50 00010101010101010101010101010101 step 51 10101010101010101010101010101010 step 52 00101010101010101010101010101010 step 53 10101010101010101010101010101010 step 54 10011010101010101010101010101010 step 55 10101010101010101010101010101010 step 56 10100110101010101010101010101010 step 57 10101010101010101010101010101010 step 58 10101001101010101010101010101010 step 59 10101010101010101010101010101010 step 60 10101010011010101010101010101010 step 61 10101010101010101010101010101010 step 62 10101010100110101010101010101010 step 63 10101010101010101010101010101010 step 64 10101010101001101010101010101010 step 65 10101010101010101010101010101010 step 66 10101010101010011010101010101010 step 67 10101010101010101010101010101010 step 68 10101010101010100110101010101010 step 69 10101010101010101010101010101010 step 70 10101010101010101001101010101010 step 71 10101010101010101010101010101010 step 72 10101010101010101010011010101010 step 73 10101010101010101010101010101010 step 74 10101010101010101010100110101010 step 75 10101010101010101010101010101010 step 76 10101010101010101010101001101010 step 77 10101010101010101010101010101010 step 78 10101010101010101010101010011010 step 79 10101010101010101010101010101010 step 80 10101010101010101010101010100110 output is: 2 O AU1 E4-8 space toggle output N next output Q quit Main menu Fri Jun 30 08:44:10 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0020 Main menu Fri Jun 30 08:44:24 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 08:44:27 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 1 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 2 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 10010101010101010101010101010101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 4 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 6 00100101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 7 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 9 00011001010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 10 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 12 00010110010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 13 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 00010101100101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O was lo 00000000000 0 0 0 0 0 0 0 0 0 0 falling v vvvvvv v rising ^ ^^^^^^^ was hi 1 11111111 1 1 1 1 1 1 1 1 1 1 1 total fails 0, total passes 0 Main menu Fri Jun 30 08:45:01 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 08:45:22 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 1 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 2 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 10010101010101010101010101010101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 4 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 6 00100101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 7 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 9 00011001010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 10 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 12 00010110010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 13 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 00010101100101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 18 00010101011001010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 19 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 21 00010101010110010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 22 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 24 00010101010101100101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 25 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 27 00010101010101011001010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 28 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 30 00010101010101010110010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 31 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 33 00010101010101010101100101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 34 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 36 00010101010101010101011001010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 37 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 00010101010101010101010110010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 42 00010101010101010101010101100101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 43 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 45 00010101010101010101010101011001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 46 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 00010101010101010101010101010110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 101010101010101010101010101010 step 51 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 52 00101010101010101010101010101010 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 53 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 54 10011010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 55 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 56 10100110101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 57 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 58 10101001101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 59 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 60 10101010011010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 61 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 62 10101010100110101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 63 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 64 10101010101001101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 65 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 66 10101010101010011010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 67 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 68 10101010101010100110101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 69 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 70 10101010101010101001101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 71 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 72 10101010101010101010011010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 73 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 74 10101010101010101010100110101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 75 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 76 10101010101010101010101001101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 77 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 78 10101010101010101010101010011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 79 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 80 10101010101010101010101010100110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 81 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 82 10101010101010101010101010101001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 83 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 84 10101010101010101010101010101010 okay test 1: *** FAIL *************************** 50 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO this fail O all fails O was hi 1 111111111111111111111111111111 rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 010101010101010101010101010101 step 1 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 2 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 step 3 10010101010101010101010101010101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 0 step 4 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 5 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 6 00100101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 7 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 8 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 9 00011001010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 10 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 11 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 12 00010110010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 13 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 14 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 15 00010101100101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 16 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 17 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 18 00010101011001010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 19 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 20 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 21 00010101010110010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 22 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 23 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 24 00010101010101100101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 25 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 26 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 27 00010101010101011001010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 28 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 29 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 30 00010101010101010110010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 31 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 32 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 33 00010101010101010101100101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 34 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 35 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 36 00010101010101010101011001010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 37 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 38 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 39 00010101010101010101010110010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 40 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 41 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 42 00010101010101010101010101100101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 43 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 44 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 45 00010101010101010101010101011001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 46 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 47 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 10 step 48 00010101010101010101010101010110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 01 step 49 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: step 50 00010101010101010101010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO changed: 1 101010101010101010101010101010 step 51 10101010101010101010101010101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails O was lo 00000000000000000000000000000000 falling v vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1 111111111111111111111111111111 total fails 1, total passes 0 Main menu Fri Jun 30 08:47:15 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 08:55:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 54 Main menu Fri Jun 30 08:55:25 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 09:12:50 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:12:52 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 181 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 182 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 183 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 184 111101111011110111101111000001 fail ^ step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 189 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 190 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 191 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 192 111101111011110111101111000001 fail ^ step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 12: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O II all fails O O II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 12, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 85 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 86 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 87 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 88 000010000100001000010000100001 fail ^ step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 93 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 94 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 95 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 96 000010000100001000010000100001 fail ^ step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 181 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 182 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 183 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 184 111101111011110111101111000001 fail ^ step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 189 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 190 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 191 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 192 111101111011110111101111000001 fail ^ step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 13: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O II all fails O O II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 13, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 85 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 86 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 87 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 88 000010000100001000010000100001 fail ^ step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 93 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 94 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 95 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 96 000010000100001000010000100001 fail ^ step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 181 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 182 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 183 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 184 111101111011110111101111000001 fail ^ step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 189 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 190 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 191 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 192 111101111011110111101111000001 fail ^ step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 14: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O II all fails O O II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 14, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 0 0 0 0 0 step 1 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 2 000100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 001100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 4 001000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 011000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 6 011100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 110000000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 10 110100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 111100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 12 111000000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 13 101000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 14 101100000000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 15 100100000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 16 100000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 17 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 18 000000001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 19 000000011000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 20 000000010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 21 000000110000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000000111000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000000101000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 24 000000100000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 25 000001100000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000001101000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 27 000001111000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 28 000001110000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 29 000001010000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000001011000000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000001001000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 32 000001000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 33 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 35 000000000000110000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 36 000000000000100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000000000001100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 38 000000000001110000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 39 000000000001010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 40 000000000001000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000000000011000000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 42 000000000011010000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000000000011110000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 44 000000000011100000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 45 000000000010100000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 46 000000000010110000000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 47 000000000010010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 48 000000000010000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 49 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 50 000000000000000000100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 51 000000000000000001100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 52 000000000000000001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 53 000000000000000011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000000000000000011100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 55 000000000000000010100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 56 000000000000000010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 57 000000000000000110000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000000000000000110100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 59 000000000000000111100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 60 000000000000000111000000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 61 000000000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000000000000000101100000000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 63 000000000000000100100000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 64 000000000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 65 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000000000000000000000001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 67 000000000000000000000011000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 68 000000000000000000000010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 69 000000000000000000000110000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 70 000000000000000000000111000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 71 000000000000000000000101000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 72 000000000000000000000100000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000000000000000000001100000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 74 000000000000000000001101000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000000000000000000001111000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 76 000000000000000000001110000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 77 000000000000000000001010000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 78 000000000000000000001011000000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 79 000000000000000000001001000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 80 000000000000000000001000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 81 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 82 000000000000000000000000000010 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000000000000000000000000000110 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 84 000000000000000000000000000100 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 85 000000000000000000000000000100 fail ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 86 000000000000000000000000000110 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 87 000000000000000000000000000010 fail ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 88 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 11 step 89 000000000000000000000000011000 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000000000000000000000000011010 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 91 000000000000000000000000011110 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 92 000000000000000000000000011100 fail ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 step 93 000000000000000000000000000100 fail ^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000000000000000000000000000110 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 95 000000000000000000000000000010 fail ^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 96 000000000000000000000000000000 fail ^ ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 97 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 98 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1111 1111 11111111111111 1111 step 99 111101111011111111111111011110 fail ^ ^ step 100 111001111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 101 101001111011110111101111011110 fail ^ step 102 101101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 103 100101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 104 100001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 105 000001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 106 000101111011110111101111011110 fail ^ step 107 001101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 108 001001111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 117 111101010011110111101111011110 fail ^ step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 120 111101000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 121 111100000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 124 111100010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 125 111100110011110111101111011110 fail ^ step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 128 111100100011110111101111011110 fail ^ step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 133 111101111010100111101111011110 fail ^ step 134 111101111010110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 135 111101111010010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 136 111101111010000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 137 111101111000000111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 138 111101111000010111101111011110 fail ^ step 139 111101111000110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 140 111101111000100111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 141 111101111001100111101111011110 fail ^ step 142 111101111001110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 143 111101111001010111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 144 111101111001000111101111011110 fail ^ step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 149 111101111011110101001111011110 fail ^ step 150 111101111011110101101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 151 111101111011110100101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 152 111101111011110100001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 153 111101111011110000001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 154 111101111011110000101111011110 fail ^ step 155 111101111011110001101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 156 111101111011110001001111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 157 111101111011110011001111011110 fail ^ step 158 111101111011110011101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 159 111101111011110010101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 160 111101111011110010001111011110 fail ^ step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 165 111101111011110111101010011110 fail ^ step 166 111101111011110111101011011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 167 111101111011110111101001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 168 111101111011110111101000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 169 111101111011110111100000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 170 111101111011110111100001011110 fail ^ step 171 111101111011110111100011011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 172 111101111011110111100010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 173 111101111011110111100110011110 fail ^ step 174 111101111011110111100111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 175 111101111011110111100101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 176 111101111011110111100100011110 fail ^ step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 step 181 111101111011110111101111000100 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 182 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 183 111101111011110111101111000010 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 184 111101111011110111101111000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 185 111101111011110111101111000000 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 186 111101111011110111101111000010 fail ^ step 187 111101111011110111101111000110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 188 111101111011110111101111000100 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 189 111101111011110111101111000100 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 190 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 191 111101111011110111101111000010 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 192 111101111011110111101111000000 fail ^ ^ step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 0000 0000 0000 0000 0000 step 197 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ test 15: *** FAIL *************************** 156 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O O O OII O all fails O O O O OII O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 15, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O O O O OII O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 15, total passes 0 Main menu Fri Jun 30 09:18:18 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:18:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 85 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 86 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 87 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 88 000010000100001000010000100001 fail ^ step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 93 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 94 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 95 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 96 000010000100001000010000100001 fail ^ step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 181 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 182 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 183 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 184 111101111011110111101111000001 fail ^ step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 189 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 190 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 191 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 192 111101111011110111101111000001 fail ^ step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 1: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O II all fails O O II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 6 011100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 110000000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 10 110100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 111100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 12 111000000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 13 101010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 85 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 86 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 87 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 88 000010000100001000010000100001 fail ^ step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 93 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 94 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 95 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 96 000010000100001000010000100001 fail ^ step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00 1 step 181 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 182 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 183 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 184 111101111011110111101111000001 fail ^ step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 189 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 190 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 191 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 192 111101111011110111101111000001 fail ^ step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 2: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O II all fails O O II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 5 O AE1 E1-8 OUTPUT A SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 111 1111111111111111111111111 fails LO: 0 00 0000000000000000000000000 fails HI: fails HI: pin: 10 O AJ2 E1-6 OUTPUT B SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111111 1 11111111111111111111 fails LO: 00000000 00000000000000000000 fails HI: fails HI: pin: 26 I AR2 E3-5 F1A 1-X SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111111111111111111111111 111 fails LO: 0000000000000000000000000 0000 fails HI: fails HI: pin: 27 I AS2 E3-4 F1B 1-X SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 1111111111111111111111111 111 fails LO: 00000000000000000000000000 000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 1 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 2 000110000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 3 001100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 4 001010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 6 011100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 110000000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 10 110100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 111100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 12 111000000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 13 101010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 14 101100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 15 100110000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 16 100010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 17 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 19 000010011000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 20 000010010100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 21 000010110100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 22 000010111000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 24 000010100100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 25 000011100000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000011101000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 27 000011111000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 28 000011110000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 29 000011010100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 30 000011011000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 32 000011000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 33 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000010000100011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 35 000010000100110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 36 000010000100101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000010000101101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000010000101110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 39 000010000101011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 40 000010000101001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 41 000010000111000000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 42 000010000111010000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000010000111110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 44 000010000111100000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 45 000010000110101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000010000110110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 47 000010000110011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 48 000010000110001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 49 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 50 000010000100001000110000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 51 000010000100001001100000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 52 000010000100001001010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 53 000010000100001011010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 54 000010000100001011100000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 55 000010000100001010110000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 56 000010000100001010010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 57 000010000100001110000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000010000100001110100000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 59 000010000100001111100000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 60 000010000100001111000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 61 000010000100001101010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 62 000010000100001101100000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 63 000010000100001100110000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 64 000010000100001100010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 65 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000010000100001000010001100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 67 000010000100001000010011000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 68 000010000100001000010010100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 69 000010000100001000010110100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 70 000010000100001000010111000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 71 000010000100001000010101100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 72 000010000100001000010100100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 73 000010000100001000011100000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 74 000010000100001000011101000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000010000100001000011111000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 76 000010000100001000011110000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 77 000010000100001000011010100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 78 000010000100001000011011000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 1 step 79 000010000100001000011001100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 80 000010000100001000011000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 81 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 82 000010000100001000010000100011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 83 000010000100001000010000100110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 01 step 84 000010000100001000010000100101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 85 000010000100001000010000100101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01110 changed: 10 step 86 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 0 1 step 87 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 0 step 88 000010000100001000010000100001 fail ^ source: 11000 changed: 11 0 step 89 000010000100001000010000111000 source: 11010 changed: 1 step 90 000010000100001000010000111010 source: 11110 changed: 1 step 91 000010000100001000010000111110 source: 11100 changed: 0 step 92 000010000100001000010000111100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 00 1 step 93 000010000100001000010000100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10110 changed: 10 step 94 000010000100001000010000100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 0 1 step 95 000010000100001000010000100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 0 step 96 000010000100001000010000100001 fail ^ source: 00001 changed: step 97 000010000100001000010000100001 source: 000010000100001000010000100001 changed: step 98 000010000100001000010000100001 source: 111101111011110111101111011110 changed: 111101111011110111101111011110 step 99 111101111011110111101111011110 source: 11100 changed: 0 step 100 111001111011110111101111011110 source: 10101 changed: 0 1 step 101 101011111011110111101111011110 source: 10110 changed: 10 step 102 101101111011110111101111011110 source: 10011 changed: 0 1 step 103 100111111011110111101111011110 source: 10001 changed: 0 step 104 100011111011110111101111011110 source: 00001 changed: 0 step 105 000011111011110111101111011110 source: 00011 changed: 1 step 106 000111111011110111101111011110 source: 00110 changed: 1 0 step 107 001101111011110111101111011110 source: 00101 changed: 01 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 1 0 step 109 011001111011110111101111011110 fail ^ source: 01110 changed: 1 step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 0 step 112 010001111011110111101111011110 fail ^ source: 11000 changed: 1 step 113 110001111011110111101111011110 source: 11010 changed: 1 step 114 110101111011110111101111011110 source: 11110 changed: 1 step 115 111101111011110111101111011110 source: 11100 changed: 0 step 116 111101110011110111101111011110 source: 10101 changed: 0 1 step 117 111101010111110111101111011110 source: 10110 changed: 10 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 0 step 119 111101001011110111101111011110 fail ^ source: 10001 changed: 01 step 120 111101000111110111101111011110 source: 00001 changed: 0 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 10 step 122 111100001011110111101111011110 fail ^ source: 00110 changed: 1 step 123 111100011011110111101111011110 source: 00101 changed: 01 step 124 111100010111110111101111011110 source: 01101 changed: 1 step 125 111100110111110111101111011110 source: 01110 changed: 10 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 0 step 127 111100101011110111101111011110 fail ^ source: 01001 changed: 01 step 128 111100100111110111101111011110 source: 11000 changed: 1 0 step 129 111101100011110111101111011110 source: 11010 changed: 1 step 130 111101101011110111101111011110 source: 11110 changed: 1 step 131 111101111011110111101111011110 source: 11100 changed: 0 step 132 111101111011100111101111011110 source: 10101 changed: 0 1 step 133 111101111010101111101111011110 source: 10110 changed: 10 step 134 111101111010110111101111011110 source: 10011 changed: 0 1 step 135 111101111010011111101111011110 source: 10001 changed: 0 step 136 111101111010001111101111011110 source: 00001 changed: 0 step 137 111101111000001111101111011110 source: 00011 changed: 1 step 138 111101111000011111101111011110 source: 00110 changed: 1 0 step 139 111101111000110111101111011110 source: 00101 changed: 01 step 140 111101111000101111101111011110 source: 01101 changed: 1 step 141 111101111001101111101111011110 source: 01110 changed: 10 step 142 111101111001110111101111011110 source: 01011 changed: 0 1 step 143 111101111001011111101111011110 source: 01001 changed: 0 step 144 111101111001001111101111011110 source: 11000 changed: 1 0 step 145 111101111011000111101111011110 source: 11010 changed: 1 step 146 111101111011010111101111011110 source: 11110 changed: 1 step 147 111101111011110111101111011110 source: 11100 changed: 0 step 148 111101111011110111001111011110 source: 10101 changed: 0 1 step 149 111101111011110101011111011110 source: 10110 changed: 10 step 150 111101111011110101101111011110 source: 10011 changed: 0 1 step 151 111101111011110100111111011110 source: 10001 changed: 0 step 152 111101111011110100011111011110 source: 00001 changed: 0 step 153 111101111011110000011111011110 source: 00011 changed: 1 step 154 111101111011110000111111011110 source: 00110 changed: 1 0 step 155 111101111011110001101111011110 source: 00101 changed: 01 step 156 111101111011110001011111011110 source: 01101 changed: 1 step 157 111101111011110011011111011110 source: 01110 changed: 10 step 158 111101111011110011101111011110 source: 01011 changed: 0 1 step 159 111101111011110010111111011110 source: 01001 changed: 0 step 160 111101111011110010011111011110 source: 11000 changed: 1 0 step 161 111101111011110110001111011110 source: 11010 changed: 1 step 162 111101111011110110101111011110 source: 11110 changed: 1 step 163 111101111011110111101111011110 source: 11100 changed: 0 step 164 111101111011110111101110011110 source: 10101 changed: 0 1 step 165 111101111011110111101010111110 source: 10110 changed: 10 step 166 111101111011110111101011011110 source: 10011 changed: 0 1 step 167 111101111011110111101001111110 source: 10001 changed: 0 step 168 111101111011110111101000111110 source: 00001 changed: 0 step 169 111101111011110111100000111110 source: 00011 changed: 1 step 170 111101111011110111100001111110 source: 00110 changed: 1 0 step 171 111101111011110111100011011110 source: 00101 changed: 01 step 172 111101111011110111100010111110 source: 01101 changed: 1 step 173 111101111011110111100110111110 source: 01110 changed: 10 step 174 111101111011110111100111011110 source: 01011 changed: 0 1 step 175 111101111011110111100101111110 source: 01001 changed: 0 step 176 111101111011110111100100111110 source: 11000 changed: 1 0 step 177 111101111011110111101100011110 source: 11010 changed: 1 step 178 111101111011110111101101011110 source: 11110 changed: 1 step 179 111101111011110111101111011110 source: 11100 changed: 0 step 180 111101111011110111101111011100 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 00 1 step 181 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10110 changed: 10 step 182 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 0 1 step 183 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 0 step 184 111101111011110111101111000001 fail ^ source: 00001 changed: step 185 111101111011110111101111000001 source: 00011 changed: 1 step 186 111101111011110111101111000011 source: 00110 changed: 1 0 step 187 111101111011110111101111000110 source: 00101 changed: 01 step 188 111101111011110111101111000101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: step 189 111101111011110111101111000101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01110 changed: 10 step 190 111101111011110111101111000110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 0 1 step 191 111101111011110111101111000011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 0 step 192 111101111011110111101111000001 fail ^ source: 11000 changed: 11 0 step 193 111101111011110111101111011000 source: 11010 changed: 1 step 194 111101111011110111101111011010 source: 11110 changed: 1 step 195 111101111011110111101111011110 source: 111101111011110111101111011110 changed: step 196 111101111011110111101111011110 source: 000010000100001000010000100001 changed: 000010000100001000010000100001 step 197 000010000100001000010000100001 test 3: *** FAIL *************************** 28 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O II all fails O O II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 000010000100001000010000100001 changed: step 1 000010000100001000010000100001 source: 00011 changed: 1 step 2 000110000100001000010000100001 source: 00110 changed: 1 0 step 3 001100000100001000010000100001 source: 00101 changed: 01 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 1 0 step 5 011000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 01110 changed: 1 step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 0 step 7 010100000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 0 step 8 010000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 11000 changed: 1 step 9 110000000100001000010000100001 source: 11010 changed: 1 step 10 110100000100001000010000100001 source: 11110 changed: 1 step 11 111100000100001000010000100001 source: 11100 changed: 0 step 12 111000000100001000010000100001 source: 10101 changed: 0 1 step 13 101010000100001000010000100001 source: 10110 changed: 10 step 14 101100000100001000010000100001 source: 10011 changed: 0 1 step 15 100110000100001000010000100001 source: 10001 changed: 0 step 16 100010000100001000010000100001 source: 00001 changed: 0 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 10 step 18 000010001000001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 00110 changed: 1 step 19 000010011000001000010000100001 source: 00101 changed: 01 step 20 000010010100001000010000100001 source: 01101 changed: 1 step 21 000010110100001000010000100001 source: 01110 changed: 10 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 0 step 23 000010101000001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 01001 changed: 01 step 24 000010100100001000010000100001 source: 11000 changed: 1 0 step 25 000011100000001000010000100001 source: 11010 changed: 1 step 26 000011101000001000010000100001 source: 11110 changed: 1 step 27 000011111000001000010000100001 source: 11100 changed: 0 step 28 000011110000001000010000100001 source: 10101 changed: 0 1 step 29 000011010100001000010000100001 source: 10110 changed: 10 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 0 step 31 000011001000001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 10001 changed: 01 step 32 000011000100001000010000100001 source: 00001 changed: 0 step 33 000010000100001000010000100001 source: 00011 changed: 1 step 34 000010000100011000010000100001 source: 00110 changed: 1 0 step 35 000010000100110000010000100001 source: 00101 changed: 01 step 36 000010000100101000010000100001 source: 01101 changed: 1 step 37 000010000101101000010000100001 source: 01110 changed: 10 step 38 000010000101110000010000100001 source: 01011 changed: 0 1 step 39 000010000101011000010000100001 source: 01001 changed: 0 step 40 000010000101001000010000100001 source: 11000 changed: 1 0 step 41 000010000111000000010000100001 source: 11010 changed: 1 step 42 000010000111010000010000100001 source: 11110 changed: 1 step 43 000010000111110000010000100001 source: 11100 changed: 0 step 44 000010000111100000010000100001 source: 10101 changed: 0 1 step 45 000010000110101000010000100001 source: 10110 changed: 10 step 46 000010000110110000010000100001 source: 10011 changed: 0 1 step 47 000010000110011000010000100001 source: 10001 changed: 0 step 48 000010000110001000010000100001 source: 00001 changed: 0 step 49 000010000100001000010000100001 source: 00011 changed: 1 step 50 000010000100001000110000100001 source: 00110 changed: 1 0 step 51 000010000100001001100000100001 source: 00101 changed: 01 step 52 000010000100001001010000100001 source: 01101 changed: 1 step 53 000010000100001011010000100001 source: 01110 changed: 10 step 54 000010000100001011100000100001 source: 01011 changed: 0 1 step 55 000010000100001010110000100001 source: 01001 changed: 0 step 56 000010000100001010010000100001 source: 11000 changed: 1 0 step 57 000010000100001110000000100001 source: 11010 changed: 1 step 58 000010000100001110100000100001 source: 11110 changed: 1 step 59 000010000100001111100000100001 source: 11100 changed: 0 step 60 000010000100001111000000100001 source: 10101 changed: 0 1 step 61 000010000100001101010000100001 source: 10110 changed: 10 step 62 000010000100001101100000100001 source: 10011 changed: 0 1 step 63 000010000100001100110000100001 source: 10001 changed: 0 step 64 000010000100001100010000100001 source: 00001 changed: 0 step 65 000010000100001000010000100001 source: 00011 changed: 1 step 66 000010000100001000010001100001 source: 00110 changed: 1 0 step 67 000010000100001000010011000001 source: 00101 changed: 01 step 68 000010000100001000010010100001 source: 01101 changed: 1 step 69 000010000100001000010110100001 source: 01110 changed: 10 step 70 000010000100001000010111000001 source: 01011 changed: 0 1 step 71 000010000100001000010101100001 source: 01001 changed: 0 step 72 000010000100001000010100100001 source: 11000 changed: 1 0 step 73 000010000100001000011100000001 source: 11010 changed: 1 step 74 000010000100001000011101000001 source: 11110 changed: 1 step 75 000010000100001000011111000001 source: 11100 changed: 0 step 76 000010000100001000011110000001 source: 10101 changed: 0 1 step 77 000010000100001000011010100001 source: 10110 changed: 10 step 78 000010000100001000011011000001 source: 10011 changed: 0 1 step 79 000010000100001000011001100001 source: 10001 changed: 0 step 80 000010000100001000011000100001 source: 00001 changed: 0 step 81 000010000100001000010000100001 source: 00011 changed: 1 step 82 000010000100001000010000100011 source: 00110 changed: 1 0 step 83 000010000100001000010000100110 source: 00101 changed: 01 step 84 000010000100001000010000100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: step 85 000010000100001000010000100101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O O II was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 3, total passes 0 Main menu Fri Jun 30 09:32:12 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m121.tst Main menu Fri Jun 30 09:32:16 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.tst reading test file: tests\7450.tst comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7410 PIN 1 1A pins: 2 I AS2 E1-15 7410 PIN 13 1B pins: 3 I AM2 E1-11 7410 PIN 9 1C pins: 4 I AN2 E1-12 7410 PIN 10 1D pins: 5 O AP2 E1-13 7410 PIN 11 X (EXPANDER) pins: 6 O AR2 E1-14 7410 PIN 12 X-N (EXPANDER) pins: 7 O AL2 E1-10 7410 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 8 I AB2 E1-2 7410 PIN 2 2A pins: 9 I AC1 E1-3 7410 PIN 3 2B pins: 10 I AD2 E1-4 7410 PIN 4 2C pins: 11 I AE2 E1-5 7410 PIN 5 2D pins: 12 O AF2 E1-6 7410 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 13 I AH2 E1-7 7410 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7410 PIN 14 VCC pins: direction: IIIIOOOIIIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000XX100001XXXX comment: comment: ; ALL INPUTS HI test 2: 1111 011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 01 0 test 4: 00 0 test 5: 10 0 test 6: 11 0 test 7: 01 0 test 8: 00 0 test 9: 10 0 test 10: 11 0 test 11: 01 0 test 12: 00 0 test 13: 10 0 test 14: 11 0 test 15: 010 test 16: 000 test 17: 100 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 0000 100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 test 32: 011 test 33: 110 test 34: 101 test 35: 001 comment: comment: ;**************************** comment: ; SHOULD TEST ALL 16 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 1, mask 0x0002 column 8: offset 0, mask 0x0040 column 9: offset 0, mask 0x2000 column 10: offset 0, mask 0x0010 column 11: offset 0, mask 0x0008 column 12: offset 0, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 3: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 5: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 7: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 8: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 9: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 11: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 12: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 13: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 15: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 16: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 17: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 19: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 20: 0x0004 0x0042 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 21: 0x8004 0x0040 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 22: 0x8004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 23: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 24: 0x0004 0x000A 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 25: 0x0004 0x000C 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 26: 0x0004 0x0006 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 27: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 28: 0x2004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 29: 0x2040 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 30: 0x0044 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 31: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 32: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 33: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 34: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0003 0x00B1 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 88 lines 7450 TRIPLE 3-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Fri Jun 30 09:32:22 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0064 Main menu Fri Jun 30 09:32:49 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:33:28 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 0, total passes 88 Main menu Fri Jun 30 09:33:33 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:36:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 0, total passes 102 Main menu Fri Jun 30 09:36:23 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:38:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 0, total passes 60 Main menu Fri Jun 30 09:38:12 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:38:39 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 0, total passes 60 Main menu Fri Jun 30 09:38:41 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:39:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNPRLBCDEFHJKT SIDE 1222222212222222 DIRECTION IIIIOOOIIIIOIIII all fails was lo 0000000000000000 falling vvvv vvvvvvv rising ^^^^ ^^^^^^^ was hi 1111 1111111 total fails 0, total passes 54 Main menu Fri Jun 30 09:39:26 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 09:43:33 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 09:43:39 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 09:43:42 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 13: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 13, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 step 85 000010000100001000010000101101 step 86 000010000100001000010000101110 step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 14: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 14, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 step 85 000010000100001000010000101101 step 86 000010000100001000010000101110 step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 15: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 15, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 step 85 000010000100001000010000101101 step 86 000010000100001000010000101110 step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 16: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 16, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000110000100001000010000100001 step 3 001100000100001000010000100001 step 4 001010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 5 011000000100001000010000100001 fail ^ step 6 011100000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 7 010100000100001000010000100001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 8 010000000100001000010000100001 fail ^ step 9 110000000100001000010000100001 step 10 110100000100001000010000100001 step 11 111100000100001000010000100001 step 12 111000000100001000010000100001 step 13 101010000100001000010000100001 step 14 101100000100001000010000100001 step 15 100110000100001000010000100001 step 16 100010000100001000010000100001 step 17 000010000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 18 000010001000001000010000100001 fail ^ step 19 000010011000001000010000100001 step 20 000010010100001000010000100001 step 21 000010110100001000010000100001 step 22 000010111000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 23 000010101000001000010000100001 fail ^ step 24 000010100100001000010000100001 step 25 000011100000001000010000100001 step 26 000011101000001000010000100001 step 27 000011111000001000010000100001 step 28 000011110000001000010000100001 step 29 000011010100001000010000100001 step 30 000011011000001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 31 000011001000001000010000100001 fail ^ step 32 000011000100001000010000100001 step 33 000010000100001000010000100001 step 34 000010000100011000010000100001 step 35 000010000100110000010000100001 step 36 000010000100101000010000100001 step 37 000010000101101000010000100001 step 38 000010000101110000010000100001 step 39 000010000101011000010000100001 step 40 000010000101001000010000100001 step 41 000010000111000000010000100001 step 42 000010000111010000010000100001 step 43 000010000111110000010000100001 step 44 000010000111100000010000100001 step 45 000010000110101000010000100001 step 46 000010000110110000010000100001 step 47 000010000110011000010000100001 step 48 000010000110001000010000100001 step 49 000010000100001000010000100001 step 50 000010000100001000110000100001 step 51 000010000100001001100000100001 step 52 000010000100001001010000100001 step 53 000010000100001011010000100001 step 54 000010000100001011100000100001 step 55 000010000100001010110000100001 step 56 000010000100001010010000100001 step 57 000010000100001110000000100001 step 58 000010000100001110100000100001 step 59 000010000100001111100000100001 step 60 000010000100001111000000100001 step 61 000010000100001101010000100001 step 62 000010000100001101100000100001 step 63 000010000100001100110000100001 step 64 000010000100001100010000100001 step 65 000010000100001000010000100001 step 66 000010000100001000010001100001 step 67 000010000100001000010011000001 step 68 000010000100001000010010100001 step 69 000010000100001000010110100001 step 70 000010000100001000010111000001 step 71 000010000100001000010101100001 step 72 000010000100001000010100100001 step 73 000010000100001000011100000001 step 74 000010000100001000011101000001 step 75 000010000100001000011111000001 step 76 000010000100001000011110000001 step 77 000010000100001000011010100001 step 78 000010000100001000011011000001 step 79 000010000100001000011001100001 step 80 000010000100001000011000100001 step 81 000010000100001000010000100001 step 82 000010000100001000010000100011 step 83 000010000100001000010000100110 step 84 000010000100001000010000100101 step 85 000010000100001000010000101101 step 86 000010000100001000010000101110 step 87 000010000100001000010000101011 step 88 000010000100001000010000101001 step 89 000010000100001000010000111000 step 90 000010000100001000010000111010 step 91 000010000100001000010000111110 step 92 000010000100001000010000111100 step 93 000010000100001000010000110101 step 94 000010000100001000010000110110 step 95 000010000100001000010000110011 step 96 000010000100001000010000110001 step 97 000010000100001000010000100001 step 98 000010000100001000010000100001 step 99 111101111011110111101111011110 step 100 111001111011110111101111011110 step 101 101011111011110111101111011110 step 102 101101111011110111101111011110 step 103 100111111011110111101111011110 step 104 100011111011110111101111011110 step 105 000011111011110111101111011110 step 106 000111111011110111101111011110 step 107 001101111011110111101111011110 step 108 001011111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 0 step 109 011001111011110111101111011110 fail ^ step 110 011101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 111 010101111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 112 010001111011110111101111011110 fail ^ step 113 110001111011110111101111011110 step 114 110101111011110111101111011110 step 115 111101111011110111101111011110 step 116 111101110011110111101111011110 step 117 111101010111110111101111011110 step 118 111101011011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 119 111101001011110111101111011110 fail ^ step 120 111101000111110111101111011110 step 121 111100000111110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 122 111100001011110111101111011110 fail ^ step 123 111100011011110111101111011110 step 124 111100010111110111101111011110 step 125 111100110111110111101111011110 step 126 111100111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0 step 127 111100101011110111101111011110 fail ^ step 128 111100100111110111101111011110 step 129 111101100011110111101111011110 step 130 111101101011110111101111011110 step 131 111101111011110111101111011110 step 132 111101111011100111101111011110 step 133 111101111010101111101111011110 step 134 111101111010110111101111011110 step 135 111101111010011111101111011110 step 136 111101111010001111101111011110 step 137 111101111000001111101111011110 step 138 111101111000011111101111011110 step 139 111101111000110111101111011110 step 140 111101111000101111101111011110 step 141 111101111001101111101111011110 step 142 111101111001110111101111011110 step 143 111101111001011111101111011110 step 144 111101111001001111101111011110 step 145 111101111011000111101111011110 step 146 111101111011010111101111011110 step 147 111101111011110111101111011110 step 148 111101111011110111001111011110 step 149 111101111011110101011111011110 step 150 111101111011110101101111011110 step 151 111101111011110100111111011110 step 152 111101111011110100011111011110 step 153 111101111011110000011111011110 step 154 111101111011110000111111011110 step 155 111101111011110001101111011110 step 156 111101111011110001011111011110 step 157 111101111011110011011111011110 step 158 111101111011110011101111011110 step 159 111101111011110010111111011110 step 160 111101111011110010011111011110 step 161 111101111011110110001111011110 step 162 111101111011110110101111011110 step 163 111101111011110111101111011110 step 164 111101111011110111101110011110 step 165 111101111011110111101010111110 step 166 111101111011110111101011011110 step 167 111101111011110111101001111110 step 168 111101111011110111101000111110 step 169 111101111011110111100000111110 step 170 111101111011110111100001111110 step 171 111101111011110111100011011110 step 172 111101111011110111100010111110 step 173 111101111011110111100110111110 step 174 111101111011110111100111011110 step 175 111101111011110111100101111110 step 176 111101111011110111100100111110 step 177 111101111011110111101100011110 step 178 111101111011110111101101011110 step 179 111101111011110111101111011110 step 180 111101111011110111101111011100 step 181 111101111011110111101111010101 step 182 111101111011110111101111010110 step 183 111101111011110111101111010011 step 184 111101111011110111101111010001 step 185 111101111011110111101111000001 step 186 111101111011110111101111000011 step 187 111101111011110111101111000110 step 188 111101111011110111101111000101 step 189 111101111011110111101111001101 step 190 111101111011110111101111001110 step 191 111101111011110111101111001011 step 192 111101111011110111101111001001 step 193 111101111011110111101111011000 step 194 111101111011110111101111011010 step 195 111101111011110111101111011110 step 196 111101111011110111101111011110 step 197 000010000100001000010000100001 test 17: *** FAIL *************************** 12 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 17, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 17, total passes 0 Main menu Fri Jun 30 10:04:30 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 10:04:40 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 26 Main menu Fri Jun 30 10:04:47 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m212.tst reading test file: tests\m212.tst comment: ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER comment: comment: ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) comment: pins: PINS pins: 1 I AB1 E3-4,10;E6-4,10;E9-4,10 CLEAR-N CLEARS FF0 THRU FF5 pins: 2 I AL2 E1-3 INA0-N pins: 3 I AM2 E2-2 INA1-N pins: 4 I AN2 E4-2 INA2-N pins: 5 I AR2 E5-2 INA3-N pins: 6 I AV1 E7-2 INA4-N pins: 7 I AV2 E8-2 INA5-N pins: 8 I AN1 ENABLE_INPUT_A pins: 9 I AP2 E1-4 INB0-N pins: 10 I AR1 E2-4 INB1-N pins: 11 I AS1 E4-4 INB2-N pins: 12 I AU1 E5-4 INB3-N pins: 13 I AA1 E7-4 INB4-N pins: 14 I AT2 E8-4 INB5-N pins: 15 I AU2 ENABLE_INPUT_B pins: 16 I AM1 E1-1 SHIFT_R_INSERT-N RIGHT SHIFTS INTO FF0 pins: 17 I AL1 ENABLE_R_SHIFT pins: 18 I AS2 E8-9 SHIFT_L_INSERT-N LEFT SHIFTS INTO FF5 pins: 19 I AP1 ENABLE_L_SHIFT pins: 20 I AC1 E3-3,11;E6-3,11;E9-3,11 CLOCK (RISING EDGE) pins: 21 O AD1 E3-6 FF0 pins: 22 O AD2 E3-5 FF0-N pins: 23 O AF1 E3-8 FF1 pins: 24 O AE1 E3-9 FF1-N pins: 25 O AH2 E6-6 FF2 pins: 26 O AE2 E6-5 FF2-N pins: 27 O AH1 E6-8 FF3 pins: 28 O AF2 E6-9 FF3-N pins: 29 O AK2 E9-6 FF4 pins: 30 O AJ2 E9-5 FF4-N pins: 31 O AK1 E9-8 FF5 pins: 32 O AJ1 A9-9 FF5-N pins: direction: IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO comment: ; CLEAR-N, NO ENABLES test 1: 01111110111111010100010101010101 test 2: 1 comment: comment: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM comment: ; see mk_m212_ld_shift.c comment: comment: comment: ; TEST A INPUTS, GRAY CODE PATTERN comment: comment: ; ENABLE A INPUTS test 3: 1 comment: ; LOAD FFs FROM INPUT A comment: test 4: 000001 test 5: 1010101010110 test 6: 0 test 7: 000011 test 8: 1010101011010 test 9: 0 test 10: 000010 test 11: 1010101011001 test 12: 0 test 13: 000110 test 14: 1010101101001 test 15: 0 test 16: 000111 test 17: 1010101101010 test 18: 0 test 19: 000101 test 20: 1010101100110 test 21: 0 test 22: 000100 test 23: 1010101100101 test 24: 0 test 25: 001100 test 26: 1010110100101 test 27: 0 test 28: 001101 test 29: 1010110100110 test 30: 0 test 31: 001111 test 32: 1010110101010 test 33: 0 test 34: 001110 test 35: 1010110101001 test 36: 0 test 37: 001010 test 38: 1010110011001 test 39: 0 test 40: 001011 test 41: 1010110011010 test 42: 0 test 43: 001001 test 44: 1010110010110 test 45: 0 test 46: 001000 test 47: 1010110010101 test 48: 0 test 49: 011000 test 50: 1011010010101 test 51: 0 test 52: 011001 test 53: 1011010010110 test 54: 0 test 55: 011011 test 56: 1011010011010 test 57: 0 test 58: 011010 test 59: 1011010011001 test 60: 0 test 61: 011110 test 62: 1011010101001 test 63: 0 test 64: 011111 test 65: 1011010101010 test 66: 0 test 67: 011101 test 68: 1011010100110 test 69: 0 test 70: 011100 test 71: 1011010100101 test 72: 0 test 73: 010100 test 74: 1011001100101 test 75: 0 test 76: 010101 test 77: 1011001100110 test 78: 0 test 79: 010111 test 80: 1011001101010 test 81: 0 test 82: 010110 test 83: 1011001101001 test 84: 0 test 85: 010010 test 86: 1011001011001 test 87: 0 test 88: 010011 test 89: 1011001011010 test 90: 0 test 91: 010001 test 92: 1011001010110 test 93: 0 test 94: 010000 test 95: 1011001010101 test 96: 0 test 97: 110000 test 98: 1101001010101 test 99: 0 test 100: 110001 test 101: 1101001010110 test 102: 0 test 103: 110011 test 104: 1101001011010 test 105: 0 test 106: 110010 test 107: 1101001011001 test 108: 0 test 109: 110110 test 110: 1101001101001 test 111: 0 test 112: 110111 test 113: 1101001101010 test 114: 0 test 115: 110101 test 116: 1101001100110 test 117: 0 test 118: 110100 test 119: 1101001100101 test 120: 0 test 121: 111100 test 122: 1101010100101 test 123: 0 test 124: 111101 test 125: 1101010100110 test 126: 0 test 127: 111111 test 128: 1101010101010 test 129: 0 test 130: 111110 test 131: 1101010101001 test 132: 0 test 133: 111010 test 134: 1101010011001 test 135: 0 test 136: 111011 test 137: 1101010011010 test 138: 0 test 139: 111001 test 140: 1101010010110 test 141: 0 test 142: 111000 test 143: 1101010010101 test 144: 0 test 145: 101000 test 146: 1100110010101 test 147: 0 test 148: 101001 test 149: 1100110010110 test 150: 0 test 151: 101011 test 152: 1100110011010 test 153: 0 test 154: 101010 test 155: 1100110011001 test 156: 0 test 157: 101110 test 158: 1100110101001 test 159: 0 test 160: 101111 test 161: 1100110101010 test 162: 0 test 163: 101101 test 164: 1100110100110 test 165: 0 test 166: 101100 test 167: 1100110100101 test 168: 0 test 169: 100100 test 170: 1100101100101 test 171: 0 test 172: 100101 test 173: 1100101100110 test 174: 0 test 175: 100111 test 176: 1100101101010 test 177: 0 test 178: 100110 test 179: 1100101101001 test 180: 0 test 181: 100010 test 182: 1100101011001 test 183: 0 test 184: 100011 test 185: 1100101011010 test 186: 0 test 187: 100001 test 188: 1100101010110 test 189: 0 test 190: 100000 test 191: 1100101010101 test 192: 0 test 193: 000000 test 194: 1010101010101 test 195: 0 comment: comment: ; DISABLE A INPUTS test 196: 0 comment: comment: comment: ; TEST B INPUTS comment: comment: ; ENABLE B INPUTS test 197: 1 comment: ; LOAD FFs FROM INPUT B comment: test 198: 000001 test 199: 1010101010110 test 200: 0 test 201: 000011 test 202: 1010101011010 test 203: 0 test 204: 000010 test 205: 1010101011001 test 206: 0 test 207: 000110 test 208: 1010101101001 test 209: 0 test 210: 000111 test 211: 1010101101010 test 212: 0 test 213: 000101 test 214: 1010101100110 test 215: 0 test 216: 000100 test 217: 1010101100101 test 218: 0 test 219: 001100 test 220: 1010110100101 test 221: 0 test 222: 001101 test 223: 1010110100110 test 224: 0 test 225: 001111 test 226: 1010110101010 test 227: 0 test 228: 001110 test 229: 1010110101001 test 230: 0 test 231: 001010 test 232: 1010110011001 test 233: 0 test 234: 001011 test 235: 1010110011010 test 236: 0 test 237: 001001 test 238: 1010110010110 test 239: 0 test 240: 001000 test 241: 1010110010101 test 242: 0 test 243: 011000 test 244: 1011010010101 test 245: 0 test 246: 011001 test 247: 1011010010110 test 248: 0 test 249: 011011 test 250: 1011010011010 test 251: 0 test 252: 011010 test 253: 1011010011001 test 254: 0 test 255: 011110 test 256: 1011010101001 test 257: 0 test 258: 011111 test 259: 1011010101010 test 260: 0 test 261: 011101 test 262: 1011010100110 test 263: 0 test 264: 011100 test 265: 1011010100101 test 266: 0 test 267: 010100 test 268: 1011001100101 test 269: 0 test 270: 010101 test 271: 1011001100110 test 272: 0 test 273: 010111 test 274: 1011001101010 test 275: 0 test 276: 010110 test 277: 1011001101001 test 278: 0 test 279: 010010 test 280: 1011001011001 test 281: 0 test 282: 010011 test 283: 1011001011010 test 284: 0 test 285: 010001 test 286: 1011001010110 test 287: 0 test 288: 010000 test 289: 1011001010101 test 290: 0 test 291: 110000 test 292: 1101001010101 test 293: 0 test 294: 110001 test 295: 1101001010110 test 296: 0 test 297: 110011 test 298: 1101001011010 test 299: 0 test 300: 110010 test 301: 1101001011001 test 302: 0 test 303: 110110 test 304: 1101001101001 test 305: 0 test 306: 110111 test 307: 1101001101010 test 308: 0 test 309: 110101 test 310: 1101001100110 test 311: 0 test 312: 110100 test 313: 1101001100101 test 314: 0 test 315: 111100 test 316: 1101010100101 test 317: 0 test 318: 111101 test 319: 1101010100110 test 320: 0 test 321: 111111 test 322: 1101010101010 test 323: 0 test 324: 111110 test 325: 1101010101001 test 326: 0 test 327: 111010 test 328: 1101010011001 test 329: 0 test 330: 111011 test 331: 1101010011010 test 332: 0 test 333: 111001 test 334: 1101010010110 test 335: 0 test 336: 111000 test 337: 1101010010101 test 338: 0 test 339: 101000 test 340: 1100110010101 test 341: 0 test 342: 101001 test 343: 1100110010110 test 344: 0 test 345: 101011 test 346: 1100110011010 test 347: 0 test 348: 101010 test 349: 1100110011001 test 350: 0 test 351: 101110 test 352: 1100110101001 test 353: 0 test 354: 101111 test 355: 1100110101010 test 356: 0 test 357: 101101 test 358: 1100110100110 test 359: 0 test 360: 101100 test 361: 1100110100101 test 362: 0 test 363: 100100 test 364: 1100101100101 test 365: 0 test 366: 100101 test 367: 1100101100110 test 368: 0 test 369: 100111 test 370: 1100101101010 test 371: 0 test 372: 100110 test 373: 1100101101001 test 374: 0 test 375: 100010 test 376: 1100101011001 test 377: 0 test 378: 100011 test 379: 1100101011010 test 380: 0 test 381: 100001 test 382: 1100101010110 test 383: 0 test 384: 100000 test 385: 1100101010101 test 386: 0 test 387: 000000 test 388: 1010101010101 test 389: 0 comment: comment: ; DISABLE B INPUTS test 390: 0 comment: comment: comment: ; TEST SHIFT R (LOAD VIA A INPUTS) comment: comment: ; SHIFT IN A ZERO test 391: 0 comment: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS comment: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT test 392: 0000011 test 393: 1010101010110 test 394: 0 1 0 test 395: 1010101010101 test 396: 0 0 test 397: 0000111 test 398: 1010101011010 test 399: 0 1 0 test 400: 1010101010110 test 401: 0 0 test 402: 0000101 test 403: 1010101011001 test 404: 0 1 0 test 405: 1010101010110 test 406: 0 0 test 407: 0001101 test 408: 1010101101001 test 409: 0 1 0 test 410: 1010101011010 test 411: 0 0 test 412: 0001111 test 413: 1010101101010 test 414: 0 1 0 test 415: 1010101011010 test 416: 0 0 test 417: 0001011 test 418: 1010101100110 test 419: 0 1 0 test 420: 1010101011001 test 421: 0 0 test 422: 0001001 test 423: 1010101100101 test 424: 0 1 0 test 425: 1010101011001 test 426: 0 0 test 427: 0011001 test 428: 1010110100101 test 429: 0 1 0 test 430: 1010101101001 test 431: 0 0 test 432: 0011011 test 433: 1010110100110 test 434: 0 1 0 test 435: 1010101101001 test 436: 0 0 test 437: 0011111 test 438: 1010110101010 test 439: 0 1 0 test 440: 1010101101010 test 441: 0 0 test 442: 0011101 test 443: 1010110101001 test 444: 0 1 0 test 445: 1010101101010 test 446: 0 0 test 447: 0010101 test 448: 1010110011001 test 449: 0 1 0 test 450: 1010101100110 test 451: 0 0 test 452: 0010111 test 453: 1010110011010 test 454: 0 1 0 test 455: 1010101100110 test 456: 0 0 test 457: 0010011 test 458: 1010110010110 test 459: 0 1 0 test 460: 1010101100101 test 461: 0 0 test 462: 0010001 test 463: 1010110010101 test 464: 0 1 0 test 465: 1010101100101 test 466: 0 0 test 467: 0110001 test 468: 1011010010101 test 469: 0 1 0 test 470: 1010110100101 test 471: 0 0 test 472: 0110011 test 473: 1011010010110 test 474: 0 1 0 test 475: 1010110100101 test 476: 0 0 test 477: 0110111 test 478: 1011010011010 test 479: 0 1 0 test 480: 1010110100110 test 481: 0 0 test 482: 0110101 test 483: 1011010011001 test 484: 0 1 0 test 485: 1010110100110 test 486: 0 0 test 487: 0111101 test 488: 1011010101001 test 489: 0 1 0 test 490: 1010110101010 test 491: 0 0 test 492: 0111111 test 493: 1011010101010 test 494: 0 1 0 test 495: 1010110101010 test 496: 0 0 test 497: 0111011 test 498: 1011010100110 test 499: 0 1 0 test 500: 1010110101001 test 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test 1391: 1010110100101 test 1392: 0 10 test 1393: 1011010010110 test 1394: 00 test 1395: 0011011 test 1396: 1010110100110 test 1397: 0 10 test 1398: 1011010011010 test 1399: 00 test 1400: 0011111 test 1401: 1010110101010 test 1402: 0 10 test 1403: 1011010101010 test 1404: 00 test 1405: 0011101 test 1406: 1010110101001 test 1407: 0 10 test 1408: 1011010100110 test 1409: 00 test 1410: 0010101 test 1411: 1010110011001 test 1412: 0 10 test 1413: 1011001100110 test 1414: 00 test 1415: 0010111 test 1416: 1010110011010 test 1417: 0 10 test 1418: 1011001101010 test 1419: 00 test 1420: 0010011 test 1421: 1010110010110 test 1422: 0 10 test 1423: 1011001011010 test 1424: 00 test 1425: 0010001 test 1426: 1010110010101 test 1427: 0 10 test 1428: 1011001010110 test 1429: 00 test 1430: 0110001 test 1431: 1011010010101 test 1432: 0 10 test 1433: 1101001010110 test 1434: 00 test 1435: 0110011 test 1436: 1011010010110 test 1437: 0 10 test 1438: 1101001011010 test 1439: 00 test 1440: 0110111 test 1441: 1011010011010 test 1442: 0 10 test 1443: 1101001101010 test 1444: 00 test 1445: 0110101 test 1446: 1011010011001 test 1447: 0 10 test 1448: 1101001100110 test 1449: 00 test 1450: 0111101 test 1451: 1011010101001 test 1452: 0 10 test 1453: 1101010100110 test 1454: 00 test 1455: 0111111 test 1456: 1011010101010 test 1457: 0 10 test 1458: 1101010101010 test 1459: 00 test 1460: 0111011 test 1461: 1011010100110 test 1462: 0 10 test 1463: 1101010011010 test 1464: 00 test 1465: 0111001 test 1466: 1011010100101 test 1467: 0 10 test 1468: 1101010010110 test 1469: 00 test 1470: 0101001 test 1471: 1011001100101 test 1472: 0 10 test 1473: 1100110010110 test 1474: 00 test 1475: 0101011 test 1476: 1011001100110 test 1477: 0 10 test 1478: 1100110011010 test 1479: 00 test 1480: 0101111 test 1481: 1011001101010 test 1482: 0 10 test 1483: 1100110101010 test 1484: 00 test 1485: 0101101 test 1486: 1011001101001 test 1487: 0 10 test 1488: 1100110100110 test 1489: 00 test 1490: 0100101 test 1491: 1011001011001 test 1492: 0 10 test 1493: 1100101100110 test 1494: 00 test 1495: 0100111 test 1496: 1011001011010 test 1497: 0 10 test 1498: 1100101101010 test 1499: 00 test 1500: 0100011 test 1501: 1011001010110 test 1502: 0 10 test 1503: 1100101011010 test 1504: 00 test 1505: 0100001 test 1506: 1011001010101 test 1507: 0 10 test 1508: 1100101010110 test 1509: 00 test 1510: 1100001 test 1511: 1101001010101 test 1512: 0 10 test 1513: 1100101010110 test 1514: 00 test 1515: 1100011 test 1516: 1101001010110 test 1517: 0 10 test 1518: 1100101011010 test 1519: 00 test 1520: 1100111 test 1521: 1101001011010 test 1522: 0 10 test 1523: 1100101101010 test 1524: 00 test 1525: 1100101 test 1526: 1101001011001 test 1527: 0 10 test 1528: 1100101100110 test 1529: 00 test 1530: 1101101 test 1531: 1101001101001 test 1532: 0 10 test 1533: 1100110100110 test 1534: 00 test 1535: 1101111 test 1536: 1101001101010 test 1537: 0 10 test 1538: 1100110101010 test 1539: 00 test 1540: 1101011 test 1541: 1101001100110 test 1542: 0 10 test 1543: 1100110011010 test 1544: 00 test 1545: 1101001 test 1546: 1101001100101 test 1547: 0 10 test 1548: 1100110010110 test 1549: 00 test 1550: 1111001 test 1551: 1101010100101 test 1552: 0 10 test 1553: 1101010010110 test 1554: 00 test 1555: 1111011 test 1556: 1101010100110 test 1557: 0 10 test 1558: 1101010011010 test 1559: 00 test 1560: 1111111 test 1561: 1101010101010 test 1562: 0 10 test 1563: 1101010101010 test 1564: 00 test 1565: 1111101 test 1566: 1101010101001 test 1567: 0 10 test 1568: 1101010100110 test 1569: 00 test 1570: 1110101 test 1571: 1101010011001 test 1572: 0 10 test 1573: 1101001100110 test 1574: 00 test 1575: 1110111 test 1576: 1101010011010 test 1577: 0 10 test 1578: 1101001101010 test 1579: 00 test 1580: 1110011 test 1581: 1101010010110 test 1582: 0 10 test 1583: 1101001011010 test 1584: 00 test 1585: 1110001 test 1586: 1101010010101 test 1587: 0 10 test 1588: 1101001010110 test 1589: 00 test 1590: 1010001 test 1591: 1100110010101 test 1592: 0 10 test 1593: 1011001010110 test 1594: 00 test 1595: 1010011 test 1596: 1100110010110 test 1597: 0 10 test 1598: 1011001011010 test 1599: 00 test 1600: 1010111 test 1601: 1100110011010 test 1602: 0 10 test 1603: 1011001101010 test 1604: 00 test 1605: 1010101 test 1606: 1100110011001 test 1607: 0 10 test 1608: 1011001100110 test 1609: 00 test 1610: 1011101 test 1611: 1100110101001 test 1612: 0 10 test 1613: 1011010100110 test 1614: 00 test 1615: 1011111 test 1616: 1100110101010 test 1617: 0 10 test 1618: 1011010101010 test 1619: 00 test 1620: 1011011 test 1621: 1100110100110 test 1622: 0 10 test 1623: 1011010011010 test 1624: 00 test 1625: 1011001 test 1626: 1100110100101 test 1627: 0 10 test 1628: 1011010010110 test 1629: 00 test 1630: 1001001 test 1631: 1100101100101 test 1632: 0 10 test 1633: 1010110010110 test 1634: 00 test 1635: 1001011 test 1636: 1100101100110 test 1637: 0 10 test 1638: 1010110011010 test 1639: 00 test 1640: 1001111 test 1641: 1100101101010 test 1642: 0 10 test 1643: 1010110101010 test 1644: 00 test 1645: 1001101 test 1646: 1100101101001 test 1647: 0 10 test 1648: 1010110100110 test 1649: 00 test 1650: 1000101 test 1651: 1100101011001 test 1652: 0 10 test 1653: 1010101100110 test 1654: 00 test 1655: 1000111 test 1656: 1100101011010 test 1657: 0 10 test 1658: 1010101101010 test 1659: 00 test 1660: 1000011 test 1661: 1100101010110 test 1662: 0 10 test 1663: 1010101011010 test 1664: 00 test 1665: 1000001 test 1666: 1100101010101 test 1667: 0 10 test 1668: 1010101010110 test 1669: 00 test 1670: 0000001 test 1671: 1010101010101 test 1672: 0 10 test 1673: 1010101010110 test 1674: 00 comment: comment: comment: ; end of SECTION GENERATED BY A PROGRAM comment: comment: comment: ; CLEAR FFs test 1675: 0 010101010101 test 1676: 1 comment: test 1677: 11111110111111010100010101010101 comment: end: END summary column 1: offset 0, mask 0x4000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0020 column 6: offset 2, mask 0x4000 column 7: offset 2, mask 0x0002 column 8: offset 1, mask 0x1000 column 9: offset 1, mask 0x0010 column 10: offset 1, mask 0x0400 column 11: offset 1, mask 0x0200 column 12: offset 2, mask 0x8000 column 13: offset 0, mask 0x8000 column 14: offset 1, mask 0x0080 column 15: offset 2, mask 0x0001 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x4000 column 18: offset 1, mask 0x0040 column 19: offset 1, mask 0x0800 column 20: offset 0, mask 0x2000 column 21: offset 0, mask 0x1000 column 22: offset 0, mask 0x0010 column 23: offset 0, mask 0x0400 column 24: offset 0, mask 0x0800 column 25: offset 0, mask 0x0002 column 26: offset 0, mask 0x0008 column 27: offset 0, mask 0x0200 column 28: offset 0, mask 0x0004 column 29: offset 1, mask 0x0001 column 30: offset 0, mask 0x0001 column 31: offset 1, mask 0x8000 column 32: offset 0, mask 0x0100 direction bits (1=input) 0x1FFF 0x8101 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x891D 0x26FE 0xC002 0x0000 0x0000 2: 0xC91D 0x26FE 0xC002 0x0000 0x0000 3: 0xC91D 0x36FE 0xC002 0x0000 0x0000 4: 0xC91D 0x36D0 0x8002 0x0000 0x0000 5: 0xE81D 0xB6D0 0x8002 0x0000 0x0000 6: 0xC81D 0xB6D0 0x8002 0x0000 0x0000 7: 0xC81D 0xB6D0 0xC002 0x0000 0x0000 8: 0xE81C 0xB6D1 0xC002 0x0000 0x0000 9: 0xC81C 0xB6D1 0xC002 0x0000 0x0000 10: 0xC81C 0xB6D1 0xC000 0x0000 0x0000 11: 0xE91C 0x36D1 0xC000 0x0000 0x0000 12: 0xC91C 0x36D1 0xC000 0x0000 0x0000 13: 0xC91C 0x36F1 0xC000 0x0000 0x0000 14: 0xEB18 0x36F1 0xC000 0x0000 0x0000 15: 0xCB18 0x36F1 0xC000 0x0000 0x0000 16: 0xCB18 0x36F1 0xC002 0x0000 0x0000 17: 0xEA18 0xB6F1 0xC002 0x0000 0x0000 18: 0xCA18 0xB6F1 0xC002 0x0000 0x0000 19: 0xCA18 0xB6F1 0x8002 0x0000 0x0000 20: 0xEA19 0xB6F0 0x8002 0x0000 0x0000 21: 0xCA19 0xB6F0 0x8002 0x0000 0x0000 22: 0xCA19 0xB6F0 0x8000 0x0000 0x0000 23: 0xEB19 0x36F0 0x8000 0x0000 0x0000 24: 0xCB19 0x36F0 0x8000 0x0000 0x0000 25: 0xCB19 0x36F8 0x8000 0x0000 0x0000 26: 0xEB13 0x36F8 0x8000 0x0000 0x0000 27: 0xCB13 0x36F8 0x8000 0x0000 0x0000 28: 0xCB13 0x36F8 0x8002 0x0000 0x0000 29: 0xEA13 0xB6F8 0x8002 0x0000 0x0000 30: 0xCA13 0xB6F8 0x8002 0x0000 0x0000 31: 0xCA13 0xB6F8 0xC002 0x0000 0x0000 32: 0xEA12 0xB6F9 0xC002 0x0000 0x0000 33: 0xCA12 0xB6F9 0xC002 0x0000 0x0000 34: 0xCA12 0xB6F9 0xC000 0x0000 0x0000 35: 0xEB12 0x36F9 0xC000 0x0000 0x0000 36: 0xCB12 0x36F9 0xC000 0x0000 0x0000 37: 0xCB12 0x36D9 0xC000 0x0000 0x0000 38: 0xE916 0x36D9 0xC000 0x0000 0x0000 39: 0xC916 0x36D9 0xC000 0x0000 0x0000 40: 0xC916 0x36D9 0xC002 0x0000 0x0000 41: 0xE816 0xB6D9 0xC002 0x0000 0x0000 42: 0xC816 0xB6D9 0xC002 0x0000 0x0000 43: 0xC816 0xB6D9 0x8002 0x0000 0x0000 44: 0xE817 0xB6D8 0x8002 0x0000 0x0000 45: 0xC817 0xB6D8 0x8002 0x0000 0x0000 46: 0xC817 0xB6D8 0x8000 0x0000 0x0000 47: 0xE917 0x36D8 0x8000 0x0000 0x0000 48: 0xC917 0x36D8 0x8000 0x0000 0x0000 49: 0xC917 0x36DC 0x8000 0x0000 0x0000 50: 0xE517 0x36DC 0x8000 0x0000 0x0000 51: 0xC517 0x36DC 0x8000 0x0000 0x0000 52: 0xC517 0x36DC 0x8002 0x0000 0x0000 53: 0xE417 0xB6DC 0x8002 0x0000 0x0000 54: 0xC417 0xB6DC 0x8002 0x0000 0x0000 55: 0xC417 0xB6DC 0xC002 0x0000 0x0000 56: 0xE416 0xB6DD 0xC002 0x0000 0x0000 57: 0xC416 0xB6DD 0xC002 0x0000 0x0000 58: 0xC416 0xB6DD 0xC000 0x0000 0x0000 59: 0xE516 0x36DD 0xC000 0x0000 0x0000 60: 0xC516 0x36DD 0xC000 0x0000 0x0000 61: 0xC516 0x36FD 0xC000 0x0000 0x0000 62: 0xE712 0x36FD 0xC000 0x0000 0x0000 63: 0xC712 0x36FD 0xC000 0x0000 0x0000 64: 0xC712 0x36FD 0xC002 0x0000 0x0000 65: 0xE612 0xB6FD 0xC002 0x0000 0x0000 66: 0xC612 0xB6FD 0xC002 0x0000 0x0000 67: 0xC612 0xB6FD 0x8002 0x0000 0x0000 68: 0xE613 0xB6FC 0x8002 0x0000 0x0000 69: 0xC613 0xB6FC 0x8002 0x0000 0x0000 70: 0xC613 0xB6FC 0x8000 0x0000 0x0000 71: 0xE713 0x36FC 0x8000 0x0000 0x0000 72: 0xC713 0x36FC 0x8000 0x0000 0x0000 73: 0xC713 0x36F4 0x8000 0x0000 0x0000 74: 0xE719 0x36F4 0x8000 0x0000 0x0000 75: 0xC719 0x36F4 0x8000 0x0000 0x0000 76: 0xC719 0x36F4 0x8002 0x0000 0x0000 77: 0xE619 0xB6F4 0x8002 0x0000 0x0000 78: 0xC619 0xB6F4 0x8002 0x0000 0x0000 79: 0xC619 0xB6F4 0xC002 0x0000 0x0000 80: 0xE618 0xB6F5 0xC002 0x0000 0x0000 81: 0xC618 0xB6F5 0xC002 0x0000 0x0000 82: 0xC618 0xB6F5 0xC000 0x0000 0x0000 83: 0xE718 0x36F5 0xC000 0x0000 0x0000 84: 0xC718 0x36F5 0xC000 0x0000 0x0000 85: 0xC718 0x36D5 0xC000 0x0000 0x0000 86: 0xE51C 0x36D5 0xC000 0x0000 0x0000 87: 0xC51C 0x36D5 0xC000 0x0000 0x0000 88: 0xC51C 0x36D5 0xC002 0x0000 0x0000 89: 0xE41C 0xB6D5 0xC002 0x0000 0x0000 90: 0xC41C 0xB6D5 0xC002 0x0000 0x0000 91: 0xC41C 0xB6D5 0x8002 0x0000 0x0000 92: 0xE41D 0xB6D4 0x8002 0x0000 0x0000 93: 0xC41D 0xB6D4 0x8002 0x0000 0x0000 94: 0xC41D 0xB6D4 0x8000 0x0000 0x0000 95: 0xE51D 0x36D4 0x8000 0x0000 0x0000 96: 0xC51D 0x36D4 0x8000 0x0000 0x0000 97: 0xC51D 0x36D6 0x8000 0x0000 0x0000 98: 0xF50D 0x36D6 0x8000 0x0000 0x0000 99: 0xD50D 0x36D6 0x8000 0x0000 0x0000 100: 0xD50D 0x36D6 0x8002 0x0000 0x0000 101: 0xF40D 0xB6D6 0x8002 0x0000 0x0000 102: 0xD40D 0xB6D6 0x8002 0x0000 0x0000 103: 0xD40D 0xB6D6 0xC002 0x0000 0x0000 104: 0xF40C 0xB6D7 0xC002 0x0000 0x0000 105: 0xD40C 0xB6D7 0xC002 0x0000 0x0000 106: 0xD40C 0xB6D7 0xC000 0x0000 0x0000 107: 0xF50C 0x36D7 0xC000 0x0000 0x0000 108: 0xD50C 0x36D7 0xC000 0x0000 0x0000 109: 0xD50C 0x36F7 0xC000 0x0000 0x0000 110: 0xF708 0x36F7 0xC000 0x0000 0x0000 111: 0xD708 0x36F7 0xC000 0x0000 0x0000 112: 0xD708 0x36F7 0xC002 0x0000 0x0000 113: 0xF608 0xB6F7 0xC002 0x0000 0x0000 114: 0xD608 0xB6F7 0xC002 0x0000 0x0000 115: 0xD608 0xB6F7 0x8002 0x0000 0x0000 116: 0xF609 0xB6F6 0x8002 0x0000 0x0000 117: 0xD609 0xB6F6 0x8002 0x0000 0x0000 118: 0xD609 0xB6F6 0x8000 0x0000 0x0000 119: 0xF709 0x36F6 0x8000 0x0000 0x0000 120: 0xD709 0x36F6 0x8000 0x0000 0x0000 121: 0xD709 0x36FE 0x8000 0x0000 0x0000 122: 0xF703 0x36FE 0x8000 0x0000 0x0000 123: 0xD703 0x36FE 0x8000 0x0000 0x0000 124: 0xD703 0x36FE 0x8002 0x0000 0x0000 125: 0xF603 0xB6FE 0x8002 0x0000 0x0000 126: 0xD603 0xB6FE 0x8002 0x0000 0x0000 127: 0xD603 0xB6FE 0xC002 0x0000 0x0000 128: 0xF602 0xB6FF 0xC002 0x0000 0x0000 129: 0xD602 0xB6FF 0xC002 0x0000 0x0000 130: 0xD602 0xB6FF 0xC000 0x0000 0x0000 131: 0xF702 0x36FF 0xC000 0x0000 0x0000 132: 0xD702 0x36FF 0xC000 0x0000 0x0000 133: 0xD702 0x36DF 0xC000 0x0000 0x0000 134: 0xF506 0x36DF 0xC000 0x0000 0x0000 135: 0xD506 0x36DF 0xC000 0x0000 0x0000 136: 0xD506 0x36DF 0xC002 0x0000 0x0000 137: 0xF406 0xB6DF 0xC002 0x0000 0x0000 138: 0xD406 0xB6DF 0xC002 0x0000 0x0000 139: 0xD406 0xB6DF 0x8002 0x0000 0x0000 140: 0xF407 0xB6DE 0x8002 0x0000 0x0000 141: 0xD407 0xB6DE 0x8002 0x0000 0x0000 142: 0xD407 0xB6DE 0x8000 0x0000 0x0000 143: 0xF507 0x36DE 0x8000 0x0000 0x0000 144: 0xD507 0x36DE 0x8000 0x0000 0x0000 145: 0xD507 0x36DA 0x8000 0x0000 0x0000 146: 0xF907 0x36DA 0x8000 0x0000 0x0000 147: 0xD907 0x36DA 0x8000 0x0000 0x0000 148: 0xD907 0x36DA 0x8002 0x0000 0x0000 149: 0xF807 0xB6DA 0x8002 0x0000 0x0000 150: 0xD807 0xB6DA 0x8002 0x0000 0x0000 151: 0xD807 0xB6DA 0xC002 0x0000 0x0000 152: 0xF806 0xB6DB 0xC002 0x0000 0x0000 153: 0xD806 0xB6DB 0xC002 0x0000 0x0000 154: 0xD806 0xB6DB 0xC000 0x0000 0x0000 155: 0xF906 0x36DB 0xC000 0x0000 0x0000 156: 0xD906 0x36DB 0xC000 0x0000 0x0000 157: 0xD906 0x36FB 0xC000 0x0000 0x0000 158: 0xFB02 0x36FB 0xC000 0x0000 0x0000 159: 0xDB02 0x36FB 0xC000 0x0000 0x0000 160: 0xDB02 0x36FB 0xC002 0x0000 0x0000 161: 0xFA02 0xB6FB 0xC002 0x0000 0x0000 162: 0xDA02 0xB6FB 0xC002 0x0000 0x0000 163: 0xDA02 0xB6FB 0x8002 0x0000 0x0000 164: 0xFA03 0xB6FA 0x8002 0x0000 0x0000 165: 0xDA03 0xB6FA 0x8002 0x0000 0x0000 166: 0xDA03 0xB6FA 0x8000 0x0000 0x0000 167: 0xFB03 0x36FA 0x8000 0x0000 0x0000 168: 0xDB03 0x36FA 0x8000 0x0000 0x0000 169: 0xDB03 0x36F2 0x8000 0x0000 0x0000 170: 0xFB09 0x36F2 0x8000 0x0000 0x0000 171: 0xDB09 0x36F2 0x8000 0x0000 0x0000 172: 0xDB09 0x36F2 0x8002 0x0000 0x0000 173: 0xFA09 0xB6F2 0x8002 0x0000 0x0000 174: 0xDA09 0xB6F2 0x8002 0x0000 0x0000 175: 0xDA09 0xB6F2 0xC002 0x0000 0x0000 176: 0xFA08 0xB6F3 0xC002 0x0000 0x0000 177: 0xDA08 0xB6F3 0xC002 0x0000 0x0000 178: 0xDA08 0xB6F3 0xC000 0x0000 0x0000 179: 0xFB08 0x36F3 0xC000 0x0000 0x0000 180: 0xDB08 0x36F3 0xC000 0x0000 0x0000 181: 0xDB08 0x36D3 0xC000 0x0000 0x0000 182: 0xF90C 0x36D3 0xC000 0x0000 0x0000 183: 0xD90C 0x36D3 0xC000 0x0000 0x0000 184: 0xD90C 0x36D3 0xC002 0x0000 0x0000 185: 0xF80C 0xB6D3 0xC002 0x0000 0x0000 186: 0xD80C 0xB6D3 0xC002 0x0000 0x0000 187: 0xD80C 0xB6D3 0x8002 0x0000 0x0000 188: 0xF80D 0xB6D2 0x8002 0x0000 0x0000 189: 0xD80D 0xB6D2 0x8002 0x0000 0x0000 190: 0xD80D 0xB6D2 0x8000 0x0000 0x0000 191: 0xF90D 0x36D2 0x8000 0x0000 0x0000 192: 0xD90D 0x36D2 0x8000 0x0000 0x0000 193: 0xD90D 0x36D0 0x8000 0x0000 0x0000 194: 0xE91D 0x36D0 0x8000 0x0000 0x0000 195: 0xC91D 0x36D0 0x8000 0x0000 0x0000 196: 0xC91D 0x26D0 0x8000 0x0000 0x0000 197: 0xC91D 0x26D0 0x8001 0x0000 0x0000 198: 0x491D 0x20C0 0x0001 0x0000 0x0000 199: 0x681D 0xA0C0 0x0001 0x0000 0x0000 200: 0x481D 0xA0C0 0x0001 0x0000 0x0000 201: 0xC81D 0xA0C0 0x0001 0x0000 0x0000 202: 0xE81C 0xA0C1 0x0001 0x0000 0x0000 203: 0xC81C 0xA0C1 0x0001 0x0000 0x0000 204: 0xC81C 0xA041 0x0001 0x0000 0x0000 205: 0xE91C 0x2041 0x0001 0x0000 0x0000 206: 0xC91C 0x2041 0x0001 0x0000 0x0000 207: 0xC91C 0x2041 0x8001 0x0000 0x0000 208: 0xEB18 0x2041 0x8001 0x0000 0x0000 209: 0xCB18 0x2041 0x8001 0x0000 0x0000 210: 0xCB18 0x20C1 0x8001 0x0000 0x0000 211: 0xEA18 0xA0C1 0x8001 0x0000 0x0000 212: 0xCA18 0xA0C1 0x8001 0x0000 0x0000 213: 0x4A18 0xA0C1 0x8001 0x0000 0x0000 214: 0x6A19 0xA0C0 0x8001 0x0000 0x0000 215: 0x4A19 0xA0C0 0x8001 0x0000 0x0000 216: 0x4A19 0xA040 0x8001 0x0000 0x0000 217: 0x6B19 0x2040 0x8001 0x0000 0x0000 218: 0x4B19 0x2040 0x8001 0x0000 0x0000 219: 0x4B19 0x2240 0x8001 0x0000 0x0000 220: 0x6B13 0x2240 0x8001 0x0000 0x0000 221: 0x4B13 0x2240 0x8001 0x0000 0x0000 222: 0x4B13 0x22C0 0x8001 0x0000 0x0000 223: 0x6A13 0xA2C0 0x8001 0x0000 0x0000 224: 0x4A13 0xA2C0 0x8001 0x0000 0x0000 225: 0xCA13 0xA2C0 0x8001 0x0000 0x0000 226: 0xEA12 0xA2C1 0x8001 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0x4002 0x0000 0x0000 1659: 0x4A18 0xA043 0x4002 0x0000 0x0000 1660: 0x4A18 0xB043 0x0002 0x0000 0x0000 1661: 0x780D 0xB042 0x0002 0x0000 0x0000 1662: 0x580D 0xA842 0x0002 0x0000 0x0000 1663: 0x681C 0xA843 0x0002 0x0000 0x0000 1664: 0x481C 0xA043 0x0002 0x0000 0x0000 1665: 0x481C 0xB043 0x0000 0x0000 0x0000 1666: 0x790D 0x3042 0x0000 0x0000 0x0000 1667: 0x590D 0x2842 0x0000 0x0000 0x0000 1668: 0x681D 0xA842 0x0000 0x0000 0x0000 1669: 0x481D 0xA042 0x0000 0x0000 0x0000 1670: 0x481D 0xB040 0x0000 0x0000 0x0000 1671: 0x691D 0x3040 0x0000 0x0000 0x0000 1672: 0x491D 0x2840 0x0000 0x0000 0x0000 1673: 0x681D 0xA840 0x0000 0x0000 0x0000 1674: 0x481D 0xA040 0x0000 0x0000 0x0000 1675: 0x091D 0x2040 0x0000 0x0000 0x0000 1676: 0x491D 0x2040 0x0000 0x0000 0x0000 1677: 0xC91D 0x26FE 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOOOOOOIIIIIIGIIP GOOOOOOIIIIIIIII G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 1677 'test steps' 1775 lines ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) PINS Main menu Fri Jun 30 10:15:17 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 10:15:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 98 11100000111111010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 99 11100000111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 100 11100010111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 101 11100010111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 102 11100010111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 103 11100110111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 104 11100110111111010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 105 11100110111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 106 11100100111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 107 11100100111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 108 11100100111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 109 11101101111111010100010101010101 fail ^^^^ ^^ step 110 11101101111111010101101001101001 step 111 11101101111111010100101001101001 step 112 11101111111111010100101001101001 step 113 11101111111111010101101001101010 step 114 11101111111111010100101001101010 step 115 11101011111111010100101001101010 step 116 11101011111111010101101001100110 step 117 11101011111111010100101001100110 step 118 11101001111111010100101001100110 step 119 11101001111111010101101001100101 step 120 11101001111111010100101001100101 step 121 11111001111111010100101001100101 step 122 11111001111111010101101010100101 step 123 11111001111111010100101010100101 step 124 11111011111111010100101010100101 step 125 11111011111111010101101010100110 step 126 11111011111111010100101010100110 step 127 11111111111111010100101010100110 step 128 11111111111111010101101010101010 step 129 11111111111111010100101010101010 step 130 11111101111111010100101010101010 step 131 11111101111111010101101010101001 step 132 11111101111111010100101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 133 11110100111111010100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10101010101 step 134 11110100111111010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 135 11110100111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 136 11110110111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 137 11110110111111010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 138 11110110111111010100010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 139 11110010111111010100010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 140 11110010111111010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 141 11110010111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 142 11110000111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 143 11110000111111010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 144 11110000111111010100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 145 11010000111111010100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 146 11010000111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 147 11010000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 148 11010010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 149 11010010111111010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 150 11010010111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 151 11010110111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 152 11010110111111010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 153 11010110111111010100010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 154 11010100111111010100010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 155 11010100111111010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 156 11010100111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 157 11011101111111010100010101010101 fail ^^ ^^ ^^ step 158 11011101111111010101100110101001 step 159 11011101111111010100100110101001 step 160 11011111111111010100100110101001 step 161 11011111111111010101100110101010 step 162 11011111111111010100100110101010 step 163 11011011111111010100100110101010 step 164 11011011111111010101100110100110 step 165 11011011111111010100100110100110 step 166 11011001111111010100100110100110 step 167 11011001111111010101100110100101 step 168 11011001111111010100100110100101 step 169 11001001111111010100100110100101 step 170 11001001111111010101100101100101 step 171 11001001111111010100100101100101 step 172 11001011111111010100100101100101 step 173 11001011111111010101100101100110 step 174 11001011111111010100100101100110 step 175 11001111111111010100100101100110 step 176 11001111111111010101100101101010 step 177 11001111111111010100100101101010 step 178 11001101111111010100100101101010 step 179 11001101111111010101100101101001 step 180 11001101111111010100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 181 11000100111111010100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 0101 step 182 11000100111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 183 11000100111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 184 11000110111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 185 11000110111111010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 186 11000110111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 187 11000010111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 188 11000010111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 189 11000010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 190 11000000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 191 11000000111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 192 11000000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 193 10000000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 194 10000000111111010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 195 10000000111111010100010101010101 fail ^ step 196 10000000111111010100010101010101 step 197 10000000111111110100010101010101 step 198 10000000000001110100010101010101 step 199 10000000000001110101010101010110 step 200 10000000000001110100010101010110 step 201 10000000000011110100010101010110 step 202 10000000000011110101010101011010 step 203 10000000000011110100010101011010 step 204 10000000000010110100010101011010 step 205 10000000000010110101010101011001 step 206 10000000000010110100010101011001 step 207 10000000000110110100010101011001 step 208 10000000000110110101010101101001 step 209 10000000000110110100010101101001 step 210 10000000000111110100010101101001 step 211 10000000000111110101010101101010 step 212 10000000000111110100010101101010 step 213 10000000000101110100010101101010 step 214 10000000000101110101010101100110 step 215 10000000000101110100010101100110 step 216 10000000000100110100010101100110 step 217 10000000000100110101010101100101 step 218 10000000000100110100010101100101 step 219 10000000001100110100010101100101 step 220 10000000001100110101010110100101 step 221 10000000001100110100010110100101 step 222 10000000001101110100010110100101 step 223 10000000001101110101010110100110 step 224 10000000001101110100010110100110 step 225 10000000001111110100010110100110 step 226 10000000001111110101010110101010 step 227 10000000001111110100010110101010 step 228 10000000001110110100010110101010 step 229 10000000001110110101010110101001 step 230 10000000001110110100010110101001 step 231 10000000001010110100010110101001 step 232 10000000001010110101010110011001 step 233 10000000001010110100010110011001 step 234 10000000001011110100010110011001 step 235 10000000001011110101010110011010 step 236 10000000001011110100010110011010 step 237 10000000001001110100010110011010 step 238 10000000001001110101010110010110 step 239 10000000001001110100010110010110 step 240 10000000001000110100010110010110 step 241 10000000001000110101010110010101 step 242 10000000001000110100010110010101 step 243 10000000011000110100010110010101 step 244 10000000011000110101011010010101 step 245 10000000011000110100011010010101 step 246 10000000011001110100011010010101 step 247 10000000011001110101011010010110 step 248 10000000011001110100011010010110 step 249 10000000011011110100011010010110 step 250 10000000011011110101011010011010 step 251 10000000011011110100011010011010 step 252 10000000011010110100011010011010 step 253 10000000011010110101011010011001 step 254 10000000011010110100011010011001 step 255 10000000011110110100011010011001 step 256 10000000011110110101011010101001 step 257 10000000011110110100011010101001 step 258 10000000011111110100011010101001 step 259 10000000011111110101011010101010 step 260 10000000011111110100011010101010 step 261 10000000011101110100011010101010 step 262 10000000011101110101011010100110 step 263 10000000011101110100011010100110 step 264 10000000011100110100011010100110 step 265 10000000011100110101011010100101 step 266 10000000011100110100011010100101 step 267 10000000010100110100011010100101 step 268 10000000010100110101011001100101 step 269 10000000010100110100011001100101 step 270 10000000010101110100011001100101 step 271 10000000010101110101011001100110 step 272 10000000010101110100011001100110 step 273 10000000010111110100011001100110 step 274 10000000010111110101011001101010 step 275 10000000010111110100011001101010 step 276 10000000010110110100011001101010 step 277 10000000010110110101011001101001 step 278 10000000010110110100011001101001 step 279 10000000010010110100011001101001 step 280 10000000010010110101011001011001 step 281 10000000010010110100011001011001 step 282 10000000010011110100011001011001 step 283 10000000010011110101011001011010 step 284 10000000010011110100011001011010 step 285 10000000010001110100011001011010 step 286 10000000010001110101011001010110 step 287 10000000010001110100011001010110 step 288 10000000010000110100011001010110 step 289 10000000010000110101011001010101 step 290 10000000010000110100011001010101 step 291 10000000110000110100011001010101 step 292 10000000110000110101101001010101 step 293 10000000110000110100101001010101 step 294 10000000110001110100101001010101 step 295 10000000110001110101101001010110 step 296 10000000110001110100101001010110 step 297 10000000110011110100101001010110 step 298 10000000110011110101101001011010 step 299 10000000110011110100101001011010 step 300 10000000110010110100101001011010 step 301 10000000110010110101101001011001 step 302 10000000110010110100101001011001 step 303 10000000110110110100101001011001 step 304 10000000110110110101101001101001 step 305 10000000110110110100101001101001 step 306 10000000110111110100101001101001 step 307 10000000110111110101101001101010 step 308 10000000110111110100101001101010 step 309 10000000110101110100101001101010 step 310 10000000110101110101101001100110 step 311 10000000110101110100101001100110 step 312 10000000110100110100101001100110 step 313 10000000110100110101101001100101 step 314 10000000110100110100101001100101 step 315 10000000111100110100101001100101 step 316 10000000111100110101101010100101 step 317 10000000111100110100101010100101 step 318 10000000111101110100101010100101 step 319 10000000111101110101101010100110 step 320 10000000111101110100101010100110 step 321 10000000111111110100101010100110 step 322 10000000111111110101101010101010 step 323 10000000111111110100101010101010 step 324 10000000111110110100101010101010 step 325 10000000111110110101101010101001 step 326 10000000111110110100101010101001 step 327 10000000111010110100101010101001 step 328 10000000111010110101101010011001 step 329 10000000111010110100101010011001 step 330 10000000111011110100101010011001 step 331 10000000111011110101101010011010 step 332 10000000111011110100101010011010 step 333 10000000111001110100101010011010 step 334 10000000111001110101101010010110 step 335 10000000111001110100101010010110 step 336 10000000111000110100101010010110 step 337 10000000111000110101101010010101 step 338 10000000111000110100101010010101 step 339 10000000101000110100101010010101 step 340 10000000101000110101100110010101 step 341 10000000101000110100100110010101 step 342 10000000101001110100100110010101 step 343 10000000101001110101100110010110 step 344 10000000101001110100100110010110 step 345 10000000101011110100100110010110 step 346 10000000101011110101100110011010 step 347 10000000101011110100100110011010 step 348 10000000101010110100100110011010 step 349 10000000101010110101100110011001 step 350 10000000101010110100100110011001 step 351 10000000101110110100100110011001 step 352 10000000101110110101100110101001 step 353 10000000101110110100100110101001 step 354 10000000101111110100100110101001 step 355 10000000101111110101100110101010 step 356 10000000101111110100100110101010 step 357 10000000101101110100100110101010 step 358 10000000101101110101100110100110 step 359 10000000101101110100100110100110 step 360 10000000101100110100100110100110 step 361 10000000101100110101100110100101 step 362 10000000101100110100100110100101 step 363 10000000100100110100100110100101 step 364 10000000100100110101100101100101 step 365 10000000100100110100100101100101 step 366 10000000100101110100100101100101 step 367 10000000100101110101100101100110 step 368 10000000100101110100100101100110 step 369 10000000100111110100100101100110 step 370 10000000100111110101100101101010 step 371 10000000100111110100100101101010 step 372 10000000100110110100100101101010 step 373 10000000100110110101100101101001 step 374 10000000100110110100100101101001 step 375 10000000100010110100100101101001 step 376 10000000100010110101100101011001 step 377 10000000100010110100100101011001 step 378 10000000100011110100100101011001 step 379 10000000100011110101100101011010 step 380 10000000100011110100100101011010 step 381 10000000100001110100100101011010 step 382 10000000100001110101100101010110 step 383 10000000100001110100100101010110 step 384 10000000100000110100100101010110 step 385 10000000100000110101100101010101 step 386 10000000100000110100100101010101 step 387 10000000000000110100100101010101 step 388 10000000000000110101010101010101 step 389 10000000000000110100010101010101 step 390 10000000000000010100010101010101 step 391 10000000000000000100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 392 10000010000000000100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 393 10000010000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 394 10000010000000001100010101010101 fail ^^ step 395 10000010000000001101010101010101 step 396 10000010000000000100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 397 10000110000000000100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 398 10000110000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 399 10000110000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 400 10000110000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 401 10000110000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 402 10000100000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 403 10000100000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 404 10000100000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 405 10000100000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 406 10000100000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 407 10001101000000000100010101010101 fail ^^ step 408 10001101000000000101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 409 10000100000000001100010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 410 10000100000000001101010101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 411 10000100000000000100010101011010 fail ^ step 412 10001111000000000100010101011010 step 413 10001111000000000101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 414 10000110000000001100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 415 10000110000000001101010101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 416 10000110000000000100010101011010 fail ^ step 417 10001011000000000100010101011010 step 418 10001011000000000101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 419 10000010000000001100010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 420 10000010000000001101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 421 10000010000000000100010101011001 fail ^ step 422 10001001000000000100010101011001 step 423 10001001000000000101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 424 10000000000000001100010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 425 10000000000000001101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 426 10000000000000000100010101011001 fail ^ step 427 10011001000000000100010101011001 step 428 10011001000000000101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 429 10010000000000001100010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 430 10010000000000001101010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 431 10010000000000000100010101101001 fail ^ step 432 10011011000000000100010101101001 step 433 10011011000000000101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 434 10010010000000001100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 1001 step 435 10010010000000001101010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 436 10010010000000000100010101101001 fail ^ step 437 10011111000000000100010101101001 step 438 10011111000000000101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 439 10010110000000001100010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 440 10010110000000001101010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 441 10010110000000000100010101101010 fail ^ step 442 10011101000000000100010101101010 step 443 10011101000000000101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 444 10010100000000001100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 445 10010100000000001101010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 446 10010100000000000100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 447 10010100000000000100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 010101 step 448 10010100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 449 10010100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 450 10010100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 451 10010100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 452 10010110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 453 10010110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 454 10010110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 455 10010110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 456 10010110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 457 10010010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 458 10010010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 459 10010010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 460 10010010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 461 10010010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 462 10010000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 463 10010000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 464 10010000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 465 10010000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 466 10010000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 467 10110000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 468 10110000000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 469 10110000000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 470 10110000000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 471 10110000000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 472 10110010000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 473 10110010000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 474 10110010000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 475 10110010000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 476 10110010000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 477 10110110000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 478 10110110000000000101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 479 10110110000000001100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 480 10110110000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 481 10110110000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 482 10110100000000000100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 483 10110100000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 484 10110100000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 485 10110100000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 486 10110100000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 487 10111101000000000100010101010101 fail ^^^^ ^^ step 488 10111101000000000101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 489 10110100000000001100011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 490 10110100000000001101010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 491 10110100000000000100010110101010 fail ^ step 492 10111111000000000100010110101010 step 493 10111111000000000101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 494 10110110000000001100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 495 10110110000000001101010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 496 10110110000000000100010110101010 fail ^ step 497 10111011000000000100010110101010 step 498 10111011000000000101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 499 10110010000000001100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 1001 step 500 10110010000000001101010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 501 10110010000000000100010110101001 fail ^ step 502 10111001000000000100010110101001 step 503 10111001000000000101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 504 10110000000000001100011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 505 10110000000000001101010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 506 10110000000000000100010110101001 fail ^ step 507 10101001000000000100010110101001 step 508 10101001000000000101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 509 10100000000000001100011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01100110 step 510 10100000000000001101010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 511 10100000000000000100010110011001 fail ^ step 512 10101011000000000100010110011001 step 513 10101011000000000101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 514 10100010000000001100011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110011001 step 515 10100010000000001101010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 516 10100010000000000100010110011001 fail ^ step 517 10101111000000000100010110011001 step 518 10101111000000000101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 519 10100110000000001100011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 520 10100110000000001101010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 521 10100110000000000100010110011010 fail ^ step 522 10101101000000000100010110011010 step 523 10101101000000000101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 524 10100100000000001100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 10 step 525 10100100000000001101010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 526 10100100000000000100010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 527 10100100000000000100010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 0101 step 528 10100100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 529 10100100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 530 10100100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 531 10100100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 532 10100110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 533 10100110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 534 10100110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 535 10100110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 536 10100110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 537 10100010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 538 10100010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 539 10100010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 540 10100010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 541 10100010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 542 10100000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 543 10100000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 544 10100000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 545 10100000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 546 10100000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 547 11100000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 548 11100000000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 549 11100000000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 550 11100000000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 551 11100000000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 552 11100010000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 553 11100010000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 554 11100010000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 555 11100010000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 556 11100010000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 557 11100110000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 558 11100110000000000101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 559 11100110000000001100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 560 11100110000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 561 11100110000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 562 11100100000000000100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 563 11100100000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 564 11100100000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 565 11100100000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 566 11100100000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 567 11101101000000000100010101010101 fail ^^^^ ^^ step 568 11101101000000000101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 569 11100100000000001100101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 10 step 570 11100100000000001101011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 571 11100100000000000100011010011010 fail ^ step 572 11101111000000000100011010011010 step 573 11101111000000000101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 574 11100110000000001100101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 step 575 11100110000000001101011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 576 11100110000000000100011010011010 fail ^ step 577 11101011000000000100011010011010 step 578 11101011000000000101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 579 11100010000000001100101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10011001 step 580 11100010000000001101011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 581 11100010000000000100011010011001 fail ^ step 582 11101001000000000100011010011001 step 583 11101001000000000101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 584 11100000000000001100101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 100110 step 585 11100000000000001101011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 586 11100000000000000100011010011001 fail ^ step 587 11111001000000000100011010011001 step 588 11111001000000000101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 589 11110000000000001100101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 590 11110000000000001101011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 591 11110000000000000100011010101001 fail ^ step 592 11111011000000000100011010101001 step 593 11111011000000000101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 594 11110010000000001100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 step 595 11110010000000001101011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 596 11110010000000000100011010101001 fail ^ step 597 11111111000000000100011010101001 step 598 11111111000000000101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 599 11110110000000001100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 600 11110110000000001101011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 601 11110110000000000100011010101010 fail ^ step 602 11111101000000000100011010101010 step 603 11111101000000000101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 604 11110100000000001100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 605 11110100000000001101011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 606 11110100000000000100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 607 11110100000000000100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0101010101 step 608 11110100000000000101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 609 11110100000000001100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 610 11110100000000001101010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 611 11110100000000000100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 612 11110110000000000100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 613 11110110000000000101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 614 11110110000000001100010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 615 11110110000000001101010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 616 11110110000000000100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 617 11110010000000000100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 618 11110010000000000101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 619 11110010000000001100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 620 11110010000000001101010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 621 11110010000000000100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 622 11110000000000000100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 623 11110000000000000101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 624 11110000000000001100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 625 11110000000000001101010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 626 11110000000000000100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 627 11010000000000000100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 628 11010000000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 629 11010000000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 630 11010000000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 631 11010000000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 632 11010010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 633 11010010000000000101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 634 11010010000000001100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 635 11010010000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 636 11010010000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 637 11010110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 638 11010110000000000101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 639 11010110000000001100010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 640 11010110000000001101010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 641 11010110000000000100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 642 11010100000000000100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 643 11010100000000000101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 644 11010100000000001100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 645 11010100000000001101010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 646 11010100000000000100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 647 11011101000000000100010101010101 fail ^^ ^^ ^^ step 648 11011101000000000101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 649 11010100000000001100100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 10 step 650 11010100000000001101011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 651 11010100000000000100011001101010 fail ^ step 652 11011111000000000100011001101010 step 653 11011111000000000101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 654 11010110000000001100100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 step 655 11010110000000001101011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 656 11010110000000000100011001101010 fail ^ step 657 11011011000000000100011001101010 step 658 11011011000000000101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 659 11010010000000001100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 1001 step 660 11010010000000001101011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 661 11010010000000000100011001101001 fail ^ step 662 11011001000000000100011001101001 step 663 11011001000000000101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 664 11010000000000001100100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 10 step 665 11010000000000001101011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 666 11010000000000000100011001101001 fail ^ step 667 11001001000000000100011001101001 step 668 11001001000000000101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 669 11000000000000001100100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 0110 step 670 11000000000000001101011001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 671 11000000000000000100011001011001 fail ^ step 672 11001011000000000100011001011001 step 673 11001011000000000101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 674 11000010000000001100100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 011001 step 675 11000010000000001101011001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 676 11000010000000000100011001011001 fail ^ step 677 11001111000000000100011001011001 step 678 11001111000000000101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 679 11000110000000001100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 680 11000110000000001101011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 681 11000110000000000100011001011010 fail ^ step 682 11001101000000000100011001011010 step 683 11001101000000000101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 684 11000100000000001100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 10 step 685 11000100000000001101011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 686 11000100000000000100011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 687 11000100000000000100011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 0101 step 688 11000100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 689 11000100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 690 11000100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 691 11000100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 692 11000110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 693 11000110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 694 11000110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 695 11000110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 696 11000110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 697 11000010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 698 11000010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 699 11000010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 700 11000010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 701 11000010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 702 11000000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 703 11000000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 704 11000000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 705 11000000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 706 11000000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 707 10000000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 708 10000000000000000101010101010101 fail ^ step 709 10000000000000001100010101010101 step 710 10000000000000001101010101010101 step 711 10000000000000000100010101010101 step 712 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 713 10000010000000010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 714 10000010000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 715 10000010000000011100010101010101 fail ^^ step 716 10000010000000011101100101010101 step 717 10000010000000010100100101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 718 10000110000000010100100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 719 10000110000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 720 10000110000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 721 10000110000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 722 10000110000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 723 10000100000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 724 10000100000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 725 10000100000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 726 10000100000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 727 10000100000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 728 10001101000000010100100101010101 fail ^^ step 729 10001101000000010101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 730 10000100000000011100010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 731 10000100000000011101100101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 732 10000100000000010100100101011010 fail ^ step 733 10001111000000010100100101011010 step 734 10001111000000010101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 735 10000110000000011100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 736 10000110000000011101100101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 737 10000110000000010100100101011010 fail ^ step 738 10001011000000010100100101011010 step 739 10001011000000010101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 740 10000010000000011100010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 011001 step 741 10000010000000011101100101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 742 10000010000000010100100101011001 fail ^ step 743 10001001000000010100100101011001 step 744 10001001000000010101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 745 10000000000000011100010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 0110 step 746 10000000000000011101100101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 747 10000000000000010100100101011001 fail ^ step 748 10011001000000010100100101011001 step 749 10011001000000010101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 750 10010000000000011100010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 751 10010000000000011101100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 752 10010000000000010100100101101001 fail ^ step 753 10011011000000010100100101101001 step 754 10011011000000010101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 755 10010010000000011100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 1001 step 756 10010010000000011101100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 757 10010010000000010100100101101001 fail ^ step 758 10011111000000010100100101101001 step 759 10011111000000010101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 760 10010110000000011100010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 761 10010110000000011101100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 762 10010110000000010100100101101010 fail ^ step 763 10011101000000010100100101101010 step 764 10011101000000010101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 765 10010100000000011100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 766 10010100000000011101100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 767 10010100000000010100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 768 10010100000000010100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 010101 step 769 10010100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 770 10010100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 771 10010100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 772 10010100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 773 10010110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 774 10010110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 775 10010110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 776 10010110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 777 10010110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 778 10010010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 779 10010010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 780 10010010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 781 10010010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 782 10010010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 783 10010000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 784 10010000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 785 10010000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 786 10010000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 787 10010000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 788 10110000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 789 10110000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 790 10110000000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 791 10110000000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 792 10110000000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 793 10110010000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 794 10110010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 795 10110010000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 796 10110010000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 797 10110010000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 798 10110110000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 799 10110110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 800 10110110000000011100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 801 10110110000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 802 10110110000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 803 10110100000000010100100101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 804 10110100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 805 10110100000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 806 10110100000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 807 10110100000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 808 10111101000000010100100101010101 fail ^^^^ ^^ step 809 10111101000000010101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 810 10110100000000011100011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 10 step 811 10110100000000011101100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 812 10110100000000010100100110101010 fail ^ step 813 10111111000000010100100110101010 step 814 10111111000000010101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 815 10110110000000011100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 step 816 10110110000000011101100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 817 10110110000000010100100110101010 fail ^ step 818 10111011000000010100100110101010 step 819 10111011000000010101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 820 10110010000000011100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 1001 step 821 10110010000000011101100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 822 10110010000000010100100110101001 fail ^ step 823 10111001000000010100100110101001 step 824 10111001000000010101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 825 10110000000000011100011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 10 step 826 10110000000000011101100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 827 10110000000000010100100110101001 fail ^ step 828 10101001000000010100100110101001 step 829 10101001000000010101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 830 10100000000000011100011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001100110 step 831 10100000000000011101100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 832 10100000000000010100100110011001 fail ^ step 833 10101011000000010100100110011001 step 834 10101011000000010101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 835 10100010000000011100011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110011001 step 836 10100010000000011101100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 837 10100010000000010100100110011001 fail ^ step 838 10101111000000010100100110011001 step 839 10101111000000010101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 840 10100110000000011100011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 step 841 10100110000000011101100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 842 10100110000000010100100110011010 fail ^ step 843 10101101000000010100100110011010 step 844 10101101000000010101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 845 10100100000000011100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 10 step 846 10100100000000011101100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 847 10100100000000010100100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 848 10100100000000010100100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 01 0101 step 849 10100100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 850 10100100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 851 10100100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 852 10100100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 853 10100110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 854 10100110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 855 10100110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 856 10100110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 857 10100110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 858 10100010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 859 10100010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 860 10100010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 861 10100010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 862 10100010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 863 10100000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 864 10100000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 865 10100000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 866 10100000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 867 10100000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 868 11100000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 869 11100000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 870 11100000000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 871 11100000000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 872 11100000000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 873 11100010000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 874 11100010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 875 11100010000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 876 11100010000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 877 11100010000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 878 11100110000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 879 11100110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 880 11100110000000011100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 881 11100110000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 882 11100110000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 883 11100100000000010100100101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 884 11100100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 885 11100100000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 886 11100100000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 887 11100100000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 888 11101101000000010100100101010101 fail ^^^^ ^^ step 889 11101101000000010101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 890 11100100000000011100101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 891 11100100000000011101101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 892 11100100000000010100101010011010 fail ^ step 893 11101111000000010100101010011010 step 894 11101111000000010101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 895 11100110000000011100101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 896 11100110000000011101101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 897 11100110000000010100101010011010 fail ^ step 898 11101011000000010100101010011010 step 899 11101011000000010101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 900 11100010000000011100101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10011001 step 901 11100010000000011101101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 902 11100010000000010100101010011001 fail ^ step 903 11101001000000010100101010011001 step 904 11101001000000010101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 905 11100000000000011100101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 100110 step 906 11100000000000011101101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 907 11100000000000010100101010011001 fail ^ step 908 11111001000000010100101010011001 step 909 11111001000000010101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 910 11110000000000011100101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 911 11110000000000011101101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 912 11110000000000010100101010101001 fail ^ step 913 11111011000000010100101010101001 step 914 11111011000000010101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 915 11110010000000011100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 916 11110010000000011101101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 917 11110010000000010100101010101001 fail ^ step 918 11111111000000010100101010101001 step 919 11111111000000010101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 920 11110110000000011100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 921 11110110000000011101101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 922 11110110000000010100101010101010 fail ^ step 923 11111101000000010100101010101010 step 924 11111101000000010101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 925 11110100000000011100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 926 11110100000000011101101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 927 11110100000000010100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 928 11110100000000010100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1010101010101 step 929 11110100000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 930 11110100000000011100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 931 11110100000000011101100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 932 11110100000000010100100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 933 11110110000000010100100101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 934 11110110000000010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 935 11110110000000011100010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 936 11110110000000011101100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 937 11110110000000010100100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 938 11110010000000010100100101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 939 11110010000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 940 11110010000000011100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 941 11110010000000011101100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 942 11110010000000010100100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 943 11110000000000010100100101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 944 11110000000000010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 945 11110000000000011100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 946 11110000000000011101100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 947 11110000000000010100100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 948 11010000000000010100100101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 949 11010000000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 950 11010000000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 951 11010000000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 952 11010000000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 953 11010010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 954 11010010000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 955 11010010000000011100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 956 11010010000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 957 11010010000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 958 11010110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 959 11010110000000010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 960 11010110000000011100010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 961 11010110000000011101100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 962 11010110000000010100100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 963 11010100000000010100100101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 964 11010100000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 965 11010100000000011100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 966 11010100000000011101100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 967 11010100000000010100100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 968 11011101000000010100100101010101 fail ^^ ^^ ^^ step 969 11011101000000010101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 970 11010100000000011100100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 971 11010100000000011101101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 972 11010100000000010100101001101010 fail ^ step 973 11011111000000010100101001101010 step 974 11011111000000010101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 975 11010110000000011100100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 976 11010110000000011101101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 977 11010110000000010100101001101010 fail ^ step 978 11011011000000010100101001101010 step 979 11011011000000010101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 980 11010010000000011100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 1001 step 981 11010010000000011101101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 982 11010010000000010100101001101001 fail ^ step 983 11011001000000010100101001101001 step 984 11011001000000010101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 985 11010000000000011100100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 986 11010000000000011101101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 987 11010000000000010100101001101001 fail ^ step 988 11001001000000010100101001101001 step 989 11001001000000010101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 990 11000000000000011100100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 991 11000000000000011101101001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 992 11000000000000010100101001011001 fail ^ step 993 11001011000000010100101001011001 step 994 11001011000000010101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 995 11000010000000011100100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 011001 step 996 11000010000000011101101001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 997 11000010000000010100101001011001 fail ^ step 998 11001111000000010100101001011001 step 999 11001111000000010101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 1000 11000110000000011100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1001 11000110000000011101101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1002 11000110000000010100101001011010 fail ^ step 1003 11001101000000010100101001011010 step 1004 11001101000000010101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 1005 11000100000000011100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 10 step 1006 11000100000000011101101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1007 11000100000000010100101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1008 11000100000000010100101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10101 0101 step 1009 11000100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1010 11000100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1011 11000100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1012 11000100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1013 11000110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1014 11000110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1015 11000110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1016 11000110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1017 11000110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1018 11000010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1019 11000010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1020 11000010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1021 11000010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1022 11000010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1023 11000000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1024 11000000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1025 11000000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1026 11000000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1027 11000000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1028 10000000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1029 10000000000000010101010101010101 fail ^ step 1030 10000000000000011100010101010101 step 1031 10000000000000011101100101010101 step 1032 10000000000000010100100101010101 step 1033 10000000000000010000100101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1034 10000010000000010000100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1035 10000010000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1036 10000010000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1037 10000010000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1038 10000010000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1039 10000110000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1040 10000110000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1041 10000110000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1042 10000110000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1043 10000110000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1044 10000100000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1045 10000100000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1046 10000100000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1047 10000100000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1048 10000100000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1049 10001101000000010000010101010101 fail ^^ step 1050 10001101000000010001010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1051 10000100000000010010010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1052 10000100000000010011010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1053 10000100000000010000010110100101 fail ^ step 1054 10001111000000010000010110100101 step 1055 10001111000000010001010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1056 10000110000000010010010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1057 10000110000000010011010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1058 10000110000000010000010110101001 fail ^ step 1059 10001011000000010000010110101001 step 1060 10001011000000010001010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1061 10000010000000010010010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10011001 step 1062 10000010000000010011010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1063 10000010000000010000010110011001 fail ^ step 1064 10001001000000010000010110011001 step 1065 10001001000000010001010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1066 10000000000000010010010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 1067 10000000000000010011010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1068 10000000000000010000010110010101 fail ^ step 1069 10011001000000010000010110010101 step 1070 10011001000000010001010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1071 10010000000000010010010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1072 10010000000000010011011010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1073 10010000000000010000011010010101 fail ^ step 1074 10011011000000010000011010010101 step 1075 10011011000000010001010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1076 10010010000000010010010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 011001 step 1077 10010010000000010011011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1078 10010010000000010000011010011001 fail ^ step 1079 10011111000000010000011010011001 step 1080 10011111000000010001010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1081 10010110000000010010010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1082 10010110000000010011011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1083 10010110000000010000011010101001 fail ^ step 1084 10011101000000010000011010101001 step 1085 10011101000000010001010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1086 10010100000000010010010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1087 10010100000000010011011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1088 10010100000000010000011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1089 10010100000000010000011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 010101 step 1090 10010100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1091 10010100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1092 10010100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1093 10010100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1094 10010110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1095 10010110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1096 10010110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1097 10010110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1098 10010110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1099 10010010000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1100 10010010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1101 10010010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1102 10010010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1103 10010010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1104 10010000000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1105 10010000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1106 10010000000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1107 10010000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1108 10010000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1109 10110000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1110 10110000000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1111 10110000000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1112 10110000000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1113 10110000000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1114 10110010000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1115 10110010000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1116 10110010000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1117 10110010000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1118 10110010000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1119 10110110000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1120 10110110000000010001010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1121 10110110000000010010010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1122 10110110000000010011010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1123 10110110000000010000010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1124 10110100000000010000010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1125 10110100000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1126 10110100000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1127 10110100000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1128 10110100000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1129 10111101000000010000010101010101 fail ^^^^ ^^ step 1130 10111101000000010001011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1131 10110100000000010010011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 1132 10110100000000010011101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1133 10110100000000010000101010100101 fail ^ step 1134 10111111000000010000101010100101 step 1135 10111111000000010001011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1136 10110110000000010010011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 1137 10110110000000010011101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1138 10110110000000010000101010101001 fail ^ step 1139 10111011000000010000101010101001 step 1140 10111011000000010001011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1141 10110010000000010010011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 011001 step 1142 10110010000000010011101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1143 10110010000000010000101010011001 fail ^ step 1144 10111001000000010000101010011001 step 1145 10111001000000010001011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1146 10110000000000010010011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 1147 10110000000000010011101010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1148 10110000000000010000101010010101 fail ^ step 1149 10101001000000010000101010010101 step 1150 10101001000000010001011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1151 10100000000000010010011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 step 1152 10100000000000010011100110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1153 10100000000000010000100110010101 fail ^ step 1154 10101011000000010000100110010101 step 1155 10101011000000010001011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1156 10100010000000010010011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110011001 step 1157 10100010000000010011100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1158 10100010000000010000100110011001 fail ^ step 1159 10101111000000010000100110011001 step 1160 10101111000000010001011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1161 10100110000000010010011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 01 step 1162 10100110000000010011100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1163 10100110000000010000100110101001 fail ^ step 1164 10101101000000010000100110101001 step 1165 10101101000000010001011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1166 10100100000000010010011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 01 step 1167 10100100000000010011100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1168 10100100000000010000100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1169 10100100000000010000100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 0101 step 1170 10100100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1171 10100100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1172 10100100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1173 10100100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1174 10100110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1175 10100110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1176 10100110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1177 10100110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1178 10100110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1179 10100010000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1180 10100010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1181 10100010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1182 10100010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1183 10100010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1184 10100000000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1185 10100000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1186 10100000000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1187 10100000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1188 10100000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1189 11100000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1190 11100000000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1191 11100000000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1192 11100000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1193 11100000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1194 11100010000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1195 11100010000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1196 11100010000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1197 11100010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1198 11100010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1199 11100110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1200 11100110000000010001010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1201 11100110000000010010010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1202 11100110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1203 11100110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1204 11100100000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1205 11100100000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1206 11100100000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1207 11100100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1208 11100100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1209 11101101000000010000010101010101 fail ^^ ^^ step 1210 11101101000000010001101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1211 11100100000000010010101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 01 step 1212 11100100000000010011100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1213 11100100000000010000100110100101 fail ^ step 1214 11101111000000010000100110100101 step 1215 11101111000000010001101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1216 11100110000000010010101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 01 step 1217 11100110000000010011100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1218 11100110000000010000100110101001 fail ^ step 1219 11101011000000010000100110101001 step 1220 11101011000000010001101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1221 11100010000000010010101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110011001 step 1222 11100010000000010011100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1223 11100010000000010000100110011001 fail ^ step 1224 11101001000000010000100110011001 step 1225 11101001000000010001101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1226 11100000000000010010101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 1227 11100000000000010011100110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1228 11100000000000010000100110010101 fail ^ step 1229 11111001000000010000100110010101 step 1230 11111001000000010001101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1231 11110000000000010010101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1232 11110000000000010011101010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1233 11110000000000010000101010010101 fail ^ step 1234 11111011000000010000101010010101 step 1235 11111011000000010001101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1236 11110010000000010010101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 1237 11110010000000010011101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1238 11110010000000010000101010011001 fail ^ step 1239 11111111000000010000101010011001 step 1240 11111111000000010001101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1241 11110110000000010010101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1242 11110110000000010011101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1243 11110110000000010000101010101001 fail ^ step 1244 11111101000000010000101010101001 step 1245 11111101000000010001101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1246 11110100000000010010101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1247 11110100000000010011101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1248 11110100000000010000101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1249 11110100000000010000101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101010101 step 1250 11110100000000010001010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1251 11110100000000010010010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1252 11110100000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1253 11110100000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1254 11110110000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1255 11110110000000010001010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1256 11110110000000010010010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1257 11110110000000010011010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1258 11110110000000010000010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1259 11110010000000010000010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1260 11110010000000010001010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1261 11110010000000010010010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1262 11110010000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1263 11110010000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1264 11110000000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1265 11110000000000010001010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1266 11110000000000010010010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1267 11110000000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1268 11110000000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1269 11010000000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1270 11010000000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1271 11010000000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1272 11010000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1273 11010000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1274 11010010000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1275 11010010000000010001010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1276 11010010000000010010010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1277 11010010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1278 11010010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1279 11010110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1280 11010110000000010001010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1281 11010110000000010010010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1282 11010110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1283 11010110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1284 11010100000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1285 11010100000000010001010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1286 11010100000000010010010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1287 11010100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1288 11010100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1289 11011101000000010000010101010101 fail ^^ ^^ step 1290 11011101000000010001100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1291 11010100000000010010100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 1292 11010100000000010011011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1293 11010100000000010000011010100101 fail ^ step 1294 11011111000000010000011010100101 step 1295 11011111000000010001100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1296 11010110000000010010100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 1297 11010110000000010011011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1298 11010110000000010000011010101001 fail ^ step 1299 11011011000000010000011010101001 step 1300 11011011000000010001100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1301 11010010000000010010100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 011001 step 1302 11010010000000010011011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1303 11010010000000010000011010011001 fail ^ step 1304 11011001000000010000011010011001 step 1305 11011001000000010001100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1306 11010000000000010010100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 1307 11010000000000010011011010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1308 11010000000000010000011010010101 fail ^ step 1309 11001001000000010000011010010101 step 1310 11001001000000010001100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1311 11000000000000010010100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 step 1312 11000000000000010011010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1313 11000000000000010000010110010101 fail ^ step 1314 11001011000000010000010110010101 step 1315 11001011000000010001100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1316 11000010000000010010100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10011001 step 1317 11000010000000010011010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1318 11000010000000010000010110011001 fail ^ step 1319 11001111000000010000010110011001 step 1320 11001111000000010001100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1321 11000110000000010010100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 01 step 1322 11000110000000010011010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1323 11000110000000010000010110101001 fail ^ step 1324 11001101000000010000010110101001 step 1325 11001101000000010001100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1326 11000100000000010010100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 01 step 1327 11000100000000010011010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1328 11000100000000010000010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1329 11000100000000010000010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0101 step 1330 11000100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1331 11000100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1332 11000100000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1333 11000100000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1334 11000110000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1335 11000110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1336 11000110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1337 11000110000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1338 11000110000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1339 11000010000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1340 11000010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1341 11000010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1342 11000010000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1343 11000010000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1344 11000000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1345 11000000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1346 11000000000000010010010101010101 fail ^^ step 1347 11000000000000010011010101010101 step 1348 11000000000000010000010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1349 10000000000000010000010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1350 10000000000000010001010101010101 fail ^ step 1351 10000000000000010010010101010101 step 1352 10000000000000010011010101010101 step 1353 10000000000000010000010101010101 step 1354 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1355 10000010000000010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1356 10000010000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1357 10000010000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1358 10000010000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1359 10000010000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1360 10000110000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1361 10000110000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1362 10000110000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1363 10000110000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1364 10000110000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1365 10000100000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1366 10000100000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1367 10000100000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1368 10000100000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1369 10000100000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1370 10001101000000010100010101010110 fail ^^ step 1371 10001101000000010101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1372 10000100000000010110010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 1373 10000100000000010111010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1374 10000100000000010100010110100110 fail ^ step 1375 10001111000000010100010110100110 step 1376 10001111000000010101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1377 10000110000000010110010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1378 10000110000000010111010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1379 10000110000000010100010110101010 fail ^ step 1380 10001011000000010100010110101010 step 1381 10001011000000010101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1382 10000010000000010110010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 100110 step 1383 10000010000000010111010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1384 10000010000000010100010110011010 fail ^ step 1385 10001001000000010100010110011010 step 1386 10001001000000010101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1387 10000000000000010110010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 1388 10000000000000010111010110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1389 10000000000000010100010110010110 fail ^ step 1390 10011001000000010100010110010110 step 1391 10011001000000010101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1392 10010000000000010110010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 10 step 1393 10010000000000010111011010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1394 10010000000000010100011010010110 fail ^ step 1395 10011011000000010100011010010110 step 1396 10011011000000010101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1397 10010010000000010110010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 1398 10010010000000010111011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1399 10010010000000010100011010011010 fail ^ step 1400 10011111000000010100011010011010 step 1401 10011111000000010101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1402 10010110000000010110010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1403 10010110000000010111011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1404 10010110000000010100011010101010 fail ^ step 1405 10011101000000010100011010101010 step 1406 10011101000000010101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1407 10010100000000010110010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 1408 10010100000000010111011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1409 10010100000000010100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1410 10010100000000010100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 010101 01 step 1411 10010100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1412 10010100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1413 10010100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1414 10010100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1415 10010110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1416 10010110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1417 10010110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1418 10010110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1419 10010110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1420 10010010000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1421 10010010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1422 10010010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1423 10010010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1424 10010010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1425 10010000000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1426 10010000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1427 10010000000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1428 10010000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1429 10010000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1430 10110000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1431 10110000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1432 10110000000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1433 10110000000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1434 10110000000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1435 10110010000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1436 10110010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1437 10110010000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1438 10110010000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1439 10110010000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1440 10110110000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1441 10110110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1442 10110110000000010110010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1443 10110110000000010111010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1444 10110110000000010100010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1445 10110100000000010100010101010110 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1446 10110100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1447 10110100000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1448 10110100000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1449 10110100000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1450 10111101000000010100010101010110 fail ^^^^ ^^ step 1451 10111101000000010101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1452 10110100000000010110011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 0110 step 1453 10110100000000010111101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1454 10110100000000010100101010100110 fail ^ step 1455 10111111000000010100101010100110 step 1456 10111111000000010101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1457 10110110000000010110011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1458 10110110000000010111101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1459 10110110000000010100101010101010 fail ^ step 1460 10111011000000010100101010101010 step 1461 10111011000000010101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1462 10110010000000010110011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 0110 step 1463 10110010000000010111101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1464 10110010000000010100101010011010 fail ^ step 1465 10111001000000010100101010011010 step 1466 10111001000000010101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1467 10110000000000010110011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 1468 10110000000000010111101010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1469 10110000000000010100101010010110 fail ^ step 1470 10101001000000010100101010010110 step 1471 10101001000000010101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1472 10100000000000010110011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 10 step 1473 10100000000000010111100110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1474 10100000000000010100100110010110 fail ^ step 1475 10101011000000010100100110010110 step 1476 10101011000000010101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1477 10100010000000010110011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001100110 step 1478 10100010000000010111100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1479 10100010000000010100100110011010 fail ^ step 1480 10101111000000010100100110011010 step 1481 10101111000000010101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1482 10100110000000010110011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 1483 10100110000000010111100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1484 10100110000000010100100110101010 fail ^ step 1485 10101101000000010100100110101010 step 1486 10101101000000010101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1487 10100100000000010110011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 0110 step 1488 10100100000000010111100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1489 10100100000000010100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1490 10100100000000010100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 0101 01 step 1491 10100100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1492 10100100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1493 10100100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1494 10100100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1495 10100110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1496 10100110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1497 10100110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1498 10100110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1499 10100110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1500 10100010000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1501 10100010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1502 10100010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1503 10100010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1504 10100010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1505 10100000000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1506 10100000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1507 10100000000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1508 10100000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1509 10100000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1510 11100000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1511 11100000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1512 11100000000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1513 11100000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1514 11100000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1515 11100010000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1516 11100010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1517 11100010000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1518 11100010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1519 11100010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1520 11100110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1521 11100110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1522 11100110000000010110010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1523 11100110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1524 11100110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1525 11100100000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1526 11100100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1527 11100100000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1528 11100100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1529 11100100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1530 11101101000000010100010101010110 fail ^^ ^^ step 1531 11101101000000010101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1532 11100100000000010110101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 0110 step 1533 11100100000000010111100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1534 11100100000000010100100110100110 fail ^ step 1535 11101111000000010100100110100110 step 1536 11101111000000010101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1537 11100110000000010110101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1538 11100110000000010111100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1539 11100110000000010100100110101010 fail ^ step 1540 11101011000000010100100110101010 step 1541 11101011000000010101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1542 11100010000000010110101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01100110 step 1543 11100010000000010111100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1544 11100010000000010100100110011010 fail ^ step 1545 11101001000000010100100110011010 step 1546 11101001000000010101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1547 11100000000000010110101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 10 step 1548 11100000000000010111100110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1549 11100000000000010100100110010110 fail ^ step 1550 11111001000000010100100110010110 step 1551 11111001000000010101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1552 11110000000000010110101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 1553 11110000000000010111101010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1554 11110000000000010100101010010110 fail ^ step 1555 11111011000000010100101010010110 step 1556 11111011000000010101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1557 11110010000000010110101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1558 11110010000000010111101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1559 11110010000000010100101010011010 fail ^ step 1560 11111111000000010100101010011010 step 1561 11111111000000010101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1562 11110110000000010110101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1563 11110110000000010111101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1564 11110110000000010100101010101010 fail ^ step 1565 11111101000000010100101010101010 step 1566 11111101000000010101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1567 11110100000000010110101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1568 11110100000000010111101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1569 11110100000000010100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1570 11110100000000010100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101010101 01 step 1571 11110100000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1572 11110100000000010110010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1573 11110100000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1574 11110100000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1575 11110110000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1576 11110110000000010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1577 11110110000000010110010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1578 11110110000000010111010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1579 11110110000000010100010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1580 11110010000000010100010101010110 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1581 11110010000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1582 11110010000000010110010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1583 11110010000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1584 11110010000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1585 11110000000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1586 11110000000000010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1587 11110000000000010110010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1588 11110000000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1589 11110000000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1590 11010000000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1591 11010000000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1592 11010000000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1593 11010000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1594 11010000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1595 11010010000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1596 11010010000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1597 11010010000000010110010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1598 11010010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1599 11010010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1600 11010110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1601 11010110000000010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1602 11010110000000010110010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1603 11010110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1604 11010110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1605 11010100000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1606 11010100000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1607 11010100000000010110010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1608 11010100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1609 11010100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1610 11011101000000010100010101010110 fail ^^ ^^ step 1611 11011101000000010101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1612 11010100000000010110100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 0110 step 1613 11010100000000010111011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1614 11010100000000010100011010100110 fail ^ step 1615 11011111000000010100011010100110 step 1616 11011111000000010101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1617 11010110000000010110100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 1618 11010110000000010111011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1619 11010110000000010100011010101010 fail ^ step 1620 11011011000000010100011010101010 step 1621 11011011000000010101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1622 11010010000000010110100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 0110 step 1623 11010010000000010111011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1624 11010010000000010100011010011010 fail ^ step 1625 11011001000000010100011010011010 step 1626 11011001000000010101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1627 11010000000000010110100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 10 step 1628 11010000000000010111011010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1629 11010000000000010100011010010110 fail ^ step 1630 11001001000000010100011010010110 step 1631 11001001000000010101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1632 11000000000000010110100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 10 step 1633 11000000000000010111010110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1634 11000000000000010100010110010110 fail ^ step 1635 11001011000000010100010110010110 step 1636 11001011000000010101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1637 11000010000000010110100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 100110 step 1638 11000010000000010111010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1639 11000010000000010100010110011010 fail ^ step 1640 11001111000000010100010110011010 step 1641 11001111000000010101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1642 11000110000000010110100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 1643 11000110000000010111010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1644 11000110000000010100010110101010 fail ^ step 1645 11001101000000010100010110101010 step 1646 11001101000000010101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1647 11000100000000010110100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 0110 step 1648 11000100000000010111010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1649 11000100000000010100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1650 11000100000000010100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0101 01 step 1651 11000100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1652 11000100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1653 11000100000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1654 11000100000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1655 11000110000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1656 11000110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1657 11000110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1658 11000110000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1659 11000110000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1660 11000010000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1661 11000010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1662 11000010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1663 11000010000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1664 11000010000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1665 11000000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1666 11000000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1667 11000000000000010110010101010101 fail ^^ step 1668 11000000000000010111010101010110 step 1669 11000000000000010100010101010110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1670 10000000000000010100010101010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1671 10000000000000010101010101010101 fail ^ step 1672 10000000000000010110010101010101 step 1673 10000000000000010111010101010110 step 1674 10000000000000010100010101010110 step 1675 00000000000000010100010101010101 step 1676 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 111 11 111111 step 1677 11110110111111010100010101010101 fail ^ test 4: *** FAIL *************************** 1123 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail I I OOOOOOOOOOOO all fails I I OOOOOOOOOOOO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 4, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1 01110110111111010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 2 11110110111111010100010101010101 fail ^ step 3 11111111111111010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00000 0 step 4 10000010111111010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 5 10000010111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 6 10000010111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 7 10000110111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 8 10000110111111010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 9 10000110111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 10 10000100111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 11 10000100111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 12 10000100111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 13 10001101111111010100010101010101 fail ^^ step 14 10001101111111010101010101101001 step 15 10001101111111010100010101101001 step 16 10001111111111010100010101101001 step 17 10001111111111010101010101101010 step 18 10001111111111010100010101101010 step 19 10001011111111010100010101101010 step 20 10001011111111010101010101100110 step 21 10001011111111010100010101100110 step 22 10001001111111010100010101100110 step 23 10001001111111010101010101100101 step 24 10001001111111010100010101100101 step 25 10011001111111010100010101100101 step 26 10011001111111010101010110100101 step 27 10011001111111010100010110100101 step 28 10011011111111010100010110100101 step 29 10011011111111010101010110100110 step 30 10011011111111010100010110100110 step 31 10011111111111010100010110100110 step 32 10011111111111010101010110101010 step 33 10011111111111010100010110101010 step 34 10011101111111010100010110101010 step 35 10011101111111010101010110101001 step 36 10011101111111010100010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 37 10010100111111010100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 010101 step 38 10010100111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 39 10010100111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 40 10010110111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 41 10010110111111010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 42 10010110111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 43 10010010111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 44 10010010111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 45 10010010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 46 10010000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 47 10010000111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 48 10010000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 49 10110000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 50 10110000111111010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 51 10110000111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 52 10110010111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 53 10110010111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 54 10110010111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 55 10110110111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 56 10110110111111010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 57 10110110111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 58 10110100111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 59 10110100111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 60 10110100111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 61 10111101111111010100010101010101 fail ^^^^ ^^ step 62 10111101111111010101011010101001 step 63 10111101111111010100011010101001 step 64 10111111111111010100011010101001 step 65 10111111111111010101011010101010 step 66 10111111111111010100011010101010 step 67 10111011111111010100011010101010 step 68 10111011111111010101011010100110 step 69 10111011111111010100011010100110 step 70 10111001111111010100011010100110 step 71 10111001111111010101011010100101 step 72 10111001111111010100011010100101 step 73 10101001111111010100011010100101 step 74 10101001111111010101011001100101 step 75 10101001111111010100011001100101 step 76 10101011111111010100011001100101 step 77 10101011111111010101011001100110 step 78 10101011111111010100011001100110 step 79 10101111111111010100011001100110 step 80 10101111111111010101011001101010 step 81 10101111111111010100011001101010 step 82 10101101111111010100011001101010 step 83 10101101111111010101011001101001 step 84 10101101111111010100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 85 10100100111111010100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 0101 step 86 10100100111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 87 10100100111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 88 10100110111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 89 10100110111111010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 90 10100110111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 91 10100010111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 92 10100010111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 93 10100010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 94 10100000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 95 10100000111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 96 10100000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 97 11100000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 98 11100000111111010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 99 11100000111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 100 11100010111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 101 11100010111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 102 11100010111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 103 11100110111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 104 11100110111111010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 105 11100110111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 106 11100100111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 107 11100100111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 108 11100100111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 109 11101101111111010100010101010101 fail ^^^^ ^^ step 110 11101101111111010101101001101001 step 111 11101101111111010100101001101001 step 112 11101111111111010100101001101001 step 113 11101111111111010101101001101010 step 114 11101111111111010100101001101010 step 115 11101011111111010100101001101010 step 116 11101011111111010101101001100110 step 117 11101011111111010100101001100110 step 118 11101001111111010100101001100110 step 119 11101001111111010101101001100101 step 120 11101001111111010100101001100101 step 121 11111001111111010100101001100101 step 122 11111001111111010101101010100101 step 123 11111001111111010100101010100101 step 124 11111011111111010100101010100101 step 125 11111011111111010101101010100110 step 126 11111011111111010100101010100110 step 127 11111111111111010100101010100110 step 128 11111111111111010101101010101010 step 129 11111111111111010100101010101010 step 130 11111101111111010100101010101010 step 131 11111101111111010101101010101001 step 132 11111101111111010100101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 133 11110100111111010100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10101010101 step 134 11110100111111010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 135 11110100111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 136 11110110111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 137 11110110111111010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 138 11110110111111010100010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 139 11110010111111010100010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 140 11110010111111010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 141 11110010111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 142 11110000111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 143 11110000111111010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 144 11110000111111010100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 145 11010000111111010100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 146 11010000111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 147 11010000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 148 11010010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 149 11010010111111010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 150 11010010111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 151 11010110111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 152 11010110111111010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 153 11010110111111010100010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 154 11010100111111010100010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 155 11010100111111010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 156 11010100111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 157 11011101111111010100010101010101 fail ^^ ^^ ^^ step 158 11011101111111010101100110101001 step 159 11011101111111010100100110101001 step 160 11011111111111010100100110101001 step 161 11011111111111010101100110101010 step 162 11011111111111010100100110101010 step 163 11011011111111010100100110101010 step 164 11011011111111010101100110100110 step 165 11011011111111010100100110100110 step 166 11011001111111010100100110100110 step 167 11011001111111010101100110100101 step 168 11011001111111010100100110100101 step 169 11001001111111010100100110100101 step 170 11001001111111010101100101100101 step 171 11001001111111010100100101100101 step 172 11001011111111010100100101100101 step 173 11001011111111010101100101100110 step 174 11001011111111010100100101100110 step 175 11001111111111010100100101100110 step 176 11001111111111010101100101101010 step 177 11001111111111010100100101101010 step 178 11001101111111010100100101101010 step 179 11001101111111010101100101101001 step 180 11001101111111010100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 181 11000100111111010100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 0101 step 182 11000100111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 183 11000100111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 184 11000110111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 185 11000110111111010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 186 11000110111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 187 11000010111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 188 11000010111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 189 11000010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 190 11000000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 191 11000000111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 192 11000000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 193 10000000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 194 10000000111111010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 195 10000000111111010100010101010101 fail ^ step 196 10000000111111010100010101010101 step 197 10000000111111110100010101010101 step 198 10000000000001110100010101010101 step 199 10000000000001110101010101010110 step 200 10000000000001110100010101010110 step 201 10000000000011110100010101010110 step 202 10000000000011110101010101011010 step 203 10000000000011110100010101011010 step 204 10000000000010110100010101011010 step 205 10000000000010110101010101011001 step 206 10000000000010110100010101011001 step 207 10000000000110110100010101011001 step 208 10000000000110110101010101101001 step 209 10000000000110110100010101101001 step 210 10000000000111110100010101101001 step 211 10000000000111110101010101101010 step 212 10000000000111110100010101101010 step 213 10000000000101110100010101101010 step 214 10000000000101110101010101100110 step 215 10000000000101110100010101100110 step 216 10000000000100110100010101100110 step 217 10000000000100110101010101100101 step 218 10000000000100110100010101100101 step 219 10000000001100110100010101100101 step 220 10000000001100110101010110100101 step 221 10000000001100110100010110100101 step 222 10000000001101110100010110100101 step 223 10000000001101110101010110100110 step 224 10000000001101110100010110100110 step 225 10000000001111110100010110100110 step 226 10000000001111110101010110101010 step 227 10000000001111110100010110101010 step 228 10000000001110110100010110101010 step 229 10000000001110110101010110101001 step 230 10000000001110110100010110101001 step 231 10000000001010110100010110101001 step 232 10000000001010110101010110011001 step 233 10000000001010110100010110011001 step 234 10000000001011110100010110011001 step 235 10000000001011110101010110011010 step 236 10000000001011110100010110011010 step 237 10000000001001110100010110011010 step 238 10000000001001110101010110010110 step 239 10000000001001110100010110010110 step 240 10000000001000110100010110010110 step 241 10000000001000110101010110010101 step 242 10000000001000110100010110010101 step 243 10000000011000110100010110010101 step 244 10000000011000110101011010010101 step 245 10000000011000110100011010010101 step 246 10000000011001110100011010010101 step 247 10000000011001110101011010010110 step 248 10000000011001110100011010010110 step 249 10000000011011110100011010010110 step 250 10000000011011110101011010011010 step 251 10000000011011110100011010011010 step 252 10000000011010110100011010011010 step 253 10000000011010110101011010011001 step 254 10000000011010110100011010011001 step 255 10000000011110110100011010011001 step 256 10000000011110110101011010101001 step 257 10000000011110110100011010101001 step 258 10000000011111110100011010101001 step 259 10000000011111110101011010101010 step 260 10000000011111110100011010101010 step 261 10000000011101110100011010101010 step 262 10000000011101110101011010100110 step 263 10000000011101110100011010100110 step 264 10000000011100110100011010100110 step 265 10000000011100110101011010100101 step 266 10000000011100110100011010100101 step 267 10000000010100110100011010100101 step 268 10000000010100110101011001100101 step 269 10000000010100110100011001100101 step 270 10000000010101110100011001100101 step 271 10000000010101110101011001100110 step 272 10000000010101110100011001100110 step 273 10000000010111110100011001100110 step 274 10000000010111110101011001101010 step 275 10000000010111110100011001101010 step 276 10000000010110110100011001101010 step 277 10000000010110110101011001101001 step 278 10000000010110110100011001101001 step 279 10000000010010110100011001101001 step 280 10000000010010110101011001011001 step 281 10000000010010110100011001011001 step 282 10000000010011110100011001011001 step 283 10000000010011110101011001011010 step 284 10000000010011110100011001011010 step 285 10000000010001110100011001011010 step 286 10000000010001110101011001010110 step 287 10000000010001110100011001010110 step 288 10000000010000110100011001010110 step 289 10000000010000110101011001010101 step 290 10000000010000110100011001010101 step 291 10000000110000110100011001010101 step 292 10000000110000110101101001010101 step 293 10000000110000110100101001010101 step 294 10000000110001110100101001010101 step 295 10000000110001110101101001010110 step 296 10000000110001110100101001010110 step 297 10000000110011110100101001010110 step 298 10000000110011110101101001011010 step 299 10000000110011110100101001011010 step 300 10000000110010110100101001011010 step 301 10000000110010110101101001011001 step 302 10000000110010110100101001011001 step 303 10000000110110110100101001011001 step 304 10000000110110110101101001101001 step 305 10000000110110110100101001101001 step 306 10000000110111110100101001101001 step 307 10000000110111110101101001101010 step 308 10000000110111110100101001101010 step 309 10000000110101110100101001101010 step 310 10000000110101110101101001100110 step 311 10000000110101110100101001100110 step 312 10000000110100110100101001100110 step 313 10000000110100110101101001100101 step 314 10000000110100110100101001100101 step 315 10000000111100110100101001100101 step 316 10000000111100110101101010100101 step 317 10000000111100110100101010100101 step 318 10000000111101110100101010100101 step 319 10000000111101110101101010100110 step 320 10000000111101110100101010100110 step 321 10000000111111110100101010100110 step 322 10000000111111110101101010101010 step 323 10000000111111110100101010101010 step 324 10000000111110110100101010101010 step 325 10000000111110110101101010101001 step 326 10000000111110110100101010101001 step 327 10000000111010110100101010101001 step 328 10000000111010110101101010011001 step 329 10000000111010110100101010011001 step 330 10000000111011110100101010011001 step 331 10000000111011110101101010011010 step 332 10000000111011110100101010011010 step 333 10000000111001110100101010011010 step 334 10000000111001110101101010010110 step 335 10000000111001110100101010010110 step 336 10000000111000110100101010010110 step 337 10000000111000110101101010010101 step 338 10000000111000110100101010010101 step 339 10000000101000110100101010010101 step 340 10000000101000110101100110010101 step 341 10000000101000110100100110010101 step 342 10000000101001110100100110010101 step 343 10000000101001110101100110010110 step 344 10000000101001110100100110010110 step 345 10000000101011110100100110010110 step 346 10000000101011110101100110011010 step 347 10000000101011110100100110011010 step 348 10000000101010110100100110011010 step 349 10000000101010110101100110011001 step 350 10000000101010110100100110011001 step 351 10000000101110110100100110011001 step 352 10000000101110110101100110101001 step 353 10000000101110110100100110101001 step 354 10000000101111110100100110101001 step 355 10000000101111110101100110101010 step 356 10000000101111110100100110101010 step 357 10000000101101110100100110101010 step 358 10000000101101110101100110100110 step 359 10000000101101110100100110100110 step 360 10000000101100110100100110100110 step 361 10000000101100110101100110100101 step 362 10000000101100110100100110100101 step 363 10000000100100110100100110100101 step 364 10000000100100110101100101100101 step 365 10000000100100110100100101100101 step 366 10000000100101110100100101100101 step 367 10000000100101110101100101100110 step 368 10000000100101110100100101100110 step 369 10000000100111110100100101100110 step 370 10000000100111110101100101101010 step 371 10000000100111110100100101101010 step 372 10000000100110110100100101101010 step 373 10000000100110110101100101101001 step 374 10000000100110110100100101101001 step 375 10000000100010110100100101101001 step 376 10000000100010110101100101011001 step 377 10000000100010110100100101011001 step 378 10000000100011110100100101011001 step 379 10000000100011110101100101011010 step 380 10000000100011110100100101011010 step 381 10000000100001110100100101011010 step 382 10000000100001110101100101010110 step 383 10000000100001110100100101010110 step 384 10000000100000110100100101010110 step 385 10000000100000110101100101010101 step 386 10000000100000110100100101010101 step 387 10000000000000110100100101010101 step 388 10000000000000110101010101010101 step 389 10000000000000110100010101010101 step 390 10000000000000010100010101010101 step 391 10000000000000000100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 392 10000010000000000100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 393 10000010000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 394 10000010000000001100010101010101 fail ^^ step 395 10000010000000001101010101010101 step 396 10000010000000000100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 397 10000110000000000100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 398 10000110000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 399 10000110000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 400 10000110000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 401 10000110000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 402 10000100000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 403 10000100000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 404 10000100000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 405 10000100000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 406 10000100000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 407 10001101000000000100010101010101 fail ^^ step 408 10001101000000000101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 409 10000100000000001100010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 410 10000100000000001101010101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 411 10000100000000000100010101011010 fail ^ step 412 10001111000000000100010101011010 step 413 10001111000000000101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 414 10000110000000001100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 415 10000110000000001101010101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 416 10000110000000000100010101011010 fail ^ step 417 10001011000000000100010101011010 step 418 10001011000000000101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 419 10000010000000001100010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 420 10000010000000001101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 421 10000010000000000100010101011001 fail ^ step 422 10001001000000000100010101011001 step 423 10001001000000000101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 424 10000000000000001100010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 425 10000000000000001101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 426 10000000000000000100010101011001 fail ^ step 427 10011001000000000100010101011001 step 428 10011001000000000101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 429 10010000000000001100010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 430 10010000000000001101010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 431 10010000000000000100010101101001 fail ^ step 432 10011011000000000100010101101001 step 433 10011011000000000101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 434 10010010000000001100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 1001 step 435 10010010000000001101010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 436 10010010000000000100010101101001 fail ^ step 437 10011111000000000100010101101001 step 438 10011111000000000101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 439 10010110000000001100010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 440 10010110000000001101010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 441 10010110000000000100010101101010 fail ^ step 442 10011101000000000100010101101010 step 443 10011101000000000101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 444 10010100000000001100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 445 10010100000000001101010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 446 10010100000000000100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 447 10010100000000000100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 010101 step 448 10010100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 449 10010100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 450 10010100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 451 10010100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 452 10010110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 453 10010110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 454 10010110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 455 10010110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 456 10010110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 457 10010010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 458 10010010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 459 10010010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 460 10010010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 461 10010010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 462 10010000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 463 10010000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 464 10010000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 465 10010000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 466 10010000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 467 10110000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 468 10110000000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 469 10110000000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 470 10110000000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 471 10110000000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 472 10110010000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 473 10110010000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 474 10110010000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 475 10110010000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 476 10110010000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 477 10110110000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 478 10110110000000000101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 479 10110110000000001100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 480 10110110000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 481 10110110000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 482 10110100000000000100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 483 10110100000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 484 10110100000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 485 10110100000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 486 10110100000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 487 10111101000000000100010101010101 fail ^^^^ ^^ step 488 10111101000000000101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 489 10110100000000001100011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 490 10110100000000001101010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 491 10110100000000000100010110101010 fail ^ step 492 10111111000000000100010110101010 step 493 10111111000000000101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 494 10110110000000001100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 495 10110110000000001101010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 496 10110110000000000100010110101010 fail ^ step 497 10111011000000000100010110101010 step 498 10111011000000000101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 499 10110010000000001100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 1001 step 500 10110010000000001101010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 501 10110010000000000100010110101001 fail ^ step 502 10111001000000000100010110101001 step 503 10111001000000000101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 504 10110000000000001100011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 505 10110000000000001101010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 506 10110000000000000100010110101001 fail ^ step 507 10101001000000000100010110101001 step 508 10101001000000000101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 509 10100000000000001100011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01100110 step 510 10100000000000001101010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 511 10100000000000000100010110011001 fail ^ step 512 10101011000000000100010110011001 step 513 10101011000000000101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 514 10100010000000001100011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110011001 step 515 10100010000000001101010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 516 10100010000000000100010110011001 fail ^ step 517 10101111000000000100010110011001 step 518 10101111000000000101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 519 10100110000000001100011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 520 10100110000000001101010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 521 10100110000000000100010110011010 fail ^ step 522 10101101000000000100010110011010 step 523 10101101000000000101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 524 10100100000000001100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 10 step 525 10100100000000001101010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 526 10100100000000000100010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 527 10100100000000000100010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 0101 step 528 10100100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 529 10100100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 530 10100100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 531 10100100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 532 10100110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 533 10100110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 534 10100110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 535 10100110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 536 10100110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 537 10100010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 538 10100010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 539 10100010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 540 10100010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 541 10100010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 542 10100000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 543 10100000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 544 10100000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 545 10100000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 546 10100000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 547 11100000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 548 11100000000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 549 11100000000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 550 11100000000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 551 11100000000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 552 11100010000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 553 11100010000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 554 11100010000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 555 11100010000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 556 11100010000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 557 11100110000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 558 11100110000000000101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 559 11100110000000001100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 560 11100110000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 561 11100110000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 562 11100100000000000100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 563 11100100000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 564 11100100000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 565 11100100000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 566 11100100000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 567 11101101000000000100010101010101 fail ^^^^ ^^ step 568 11101101000000000101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 569 11100100000000001100101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 10 step 570 11100100000000001101011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 571 11100100000000000100011010011010 fail ^ step 572 11101111000000000100011010011010 step 573 11101111000000000101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 574 11100110000000001100101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 step 575 11100110000000001101011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 576 11100110000000000100011010011010 fail ^ step 577 11101011000000000100011010011010 step 578 11101011000000000101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 579 11100010000000001100101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10011001 step 580 11100010000000001101011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 581 11100010000000000100011010011001 fail ^ step 582 11101001000000000100011010011001 step 583 11101001000000000101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 584 11100000000000001100101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 100110 step 585 11100000000000001101011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 586 11100000000000000100011010011001 fail ^ step 587 11111001000000000100011010011001 step 588 11111001000000000101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 589 11110000000000001100101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 590 11110000000000001101011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 591 11110000000000000100011010101001 fail ^ step 592 11111011000000000100011010101001 step 593 11111011000000000101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 594 11110010000000001100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 step 595 11110010000000001101011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 596 11110010000000000100011010101001 fail ^ step 597 11111111000000000100011010101001 step 598 11111111000000000101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 599 11110110000000001100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 600 11110110000000001101011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 601 11110110000000000100011010101010 fail ^ step 602 11111101000000000100011010101010 step 603 11111101000000000101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 604 11110100000000001100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 605 11110100000000001101011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 606 11110100000000000100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 607 11110100000000000100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0101010101 step 608 11110100000000000101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 609 11110100000000001100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 610 11110100000000001101010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 611 11110100000000000100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 612 11110110000000000100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 613 11110110000000000101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 614 11110110000000001100010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 615 11110110000000001101010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 616 11110110000000000100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 617 11110010000000000100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 618 11110010000000000101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 619 11110010000000001100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 620 11110010000000001101010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 621 11110010000000000100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 622 11110000000000000100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 623 11110000000000000101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 624 11110000000000001100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 625 11110000000000001101010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 626 11110000000000000100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 627 11010000000000000100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 628 11010000000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 629 11010000000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 630 11010000000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 631 11010000000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 632 11010010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 633 11010010000000000101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 634 11010010000000001100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 635 11010010000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 636 11010010000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 637 11010110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 638 11010110000000000101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 639 11010110000000001100010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 640 11010110000000001101010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 641 11010110000000000100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 642 11010100000000000100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 643 11010100000000000101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 644 11010100000000001100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 645 11010100000000001101010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 646 11010100000000000100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 647 11011101000000000100010101010101 fail ^^ ^^ ^^ step 648 11011101000000000101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 649 11010100000000001100100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 10 step 650 11010100000000001101011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 651 11010100000000000100011001101010 fail ^ step 652 11011111000000000100011001101010 step 653 11011111000000000101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 654 11010110000000001100100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 step 655 11010110000000001101011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 656 11010110000000000100011001101010 fail ^ step 657 11011011000000000100011001101010 step 658 11011011000000000101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 659 11010010000000001100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 1001 step 660 11010010000000001101011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 661 11010010000000000100011001101001 fail ^ step 662 11011001000000000100011001101001 step 663 11011001000000000101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 664 11010000000000001100100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1011001 10 step 665 11010000000000001101011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 666 11010000000000000100011001101001 fail ^ step 667 11001001000000000100011001101001 step 668 11001001000000000101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 669 11000000000000001100100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 0110 step 670 11000000000000001101011001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 671 11000000000000000100011001011001 fail ^ step 672 11001011000000000100011001011001 step 673 11001011000000000101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 674 11000010000000001100100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 011001 step 675 11000010000000001101011001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 676 11000010000000000100011001011001 fail ^ step 677 11001111000000000100011001011001 step 678 11001111000000000101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 679 11000110000000001100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 680 11000110000000001101011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 681 11000110000000000100011001011010 fail ^ step 682 11001101000000000100011001011010 step 683 11001101000000000101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 684 11000100000000001100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 10 step 685 11000100000000001101011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 686 11000100000000000100011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 687 11000100000000000100011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 0101 step 688 11000100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 689 11000100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 690 11000100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 691 11000100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 692 11000110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 693 11000110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 694 11000110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 695 11000110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 696 11000110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 697 11000010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 698 11000010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 699 11000010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 700 11000010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 701 11000010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 702 11000000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 703 11000000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 704 11000000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 705 11000000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 706 11000000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 707 10000000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 708 10000000000000000101010101010101 fail ^ step 709 10000000000000001100010101010101 step 710 10000000000000001101010101010101 step 711 10000000000000000100010101010101 step 712 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 713 10000010000000010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 714 10000010000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 715 10000010000000011100010101010101 fail ^^ step 716 10000010000000011101100101010101 step 717 10000010000000010100100101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 718 10000110000000010100100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 719 10000110000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 720 10000110000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 721 10000110000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 722 10000110000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 723 10000100000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 724 10000100000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 725 10000100000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 726 10000100000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 727 10000100000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 728 10001101000000010100100101010101 fail ^^ step 729 10001101000000010101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 730 10000100000000011100010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 731 10000100000000011101100101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 732 10000100000000010100100101011010 fail ^ step 733 10001111000000010100100101011010 step 734 10001111000000010101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 735 10000110000000011100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 736 10000110000000011101100101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 737 10000110000000010100100101011010 fail ^ step 738 10001011000000010100100101011010 step 739 10001011000000010101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 740 10000010000000011100010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 011001 step 741 10000010000000011101100101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 742 10000010000000010100100101011001 fail ^ step 743 10001001000000010100100101011001 step 744 10001001000000010101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 745 10000000000000011100010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 0110 step 746 10000000000000011101100101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 747 10000000000000010100100101011001 fail ^ step 748 10011001000000010100100101011001 step 749 10011001000000010101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 750 10010000000000011100010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 751 10010000000000011101100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 752 10010000000000010100100101101001 fail ^ step 753 10011011000000010100100101101001 step 754 10011011000000010101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 755 10010010000000011100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 1001 step 756 10010010000000011101100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 757 10010010000000010100100101101001 fail ^ step 758 10011111000000010100100101101001 step 759 10011111000000010101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 760 10010110000000011100010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 761 10010110000000011101100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 762 10010110000000010100100101101010 fail ^ step 763 10011101000000010100100101101010 step 764 10011101000000010101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 765 10010100000000011100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 766 10010100000000011101100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 767 10010100000000010100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 768 10010100000000010100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 010101 step 769 10010100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 770 10010100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 771 10010100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 772 10010100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 773 10010110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 774 10010110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 775 10010110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 776 10010110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 777 10010110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 778 10010010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 779 10010010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 780 10010010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 781 10010010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 782 10010010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 783 10010000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 784 10010000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 785 10010000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 786 10010000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 787 10010000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 788 10110000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 789 10110000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 790 10110000000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 791 10110000000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 792 10110000000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 793 10110010000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 794 10110010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 795 10110010000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 796 10110010000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 797 10110010000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 798 10110110000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 799 10110110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 800 10110110000000011100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 801 10110110000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 802 10110110000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 803 10110100000000010100100101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 804 10110100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 805 10110100000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 806 10110100000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 807 10110100000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 808 10111101000000010100100101010101 fail ^^^^ ^^ step 809 10111101000000010101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 810 10110100000000011100011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 10 step 811 10110100000000011101100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 812 10110100000000010100100110101010 fail ^ step 813 10111111000000010100100110101010 step 814 10111111000000010101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 815 10110110000000011100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 step 816 10110110000000011101100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 817 10110110000000010100100110101010 fail ^ step 818 10111011000000010100100110101010 step 819 10111011000000010101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 820 10110010000000011100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 1001 step 821 10110010000000011101100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 822 10110010000000010100100110101001 fail ^ step 823 10111001000000010100100110101001 step 824 10111001000000010101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 825 10110000000000011100011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001 10 step 826 10110000000000011101100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 827 10110000000000010100100110101001 fail ^ step 828 10101001000000010100100110101001 step 829 10101001000000010101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 830 10100000000000011100011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001100110 step 831 10100000000000011101100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 832 10100000000000010100100110011001 fail ^ step 833 10101011000000010100100110011001 step 834 10101011000000010101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 835 10100010000000011100011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110011001 step 836 10100010000000011101100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 837 10100010000000010100100110011001 fail ^ step 838 10101111000000010100100110011001 step 839 10101111000000010101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 840 10100110000000011100011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 step 841 10100110000000011101100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 842 10100110000000010100100110011010 fail ^ step 843 10101101000000010100100110011010 step 844 10101101000000010101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 845 10100100000000011100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 10 step 846 10100100000000011101100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 847 10100100000000010100100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 848 10100100000000010100100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 01 0101 step 849 10100100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 850 10100100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 851 10100100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 852 10100100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 853 10100110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 854 10100110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 855 10100110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 856 10100110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 857 10100110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 858 10100010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 859 10100010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 860 10100010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 861 10100010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 862 10100010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 863 10100000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 864 10100000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 865 10100000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 866 10100000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 867 10100000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 868 11100000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 869 11100000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 870 11100000000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 871 11100000000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 872 11100000000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 873 11100010000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 874 11100010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 875 11100010000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 876 11100010000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 877 11100010000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 878 11100110000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 879 11100110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 880 11100110000000011100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 881 11100110000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 882 11100110000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 883 11100100000000010100100101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 884 11100100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 885 11100100000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 886 11100100000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 887 11100100000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 888 11101101000000010100100101010101 fail ^^^^ ^^ step 889 11101101000000010101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 890 11100100000000011100101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 891 11100100000000011101101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 892 11100100000000010100101010011010 fail ^ step 893 11101111000000010100101010011010 step 894 11101111000000010101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 895 11100110000000011100101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 896 11100110000000011101101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 897 11100110000000010100101010011010 fail ^ step 898 11101011000000010100101010011010 step 899 11101011000000010101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 900 11100010000000011100101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10011001 step 901 11100010000000011101101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 902 11100010000000010100101010011001 fail ^ step 903 11101001000000010100101010011001 step 904 11101001000000010101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 905 11100000000000011100101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 100110 step 906 11100000000000011101101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 907 11100000000000010100101010011001 fail ^ step 908 11111001000000010100101010011001 step 909 11111001000000010101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 910 11110000000000011100101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 911 11110000000000011101101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 912 11110000000000010100101010101001 fail ^ step 913 11111011000000010100101010101001 step 914 11111011000000010101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 915 11110010000000011100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 916 11110010000000011101101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 917 11110010000000010100101010101001 fail ^ step 918 11111111000000010100101010101001 step 919 11111111000000010101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 920 11110110000000011100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 921 11110110000000011101101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 922 11110110000000010100101010101010 fail ^ step 923 11111101000000010100101010101010 step 924 11111101000000010101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 925 11110100000000011100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 926 11110100000000011101101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 927 11110100000000010100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 928 11110100000000010100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1010101010101 step 929 11110100000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 930 11110100000000011100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 931 11110100000000011101100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 932 11110100000000010100100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 933 11110110000000010100100101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 934 11110110000000010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 935 11110110000000011100010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 936 11110110000000011101100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 937 11110110000000010100100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 938 11110010000000010100100101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 939 11110010000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 940 11110010000000011100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 941 11110010000000011101100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 942 11110010000000010100100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 943 11110000000000010100100101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 944 11110000000000010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 945 11110000000000011100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 946 11110000000000011101100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 947 11110000000000010100100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 948 11010000000000010100100101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 949 11010000000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 950 11010000000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 951 11010000000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 952 11010000000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 953 11010010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 954 11010010000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 955 11010010000000011100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 956 11010010000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 957 11010010000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 958 11010110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 959 11010110000000010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 960 11010110000000011100010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 961 11010110000000011101100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 962 11010110000000010100100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 963 11010100000000010100100101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 964 11010100000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 965 11010100000000011100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 966 11010100000000011101100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 967 11010100000000010100100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 968 11011101000000010100100101010101 fail ^^ ^^ ^^ step 969 11011101000000010101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 970 11010100000000011100100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 971 11010100000000011101101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 972 11010100000000010100101001101010 fail ^ step 973 11011111000000010100101001101010 step 974 11011111000000010101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 975 11010110000000011100100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 976 11010110000000011101101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 977 11010110000000010100101001101010 fail ^ step 978 11011011000000010100101001101010 step 979 11011011000000010101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 980 11010010000000011100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 1001 step 981 11010010000000011101101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 982 11010010000000010100101001101001 fail ^ step 983 11011001000000010100101001101001 step 984 11011001000000010101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 985 11010000000000011100100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 986 11010000000000011101101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 987 11010000000000010100101001101001 fail ^ step 988 11001001000000010100101001101001 step 989 11001001000000010101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 990 11000000000000011100100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 991 11000000000000011101101001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 992 11000000000000010100101001011001 fail ^ step 993 11001011000000010100101001011001 step 994 11001011000000010101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 995 11000010000000011100100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 011001 step 996 11000010000000011101101001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 997 11000010000000010100101001011001 fail ^ step 998 11001111000000010100101001011001 step 999 11001111000000010101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 1000 11000110000000011100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1001 11000110000000011101101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1002 11000110000000010100101001011010 fail ^ step 1003 11001101000000010100101001011010 step 1004 11001101000000010101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 1 0 step 1005 11000100000000011100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 10 step 1006 11000100000000011101101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1007 11000100000000010100101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1008 11000100000000010100101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10101 0101 step 1009 11000100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1010 11000100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1011 11000100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1012 11000100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1013 11000110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1014 11000110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1015 11000110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1016 11000110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1017 11000110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1018 11000010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1019 11000010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1020 11000010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1021 11000010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1022 11000010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1023 11000000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1024 11000000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0 step 1025 11000000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1026 11000000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1027 11000000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1028 10000000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1029 10000000000000010101010101010101 fail ^ step 1030 10000000000000011100010101010101 step 1031 10000000000000011101100101010101 step 1032 10000000000000010100100101010101 step 1033 10000000000000010000100101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1034 10000010000000010000100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 step 1035 10000010000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1036 10000010000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1037 10000010000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1038 10000010000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1039 10000110000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1040 10000110000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1041 10000110000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1042 10000110000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1043 10000110000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1044 10000100000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1045 10000100000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1046 10000100000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1047 10000100000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1048 10000100000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1049 10001101000000010000010101010101 fail ^^ step 1050 10001101000000010001010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1051 10000100000000010010010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1052 10000100000000010011010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1053 10000100000000010000010110100101 fail ^ step 1054 10001111000000010000010110100101 step 1055 10001111000000010001010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1056 10000110000000010010010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1057 10000110000000010011010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1058 10000110000000010000010110101001 fail ^ step 1059 10001011000000010000010110101001 step 1060 10001011000000010001010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1061 10000010000000010010010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10011001 step 1062 10000010000000010011010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1063 10000010000000010000010110011001 fail ^ step 1064 10001001000000010000010110011001 step 1065 10001001000000010001010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1066 10000000000000010010010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 1067 10000000000000010011010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1068 10000000000000010000010110010101 fail ^ step 1069 10011001000000010000010110010101 step 1070 10011001000000010001010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1071 10010000000000010010010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1072 10010000000000010011011010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1073 10010000000000010000011010010101 fail ^ step 1074 10011011000000010000011010010101 step 1075 10011011000000010001010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1076 10010010000000010010010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 011001 step 1077 10010010000000010011011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1078 10010010000000010000011010011001 fail ^ step 1079 10011111000000010000011010011001 step 1080 10011111000000010001010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1081 10010110000000010010010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1082 10010110000000010011011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1083 10010110000000010000011010101001 fail ^ step 1084 10011101000000010000011010101001 step 1085 10011101000000010001010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1086 10010100000000010010010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 step 1087 10010100000000010011011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1088 10010100000000010000011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1089 10010100000000010000011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 010101 step 1090 10010100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1091 10010100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1092 10010100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1093 10010100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1094 10010110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1095 10010110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1096 10010110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1097 10010110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1098 10010110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1099 10010010000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1100 10010010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1101 10010010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1102 10010010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1103 10010010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1104 10010000000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1105 10010000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1106 10010000000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1107 10010000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1108 10010000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1109 10110000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1110 10110000000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1111 10110000000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1112 10110000000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1113 10110000000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1114 10110010000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1115 10110010000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1116 10110010000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1117 10110010000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1118 10110010000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1119 10110110000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1120 10110110000000010001010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1121 10110110000000010010010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1122 10110110000000010011010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1123 10110110000000010000010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1124 10110100000000010000010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1125 10110100000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1126 10110100000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1127 10110100000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1128 10110100000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1129 10111101000000010000010101010101 fail ^^^^ ^^ step 1130 10111101000000010001011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1131 10110100000000010010011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 1132 10110100000000010011101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1133 10110100000000010000101010100101 fail ^ step 1134 10111111000000010000101010100101 step 1135 10111111000000010001011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1136 10110110000000010010011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 1137 10110110000000010011101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1138 10110110000000010000101010101001 fail ^ step 1139 10111011000000010000101010101001 step 1140 10111011000000010001011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1141 10110010000000010010011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 011001 step 1142 10110010000000010011101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1143 10110010000000010000101010011001 fail ^ step 1144 10111001000000010000101010011001 step 1145 10111001000000010001011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1146 10110000000000010010011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 step 1147 10110000000000010011101010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1148 10110000000000010000101010010101 fail ^ step 1149 10101001000000010000101010010101 step 1150 10101001000000010001011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1151 10100000000000010010011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 step 1152 10100000000000010011100110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1153 10100000000000010000100110010101 fail ^ step 1154 10101011000000010000100110010101 step 1155 10101011000000010001011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1156 10100010000000010010011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110011001 step 1157 10100010000000010011100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1158 10100010000000010000100110011001 fail ^ step 1159 10101111000000010000100110011001 step 1160 10101111000000010001011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1161 10100110000000010010011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 01 step 1162 10100110000000010011100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1163 10100110000000010000100110101001 fail ^ step 1164 10101101000000010000100110101001 step 1165 10101101000000010001011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1166 10100100000000010010011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 01 step 1167 10100100000000010011100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1168 10100100000000010000100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1169 10100100000000010000100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 0101 step 1170 10100100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1171 10100100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1172 10100100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1173 10100100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1174 10100110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1175 10100110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1176 10100110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1177 10100110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1178 10100110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1179 10100010000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1180 10100010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1181 10100010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1182 10100010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1183 10100010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1184 10100000000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1185 10100000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1186 10100000000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1187 10100000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1188 10100000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1189 11100000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1190 11100000000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1191 11100000000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1192 11100000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1193 11100000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1194 11100010000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1195 11100010000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1196 11100010000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1197 11100010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1198 11100010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1199 11100110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1200 11100110000000010001010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1201 11100110000000010010010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1202 11100110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1203 11100110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1204 11100100000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1205 11100100000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1206 11100100000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1207 11100100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1208 11100100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1209 11101101000000010000010101010101 fail ^^ ^^ step 1210 11101101000000010001101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1211 11100100000000010010101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 01 step 1212 11100100000000010011100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1213 11100100000000010000100110100101 fail ^ step 1214 11101111000000010000100110100101 step 1215 11101111000000010001101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1216 11100110000000010010101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 01 step 1217 11100110000000010011100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1218 11100110000000010000100110101001 fail ^ step 1219 11101011000000010000100110101001 step 1220 11101011000000010001101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1221 11100010000000010010101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110011001 step 1222 11100010000000010011100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1223 11100010000000010000100110011001 fail ^ step 1224 11101001000000010000100110011001 step 1225 11101001000000010001101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1226 11100000000000010010101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 1227 11100000000000010011100110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1228 11100000000000010000100110010101 fail ^ step 1229 11111001000000010000100110010101 step 1230 11111001000000010001101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1231 11110000000000010010101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1232 11110000000000010011101010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1233 11110000000000010000101010010101 fail ^ step 1234 11111011000000010000101010010101 step 1235 11111011000000010001101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1236 11110010000000010010101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 step 1237 11110010000000010011101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1238 11110010000000010000101010011001 fail ^ step 1239 11111111000000010000101010011001 step 1240 11111111000000010001101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1241 11110110000000010010101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1242 11110110000000010011101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1243 11110110000000010000101010101001 fail ^ step 1244 11111101000000010000101010101001 step 1245 11111101000000010001101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1246 11110100000000010010101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1247 11110100000000010011101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1248 11110100000000010000101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1249 11110100000000010000101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101010101 step 1250 11110100000000010001010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1251 11110100000000010010010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1252 11110100000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1253 11110100000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1254 11110110000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1255 11110110000000010001010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1256 11110110000000010010010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1257 11110110000000010011010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1258 11110110000000010000010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1259 11110010000000010000010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1260 11110010000000010001010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1261 11110010000000010010010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1262 11110010000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1263 11110010000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1264 11110000000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1265 11110000000000010001010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1266 11110000000000010010010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1267 11110000000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1268 11110000000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1269 11010000000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1270 11010000000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1271 11010000000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1272 11010000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1273 11010000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1274 11010010000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1275 11010010000000010001010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1276 11010010000000010010010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1277 11010010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1278 11010010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1279 11010110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1280 11010110000000010001010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1281 11010110000000010010010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1282 11010110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1283 11010110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1284 11010100000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1285 11010100000000010001010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1286 11010100000000010010010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1287 11010100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1288 11010100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1289 11011101000000010000010101010101 fail ^^ ^^ step 1290 11011101000000010001100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1291 11010100000000010010100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 1292 11010100000000010011011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1293 11010100000000010000011010100101 fail ^ step 1294 11011111000000010000011010100101 step 1295 11011111000000010001100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1296 11010110000000010010100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 1297 11010110000000010011011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1298 11010110000000010000011010101001 fail ^ step 1299 11011011000000010000011010101001 step 1300 11011011000000010001100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1301 11010010000000010010100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 011001 step 1302 11010010000000010011011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1303 11010010000000010000011010011001 fail ^ step 1304 11011001000000010000011010011001 step 1305 11011001000000010001100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1306 11010000000000010010100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 step 1307 11010000000000010011011010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1308 11010000000000010000011010010101 fail ^ step 1309 11001001000000010000011010010101 step 1310 11001001000000010001100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1311 11000000000000010010100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 step 1312 11000000000000010011010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1313 11000000000000010000010110010101 fail ^ step 1314 11001011000000010000010110010101 step 1315 11001011000000010001100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1316 11000010000000010010100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10011001 step 1317 11000010000000010011010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1318 11000010000000010000010110011001 fail ^ step 1319 11001111000000010000010110011001 step 1320 11001111000000010001100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1321 11000110000000010010100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 01 step 1322 11000110000000010011010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1323 11000110000000010000010110101001 fail ^ step 1324 11001101000000010000010110101001 step 1325 11001101000000010001100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1326 11000100000000010010100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 01 step 1327 11000100000000010011010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1328 11000100000000010000010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1329 11000100000000010000010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0101 step 1330 11000100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1331 11000100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1332 11000100000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1333 11000100000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1334 11000110000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1335 11000110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1336 11000110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1337 11000110000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1338 11000110000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1339 11000010000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1340 11000010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1341 11000010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1342 11000010000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1343 11000010000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1344 11000000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1345 11000000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1346 11000000000000010010010101010101 fail ^^ step 1347 11000000000000010011010101010101 step 1348 11000000000000010000010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1349 10000000000000010000010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1350 10000000000000010001010101010101 fail ^ step 1351 10000000000000010010010101010101 step 1352 10000000000000010011010101010101 step 1353 10000000000000010000010101010101 step 1354 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1355 10000010000000010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1356 10000010000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1357 10000010000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1358 10000010000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1359 10000010000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1360 10000110000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1361 10000110000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1362 10000110000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1363 10000110000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1364 10000110000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1365 10000100000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1366 10000100000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1367 10000100000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1368 10000100000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1369 10000100000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1370 10001101000000010100010101010110 fail ^^ step 1371 10001101000000010101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1372 10000100000000010110010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 1373 10000100000000010111010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1374 10000100000000010100010110100110 fail ^ step 1375 10001111000000010100010110100110 step 1376 10001111000000010101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1377 10000110000000010110010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1378 10000110000000010111010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1379 10000110000000010100010110101010 fail ^ step 1380 10001011000000010100010110101010 step 1381 10001011000000010101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1382 10000010000000010110010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 100110 step 1383 10000010000000010111010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1384 10000010000000010100010110011010 fail ^ step 1385 10001001000000010100010110011010 step 1386 10001001000000010101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1387 10000000000000010110010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 10 step 1388 10000000000000010111010110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1389 10000000000000010100010110010110 fail ^ step 1390 10011001000000010100010110010110 step 1391 10011001000000010101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1392 10010000000000010110010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 01 10 step 1393 10010000000000010111011010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1394 10010000000000010100011010010110 fail ^ step 1395 10011011000000010100011010010110 step 1396 10011011000000010101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1397 10010010000000010110010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 1398 10010010000000010111011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1399 10010010000000010100011010011010 fail ^ step 1400 10011111000000010100011010011010 step 1401 10011111000000010101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1402 10010110000000010110010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1403 10010110000000010111011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1404 10010110000000010100011010101010 fail ^ step 1405 10011101000000010100011010101010 step 1406 10011101000000010101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1407 10010100000000010110010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 0110 step 1408 10010100000000010111011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1409 10010100000000010100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1410 10010100000000010100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 010101 01 step 1411 10010100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1412 10010100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1413 10010100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1414 10010100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1415 10010110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1416 10010110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1417 10010110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1418 10010110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1419 10010110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1420 10010010000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1421 10010010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1422 10010010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1423 10010010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1424 10010010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1425 10010000000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1426 10010000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1427 10010000000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1428 10010000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1429 10010000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1430 10110000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1431 10110000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1432 10110000000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1433 10110000000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1434 10110000000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1435 10110010000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1436 10110010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1437 10110010000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1438 10110010000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1439 10110010000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1440 10110110000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1441 10110110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1442 10110110000000010110010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1443 10110110000000010111010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1444 10110110000000010100010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1445 10110100000000010100010101010110 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1446 10110100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1447 10110100000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1448 10110100000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1449 10110100000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1450 10111101000000010100010101010110 fail ^^^^ ^^ step 1451 10111101000000010101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1452 10110100000000010110011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 0110 step 1453 10110100000000010111101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1454 10110100000000010100101010100110 fail ^ step 1455 10111111000000010100101010100110 step 1456 10111111000000010101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1457 10110110000000010110011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1458 10110110000000010111101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1459 10110110000000010100101010101010 fail ^ step 1460 10111011000000010100101010101010 step 1461 10111011000000010101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1462 10110010000000010110011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 0110 step 1463 10110010000000010111101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1464 10110010000000010100101010011010 fail ^ step 1465 10111001000000010100101010011010 step 1466 10111001000000010101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1467 10110000000000010110011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 01 10 step 1468 10110000000000010111101010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1469 10110000000000010100101010010110 fail ^ step 1470 10101001000000010100101010010110 step 1471 10101001000000010101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1472 10100000000000010110011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110011001 10 step 1473 10100000000000010111100110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1474 10100000000000010100100110010110 fail ^ step 1475 10101011000000010100100110010110 step 1476 10101011000000010101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1477 10100010000000010110011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11001100110 step 1478 10100010000000010111100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1479 10100010000000010100100110011010 fail ^ step 1480 10101111000000010100100110011010 step 1481 10101111000000010101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1482 10100110000000010110011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 1483 10100110000000010111100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1484 10100110000000010100100110101010 fail ^ step 1485 10101101000000010100100110101010 step 1486 10101101000000010101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1487 10100100000000010110011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 0110 step 1488 10100100000000010111100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1489 10100100000000010100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1490 10100100000000010100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 0101 01 step 1491 10100100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1492 10100100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1493 10100100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1494 10100100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1495 10100110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1496 10100110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1497 10100110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1498 10100110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1499 10100110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1500 10100010000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1501 10100010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1502 10100010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1503 10100010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1504 10100010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1505 10100000000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1506 10100000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1507 10100000000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1508 10100000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1509 10100000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1510 11100000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1511 11100000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1512 11100000000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1513 11100000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1514 11100000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1515 11100010000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1516 11100010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1517 11100010000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1518 11100010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1519 11100010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1520 11100110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1521 11100110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1522 11100110000000010110010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1523 11100110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1524 11100110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1525 11100100000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1526 11100100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1527 11100100000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1528 11100100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1529 11100100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1530 11101101000000010100010101010110 fail ^^ ^^ step 1531 11101101000000010101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1532 11100100000000010110101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 0110 step 1533 11100100000000010111100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1534 11100100000000010100100110100110 fail ^ step 1535 11101111000000010100100110100110 step 1536 11101111000000010101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1537 11100110000000010110101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1538 11100110000000010111100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1539 11100110000000010100100110101010 fail ^ step 1540 11101011000000010100100110101010 step 1541 11101011000000010101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1542 11100010000000010110101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01100110 step 1543 11100010000000010111100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1544 11100010000000010100100110011010 fail ^ step 1545 11101001000000010100100110011010 step 1546 11101001000000010101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1547 11100000000000010110101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 011001 10 step 1548 11100000000000010111100110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1549 11100000000000010100100110010110 fail ^ step 1550 11111001000000010100100110010110 step 1551 11111001000000010101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1552 11110000000000010110101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 10 step 1553 11110000000000010111101010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1554 11110000000000010100101010010110 fail ^ step 1555 11111011000000010100101010010110 step 1556 11111011000000010101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1557 11110010000000010110101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1558 11110010000000010111101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1559 11110010000000010100101010011010 fail ^ step 1560 11111111000000010100101010011010 step 1561 11111111000000010101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1562 11110110000000010110101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1563 11110110000000010111101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1564 11110110000000010100101010101010 fail ^ step 1565 11111101000000010100101010101010 step 1566 11111101000000010101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1567 11110100000000010110101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1568 11110100000000010111101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1569 11110100000000010100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1570 11110100000000010100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101010101 01 step 1571 11110100000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1572 11110100000000010110010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1573 11110100000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1574 11110100000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1575 11110110000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1576 11110110000000010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1577 11110110000000010110010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1578 11110110000000010111010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1579 11110110000000010100010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1580 11110010000000010100010101010110 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1581 11110010000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1582 11110010000000010110010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1583 11110010000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1584 11110010000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1585 11110000000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1586 11110000000000010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1587 11110000000000010110010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1588 11110000000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1589 11110000000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1590 11010000000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1591 11010000000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1592 11010000000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1593 11010000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1594 11010000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1595 11010010000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1596 11010010000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1597 11010010000000010110010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1598 11010010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1599 11010010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1600 11010110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1601 11010110000000010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1602 11010110000000010110010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1603 11010110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1604 11010110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1605 11010100000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1606 11010100000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1607 11010100000000010110010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1608 11010100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1609 11010100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1610 11011101000000010100010101010110 fail ^^ ^^ step 1611 11011101000000010101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1612 11010100000000010110100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 0110 step 1613 11010100000000010111011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1614 11010100000000010100011010100110 fail ^ step 1615 11011111000000010100011010100110 step 1616 11011111000000010101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1617 11010110000000010110100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 1618 11010110000000010111011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1619 11010110000000010100011010101010 fail ^ step 1620 11011011000000010100011010101010 step 1621 11011011000000010101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1622 11010010000000010110100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 0110 step 1623 11010010000000010111011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1624 11010010000000010100011010011010 fail ^ step 1625 11011001000000010100011010011010 step 1626 11011001000000010101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1627 11010000000000010110100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 01 10 step 1628 11010000000000010111011010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1629 11010000000000010100011010010110 fail ^ step 1630 11001001000000010100011010010110 step 1631 11001001000000010101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1632 11000000000000010110100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 1001 10 step 1633 11000000000000010111010110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1634 11000000000000010100010110010110 fail ^ step 1635 11001011000000010100010110010110 step 1636 11001011000000010101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1637 11000010000000010110100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 100110 step 1638 11000010000000010111010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1639 11000010000000010100010110011010 fail ^ step 1640 11001111000000010100010110011010 step 1641 11001111000000010101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1642 11000110000000010110100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 1643 11000110000000010111010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1644 11000110000000010100010110101010 fail ^ step 1645 11001101000000010100010110101010 step 1646 11001101000000010101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 10 step 1647 11000100000000010110100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 0110 step 1648 11000100000000010111010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1649 11000100000000010100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: step 1650 11000100000000010100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0101 01 step 1651 11000100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1652 11000100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1653 11000100000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1654 11000100000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1655 11000110000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1656 11000110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1657 11000110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1658 11000110000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1659 11000110000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1660 11000010000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1661 11000010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1662 11000010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1663 11000010000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1664 11000010000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1665 11000000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1666 11000000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10 step 1667 11000000000000010110010101010101 fail ^^ step 1668 11000000000000010111010101010110 step 1669 11000000000000010100010101010110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1670 10000000000000010100010101010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 01 step 1671 10000000000000010101010101010101 fail ^ step 1672 10000000000000010110010101010101 step 1673 10000000000000010111010101010110 step 1674 10000000000000010100010101010110 step 1675 00000000000000010100010101010101 step 1676 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 111 11 111111 step 1677 11110110111111010100010101010101 fail ^ test 5: *** FAIL *************************** 1123 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail I I OOOOOOOOOOOO all fails I I OOOOOOOOOOOO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 5, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 step 1 01110110111111010100010101010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1 changed: 1 step 2 11110110111111010100010101010101 fail ^ source: source: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM source: ; see mk_m212_ld_shift.c source: source: source: ; TEST A INPUTS, GRAY CODE PATTERN source: source: ; ENABLE A INPUTS source: 1 changed: 1 1 step 3 11111111111111010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; LOAD FFs FROM INPUT A source: source: 000001 changed: 00000 0 step 4 10000010111111010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 5 10000010111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 6 10000010111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000011 changed: 1 step 7 10000110111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 8 10000110111111010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 9 10000110111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000010 changed: 0 step 10 10000100111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 11 10000100111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 12 10000100111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000110 changed: 1 1 step 13 10001101111111010100010101010101 fail ^^ source: 1010101101001 changed: 1 1010 step 14 10001101111111010101010101101001 source: 0 changed: 0 step 15 10001101111111010100010101101001 source: 000111 changed: 1 step 16 10001111111111010100010101101001 source: 1010101101010 changed: 1 10 step 17 10001111111111010101010101101010 source: 0 changed: 0 step 18 10001111111111010100010101101010 source: 000101 changed: 0 step 19 10001011111111010100010101101010 source: 1010101100110 changed: 1 01 step 20 10001011111111010101010101100110 source: 0 changed: 0 step 21 10001011111111010100010101100110 source: 000100 changed: 0 step 22 10001001111111010100010101100110 source: 1010101100101 changed: 1 01 step 23 10001001111111010101010101100101 source: 0 changed: 0 step 24 10001001111111010100010101100101 source: 001100 changed: 1 step 25 10011001111111010100010101100101 source: 1010110100101 changed: 1 10 step 26 10011001111111010101010110100101 source: 0 changed: 0 step 27 10011001111111010100010110100101 source: 001101 changed: 1 step 28 10011011111111010100010110100101 source: 1010110100110 changed: 1 10 step 29 10011011111111010101010110100110 source: 0 changed: 0 step 30 10011011111111010100010110100110 source: 001111 changed: 1 step 31 10011111111111010100010110100110 source: 1010110101010 changed: 1 10 step 32 10011111111111010101010110101010 source: 0 changed: 0 step 33 10011111111111010100010110101010 source: 001110 changed: 0 step 34 10011101111111010100010110101010 source: 1010110101001 changed: 1 01 step 35 10011101111111010101010110101001 source: 0 changed: 0 step 36 10011101111111010100010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001010 changed: 0 0 step 37 10010100111111010100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 010101 step 38 10010100111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 39 10010100111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001011 changed: 1 step 40 10010110111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 41 10010110111111010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 42 10010110111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001001 changed: 0 step 43 10010010111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 44 10010010111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 45 10010010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001000 changed: 0 step 46 10010000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 47 10010000111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 48 10010000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011000 changed: 1 step 49 10110000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 50 10110000111111010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 51 10110000111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011001 changed: 1 step 52 10110010111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 53 10110010111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 54 10110010111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011011 changed: 1 step 55 10110110111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 56 10110110111111010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 57 10110110111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011010 changed: 0 step 58 10110100111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 59 10110100111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 60 10110100111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011110 changed: 1 1 step 61 10111101111111010100010101010101 fail ^^^^ ^^ source: 1011010101001 changed: 1 10101010 step 62 10111101111111010101011010101001 source: 0 changed: 0 step 63 10111101111111010100011010101001 source: 011111 changed: 1 step 64 10111111111111010100011010101001 source: 1011010101010 changed: 1 10 step 65 10111111111111010101011010101010 source: 0 changed: 0 step 66 10111111111111010100011010101010 source: 011101 changed: 0 step 67 10111011111111010100011010101010 source: 1011010100110 changed: 1 01 step 68 10111011111111010101011010100110 source: 0 changed: 0 step 69 10111011111111010100011010100110 source: 011100 changed: 0 step 70 10111001111111010100011010100110 source: 1011010100101 changed: 1 01 step 71 10111001111111010101011010100101 source: 0 changed: 0 step 72 10111001111111010100011010100101 source: 010100 changed: 0 step 73 10101001111111010100011010100101 source: 1011001100101 changed: 1 01 step 74 10101001111111010101011001100101 source: 0 changed: 0 step 75 10101001111111010100011001100101 source: 010101 changed: 1 step 76 10101011111111010100011001100101 source: 1011001100110 changed: 1 10 step 77 10101011111111010101011001100110 source: 0 changed: 0 step 78 10101011111111010100011001100110 source: 010111 changed: 1 step 79 10101111111111010100011001100110 source: 1011001101010 changed: 1 10 step 80 10101111111111010101011001101010 source: 0 changed: 0 step 81 10101111111111010100011001101010 source: 010110 changed: 0 step 82 10101101111111010100011001101010 source: 1011001101001 changed: 1 01 step 83 10101101111111010101011001101001 source: 0 changed: 0 step 84 10101101111111010100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010010 changed: 0 0 step 85 10100100111111010100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 01 0101 step 86 10100100111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 87 10100100111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010011 changed: 1 step 88 10100110111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 89 10100110111111010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 90 10100110111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010001 changed: 0 step 91 10100010111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 92 10100010111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 93 10100010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010000 changed: 0 step 94 10100000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 95 10100000111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 96 10100000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110000 changed: 1 step 97 11100000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 98 11100000111111010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 99 11100000111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110001 changed: 1 step 100 11100010111111010100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 101 11100010111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 102 11100010111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110011 changed: 1 step 103 11100110111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 104 11100110111111010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 105 11100110111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110010 changed: 0 step 106 11100100111111010100010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 107 11100100111111010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 108 11100100111111010100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110110 changed: 1 1 step 109 11101101111111010100010101010101 fail ^^^^ ^^ source: 1101001101001 changed: 11010 1010 step 110 11101101111111010101101001101001 source: 0 changed: 0 step 111 11101101111111010100101001101001 source: 110111 changed: 1 step 112 11101111111111010100101001101001 source: 1101001101010 changed: 1 10 step 113 11101111111111010101101001101010 source: 0 changed: 0 step 114 11101111111111010100101001101010 source: 110101 changed: 0 step 115 11101011111111010100101001101010 source: 1101001100110 changed: 1 01 step 116 11101011111111010101101001100110 source: 0 changed: 0 step 117 11101011111111010100101001100110 source: 110100 changed: 0 step 118 11101001111111010100101001100110 source: 1101001100101 changed: 1 01 step 119 11101001111111010101101001100101 source: 0 changed: 0 step 120 11101001111111010100101001100101 source: 111100 changed: 1 step 121 11111001111111010100101001100101 source: 1101010100101 changed: 1 10 step 122 11111001111111010101101010100101 source: 0 changed: 0 step 123 11111001111111010100101010100101 source: 111101 changed: 1 step 124 11111011111111010100101010100101 source: 1101010100110 changed: 1 10 step 125 11111011111111010101101010100110 source: 0 changed: 0 step 126 11111011111111010100101010100110 source: 111111 changed: 1 step 127 11111111111111010100101010100110 source: 1101010101010 changed: 1 10 step 128 11111111111111010101101010101010 source: 0 changed: 0 step 129 11111111111111010100101010101010 source: 111110 changed: 0 step 130 11111101111111010100101010101010 source: 1101010101001 changed: 1 01 step 131 11111101111111010101101010101001 source: 0 changed: 0 step 132 11111101111111010100101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111010 changed: 0 0 step 133 11110100111111010100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 10101010101 step 134 11110100111111010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 135 11110100111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111011 changed: 1 step 136 11110110111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 137 11110110111111010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 138 11110110111111010100010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111001 changed: 0 step 139 11110010111111010100010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 140 11110010111111010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 141 11110010111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111000 changed: 0 step 142 11110000111111010100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 143 11110000111111010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 144 11110000111111010100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101000 changed: 0 step 145 11010000111111010100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 146 11010000111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 147 11010000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101001 changed: 1 step 148 11010010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 149 11010010111111010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 150 11010010111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101011 changed: 1 step 151 11010110111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 152 11010110111111010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 153 11010110111111010100010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101010 changed: 0 step 154 11010100111111010100010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 155 11010100111111010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 156 11010100111111010100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101110 changed: 1 1 step 157 11011101111111010100010101010101 fail ^^ ^^ ^^ source: 1100110101001 changed: 110 101010 step 158 11011101111111010101100110101001 source: 0 changed: 0 step 159 11011101111111010100100110101001 source: 101111 changed: 1 step 160 11011111111111010100100110101001 source: 1100110101010 changed: 1 10 step 161 11011111111111010101100110101010 source: 0 changed: 0 step 162 11011111111111010100100110101010 source: 101101 changed: 0 step 163 11011011111111010100100110101010 source: 1100110100110 changed: 1 01 step 164 11011011111111010101100110100110 source: 0 changed: 0 step 165 11011011111111010100100110100110 source: 101100 changed: 0 step 166 11011001111111010100100110100110 source: 1100110100101 changed: 1 01 step 167 11011001111111010101100110100101 source: 0 changed: 0 step 168 11011001111111010100100110100101 source: 100100 changed: 0 step 169 11001001111111010100100110100101 source: 1100101100101 changed: 1 01 step 170 11001001111111010101100101100101 source: 0 changed: 0 step 171 11001001111111010100100101100101 source: 100101 changed: 1 step 172 11001011111111010100100101100101 source: 1100101100110 changed: 1 10 step 173 11001011111111010101100101100110 source: 0 changed: 0 step 174 11001011111111010100100101100110 source: 100111 changed: 1 step 175 11001111111111010100100101100110 source: 1100101101010 changed: 1 10 step 176 11001111111111010101100101101010 source: 0 changed: 0 step 177 11001111111111010100100101101010 source: 100110 changed: 0 step 178 11001101111111010100100101101010 source: 1100101101001 changed: 1 01 step 179 11001101111111010101100101101001 source: 0 changed: 0 step 180 11001101111111010100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100010 changed: 0 0 step 181 11000100111111010100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 101 0101 step 182 11000100111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 183 11000100111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100011 changed: 1 step 184 11000110111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 185 11000110111111010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 186 11000110111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100001 changed: 0 step 187 11000010111111010100010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 188 11000010111111010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 189 11000010111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100000 changed: 0 step 190 11000000111111010100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 191 11000000111111010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 192 11000000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000000 changed: 0 step 193 10000000111111010100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 194 10000000111111010101010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 195 10000000111111010100010101010101 fail ^ source: source: ; DISABLE A INPUTS source: 0 changed: step 196 10000000111111010100010101010101 source: source: source: ; TEST B INPUTS source: source: ; ENABLE B INPUTS source: 1 changed: 1 step 197 10000000111111110100010101010101 source: ; LOAD FFs FROM INPUT B source: source: 000001 changed: 00000 step 198 10000000000001110100010101010101 source: 1010101010110 changed: 1 10 step 199 10000000000001110101010101010110 source: 0 changed: 0 step 200 10000000000001110100010101010110 source: 000011 changed: 1 step 201 10000000000011110100010101010110 source: 1010101011010 changed: 1 10 step 202 10000000000011110101010101011010 source: 0 changed: 0 step 203 10000000000011110100010101011010 source: 000010 changed: 0 step 204 10000000000010110100010101011010 source: 1010101011001 changed: 1 01 step 205 10000000000010110101010101011001 source: 0 changed: 0 step 206 10000000000010110100010101011001 source: 000110 changed: 1 step 207 10000000000110110100010101011001 source: 1010101101001 changed: 1 10 step 208 10000000000110110101010101101001 source: 0 changed: 0 step 209 10000000000110110100010101101001 source: 000111 changed: 1 step 210 10000000000111110100010101101001 source: 1010101101010 changed: 1 10 step 211 10000000000111110101010101101010 source: 0 changed: 0 step 212 10000000000111110100010101101010 source: 000101 changed: 0 step 213 10000000000101110100010101101010 source: 1010101100110 changed: 1 01 step 214 10000000000101110101010101100110 source: 0 changed: 0 step 215 10000000000101110100010101100110 source: 000100 changed: 0 step 216 10000000000100110100010101100110 source: 1010101100101 changed: 1 01 step 217 10000000000100110101010101100101 source: 0 changed: 0 step 218 10000000000100110100010101100101 source: 001100 changed: 1 step 219 10000000001100110100010101100101 source: 1010110100101 changed: 1 10 step 220 10000000001100110101010110100101 source: 0 changed: 0 step 221 10000000001100110100010110100101 source: 001101 changed: 1 step 222 10000000001101110100010110100101 source: 1010110100110 changed: 1 10 step 223 10000000001101110101010110100110 source: 0 changed: 0 step 224 10000000001101110100010110100110 source: 001111 changed: 1 step 225 10000000001111110100010110100110 source: 1010110101010 changed: 1 10 step 226 10000000001111110101010110101010 source: 0 changed: 0 step 227 10000000001111110100010110101010 source: 001110 changed: 0 step 228 10000000001110110100010110101010 source: 1010110101001 changed: 1 01 step 229 10000000001110110101010110101001 source: 0 changed: 0 step 230 10000000001110110100010110101001 source: 001010 changed: 0 step 231 10000000001010110100010110101001 source: 1010110011001 changed: 1 01 step 232 10000000001010110101010110011001 source: 0 changed: 0 step 233 10000000001010110100010110011001 source: 001011 changed: 1 step 234 10000000001011110100010110011001 source: 1010110011010 changed: 1 10 step 235 10000000001011110101010110011010 source: 0 changed: 0 step 236 10000000001011110100010110011010 source: 001001 changed: 0 step 237 10000000001001110100010110011010 source: 1010110010110 changed: 1 01 step 238 10000000001001110101010110010110 source: 0 changed: 0 step 239 10000000001001110100010110010110 source: 001000 changed: 0 step 240 10000000001000110100010110010110 source: 1010110010101 changed: 1 01 step 241 10000000001000110101010110010101 source: 0 changed: 0 step 242 10000000001000110100010110010101 source: 011000 changed: 1 step 243 10000000011000110100010110010101 source: 1011010010101 changed: 1 10 step 244 10000000011000110101011010010101 source: 0 changed: 0 step 245 10000000011000110100011010010101 source: 011001 changed: 1 step 246 10000000011001110100011010010101 source: 1011010010110 changed: 1 10 step 247 10000000011001110101011010010110 source: 0 changed: 0 step 248 10000000011001110100011010010110 source: 011011 changed: 1 step 249 10000000011011110100011010010110 source: 1011010011010 changed: 1 10 step 250 10000000011011110101011010011010 source: 0 changed: 0 step 251 10000000011011110100011010011010 source: 011010 changed: 0 step 252 10000000011010110100011010011010 source: 1011010011001 changed: 1 01 step 253 10000000011010110101011010011001 source: 0 changed: 0 step 254 10000000011010110100011010011001 source: 011110 changed: 1 step 255 10000000011110110100011010011001 source: 1011010101001 changed: 1 10 step 256 10000000011110110101011010101001 source: 0 changed: 0 step 257 10000000011110110100011010101001 source: 011111 changed: 1 step 258 10000000011111110100011010101001 source: 1011010101010 changed: 1 10 step 259 10000000011111110101011010101010 source: 0 changed: 0 step 260 10000000011111110100011010101010 source: 011101 changed: 0 step 261 10000000011101110100011010101010 source: 1011010100110 changed: 1 01 step 262 10000000011101110101011010100110 source: 0 changed: 0 step 263 10000000011101110100011010100110 source: 011100 changed: 0 step 264 10000000011100110100011010100110 source: 1011010100101 changed: 1 01 step 265 10000000011100110101011010100101 source: 0 changed: 0 step 266 10000000011100110100011010100101 source: 010100 changed: 0 step 267 10000000010100110100011010100101 source: 1011001100101 changed: 1 01 step 268 10000000010100110101011001100101 source: 0 changed: 0 step 269 10000000010100110100011001100101 source: 010101 changed: 1 step 270 10000000010101110100011001100101 source: 1011001100110 changed: 1 10 step 271 10000000010101110101011001100110 source: 0 changed: 0 step 272 10000000010101110100011001100110 source: 010111 changed: 1 step 273 10000000010111110100011001100110 source: 1011001101010 changed: 1 10 step 274 10000000010111110101011001101010 source: 0 changed: 0 step 275 10000000010111110100011001101010 source: 010110 changed: 0 step 276 10000000010110110100011001101010 source: 1011001101001 changed: 1 01 step 277 10000000010110110101011001101001 source: 0 changed: 0 step 278 10000000010110110100011001101001 source: 010010 changed: 0 step 279 10000000010010110100011001101001 source: 1011001011001 changed: 1 01 step 280 10000000010010110101011001011001 source: 0 changed: 0 step 281 10000000010010110100011001011001 source: 010011 changed: 1 step 282 10000000010011110100011001011001 source: 1011001011010 changed: 1 10 step 283 10000000010011110101011001011010 source: 0 changed: 0 step 284 10000000010011110100011001011010 source: 010001 changed: 0 step 285 10000000010001110100011001011010 source: 1011001010110 changed: 1 01 step 286 10000000010001110101011001010110 source: 0 changed: 0 step 287 10000000010001110100011001010110 source: 010000 changed: 0 step 288 10000000010000110100011001010110 source: 1011001010101 changed: 1 01 step 289 10000000010000110101011001010101 source: 0 changed: 0 step 290 10000000010000110100011001010101 source: 110000 changed: 1 step 291 10000000110000110100011001010101 source: 1101001010101 changed: 110 step 292 10000000110000110101101001010101 source: 0 changed: 0 step 293 10000000110000110100101001010101 source: 110001 changed: 1 step 294 10000000110001110100101001010101 source: 1101001010110 changed: 1 10 step 295 10000000110001110101101001010110 source: 0 changed: 0 step 296 10000000110001110100101001010110 source: 110011 changed: 1 step 297 10000000110011110100101001010110 source: 1101001011010 changed: 1 10 step 298 10000000110011110101101001011010 source: 0 changed: 0 step 299 10000000110011110100101001011010 source: 110010 changed: 0 step 300 10000000110010110100101001011010 source: 1101001011001 changed: 1 01 step 301 10000000110010110101101001011001 source: 0 changed: 0 step 302 10000000110010110100101001011001 source: 110110 changed: 1 step 303 10000000110110110100101001011001 source: 1101001101001 changed: 1 10 step 304 10000000110110110101101001101001 source: 0 changed: 0 step 305 10000000110110110100101001101001 source: 110111 changed: 1 step 306 10000000110111110100101001101001 source: 1101001101010 changed: 1 10 step 307 10000000110111110101101001101010 source: 0 changed: 0 step 308 10000000110111110100101001101010 source: 110101 changed: 0 step 309 10000000110101110100101001101010 source: 1101001100110 changed: 1 01 step 310 10000000110101110101101001100110 source: 0 changed: 0 step 311 10000000110101110100101001100110 source: 110100 changed: 0 step 312 10000000110100110100101001100110 source: 1101001100101 changed: 1 01 step 313 10000000110100110101101001100101 source: 0 changed: 0 step 314 10000000110100110100101001100101 source: 111100 changed: 1 step 315 10000000111100110100101001100101 source: 1101010100101 changed: 1 10 step 316 10000000111100110101101010100101 source: 0 changed: 0 step 317 10000000111100110100101010100101 source: 111101 changed: 1 step 318 10000000111101110100101010100101 source: 1101010100110 changed: 1 10 step 319 10000000111101110101101010100110 source: 0 changed: 0 step 320 10000000111101110100101010100110 source: 111111 changed: 1 step 321 10000000111111110100101010100110 source: 1101010101010 changed: 1 10 step 322 10000000111111110101101010101010 source: 0 changed: 0 step 323 10000000111111110100101010101010 source: 111110 changed: 0 step 324 10000000111110110100101010101010 source: 1101010101001 changed: 1 01 step 325 10000000111110110101101010101001 source: 0 changed: 0 step 326 10000000111110110100101010101001 source: 111010 changed: 0 step 327 10000000111010110100101010101001 source: 1101010011001 changed: 1 01 step 328 10000000111010110101101010011001 source: 0 changed: 0 step 329 10000000111010110100101010011001 source: 111011 changed: 1 step 330 10000000111011110100101010011001 source: 1101010011010 changed: 1 10 step 331 10000000111011110101101010011010 source: 0 changed: 0 step 332 10000000111011110100101010011010 source: 111001 changed: 0 step 333 10000000111001110100101010011010 source: 1101010010110 changed: 1 01 step 334 10000000111001110101101010010110 source: 0 changed: 0 step 335 10000000111001110100101010010110 source: 111000 changed: 0 step 336 10000000111000110100101010010110 source: 1101010010101 changed: 1 01 step 337 10000000111000110101101010010101 source: 0 changed: 0 step 338 10000000111000110100101010010101 source: 101000 changed: 0 step 339 10000000101000110100101010010101 source: 1100110010101 changed: 1 01 step 340 10000000101000110101100110010101 source: 0 changed: 0 step 341 10000000101000110100100110010101 source: 101001 changed: 1 step 342 10000000101001110100100110010101 source: 1100110010110 changed: 1 10 step 343 10000000101001110101100110010110 source: 0 changed: 0 step 344 10000000101001110100100110010110 source: 101011 changed: 1 step 345 10000000101011110100100110010110 source: 1100110011010 changed: 1 10 step 346 10000000101011110101100110011010 source: 0 changed: 0 step 347 10000000101011110100100110011010 source: 101010 changed: 0 step 348 10000000101010110100100110011010 source: 1100110011001 changed: 1 01 step 349 10000000101010110101100110011001 source: 0 changed: 0 step 350 10000000101010110100100110011001 source: 101110 changed: 1 step 351 10000000101110110100100110011001 source: 1100110101001 changed: 1 10 step 352 10000000101110110101100110101001 source: 0 changed: 0 step 353 10000000101110110100100110101001 source: 101111 changed: 1 step 354 10000000101111110100100110101001 source: 1100110101010 changed: 1 10 step 355 10000000101111110101100110101010 source: 0 changed: 0 step 356 10000000101111110100100110101010 source: 101101 changed: 0 step 357 10000000101101110100100110101010 source: 1100110100110 changed: 1 01 step 358 10000000101101110101100110100110 source: 0 changed: 0 step 359 10000000101101110100100110100110 source: 101100 changed: 0 step 360 10000000101100110100100110100110 source: 1100110100101 changed: 1 01 step 361 10000000101100110101100110100101 source: 0 changed: 0 step 362 10000000101100110100100110100101 source: 100100 changed: 0 step 363 10000000100100110100100110100101 source: 1100101100101 changed: 1 01 step 364 10000000100100110101100101100101 source: 0 changed: 0 step 365 10000000100100110100100101100101 source: 100101 changed: 1 step 366 10000000100101110100100101100101 source: 1100101100110 changed: 1 10 step 367 10000000100101110101100101100110 source: 0 changed: 0 step 368 10000000100101110100100101100110 source: 100111 changed: 1 step 369 10000000100111110100100101100110 source: 1100101101010 changed: 1 10 step 370 10000000100111110101100101101010 source: 0 changed: 0 step 371 10000000100111110100100101101010 source: 100110 changed: 0 step 372 10000000100110110100100101101010 source: 1100101101001 changed: 1 01 step 373 10000000100110110101100101101001 source: 0 changed: 0 step 374 10000000100110110100100101101001 source: 100010 changed: 0 step 375 10000000100010110100100101101001 source: 1100101011001 changed: 1 01 step 376 10000000100010110101100101011001 source: 0 changed: 0 step 377 10000000100010110100100101011001 source: 100011 changed: 1 step 378 10000000100011110100100101011001 source: 1100101011010 changed: 1 10 step 379 10000000100011110101100101011010 source: 0 changed: 0 step 380 10000000100011110100100101011010 source: 100001 changed: 0 step 381 10000000100001110100100101011010 source: 1100101010110 changed: 1 01 step 382 10000000100001110101100101010110 source: 0 changed: 0 step 383 10000000100001110100100101010110 source: 100000 changed: 0 step 384 10000000100000110100100101010110 source: 1100101010101 changed: 1 01 step 385 10000000100000110101100101010101 source: 0 changed: 0 step 386 10000000100000110100100101010101 source: 000000 changed: 0 step 387 10000000000000110100100101010101 source: 1010101010101 changed: 101 step 388 10000000000000110101010101010101 source: 0 changed: 0 step 389 10000000000000110100010101010101 source: source: ; DISABLE B INPUTS source: 0 changed: 0 step 390 10000000000000010100010101010101 source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 391 10000000000000000100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 1 step 392 10000010000000000100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 393 10000010000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 394 10000010000000001100010101010101 fail ^^ source: 1010101010101 changed: 1 step 395 10000010000000001101010101010101 source: 0 0 changed: 0 0 step 396 10000010000000000100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 step 397 10000110000000000100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 398 10000110000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 399 10000110000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 400 10000110000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 401 10000110000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 0 step 402 10000100000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 403 10000100000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 404 10000100000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 405 10000100000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 406 10000100000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 407 10001101000000000100010101010101 fail ^^ source: 1010101101001 changed: 1 1010 step 408 10001101000000000101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 409 10000100000000001100010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 01 10 step 410 10000100000000001101010101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 411 10000100000000000100010101011010 fail ^ source: 0001111 changed: 1 11 step 412 10001111000000000100010101011010 source: 1010101101010 changed: 1 10 step 413 10001111000000000101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 414 10000110000000001100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 01 step 415 10000110000000001101010101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 416 10000110000000000100010101011010 fail ^ source: 0001011 changed: 10 1 step 417 10001011000000000100010101011010 source: 1010101100110 changed: 1 1001 step 418 10001011000000000101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 419 10000010000000001100010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 011001 step 420 10000010000000001101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 421 10000010000000000100010101011001 fail ^ source: 0001001 changed: 1 01 step 422 10001001000000000100010101011001 source: 1010101100101 changed: 1 1001 step 423 10001001000000000101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 424 10000000000000001100010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 0110 step 425 10000000000000001101010101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 426 10000000000000000100010101011001 fail ^ source: 0011001 changed: 11 1 step 427 10011001000000000100010101011001 source: 1010110100101 changed: 1 101001 step 428 10011001000000000101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 429 10010000000000001100010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 01 10 step 430 10010000000000001101010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 431 10010000000000000100010101101001 fail ^ source: 0011011 changed: 1 11 step 432 10011011000000000100010101101001 source: 1010110100110 changed: 1 10 0110 step 433 10011011000000000101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 434 10010010000000001100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 01 1001 step 435 10010010000000001101010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 436 10010010000000000100010101101001 fail ^ source: 0011111 changed: 11 1 step 437 10011111000000000100010101101001 source: 1010110101010 changed: 1 10 10 step 438 10011111000000000101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 439 10010110000000001100010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 01 step 440 10010110000000001101010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 441 10010110000000000100010101101010 fail ^ source: 0011101 changed: 1 01 step 442 10011101000000000100010101101010 source: 1010110101001 changed: 1 10 01 step 443 10011101000000000101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 444 10010100000000001100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 01 10 step 445 10010100000000001101010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 446 10010100000000000100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: step 447 10010100000000000100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 010101 step 448 10010100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 449 10010100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 450 10010100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 451 10010100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 1 step 452 10010110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 453 10010110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 454 10010110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 455 10010110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 456 10010110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 step 457 10010010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 458 10010010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 459 10010010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 460 10010010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 461 10010010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 0 step 462 10010000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 463 10010000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 464 10010000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 465 10010000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 466 10010000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 step 467 10110000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 468 10110000000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 469 10110000000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 470 10110000000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 471 10110000000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 1 step 472 10110010000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 473 10110010000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 474 10110010000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 475 10110010000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 476 10110010000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 step 477 10110110000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 478 10110110000000000101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 479 10110110000000001100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 480 10110110000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 481 10110110000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 0 step 482 10110100000000000100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 483 10110100000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 484 10110100000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 485 10110100000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 486 10110100000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 487 10111101000000000100010101010101 fail ^^^^ ^^ source: 1011010101001 changed: 1 10101010 step 488 10111101000000000101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 489 10110100000000001100011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 01 10 step 490 10110100000000001101010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 491 10110100000000000100010110101010 fail ^ source: 0111111 changed: 1 11 step 492 10111111000000000100010110101010 source: 1011010101010 changed: 1 10 step 493 10111111000000000101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 494 10110110000000001100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 01 step 495 10110110000000001101010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 496 10110110000000000100010110101010 fail ^ source: 0111011 changed: 10 1 step 497 10111011000000000100010110101010 source: 1011010100110 changed: 1 10 01 step 498 10111011000000000101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 499 10110010000000001100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 01 1001 step 500 10110010000000001101010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 501 10110010000000000100010110101001 fail ^ source: 0111001 changed: 1 01 step 502 10111001000000000100010110101001 source: 1011010100101 changed: 1 10 01 step 503 10111001000000000101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 504 10110000000000001100011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 01 10 step 505 10110000000000001101010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 506 10110000000000000100010110101001 fail ^ source: 0101001 changed: 01 1 step 507 10101001000000000100010110101001 source: 1011001100101 changed: 1 1001 01 step 508 10101001000000000101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 509 10100000000000001100011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 01100110 step 510 10100000000000001101010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 511 10100000000000000100010110011001 fail ^ source: 0101011 changed: 1 11 step 512 10101011000000000100010110011001 source: 1011001100110 changed: 1 1001100110 step 513 10101011000000000101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 514 10100010000000001100011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 0110011001 step 515 10100010000000001101010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 516 10100010000000000100010110011001 fail ^ source: 0101111 changed: 11 1 step 517 10101111000000000100010110011001 source: 1011001101010 changed: 1 100110 10 step 518 10101111000000000101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 519 10100110000000001100011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 011001 step 520 10100110000000001101010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 521 10100110000000000100010110011010 fail ^ source: 0101101 changed: 1 01 step 522 10101101000000000100010110011010 source: 1011001101001 changed: 1 100110 01 step 523 10101101000000000101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 524 10100100000000001100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 011001 10 step 525 10100100000000001101010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 526 10100100000000000100010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: step 527 10100100000000000100010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 01 0101 step 528 10100100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 529 10100100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 530 10100100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 531 10100100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 1 step 532 10100110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 533 10100110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 534 10100110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 535 10100110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 536 10100110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 step 537 10100010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 538 10100010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 539 10100010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 540 10100010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 541 10100010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 0 step 542 10100000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 543 10100000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 544 10100000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 545 10100000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 546 10100000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 step 547 11100000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 548 11100000000000000101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 549 11100000000000001100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 550 11100000000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 551 11100000000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 1 step 552 11100010000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 553 11100010000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 554 11100010000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 555 11100010000000001101010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 556 11100010000000000100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 step 557 11100110000000000100010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 558 11100110000000000101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 559 11100110000000001100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 560 11100110000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 561 11100110000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 0 step 562 11100100000000000100010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 563 11100100000000000101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 564 11100100000000001100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 565 11100100000000001101010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 566 11100100000000000100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 567 11101101000000000100010101010101 fail ^^^^ ^^ source: 1101001101001 changed: 11010 1010 step 568 11101101000000000101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 569 11100100000000001100101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 101 1001 10 step 570 11100100000000001101011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 571 11100100000000000100011010011010 fail ^ source: 1101111 changed: 1 11 step 572 11101111000000000100011010011010 source: 1101001101010 changed: 110 0110 step 573 11101111000000000101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 574 11100110000000001100101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 101 1001 step 575 11100110000000001101011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 576 11100110000000000100011010011010 fail ^ source: 1101011 changed: 10 1 step 577 11101011000000000100011010011010 source: 1101001100110 changed: 110 011001 step 578 11101011000000000101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 579 11100010000000001100101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 101 10011001 step 580 11100010000000001101011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 581 11100010000000000100011010011001 fail ^ source: 1101001 changed: 1 01 step 582 11101001000000000100011010011001 source: 1101001100101 changed: 110 011001 step 583 11101001000000000101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 584 11100000000000001100101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 101 100110 step 585 11100000000000001101011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 586 11100000000000000100011010011001 fail ^ source: 1111001 changed: 11 1 step 587 11111001000000000100011010011001 source: 1101010100101 changed: 110 1001 step 588 11111001000000000101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 589 11110000000000001100101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 101 10 step 590 11110000000000001101011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 591 11110000000000000100011010101001 fail ^ source: 1111011 changed: 1 11 step 592 11111011000000000100011010101001 source: 1101010100110 changed: 110 0110 step 593 11111011000000000101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 594 11110010000000001100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 101 1001 step 595 11110010000000001101011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 596 11110010000000000100011010101001 fail ^ source: 1111111 changed: 11 1 step 597 11111111000000000100011010101001 source: 1101010101010 changed: 110 10 step 598 11111111000000000101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 599 11110110000000001100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 101 step 600 11110110000000001101011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 601 11110110000000000100011010101010 fail ^ source: 1111101 changed: 1 01 step 602 11111101000000000100011010101010 source: 1101010101001 changed: 110 01 step 603 11111101000000000101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 604 11110100000000001100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 101 10 step 605 11110100000000001101011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 606 11110100000000000100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: step 607 11110100000000000100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 0101010101 step 608 11110100000000000101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 609 11110100000000001100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 610 11110100000000001101010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 611 11110100000000000100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 1 step 612 11110110000000000100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 613 11110110000000000101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 614 11110110000000001100010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 615 11110110000000001101010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 616 11110110000000000100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 step 617 11110010000000000100010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 618 11110010000000000101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 619 11110010000000001100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 620 11110010000000001101010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 621 11110010000000000100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 0 step 622 11110000000000000100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 623 11110000000000000101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 624 11110000000000001100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 625 11110000000000001101010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 626 11110000000000000100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 step 627 11010000000000000100010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 628 11010000000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 629 11010000000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 630 11010000000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 631 11010000000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 1 step 632 11010010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 633 11010010000000000101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 634 11010010000000001100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 635 11010010000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 636 11010010000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 step 637 11010110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 638 11010110000000000101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 639 11010110000000001100010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 640 11010110000000001101010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 641 11010110000000000100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 0 step 642 11010100000000000100010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 643 11010100000000000101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 644 11010100000000001100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 645 11010100000000001101010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 646 11010100000000000100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 647 11011101000000000100010101010101 fail ^^ ^^ ^^ source: 1100110101001 changed: 110 101010 step 648 11011101000000000101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 649 11010100000000001100100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1011001 10 step 650 11010100000000001101011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 651 11010100000000000100011001101010 fail ^ source: 1011111 changed: 1 11 step 652 11011111000000000100011001101010 source: 1100110101010 changed: 1100110 step 653 11011111000000000101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 654 11010110000000001100100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1011001 step 655 11010110000000001101011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 656 11010110000000000100011001101010 fail ^ source: 1011011 changed: 10 1 step 657 11011011000000000100011001101010 source: 1100110100110 changed: 1100110 01 step 658 11011011000000000101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 659 11010010000000001100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1011001 1001 step 660 11010010000000001101011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 661 11010010000000000100011001101001 fail ^ source: 1011001 changed: 1 01 step 662 11011001000000000100011001101001 source: 1100110100101 changed: 1100110 01 step 663 11011001000000000101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 664 11010000000000001100100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1011001 10 step 665 11010000000000001101011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 666 11010000000000000100011001101001 fail ^ source: 1001001 changed: 01 1 step 667 11001001000000000100011001101001 source: 1100101100101 changed: 11001 01 step 668 11001001000000000101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 669 11000000000000001100100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 10110 0110 step 670 11000000000000001101011001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 671 11000000000000000100011001011001 fail ^ source: 1001011 changed: 1 11 step 672 11001011000000000100011001011001 source: 1100101100110 changed: 11001 100110 step 673 11001011000000000101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 674 11000010000000001100100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 10110 011001 step 675 11000010000000001101011001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 676 11000010000000000100011001011001 fail ^ source: 1001111 changed: 11 1 step 677 11001111000000000100011001011001 source: 1100101101010 changed: 11001 10 10 step 678 11001111000000000101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 679 11000110000000001100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 10110 01 step 680 11000110000000001101011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 681 11000110000000000100011001011010 fail ^ source: 1001101 changed: 1 01 step 682 11001101000000000100011001011010 source: 1100101101001 changed: 11001 10 01 step 683 11001101000000000101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 684 11000100000000001100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 10110 01 10 step 685 11000100000000001101011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 686 11000100000000000100011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: step 687 11000100000000000100011001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 01 0101 step 688 11000100000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 689 11000100000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 690 11000100000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 691 11000100000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 1 step 692 11000110000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 693 11000110000000000101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 694 11000110000000001100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 695 11000110000000001101010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 696 11000110000000000100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 step 697 11000010000000000100010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 698 11000010000000000101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 699 11000010000000001100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 700 11000010000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 701 11000010000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 0 step 702 11000000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 703 11000000000000000101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 704 11000000000000001100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 705 11000000000000001101010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 706 11000000000000000100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 step 707 10000000000000000100010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 708 10000000000000000101010101010101 fail ^ source: 0 1 0 changed: 1 0 step 709 10000000000000001100010101010101 source: 1010101010101 changed: 1 step 710 10000000000000001101010101010101 source: 0 0 changed: 0 0 step 711 10000000000000000100010101010101 source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 712 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 1 step 713 10000010000000010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 714 10000010000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 715 10000010000000011100010101010101 fail ^^ source: 1100101010101 changed: 110 step 716 10000010000000011101100101010101 source: 0 0 changed: 0 0 step 717 10000010000000010100100101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 step 718 10000110000000010100100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 101 step 719 10000110000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 720 10000110000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 110 step 721 10000110000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 722 10000110000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 0 step 723 10000100000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 101 step 724 10000100000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 725 10000100000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 110 step 726 10000100000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 727 10000100000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 728 10001101000000010100100101010101 fail ^^ source: 1010101101001 changed: 101 1010 step 729 10001101000000010101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 730 10000100000000011100010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 110 01 10 step 731 10000100000000011101100101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 732 10000100000000010100100101011010 fail ^ source: 0001111 changed: 1 11 step 733 10001111000000010100100101011010 source: 1010101101010 changed: 101 10 step 734 10001111000000010101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 735 10000110000000011100010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 110 01 step 736 10000110000000011101100101011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 737 10000110000000010100100101011010 fail ^ source: 0001011 changed: 10 1 step 738 10001011000000010100100101011010 source: 1010101100110 changed: 101 1001 step 739 10001011000000010101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 740 10000010000000011100010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 110 011001 step 741 10000010000000011101100101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 742 10000010000000010100100101011001 fail ^ source: 0001001 changed: 1 01 step 743 10001001000000010100100101011001 source: 1010101100101 changed: 101 1001 step 744 10001001000000010101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 745 10000000000000011100010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 110 0110 step 746 10000000000000011101100101011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 747 10000000000000010100100101011001 fail ^ source: 0011001 changed: 11 1 step 748 10011001000000010100100101011001 source: 1010110100101 changed: 101 101001 step 749 10011001000000010101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 750 10010000000000011100010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 110 01 10 step 751 10010000000000011101100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 752 10010000000000010100100101101001 fail ^ source: 0011011 changed: 1 11 step 753 10011011000000010100100101101001 source: 1010110100110 changed: 101 10 0110 step 754 10011011000000010101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 755 10010010000000011100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 110 01 1001 step 756 10010010000000011101100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 757 10010010000000010100100101101001 fail ^ source: 0011111 changed: 11 1 step 758 10011111000000010100100101101001 source: 1010110101010 changed: 101 10 10 step 759 10011111000000010101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 760 10010110000000011100010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 110 01 step 761 10010110000000011101100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 762 10010110000000010100100101101010 fail ^ source: 0011101 changed: 1 01 step 763 10011101000000010100100101101010 source: 1010110101001 changed: 101 10 01 step 764 10011101000000010101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 765 10010100000000011100010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 110 01 10 step 766 10010100000000011101100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 767 10010100000000010100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: step 768 10010100000000010100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 101 010101 step 769 10010100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 770 10010100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 110 step 771 10010100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 772 10010100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 1 step 773 10010110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 101 step 774 10010110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 775 10010110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 110 step 776 10010110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 777 10010110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 step 778 10010010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 101 step 779 10010010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 780 10010010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 110 step 781 10010010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 782 10010010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 0 step 783 10010000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 101 step 784 10010000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 785 10010000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 110 step 786 10010000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 787 10010000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 step 788 10110000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 101 step 789 10110000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 790 10110000000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 110 step 791 10110000000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 792 10110000000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 1 step 793 10110010000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 101 step 794 10110010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 795 10110010000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 110 step 796 10110010000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 797 10110010000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 step 798 10110110000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 101 step 799 10110110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 800 10110110000000011100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 110 step 801 10110110000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 802 10110110000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 0 step 803 10110100000000010100100101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 101 step 804 10110100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 805 10110100000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 110 step 806 10110100000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 807 10110100000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 808 10111101000000010100100101010101 fail ^^^^ ^^ source: 1011010101001 changed: 10110101010 step 809 10111101000000010101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 810 10110100000000011100011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 11001 10 step 811 10110100000000011101100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 812 10110100000000010100100110101010 fail ^ source: 0111111 changed: 1 11 step 813 10111111000000010100100110101010 source: 1011010101010 changed: 10110 step 814 10111111000000010101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 815 10110110000000011100011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 11001 step 816 10110110000000011101100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 817 10110110000000010100100110101010 fail ^ source: 0111011 changed: 10 1 step 818 10111011000000010100100110101010 source: 1011010100110 changed: 10110 01 step 819 10111011000000010101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 820 10110010000000011100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 11001 1001 step 821 10110010000000011101100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 822 10110010000000010100100110101001 fail ^ source: 0111001 changed: 1 01 step 823 10111001000000010100100110101001 source: 1011010100101 changed: 10110 01 step 824 10111001000000010101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 825 10110000000000011100011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 11001 10 step 826 10110000000000011101100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 827 10110000000000010100100110101001 fail ^ source: 0101001 changed: 01 1 step 828 10101001000000010100100110101001 source: 1011001100101 changed: 1011001 01 step 829 10101001000000010101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 830 10100000000000011100011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 11001100110 step 831 10100000000000011101100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 832 10100000000000010100100110011001 fail ^ source: 0101011 changed: 1 11 step 833 10101011000000010100100110011001 source: 1011001100110 changed: 1011001100110 step 834 10101011000000010101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 835 10100010000000011100011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110011001 step 836 10100010000000011101100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 837 10100010000000010100100110011001 fail ^ source: 0101111 changed: 11 1 step 838 10101111000000010100100110011001 source: 1011001101010 changed: 101100110 10 step 839 10101111000000010101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 840 10100110000000011100011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 110011001 step 841 10100110000000011101100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 842 10100110000000010100100110011010 fail ^ source: 0101101 changed: 1 01 step 843 10101101000000010100100110011010 source: 1011001101001 changed: 101100110 01 step 844 10101101000000010101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 845 10100100000000011100011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 110011001 10 step 846 10100100000000011101100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 847 10100100000000010100100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: step 848 10100100000000010100100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 101 01 0101 step 849 10100100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 850 10100100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 110 step 851 10100100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 852 10100100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 1 step 853 10100110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 101 step 854 10100110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 855 10100110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 110 step 856 10100110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 857 10100110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 step 858 10100010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 101 step 859 10100010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 860 10100010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 110 step 861 10100010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 862 10100010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 0 step 863 10100000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 101 step 864 10100000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 865 10100000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 110 step 866 10100000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 867 10100000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 step 868 11100000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 101 step 869 11100000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 870 11100000000000011100010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 110 step 871 11100000000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 872 11100000000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 1 step 873 11100010000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 101 step 874 11100010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 875 11100010000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 110 step 876 11100010000000011101100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 877 11100010000000010100100101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 step 878 11100110000000010100100101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 101 step 879 11100110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 880 11100110000000011100010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 110 step 881 11100110000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 882 11100110000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 0 step 883 11100100000000010100100101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 101 step 884 11100100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 885 11100100000000011100010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 110 step 886 11100100000000011101100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 887 11100100000000010100100101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 888 11101101000000010100100101010101 fail ^^^^ ^^ source: 1101001101001 changed: 1 10 1010 step 889 11101101000000010101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 890 11100100000000011100101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 1001 10 step 891 11100100000000011101101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 892 11100100000000010100101010011010 fail ^ source: 1101111 changed: 1 11 step 893 11101111000000010100101010011010 source: 1101001101010 changed: 1 0110 step 894 11101111000000010101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 895 11100110000000011100101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 1001 step 896 11100110000000011101101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 897 11100110000000010100101010011010 fail ^ source: 1101011 changed: 10 1 step 898 11101011000000010100101010011010 source: 1101001100110 changed: 1 011001 step 899 11101011000000010101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 900 11100010000000011100101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 10011001 step 901 11100010000000011101101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 902 11100010000000010100101010011001 fail ^ source: 1101001 changed: 1 01 step 903 11101001000000010100101010011001 source: 1101001100101 changed: 1 011001 step 904 11101001000000010101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 905 11100000000000011100101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 100110 step 906 11100000000000011101101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 907 11100000000000010100101010011001 fail ^ source: 1111001 changed: 11 1 step 908 11111001000000010100101010011001 source: 1101010100101 changed: 1 1001 step 909 11111001000000010101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 910 11110000000000011100101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 10 step 911 11110000000000011101101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 912 11110000000000010100101010101001 fail ^ source: 1111011 changed: 1 11 step 913 11111011000000010100101010101001 source: 1101010100110 changed: 1 0110 step 914 11111011000000010101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 915 11110010000000011100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 1001 step 916 11110010000000011101101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 917 11110010000000010100101010101001 fail ^ source: 1111111 changed: 11 1 step 918 11111111000000010100101010101001 source: 1101010101010 changed: 1 10 step 919 11111111000000010101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 920 11110110000000011100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 921 11110110000000011101101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 922 11110110000000010100101010101010 fail ^ source: 1111101 changed: 1 01 step 923 11111101000000010100101010101010 source: 1101010101001 changed: 1 01 step 924 11111101000000010101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 925 11110100000000011100101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 10 step 926 11110100000000011101101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 927 11110100000000010100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: step 928 11110100000000010100101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1010101010101 step 929 11110100000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 930 11110100000000011100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 110 step 931 11110100000000011101100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 932 11110100000000010100100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 1 step 933 11110110000000010100100101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 101 step 934 11110110000000010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 935 11110110000000011100010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 110 step 936 11110110000000011101100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 937 11110110000000010100100101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 step 938 11110010000000010100100101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 101 step 939 11110010000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 940 11110010000000011100010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 110 step 941 11110010000000011101100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 942 11110010000000010100100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 0 step 943 11110000000000010100100101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 101 step 944 11110000000000010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 945 11110000000000011100010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 110 step 946 11110000000000011101100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 947 11110000000000010100100101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 step 948 11010000000000010100100101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 101 step 949 11010000000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 950 11010000000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 110 step 951 11010000000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 952 11010000000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 1 step 953 11010010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 101 step 954 11010010000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 955 11010010000000011100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 110 step 956 11010010000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 957 11010010000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 step 958 11010110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 101 step 959 11010110000000010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 960 11010110000000011100010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 110 step 961 11010110000000011101100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 962 11010110000000010100100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 0 step 963 11010100000000010100100101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 101 step 964 11010100000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 965 11010100000000011100010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 110 step 966 11010100000000011101100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 967 11010100000000010100100101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 968 11011101000000010100100101010101 fail ^^ ^^ ^^ source: 1100110101001 changed: 1 101010 step 969 11011101000000010101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 970 11010100000000011100100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 1001 10 step 971 11010100000000011101101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 972 11010100000000010100101001101010 fail ^ source: 1011111 changed: 1 11 step 973 11011111000000010100101001101010 source: 1100110101010 changed: 1 0110 step 974 11011111000000010101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 975 11010110000000011100100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 1001 step 976 11010110000000011101101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 977 11010110000000010100101001101010 fail ^ source: 1011011 changed: 10 1 step 978 11011011000000010100101001101010 source: 1100110100110 changed: 1 0110 01 step 979 11011011000000010101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 980 11010010000000011100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 1001 1001 step 981 11010010000000011101101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 982 11010010000000010100101001101001 fail ^ source: 1011001 changed: 1 01 step 983 11011001000000010100101001101001 source: 1100110100101 changed: 1 0110 01 step 984 11011001000000010101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 985 11010000000000011100100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 1001 10 step 986 11010000000000011101101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 987 11010000000000010100101001101001 fail ^ source: 1001001 changed: 01 1 step 988 11001001000000010100101001101001 source: 1100101100101 changed: 1 01 01 step 989 11001001000000010101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 990 11000000000000011100100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 10 0110 step 991 11000000000000011101101001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 992 11000000000000010100101001011001 fail ^ source: 1001011 changed: 1 11 step 993 11001011000000010100101001011001 source: 1100101100110 changed: 1 01 100110 step 994 11001011000000010101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 995 11000010000000011100100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 10 011001 step 996 11000010000000011101101001011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 997 11000010000000010100101001011001 fail ^ source: 1001111 changed: 11 1 step 998 11001111000000010100101001011001 source: 1100101101010 changed: 1 01 10 10 step 999 11001111000000010101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 1000 11000110000000011100100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 01 step 1001 11000110000000011101101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1002 11000110000000010100101001011010 fail ^ source: 1001101 changed: 1 01 step 1003 11001101000000010100101001011010 source: 1100101101001 changed: 1 01 10 01 step 1004 11001101000000010101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 0 1 0 step 1005 11000100000000011100100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 01 10 step 1006 11000100000000011101101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1007 11000100000000010100101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: step 1008 11000100000000010100101001011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 10101 0101 step 1009 11000100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 1010 11000100000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 110 step 1011 11000100000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1012 11000100000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 1 step 1013 11000110000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 101 step 1014 11000110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 1015 11000110000000011100010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 110 step 1016 11000110000000011101100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1017 11000110000000010100100101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 step 1018 11000010000000010100100101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 101 step 1019 11000010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 1020 11000010000000011100010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 110 step 1021 11000010000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1022 11000010000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 0 step 1023 11000000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 101 step 1024 11000000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 1 0 step 1025 11000000000000011100010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 110 step 1026 11000000000000011101100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1027 11000000000000010100100101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 step 1028 10000000000000010100100101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 101 step 1029 10000000000000010101010101010101 fail ^ source: 0 1 0 changed: 1 0 step 1030 10000000000000011100010101010101 source: 1100101010101 changed: 110 step 1031 10000000000000011101100101010101 source: 0 0 changed: 0 0 step 1032 10000000000000010100100101010101 source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 1033 10000000000000010000100101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 1 step 1034 10000010000000010000100101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 101 step 1035 10000010000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1036 10000010000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 1037 10000010000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1038 10000010000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 step 1039 10000110000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 1040 10000110000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1041 10000110000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 1042 10000110000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1043 10000110000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 0 step 1044 10000100000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 1045 10000100000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1046 10000100000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 1047 10000100000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1048 10000100000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 1049 10001101000000010000010101010101 fail ^^ source: 1010101101001 changed: 1 1010 step 1050 10001101000000010001010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1051 10000100000000010010010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 10 01 step 1052 10000100000000010011010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1053 10000100000000010000010110100101 fail ^ source: 0001111 changed: 1 11 step 1054 10001111000000010000010110100101 source: 1010101101010 changed: 1 01 1010 step 1055 10001111000000010001010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1056 10000110000000010010010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 10 01 step 1057 10000110000000010011010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1058 10000110000000010000010110101001 fail ^ source: 0001011 changed: 10 1 step 1059 10001011000000010000010110101001 source: 1010101100110 changed: 1 01 0110 step 1060 10001011000000010001010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1061 10000010000000010010010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 10011001 step 1062 10000010000000010011010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1063 10000010000000010000010110011001 fail ^ source: 0001001 changed: 1 01 step 1064 10001001000000010000010110011001 source: 1010101100101 changed: 1 011001 step 1065 10001001000000010001010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1066 10000000000000010010010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 1001 step 1067 10000000000000010011010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1068 10000000000000010000010110010101 fail ^ source: 0011001 changed: 11 1 step 1069 10011001000000010000010110010101 source: 1010110100101 changed: 1 10 step 1070 10011001000000010001010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1071 10010000000000010010010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 10 01 step 1072 10010000000000010011011010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1073 10010000000000010000011010010101 fail ^ source: 0011011 changed: 1 11 step 1074 10011011000000010000011010010101 source: 1010110100110 changed: 1 01 10 10 step 1075 10011011000000010001010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1076 10010010000000010010010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 10 011001 step 1077 10010010000000010011011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1078 10010010000000010000011010011001 fail ^ source: 0011111 changed: 11 1 step 1079 10011111000000010000011010011001 source: 1010110101010 changed: 1 01 10 10 step 1080 10011111000000010001010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1081 10010110000000010010010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 10 01 step 1082 10010110000000010011011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1083 10010110000000010000011010101001 fail ^ source: 0011101 changed: 1 01 step 1084 10011101000000010000011010101001 source: 1010110101001 changed: 1 01 step 1085 10011101000000010001010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1086 10010100000000010010010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 10 01 step 1087 10010100000000010011011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1088 10010100000000010000011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: step 1089 10010100000000010000011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 010101 step 1090 10010100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1091 10010100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 1092 10010100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1093 10010100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 1 step 1094 10010110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 1095 10010110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1096 10010110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 1097 10010110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1098 10010110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 step 1099 10010010000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 1100 10010010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1101 10010010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 1102 10010010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1103 10010010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 0 step 1104 10010000000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 1105 10010000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1106 10010000000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 1107 10010000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1108 10010000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 step 1109 10110000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 1110 10110000000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1111 10110000000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1112 10110000000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1113 10110000000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 1 step 1114 10110010000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 1115 10110010000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1116 10110010000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 1117 10110010000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1118 10110010000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 step 1119 10110110000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 1120 10110110000000010001010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1121 10110110000000010010010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 1122 10110110000000010011010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1123 10110110000000010000010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 0 step 1124 10110100000000010000010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 1125 10110100000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1126 10110100000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 1127 10110100000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1128 10110100000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 1129 10111101000000010000010101010101 fail ^^^^ ^^ source: 1011010101001 changed: 1 10101010 step 1130 10111101000000010001011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1131 10110100000000010010011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 110 01 step 1132 10110100000000010011101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1133 10110100000000010000101010100101 fail ^ source: 0111111 changed: 1 11 step 1134 10111111000000010000101010100101 source: 1011010101010 changed: 101 1010 step 1135 10111111000000010001011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1136 10110110000000010010011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 110 01 step 1137 10110110000000010011101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1138 10110110000000010000101010101001 fail ^ source: 0111011 changed: 10 1 step 1139 10111011000000010000101010101001 source: 1011010100110 changed: 101 0110 step 1140 10111011000000010001011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1141 10110010000000010010011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 110 011001 step 1142 10110010000000010011101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1143 10110010000000010000101010011001 fail ^ source: 0111001 changed: 1 01 step 1144 10111001000000010000101010011001 source: 1011010100101 changed: 101 1001 step 1145 10111001000000010001011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1146 10110000000000010010011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 110 01 step 1147 10110000000000010011101010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1148 10110000000000010000101010010101 fail ^ source: 0101001 changed: 01 1 step 1149 10101001000000010000101010010101 source: 1011001100101 changed: 101 0110 step 1150 10101001000000010001011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1151 10100000000000010010011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 110011001 step 1152 10100000000000010011100110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1153 10100000000000010000100110010101 fail ^ source: 0101011 changed: 1 11 step 1154 10101011000000010000100110010101 source: 1011001100110 changed: 101100110 10 step 1155 10101011000000010001011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1156 10100010000000010010011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110011001 step 1157 10100010000000010011100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1158 10100010000000010000100110011001 fail ^ source: 0101111 changed: 11 1 step 1159 10101111000000010000100110011001 source: 1011001101010 changed: 101100110 10 step 1160 10101111000000010001011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1161 10100110000000010010011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1100110 01 step 1162 10100110000000010011100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1163 10100110000000010000100110101001 fail ^ source: 0101101 changed: 1 01 step 1164 10101101000000010000100110101001 source: 1011001101001 changed: 1011001 step 1165 10101101000000010001011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1166 10100100000000010010011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1100110 01 step 1167 10100100000000010011100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1168 10100100000000010000100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: step 1169 10100100000000010000100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 101 0101 step 1170 10100100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1171 10100100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 1172 10100100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1173 10100100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 1 step 1174 10100110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 1175 10100110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1176 10100110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 1177 10100110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1178 10100110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 step 1179 10100010000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 1180 10100010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1181 10100010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 1182 10100010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1183 10100010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 0 step 1184 10100000000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 1185 10100000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1186 10100000000000010010010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1187 10100000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1188 10100000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 step 1189 11100000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1190 11100000000000010001010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1191 11100000000000010010010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1192 11100000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1193 11100000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 1 step 1194 11100010000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 1195 11100010000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1196 11100010000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 1197 11100010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1198 11100010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 step 1199 11100110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 1200 11100110000000010001010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1201 11100110000000010010010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 1202 11100110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1203 11100110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 0 step 1204 11100100000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 1205 11100100000000010001010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1206 11100100000000010010010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 1207 11100100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1208 11100100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 1209 11101101000000010000010101010101 fail ^^ ^^ source: 1101001101001 changed: 11010 1010 step 1210 11101101000000010001101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1211 11100100000000010010101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 0110 01 step 1212 11100100000000010011100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1213 11100100000000010000100110100101 fail ^ source: 1101111 changed: 1 11 step 1214 11101111000000010000100110100101 source: 1101001101010 changed: 1 1001 1010 step 1215 11101111000000010001101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1216 11100110000000010010101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 0110 01 step 1217 11100110000000010011100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1218 11100110000000010000100110101001 fail ^ source: 1101011 changed: 10 1 step 1219 11101011000000010000100110101001 source: 1101001100110 changed: 1 1001 0110 step 1220 11101011000000010001101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1221 11100010000000010010101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 0110011001 step 1222 11100010000000010011100110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1223 11100010000000010000100110011001 fail ^ source: 1101001 changed: 1 01 step 1224 11101001000000010000100110011001 source: 1101001100101 changed: 1 10011001 step 1225 11101001000000010001101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1226 11100000000000010010101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 011001 step 1227 11100000000000010011100110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1228 11100000000000010000100110010101 fail ^ source: 1111001 changed: 11 1 step 1229 11111001000000010000100110010101 source: 1101010100101 changed: 1 10 10 step 1230 11111001000000010001101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1231 11110000000000010010101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 01 step 1232 11110000000000010011101010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1233 11110000000000010000101010010101 fail ^ source: 1111011 changed: 1 11 step 1234 11111011000000010000101010010101 source: 1101010100110 changed: 1 10 10 step 1235 11111011000000010001101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1236 11110010000000010010101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 011001 step 1237 11110010000000010011101010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1238 11110010000000010000101010011001 fail ^ source: 1111111 changed: 11 1 step 1239 11111111000000010000101010011001 source: 1101010101010 changed: 1 10 10 step 1240 11111111000000010001101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1241 11110110000000010010101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 01 step 1242 11110110000000010011101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1243 11110110000000010000101010101001 fail ^ source: 1111101 changed: 1 01 step 1244 11111101000000010000101010101001 source: 1101010101001 changed: 1 step 1245 11111101000000010001101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1246 11110100000000010010101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 01 step 1247 11110100000000010011101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1248 11110100000000010000101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: step 1249 11110100000000010000101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 101010101 step 1250 11110100000000010001010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1251 11110100000000010010010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 1252 11110100000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1253 11110100000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 1 step 1254 11110110000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 1255 11110110000000010001010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1256 11110110000000010010010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 1257 11110110000000010011010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1258 11110110000000010000010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 step 1259 11110010000000010000010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 1260 11110010000000010001010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1261 11110010000000010010010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 1262 11110010000000010011010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1263 11110010000000010000010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 0 step 1264 11110000000000010000010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 1265 11110000000000010001010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1266 11110000000000010010010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1267 11110000000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1268 11110000000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 step 1269 11010000000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 1270 11010000000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1271 11010000000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 1272 11010000000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1273 11010000000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 1 step 1274 11010010000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 1275 11010010000000010001010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1276 11010010000000010010010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 1277 11010010000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1278 11010010000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 step 1279 11010110000000010000010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 1280 11010110000000010001010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1281 11010110000000010010010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 1282 11010110000000010011010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1283 11010110000000010000010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 0 step 1284 11010100000000010000010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 1285 11010100000000010001010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1286 11010100000000010010010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 1287 11010100000000010011010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1288 11010100000000010000010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 1289 11011101000000010000010101010101 fail ^^ ^^ source: 1100110101001 changed: 110 101010 step 1290 11011101000000010001100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1291 11010100000000010010100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 10110 01 step 1292 11010100000000010011011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1293 11010100000000010000011010100101 fail ^ source: 1011111 changed: 1 11 step 1294 11011111000000010000011010100101 source: 1100110101010 changed: 11001 1010 step 1295 11011111000000010001100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1296 11010110000000010010100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 10110 01 step 1297 11010110000000010011011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1298 11010110000000010000011010101001 fail ^ source: 1011011 changed: 10 1 step 1299 11011011000000010000011010101001 source: 1100110100110 changed: 11001 0110 step 1300 11011011000000010001100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1301 11010010000000010010100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 10110 011001 step 1302 11010010000000010011011010011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1303 11010010000000010000011010011001 fail ^ source: 1011001 changed: 1 01 step 1304 11011001000000010000011010011001 source: 1100110100101 changed: 11001 1001 step 1305 11011001000000010001100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1306 11010000000000010010100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 10110 01 step 1307 11010000000000010011011010010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1308 11010000000000010000011010010101 fail ^ source: 1001001 changed: 01 1 step 1309 11001001000000010000011010010101 source: 1100101100101 changed: 110010110 step 1310 11001001000000010001100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1311 11000000000000010010100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 101 1001 step 1312 11000000000000010011010110010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1313 11000000000000010000010110010101 fail ^ source: 1001011 changed: 1 11 step 1314 11001011000000010000010110010101 source: 1100101100110 changed: 110 0110 10 step 1315 11001011000000010001100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1316 11000010000000010010100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 101 10011001 step 1317 11000010000000010011010110011001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1318 11000010000000010000010110011001 fail ^ source: 1001111 changed: 11 1 step 1319 11001111000000010000010110011001 source: 1100101101010 changed: 110 0110 10 step 1320 11001111000000010001100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1321 11000110000000010010100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 101 10 01 step 1322 11000110000000010011010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1323 11000110000000010000010110101001 fail ^ source: 1001101 changed: 1 01 step 1324 11001101000000010000010110101001 source: 1100101101001 changed: 110 01 step 1325 11001101000000010001100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1326 11000100000000010010100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 101 10 01 step 1327 11000100000000010011010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1328 11000100000000010000010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: step 1329 11000100000000010000010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 0101 step 1330 11000100000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1331 11000100000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 1332 11000100000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1333 11000100000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 1 step 1334 11000110000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 1335 11000110000000010001010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1336 11000110000000010010010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 1337 11000110000000010011010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1338 11000110000000010000010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 step 1339 11000010000000010000010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 1340 11000010000000010001010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1341 11000010000000010010010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 1342 11000010000000010011010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1343 11000010000000010000010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 0 step 1344 11000000000000010000010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1345 11000000000000010001010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1346 11000000000000010010010101010101 fail ^^ source: 1010101010101 changed: 1 step 1347 11000000000000010011010101010101 source: 00 changed: 00 step 1348 11000000000000010000010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 step 1349 10000000000000010000010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 1350 10000000000000010001010101010101 fail ^ source: 0 10 changed: 10 step 1351 10000000000000010010010101010101 source: 1010101010101 changed: 1 step 1352 10000000000000010011010101010101 source: 00 changed: 00 step 1353 10000000000000010000010101010101 source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 1354 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 1 step 1355 10000010000000010100010101010101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 1356 10000010000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1357 10000010000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 10 step 1358 10000010000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1359 10000010000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 step 1360 10000110000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 01 step 1361 10000110000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1362 10000110000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 10 step 1363 10000110000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1364 10000110000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 0 step 1365 10000100000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 01 step 1366 10000100000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1367 10000100000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 10 step 1368 10000100000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1369 10000100000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 1370 10001101000000010100010101010110 fail ^^ source: 1010101101001 changed: 1 101001 step 1371 10001101000000010101010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1372 10000100000000010110010101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 10 0110 step 1373 10000100000000010111010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1374 10000100000000010100010110100110 fail ^ source: 0001111 changed: 1 11 step 1375 10001111000000010100010110100110 source: 1010101101010 changed: 1 01 10 step 1376 10001111000000010101010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1377 10000110000000010110010101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 10 step 1378 10000110000000010111010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1379 10000110000000010100010110101010 fail ^ source: 0001011 changed: 10 1 step 1380 10001011000000010100010110101010 source: 1010101100110 changed: 1 01 01 step 1381 10001011000000010101010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1382 10000010000000010110010101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 100110 step 1383 10000010000000010111010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1384 10000010000000010100010110011010 fail ^ source: 0001001 changed: 1 01 step 1385 10001001000000010100010110011010 source: 1010101100101 changed: 1 01100101 step 1386 10001001000000010101010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1387 10000000000000010110010101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 1001 10 step 1388 10000000000000010111010110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1389 10000000000000010100010110010110 fail ^ source: 0011001 changed: 11 1 step 1390 10011001000000010100010110010110 source: 1010110100101 changed: 1 10 01 step 1391 10011001000000010101010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1392 10010000000000010110010110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 10 01 10 step 1393 10010000000000010111011010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1394 10010000000000010100011010010110 fail ^ source: 0011011 changed: 1 11 step 1395 10011011000000010100011010010110 source: 1010110100110 changed: 1 01 10 step 1396 10011011000000010101010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1397 10010010000000010110010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 10 0110 step 1398 10010010000000010111011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1399 10010010000000010100011010011010 fail ^ source: 0011111 changed: 11 1 step 1400 10011111000000010100011010011010 source: 1010110101010 changed: 1 01 10 step 1401 10011111000000010101010110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1402 10010110000000010110010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 10 step 1403 10010110000000010111011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1404 10010110000000010100011010101010 fail ^ source: 0011101 changed: 1 01 step 1405 10011101000000010100011010101010 source: 1010110101001 changed: 1 01 01 step 1406 10011101000000010101010110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1407 10010100000000010110010110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 10 0110 step 1408 10010100000000010111011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1409 10010100000000010100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: step 1410 10010100000000010100011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 010101 01 step 1411 10010100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1412 10010100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 10 step 1413 10010100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1414 10010100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 1 step 1415 10010110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 01 step 1416 10010110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1417 10010110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 10 step 1418 10010110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1419 10010110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 step 1420 10010010000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 01 step 1421 10010010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1422 10010010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 10 step 1423 10010010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1424 10010010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 0 step 1425 10010000000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 01 step 1426 10010000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1427 10010000000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 10 step 1428 10010000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1429 10010000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 step 1430 10110000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 01 step 1431 10110000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1432 10110000000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 10 step 1433 10110000000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1434 10110000000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 1 step 1435 10110010000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 01 step 1436 10110010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1437 10110010000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 step 1438 10110010000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1439 10110010000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 step 1440 10110110000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 01 step 1441 10110110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1442 10110110000000010110010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 10 step 1443 10110110000000010111010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1444 10110110000000010100010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 0 step 1445 10110100000000010100010101010110 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 01 step 1446 10110100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1447 10110100000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 10 step 1448 10110100000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1449 10110100000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 1450 10111101000000010100010101010110 fail ^^^^ ^^ source: 1011010101001 changed: 1 1010101001 step 1451 10111101000000010101011010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1452 10110100000000010110011010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 110 0110 step 1453 10110100000000010111101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1454 10110100000000010100101010100110 fail ^ source: 0111111 changed: 1 11 step 1455 10111111000000010100101010100110 source: 1011010101010 changed: 101 10 step 1456 10111111000000010101011010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1457 10110110000000010110011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 110 step 1458 10110110000000010111101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1459 10110110000000010100101010101010 fail ^ source: 0111011 changed: 10 1 step 1460 10111011000000010100101010101010 source: 1011010100110 changed: 101 01 step 1461 10111011000000010101011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1462 10110010000000010110011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 110 0110 step 1463 10110010000000010111101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1464 10110010000000010100101010011010 fail ^ source: 0111001 changed: 1 01 step 1465 10111001000000010100101010011010 source: 1011010100101 changed: 101 100101 step 1466 10111001000000010101011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1467 10110000000000010110011010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 110 01 10 step 1468 10110000000000010111101010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1469 10110000000000010100101010010110 fail ^ source: 0101001 changed: 01 1 step 1470 10101001000000010100101010010110 source: 1011001100101 changed: 101 0110 01 step 1471 10101001000000010101011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1472 10100000000000010110011001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 110011001 10 step 1473 10100000000000010111100110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1474 10100000000000010100100110010110 fail ^ source: 0101011 changed: 1 11 step 1475 10101011000000010100100110010110 source: 1011001100110 changed: 101100110 step 1476 10101011000000010101011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1477 10100010000000010110011001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 11001100110 step 1478 10100010000000010111100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1479 10100010000000010100100110011010 fail ^ source: 0101111 changed: 11 1 step 1480 10101111000000010100100110011010 source: 1011001101010 changed: 101100110 step 1481 10101111000000010101011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1482 10100110000000010110011001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1100110 step 1483 10100110000000010111100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1484 10100110000000010100100110101010 fail ^ source: 0101101 changed: 1 01 step 1485 10101101000000010100100110101010 source: 1011001101001 changed: 1011001 01 step 1486 10101101000000010101011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1487 10100100000000010110011001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1100110 0110 step 1488 10100100000000010111100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1489 10100100000000010100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: step 1490 10100100000000010100100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 101 0101 01 step 1491 10100100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1492 10100100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 10 step 1493 10100100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1494 10100100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 1 step 1495 10100110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 01 step 1496 10100110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1497 10100110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 10 step 1498 10100110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1499 10100110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 step 1500 10100010000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 01 step 1501 10100010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1502 10100010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 10 step 1503 10100010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1504 10100010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 0 step 1505 10100000000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 01 step 1506 10100000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1507 10100000000000010110010101010101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 10 step 1508 10100000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1509 10100000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 step 1510 11100000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 01 step 1511 11100000000000010101010101010101 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1512 11100000000000010110010101010101 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 10 step 1513 11100000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1514 11100000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 1 step 1515 11100010000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 01 step 1516 11100010000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1517 11100010000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 10 step 1518 11100010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1519 11100010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 step 1520 11100110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 01 step 1521 11100110000000010101010101010101 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1522 11100110000000010110010101010101 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 10 step 1523 11100110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1524 11100110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 0 step 1525 11100100000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 01 step 1526 11100100000000010101010101010101 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1527 11100100000000010110010101010101 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 10 step 1528 11100100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1529 11100100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 1530 11101101000000010100010101010110 fail ^^ ^^ source: 1101001101001 changed: 11010 101001 step 1531 11101101000000010101101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1532 11100100000000010110101001101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 0110 0110 step 1533 11100100000000010111100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1534 11100100000000010100100110100110 fail ^ source: 1101111 changed: 1 11 step 1535 11101111000000010100100110100110 source: 1101001101010 changed: 1 1001 10 step 1536 11101111000000010101101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1537 11100110000000010110101001101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 0110 step 1538 11100110000000010111100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1539 11100110000000010100100110101010 fail ^ source: 1101011 changed: 10 1 step 1540 11101011000000010100100110101010 source: 1101001100110 changed: 1 1001 01 step 1541 11101011000000010101101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1542 11100010000000010110101001100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 01100110 step 1543 11100010000000010111100110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1544 11100010000000010100100110011010 fail ^ source: 1101001 changed: 1 01 step 1545 11101001000000010100100110011010 source: 1101001100101 changed: 1 1001100101 step 1546 11101001000000010101101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1547 11100000000000010110101001100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 011001 10 step 1548 11100000000000010111100110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1549 11100000000000010100100110010110 fail ^ source: 1111001 changed: 11 1 step 1550 11111001000000010100100110010110 source: 1101010100101 changed: 1 10 10 01 step 1551 11111001000000010101101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1552 11110000000000010110101010100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 01 10 step 1553 11110000000000010111101010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1554 11110000000000010100101010010110 fail ^ source: 1111011 changed: 1 11 step 1555 11111011000000010100101010010110 source: 1101010100110 changed: 1 10 step 1556 11111011000000010101101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1557 11110010000000010110101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 0110 step 1558 11110010000000010111101010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1559 11110010000000010100101010011010 fail ^ source: 1111111 changed: 11 1 step 1560 11111111000000010100101010011010 source: 1101010101010 changed: 1 10 step 1561 11111111000000010101101010101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1562 11110110000000010110101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 1563 11110110000000010111101010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1564 11110110000000010100101010101010 fail ^ source: 1111101 changed: 1 01 step 1565 11111101000000010100101010101010 source: 1101010101001 changed: 1 01 step 1566 11111101000000010101101010101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1567 11110100000000010110101010101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 0110 step 1568 11110100000000010111101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1569 11110100000000010100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: step 1570 11110100000000010100101010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 101010101 01 step 1571 11110100000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1572 11110100000000010110010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 10 step 1573 11110100000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1574 11110100000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 1 step 1575 11110110000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 01 step 1576 11110110000000010101010101010101 fail ^ ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1577 11110110000000010110010101010101 fail ^^^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 10 step 1578 11110110000000010111010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1579 11110110000000010100010101010110 fail ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 step 1580 11110010000000010100010101010110 fail ^ ^^^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 01 step 1581 11110010000000010101010101010101 fail ^ ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1582 11110010000000010110010101010101 fail ^^^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 step 1583 11110010000000010111010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1584 11110010000000010100010101010110 fail ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 0 step 1585 11110000000000010100010101010110 fail ^ ^^^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 01 step 1586 11110000000000010101010101010101 fail ^ ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1587 11110000000000010110010101010101 fail ^^^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 10 step 1588 11110000000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1589 11110000000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 step 1590 11010000000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 01 step 1591 11010000000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1592 11010000000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 10 step 1593 11010000000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1594 11010000000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 1 step 1595 11010010000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 01 step 1596 11010010000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1597 11010010000000010110010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 10 step 1598 11010010000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1599 11010010000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 step 1600 11010110000000010100010101010110 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 01 step 1601 11010110000000010101010101010101 fail ^ ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1602 11010110000000010110010101010101 fail ^^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 10 step 1603 11010110000000010111010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1604 11010110000000010100010101010110 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 0 step 1605 11010100000000010100010101010110 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 01 step 1606 11010100000000010101010101010101 fail ^ ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1607 11010100000000010110010101010101 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 10 step 1608 11010100000000010111010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1609 11010100000000010100010101010110 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 1610 11011101000000010100010101010110 fail ^^ ^^ source: 1100110101001 changed: 110 10101001 step 1611 11011101000000010101100110101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1612 11010100000000010110100110101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 10110 0110 step 1613 11010100000000010111011010100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1614 11010100000000010100011010100110 fail ^ source: 1011111 changed: 1 11 step 1615 11011111000000010100011010100110 source: 1100110101010 changed: 11001 10 step 1616 11011111000000010101100110101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1617 11010110000000010110100110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 10110 step 1618 11010110000000010111011010101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1619 11010110000000010100011010101010 fail ^ source: 1011011 changed: 10 1 step 1620 11011011000000010100011010101010 source: 1100110100110 changed: 11001 01 step 1621 11011011000000010101100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1622 11010010000000010110100110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 10110 0110 step 1623 11010010000000010111011010011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1624 11010010000000010100011010011010 fail ^ source: 1011001 changed: 1 01 step 1625 11011001000000010100011010011010 source: 1100110100101 changed: 11001 100101 step 1626 11011001000000010101100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1627 11010000000000010110100110100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 10110 01 10 step 1628 11010000000000010111011010010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1629 11010000000000010100011010010110 fail ^ source: 1001001 changed: 01 1 step 1630 11001001000000010100011010010110 source: 1100101100101 changed: 110010110 01 step 1631 11001001000000010101100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1632 11000000000000010110100101100101 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 101 1001 10 step 1633 11000000000000010111010110010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1634 11000000000000010100010110010110 fail ^ source: 1001011 changed: 1 11 step 1635 11001011000000010100010110010110 source: 1100101100110 changed: 110 0110 step 1636 11001011000000010101100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1637 11000010000000010110100101100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 101 100110 step 1638 11000010000000010111010110011010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1639 11000010000000010100010110011010 fail ^ source: 1001111 changed: 11 1 step 1640 11001111000000010100010110011010 source: 1100101101010 changed: 110 0110 step 1641 11001111000000010101100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1642 11000110000000010110100101101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 101 10 step 1643 11000110000000010111010110101010 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1644 11000110000000010100010110101010 fail ^ source: 1001101 changed: 1 01 step 1645 11001101000000010100010110101010 source: 1100101101001 changed: 110 01 01 step 1646 11001101000000010101100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 0 10 step 1647 11000100000000010110100101101001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 101 10 0110 step 1648 11000100000000010111010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1649 11000100000000010100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: step 1650 11000100000000010100010110100110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 0101 01 step 1651 11000100000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1652 11000100000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 10 step 1653 11000100000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1654 11000100000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 1 step 1655 11000110000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 01 step 1656 11000110000000010101010101010101 fail ^ ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1657 11000110000000010110010101010101 fail ^^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 10 step 1658 11000110000000010111010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1659 11000110000000010100010101010110 fail ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 step 1660 11000010000000010100010101010110 fail ^ ^^^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 01 step 1661 11000010000000010101010101010101 fail ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1662 11000010000000010110010101010101 fail ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 10 step 1663 11000010000000010111010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1664 11000010000000010100010101010110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 0 step 1665 11000000000000010100010101010110 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 01 step 1666 11000000000000010101010101010101 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 10 step 1667 11000000000000010110010101010101 fail ^^ source: 1010101010110 changed: 1 10 step 1668 11000000000000010111010101010110 source: 00 changed: 00 step 1669 11000000000000010100010101010110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 step 1670 10000000000000010100010101010110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 01 step 1671 10000000000000010101010101010101 fail ^ source: 0 10 changed: 10 step 1672 10000000000000010110010101010101 source: 1010101010110 changed: 1 10 step 1673 10000000000000010111010101010110 source: 00 changed: 00 step 1674 10000000000000010100010101010110 source: source: source: ; end of SECTION GENERATED BY A PROGRAM source: source: source: ; CLEAR FFs source: 0 010101010101 changed: 0 01 step 1675 00000000000000010100010101010101 source: 1 changed: 1 step 1676 10000000000000010100010101010101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: 11111110111111010100010101010101 changed: 111 11 111111 step 1677 11110110111111010100010101010101 fail ^ test 6: *** FAIL *************************** 1123 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail I I OOOOOOOOOOOO all fails I I OOOOOOOOOOOO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 6, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails I I OOOOOOOOOOOO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 6, total passes 0 Main menu Fri Jun 30 10:53:26 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 13:10:21 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7453.tst reading test file: tests\7453.tst comment: 7453 4 WIDE AND-OR-INVERT comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7453 PIN 1 A pins: 2 I AS2 E1-15 7453 PIN 13 B pins: 8 I AB2 E1-2 7453 PIN 2 C error: expected column 3: 8 I AB2 E1-2 7453 PIN 2 C direction: 9 I AC1 E1-3 7453 PIN 3 D expected 'direction' (2 columns of 'I' or 'O' or 'P') bad test file Main menu Fri Jun 30 13:15:10 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 13:24:53 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7453.tst reading test file: tests\7453.tst comment: 7453 4 WIDE AND-OR-INVERT comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7453 PIN 1 A pins: 2 I AS2 E1-15 7453 PIN 13 B pins: 3 I AB2 E1-2 7453 PIN 2 C pins: 4 I AC1 E1-3 7453 PIN 3 D pins: 5 I AD2 E1-4 7453 PIN 4 E pins: 6 I AE2 E1-5 7453 PIN 5 F pins: 7 I AM2 E1-11 7453 PIN 9 G pins: 8 I AN2 E1-12 7453 PIN 10 H pins: 9 O AL2 E1-10 7453 PIN 8 Y = (A AND B) NOR (C AND D) NOR (E AND F) NOR (G AND H) (X,X-N EXPANDER) pins: 10 I AF2 E1-6 7453 PIN 6 N.C. pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 11 I AH2 E1-7 7453 PIN 7 GROUND error: expected column 13: 11 I AH2 E1-7 7453 PIN 7 GROUND direction: 12 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) expected 'direction' (12 columns of 'I' or 'O' or 'P') bad test file Main menu Fri Jun 30 13:24:59 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7453.tst reading test file: tests\7453.tst comment: 7453 4 WIDE AND-OR-INVERT comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7453 PIN 1 A pins: 2 I AS2 E1-15 7453 PIN 13 B pins: 3 I AB2 E1-2 7453 PIN 2 C pins: 4 I AC1 E1-3 7453 PIN 3 D pins: 5 I AD2 E1-4 7453 PIN 4 E pins: 6 I AE2 E1-5 7453 PIN 5 F pins: 7 I AM2 E1-11 7453 PIN 9 G pins: 8 I AN2 E1-12 7453 PIN 10 H pins: 9 O AL2 E1-10 7453 PIN 8 Y = (A AND B) NOR (C AND D) NOR (E AND F) NOR (G AND H) (X,X-N EXPANDER) pins: 10 I AF2 E1-6 7453 PIN 6 N.C. pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7453 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7453 PIN 14 VCC pins: direction: IIIIIIIIOIOOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000000010XX0000 comment: comment: ; ALL INPUTS HI test 2: 111111110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 10 0 test 4: 00 0 test 5: 01 0 test 6: 11 0 test 7: 10 0 test 8: 00 0 test 9: 01 0 test 10: 11 0 test 11: 10 0 test 12: 00 0 test 13: 01 0 test 14: 11 0 test 15: 100 test 16: 000 test 17: 010 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 000000001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 0, mask 0x0040 column 4: offset 0, mask 0x2000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 1, mask 0x0004 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 0, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0020 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 3: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 5: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 7: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 8: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 9: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 11: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 12: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 13: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 15: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 16: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 17: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 19: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIOIIOOII G P G UUT inputs: 13 UUT outputs: 3 pins used: 16 not used: 50 19 'test steps' 72 lines 7453 4 WIDE AND-OR-INVERT REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Fri Jun 30 13:25:28 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:25:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 test 172: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 172 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 test 173: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 173 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvv v rising ^^^^^^^^^ ^ was hi 111111111 1 total fails 0, total passes 173 Main menu Fri Jun 30 13:26:41 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7453.tst reading test file: tests\7453.tst comment: 7453 4 WIDE AND-OR-INVERT comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7453 PIN 1 A pins: 2 I AS2 E1-15 7453 PIN 13 B pins: 3 I AB2 E1-2 7453 PIN 2 C pins: 4 I AC1 E1-3 7453 PIN 3 D pins: 5 I AD2 E1-4 7453 PIN 4 E pins: 6 I AE2 E1-5 7453 PIN 5 F pins: 7 I AM2 E1-11 7453 PIN 9 G pins: 8 I AN2 E1-12 7453 PIN 10 H pins: 9 O AL2 E1-10 7453 PIN 8 Y = (A AND B) NOR (C AND D) NOR (E AND F) NOR (G AND H) (X,X-N EXPANDER) pins: 10 I AF2 E1-6 7453 PIN 6 N.C. pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7453 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7453 PIN 14 VCC pins: direction: IIIIIIIIOIOOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000000010XX0000 comment: comment: ; ALL INPUTS HI test 2: 111111110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 10 0 test 4: 00 0 test 5: 01 0 test 6: 11 0 test 7: 10 0 test 8: 00 0 test 9: 01 0 test 10: 11 0 test 11: 10 0 test 12: 00 0 test 13: 01 0 test 14: 11 0 test 15: 100 test 16: 000 test 17: 010 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 000000001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 0, mask 0x0040 column 4: offset 0, mask 0x2000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 1, mask 0x0004 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 0, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0020 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 3: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 5: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 7: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 8: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 9: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 11: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 12: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 13: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 15: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 16: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 17: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 19: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 20: 0x0000 0x0042 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 21: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 22: 0x8000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 23: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 24: 0x2000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 25: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 26: 0x0040 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 27: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIOIIOOII G P G UUT inputs: 13 UUT outputs: 3 pins used: 16 not used: 50 27 'test steps' 80 lines 7453 4 WIDE AND-OR-INVERT REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Fri Jun 30 13:26:46 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:26:47 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 test 92: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 92 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 test 93: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 93 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvv v rising ^^^^^^^^^ ^ was hi 111111111 1 total fails 0, total passes 93 Main menu Fri Jun 30 13:27:17 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7453.tst reading test file: tests\7453.tst comment: 7453 4 WIDE AND-OR-INVERT comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7453 PIN 1 A pins: 2 I AS2 E1-15 7453 PIN 13 B pins: 3 I AB2 E1-2 7453 PIN 2 C pins: 4 I AC1 E1-3 7453 PIN 3 D pins: 5 I AD2 E1-4 7453 PIN 4 E pins: 6 I AE2 E1-5 7453 PIN 5 F pins: 7 I AM2 E1-11 7453 PIN 9 G pins: 8 I AN2 E1-12 7453 PIN 10 H pins: 9 O AL2 E1-10 7453 PIN 8 Y = (A AND B) NOR (C AND D) NOR (E AND F) NOR (G AND H) (X,X-N EXPANDER) pins: 10 I AF2 E1-6 7453 PIN 6 N.C. pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7453 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7453 PIN 14 VCC pins: direction: IIIIIIIIOIOOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000000010XX0000 comment: comment: ; ALL INPUTS HI test 2: 111111110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 10 0 test 4: 00 0 test 5: 01 0 test 6: 11 0 test 7: 10 0 test 8: 00 0 test 9: 01 0 test 10: 11 0 test 11: 10 0 test 12: 00 0 test 13: 01 0 test 14: 11 0 test 15: 100 test 16: 000 test 17: 010 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 000000001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 test 28: 01 1 test 29: 11 0 test 30: 10 0 test 31: 00 0 comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 0, mask 0x0040 column 4: offset 0, mask 0x2000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 1, mask 0x0004 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 0, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0020 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 3: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 5: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 7: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 8: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 9: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 11: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 12: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 13: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 15: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 16: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 17: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 19: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 20: 0x0000 0x0042 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 21: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 22: 0x8000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 23: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 24: 0x2000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 25: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 26: 0x0040 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 27: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 28: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 29: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 30: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 31: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIOIIOOII G P G UUT inputs: 13 UUT outputs: 3 pins used: 16 not used: 50 31 'test steps' 84 lines 7453 4 WIDE AND-OR-INVERT REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Fri Jun 30 13:27:21 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:27:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 0 1 1 step 30 0000100010010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 0 step 31 0000000010010000 fail ^ test 78: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail O all fails O was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 78, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 0 1 1 step 30 0000100010010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 0 step 31 0000000010010000 fail ^ test 79: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail O all fails O was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 79, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 0 1 1 step 30 0000100010010000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII source: 00 0 changed: 0 step 31 0000000010010000 fail ^ test 80: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail O all fails O was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 80, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; START WITH ALL INPUTS ZERO source: 0000000010XX0000 changed: step 1 0000000010010000 source: source: ; ALL INPUTS HI source: 111111110 changed: 111111110 0 step 2 1111111100000000 source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: 10 0 changed: 0 step 3 1011111100000000 source: 00 0 changed: 0 step 4 0011111100000000 source: 01 0 changed: 1 step 5 0111111100000000 source: 11 0 changed: 1 step 6 1111111100000000 source: 10 0 changed: 0 step 7 1110111100000000 source: 00 0 changed: 0 step 8 1100111100000000 source: 01 0 changed: 1 step 9 1101111100000000 source: 11 0 changed: 1 step 10 1111111100000000 source: 10 0 changed: 0 step 11 1111101100000000 source: 00 0 changed: 0 step 12 1111001100000000 source: 01 0 changed: 1 step 13 1111011100000000 source: 11 0 changed: 1 step 14 1111111100000000 source: 100 changed: 0 step 15 1111111000000000 source: 000 changed: 0 step 16 1111110000000000 source: 010 changed: 1 step 17 1111110100000000 source: 110 changed: 1 step 18 1111111100000000 source: source: ; ALL INPUTS LO source: 000000001 changed: 000000001 1 step 19 0000000010010000 source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: 01 1 changed: 1 step 20 0100000010010000 source: 11 0 changed: 1 0 0 step 21 1100000000000000 source: 10 1 changed: 0 1 1 step 22 1000000010010000 source: 00 1 changed: 0 step 23 0000000010010000 source: 01 1 changed: 1 step 24 0001000010010000 source: 11 0 changed: 1 0 0 step 25 0011000000000000 source: 10 1 changed: 0 1 1 step 26 0010000010010000 source: 00 1 changed: 0 step 27 0000000010010000 source: 01 1 changed: 1 step 28 0000010010010000 source: 11 0 changed: 1 0 0 step 29 0000110000000000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII source: 10 0 changed: 0 1 1 step 30 0000100010010000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII source: 00 0 changed: 0 step 31 0000000010010000 fail ^ test 81: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail O all fails O was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 81, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; START WITH ALL INPUTS ZERO source: 0000000010XX0000 changed: step 1 0000000010010000 source: source: ; ALL INPUTS HI source: 111111110 changed: 111111110 0 step 2 1111111100000000 source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: 10 0 changed: 0 step 3 1011111100000000 source: 00 0 changed: 0 step 4 0011111100000000 source: 01 0 changed: 1 step 5 0111111100000000 source: 11 0 changed: 1 step 6 1111111100000000 source: 10 0 changed: 0 step 7 1110111100000000 source: 00 0 changed: 0 step 8 1100111100000000 source: 01 0 changed: 1 step 9 1101111100000000 source: 11 0 changed: 1 step 10 1111111100000000 source: 10 0 changed: 0 step 11 1111101100000000 source: 00 0 changed: 0 step 12 1111001100000000 source: 01 0 changed: 1 step 13 1111011100000000 source: 11 0 changed: 1 step 14 1111111100000000 source: 100 changed: 0 step 15 1111111000000000 source: 000 changed: 0 step 16 1111110000000000 source: 010 changed: 1 step 17 1111110100000000 source: 110 changed: 1 step 18 1111111100000000 source: source: ; ALL INPUTS LO source: 000000001 changed: 000000001 1 step 19 0000000010010000 source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: 01 1 changed: 1 step 20 0100000010010000 source: 11 0 changed: 1 0 0 step 21 1100000000000000 source: 10 1 changed: 0 1 1 step 22 1000000010010000 source: 00 1 changed: 0 step 23 0000000010010000 source: 01 1 changed: 1 step 24 0001000010010000 source: 11 0 changed: 1 0 0 step 25 0011000000000000 source: 10 1 changed: 0 1 1 step 26 0010000010010000 source: 00 1 changed: 0 step 27 0000000010010000 source: 01 1 changed: 1 step 28 0000010010010000 source: 11 0 changed: 1 0 0 step 29 0000110000000000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII source: 10 0 changed: 0 1 1 step 30 0000100010010000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII all fails O was lo 0000000000000000 falling vvvvvvvvv v rising ^^^^^^^^^ ^ was hi 111111111 1 total fails 81, total passes 0 Main menu Fri Jun 30 13:28:32 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7453.tst reading test file: tests\7453.tst comment: 7453 4 WIDE AND-OR-INVERT comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7453 PIN 1 A pins: 2 I AS2 E1-15 7453 PIN 13 B pins: 3 I AB2 E1-2 7453 PIN 2 C pins: 4 I AC1 E1-3 7453 PIN 3 D pins: 5 I AD2 E1-4 7453 PIN 4 E pins: 6 I AE2 E1-5 7453 PIN 5 F pins: 7 I AM2 E1-11 7453 PIN 9 G pins: 8 I AN2 E1-12 7453 PIN 10 H pins: 9 O AL2 E1-10 7453 PIN 8 Y = (A AND B) NOR (C AND D) NOR (E AND F) NOR (G AND H) (X,X-N EXPANDER) pins: 10 I AF2 E1-6 7453 PIN 6 N.C. pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7453 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7453 PIN 14 VCC pins: direction: IIIIIIIIOIOOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000000010XX0000 comment: comment: ; ALL INPUTS HI test 2: 111111110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 10 0 test 4: 00 0 test 5: 01 0 test 6: 11 0 test 7: 10 0 test 8: 00 0 test 9: 01 0 test 10: 11 0 test 11: 10 0 test 12: 00 0 test 13: 01 0 test 14: 11 0 test 15: 100 test 16: 000 test 17: 010 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 000000001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 0, mask 0x0040 column 4: offset 0, mask 0x2000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 1, mask 0x0004 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 0, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0020 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 3: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 5: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 7: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 8: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 9: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 11: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 12: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 13: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 15: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 16: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 17: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 19: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 20: 0x0000 0x0042 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 21: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 22: 0x8000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 23: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 24: 0x2000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 25: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 26: 0x0040 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 27: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 28: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 29: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 30: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 31: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIOIIOOII G P G UUT inputs: 13 UUT outputs: 3 pins used: 16 not used: 50 31 'test steps' 84 lines 7453 4 WIDE AND-OR-INVERT REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Fri Jun 30 13:28:36 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:28:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 step 30 0000100010010000 step 31 0000000010010000 test 110: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 110 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 step 30 0000100010010000 step 31 0000000010010000 test 111: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 111 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 step 30 0000100010010000 step 31 0000000010010000 test 112: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 112 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 step 30 0000100010010000 step 31 0000000010010000 test 113: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 113 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 step 25 0011000000000000 step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 step 29 0000110000000000 step 30 0000100010010000 step 31 0000000010010000 test 114: pass SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail all fails was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 0, total passes 114 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvv v rising ^^^^^^^^^ ^ was hi 111111111 1 total fails 0, total passes 114 Main menu Fri Jun 30 13:29:13 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:30:39 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvv v rising ^^^^^^^^^ ^ was hi 111111111 1 total fails 0, total passes 76 Main menu Fri Jun 30 13:39:00 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.tst reading test file: tests\7450.tst comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AS2 E1-15 7450 PIN 13 1B pins: 3 I AM2 E1-11 7450 PIN 9 1C pins: 4 I AN2 E1-12 7450 PIN 10 1D pins: 5 O AL2 E1-10 7450 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 6 I AB2 E1-2 7450 PIN 2 2A pins: 7 I AC1 E1-3 7450 PIN 3 2B pins: 8 I AD2 E1-4 7450 PIN 4 2C pins: 9 I AE2 E1-5 7450 PIN 5 2D pins: 10 O AF2 E1-6 7450 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOIIIIOIIII expected 'direction' (16 columns of 'I' or 'O' or 'P') bad test file Main menu Fri Jun 30 13:39:04 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Fri Jun 30 13:39:06 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 13:39:07 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7453.tst reading test file: tests\7453.tst comment: 7453 4 WIDE AND-OR-INVERT comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7453 PIN 1 A pins: 2 I AS2 E1-15 7453 PIN 13 B pins: 3 I AB2 E1-2 7453 PIN 2 C pins: 4 I AC1 E1-3 7453 PIN 3 D pins: 5 I AD2 E1-4 7453 PIN 4 E pins: 6 I AE2 E1-5 7453 PIN 5 F pins: 7 I AM2 E1-11 7453 PIN 9 G pins: 8 I AN2 E1-12 7453 PIN 10 H pins: 9 O AL2 E1-10 7453 PIN 8 Y = (A AND B) NOR (C AND D) NOR (E AND F) NOR (G AND H) (X,X-N EXPANDER) pins: 10 I AF2 E1-6 7453 PIN 6 N.C. pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7453 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7453 PIN 14 VCC pins: direction: IIIIIIIIOIOOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000000010XX0000 comment: comment: ; ALL INPUTS HI test 2: 111111110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 10 0 test 4: 00 0 test 5: 01 0 test 6: 11 0 test 7: 10 0 test 8: 00 0 test 9: 01 0 test 10: 11 0 test 11: 10 0 test 12: 00 0 test 13: 01 0 test 14: 11 0 test 15: 100 test 16: 000 test 17: 010 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 000000001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 01 1 test 25: 11 0 test 26: 10 1 test 27: 00 1 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 0, mask 0x0040 column 4: offset 0, mask 0x2000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 1, mask 0x0004 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 0, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0020 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 3: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 5: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 7: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 8: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 9: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 11: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 12: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 13: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 15: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 16: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 17: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 19: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 20: 0x0000 0x0042 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 21: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 22: 0x8000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 23: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 24: 0x2000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 25: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 26: 0x0040 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 27: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 28: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 29: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 30: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 31: 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIOIIOOII G P G UUT inputs: 13 UUT outputs: 3 pins used: 16 not used: 50 31 'test steps' 84 lines 7453 4 WIDE AND-OR-INVERT REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Fri Jun 30 13:39:13 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:39:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 1 step 25 0011000010010000 fail ^ step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 1 step 29 0000110010010000 fail ^ step 30 0000100010010000 step 31 0000000010010000 test 61: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail O all fails O was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 61, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000010010000 step 2 1111111100000000 step 3 1011111100000000 step 4 0011111100000000 step 5 0111111100000000 step 6 1111111100000000 step 7 1110111100000000 step 8 1100111100000000 step 9 1101111100000000 step 10 1111111100000000 step 11 1111101100000000 step 12 1111001100000000 step 13 1111011100000000 step 14 1111111100000000 step 15 1111111000000000 step 16 1111110000000000 step 17 1111110100000000 step 18 1111111100000000 step 19 0000000010010000 step 20 0100000010010000 step 21 1100000000000000 step 22 1000000010010000 step 23 0000000010010000 step 24 0001000010010000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 1 step 25 0011000010010000 fail ^ step 26 0010000010010000 step 27 0000000010010000 step 28 0000010010010000 SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII changed: 1 step 29 0000110010010000 fail ^ step 30 0000100010010000 step 31 0000000010010000 test 62: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII this fail O all fails O was hi 111111111 1 rising ^^^^^^^^^ ^ falling vvvvvvvvv v was lo 0000000000000000 total fails 62, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASBCDEMNLFPRHJKT SIDE 1221222222222222 DIRECTION IIIIIIIIOIOOIIII all fails O was lo 0000000000000000 falling vvvvvvvvv v rising ^^^^^^^^^ ^ was hi 111111111 1 total fails 62, total passes 0 Main menu Fri Jun 30 13:39:46 2017 test file is: tests\7453.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.tst reading test file: tests\7450.tst comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AS2 E1-15 7450 PIN 13 1B pins: 3 I AM2 E1-11 7450 PIN 9 1C pins: 4 I AN2 E1-12 7450 PIN 10 1D pins: 5 O AL2 E1-10 7450 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 6 I AB2 E1-2 7450 PIN 2 2A pins: 7 I AC1 E1-3 7450 PIN 3 2B pins: 8 I AD2 E1-4 7450 PIN 4 2C pins: 9 I AE2 E1-5 7450 PIN 5 2D pins: 10 O AF2 E1-6 7450 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOIIIIOIIII expected 'direction' (16 columns of 'I' or 'O' or 'P') bad test file Main menu Fri Jun 30 13:39:51 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7450.tst reading test file: tests\7450.tst comment: 7450 TRIPLE 3-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AS2 E1-15 7450 PIN 13 1B pins: 3 I AM2 E1-11 7450 PIN 9 1C pins: 4 I AN2 E1-12 7450 PIN 10 1D pins: 5 O AL2 E1-10 7450 PIN 8 1Y = (1A AND 1B) NOR (1C AND 1D) NOR (X,X-N EXPANDER) pins: 6 I AB2 E1-2 7450 PIN 2 2A pins: 7 I AC1 E1-3 7450 PIN 3 2B pins: 8 I AD2 E1-4 7450 PIN 4 2C pins: 9 I AE2 E1-5 7450 PIN 5 2D pins: 10 O AF2 E1-6 7450 PIN 6 2Y = (2A AND 2B) NOR (2C AND 2D) pins: 11 O AP2 E1-13 7450 PIN 11 X (EXPANDER) pins: 12 O AR2 E1-14 7450 PIN 12 X-N (EXPANDER) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOIIIIOOOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000100001XX0000 comment: comment: ; ALL INPUTS HI test 2: 1111011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 01 0 test 4: 00 0 test 5: 10 0 test 6: 11 0 test 7: 010 test 8: 000 test 9: 100 test 10: 110 test 11: 01 0 test 12: 00 0 test 13: 10 0 test 14: 11 0 test 15: 010 test 16: 000 test 17: 100 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 0000100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 01 1 test 21: 11 0 test 22: 10 1 test 23: 00 1 test 24: 011 test 25: 110 test 26: 101 test 27: 001 test 28: 01 1 test 29: 11 0 test 30: 10 1 test 31: 00 1 test 32: 011 test 33: 110 test 34: 101 test 35: 001 comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 1, mask 0x0040 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0002 column 6: offset 0, mask 0x0040 column 7: offset 0, mask 0x2000 column 8: offset 0, mask 0x0010 column 9: offset 0, mask 0x0008 column 10: offset 0, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0020 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF32 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 2: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 3: 0x2058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 4: 0x2058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 5: 0xA058 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 6: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 7: 0xA058 0x0048 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 8: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 9: 0xA058 0x0044 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 10: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 11: 0xA018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 12: 0x8018 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 13: 0x8058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 14: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 15: 0xA048 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 16: 0xA040 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 17: 0xA050 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 18: 0xA058 0x004C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 19: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 20: 0x0004 0x0042 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 21: 0x8004 0x0040 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 22: 0x8004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 23: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 24: 0x0004 0x000A 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 25: 0x0004 0x000C 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 26: 0x0004 0x0006 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 27: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 28: 0x2004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 29: 0x2040 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 30: 0x0044 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 31: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 32: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 33: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 34: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x0030 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 88 lines 7450 TRIPLE 3-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V DOES NOT TEST EXPANDER INPUTS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! PINS Main menu Fri Jun 30 13:40:51 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:40:55 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ASMNLBCDEFPRHJKT SIDE 1222221222222222 DIRECTION IIIIOIIIIOOOIIII all fails was lo 0000000000000000 falling vvvvvvvvvv v rising ^^^^^^^^^^ ^ was hi 1111111111 1 total fails 0, total passes 137 Main menu Fri Jun 30 13:41:00 2017 test file is: tests\7450.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m310.tst reading test file: tests\m310.tst comment: M310 REV D DELAY LINE comment: comment: USE SINGLE STEP AND DMM. comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AH2 PULSE INPUT (EDGE?) pins: 2 O AJ2 0 NS DELAY TAP pins: 3 O AK2 50 NS DELAY TAP pins: 4 O AL2 100 NS DELAY TAP pins: 5 O AM2 150 NS DELAY TAP pins: 6 O AN2 200 NS DELAY TAP pins: 7 O AP2 250 NS DELAY TAP pins: 8 O AR2 300 NS DELAY TAP pins: 9 O AS2 350 NS DELAY TAP pins: 10 O AT2 400 NS DELAY TAP pins: 11 O AU2 450 NS DELAY TAP pins: 12 O AV2 500 NS DELAY TAP pins: 13 I AE1 INPUT 1 (NORMALLY CONNECTED TO A DELAY TAP) pins: 14 O AF1 OUTPUT 1 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: 15 I AH1 INPUT 2 (NORMALLY CONNECTED TO A DELAY TAP) pins: 16 O AJ1 OUTPUT 2 7440 BUFFER 48MA DRIVE PULSES HI (100 NS) pins: direction: IOOOOOOOOOOOIOIO test 1: 0111111111110000 test 2: 100000000000 test 3: 011111111111001X test 4: 100000000000 test 5: 0111111111111X00 test 6: 100000000000 test 7: 0111111111110X0X test 8: 100000000000 end: END summary column 1: offset 0, mask 0x0002 column 2: offset 0, mask 0x0001 column 3: offset 1, mask 0x0001 column 4: offset 1, mask 0x0002 column 5: offset 1, mask 0x0004 column 6: offset 1, mask 0x0008 column 7: offset 1, mask 0x0010 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0080 column 11: offset 2, mask 0x0001 column 12: offset 2, mask 0x0002 column 13: offset 0, mask 0x0800 column 14: offset 0, mask 0x0400 column 15: offset 0, mask 0x0200 column 16: offset 0, mask 0x0100 direction bits (1=input) 0xF5FD 0xFFFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x00FF 0x0003 0x0000 0x0000 2: 0x0002 0x0000 0x0000 0x0000 0x0000 3: 0x0201 0x00FF 0x0003 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 4: 0x0202 0x0000 0x0000 0x0000 0x0000 0x0100 0x0000 0x0000 0x0000 0x0000 5: 0x0801 0x00FF 0x0003 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 6: 0x0802 0x0000 0x0000 0x0000 0x0000 0x0400 0x0000 0x0000 0x0000 0x0000 7: 0x0001 0x00FF 0x0003 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 8: 0x0002 0x0000 0x0000 0x0000 0x0000 0x0500 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIO G P G IOOOOOOOOOOO G P G UUT inputs: 3 UUT outputs: 13 pins used: 16 not used: 50 8 'test steps' 37 lines M310 REV D DELAY LINE USE SINGLE STEP AND DMM. USE OSCILLOSCOPE TO SEE PULSES. AE1 IS THE INPUT FOR THE AF1 OUTPUT. AH1 IS THE INPUT FOR THE AJ1 OUTPUT. CONNECT AE1 TO EACH TAP: PINS Main menu Fri Jun 30 13:43:06 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:43:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 542 Main menu Fri Jun 30 13:43:19 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:43:31 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 285 Main menu Fri Jun 30 13:43:33 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:43:48 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 302 Main menu Fri Jun 30 13:43:50 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:44:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 239 Main menu Fri Jun 30 13:44:02 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:44:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 325 Main menu Fri Jun 30 13:44:15 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:44:27 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER HJKLMNPRSTUVEFHJ SIDE 2222222222221111 DIRECTION IOOOOOOOOOOOIOIO all fails was lo 0000000000000000 falling vvvvvvvvvvvvv v rising ^^^^^^^^^^^^^ ^ was hi 1111111111111 1 total fails 0, total passes 278 Main menu Fri Jun 30 13:44:29 2017 test file is: tests\m310.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 13:44:57 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:45:05 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 44 Main menu Fri Jun 30 13:45:08 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m720.tst could not open test file. valid test files are: reverting back to test file: tests\m113.tst Main menu Fri Jun 30 13:46:15 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 13:46:54 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:46:57 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 109 Main menu Fri Jun 30 13:47:03 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:47:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 63 Main menu Fri Jun 30 13:47:24 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 13:47:42 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:47:44 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 37 Main menu Fri Jun 30 13:47:46 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:47:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 36 Main menu Fri Jun 30 13:47:59 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 13:48:15 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:48:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 28 Main menu Fri Jun 30 13:48:19 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst could not open test file. valid test files are: reverting back to test file: tests\m115.tst Main menu Fri Jun 30 13:48:32 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:48:34 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails O OI OI O I O I O IO IO was lo 000000000000000000000000000 000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv vvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^ was hi 11111111111111111111111111111111 total fails 23, total passes 0 Main menu Fri Jun 30 13:48:38 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst could not open test file. valid test files are: reverting back to test file: tests\m115.tst Main menu Fri Jun 30 13:48:55 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:48:59 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Fri Jun 30 13:49:00 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:49:02 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails O OI OI O I O I O IO IO was lo 000000000000000000000000000 000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv vvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^ was hi 11111111111111111111111111111111 total fails 20, total passes 0 Main menu Fri Jun 30 13:49:15 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst could not open test file. valid test files are: reverting back to test file: tests\m115.tst Main menu Fri Jun 30 13:49:43 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 13:49:54 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 13:49:58 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:50:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 33 Main menu Fri Jun 30 13:50:04 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 13:50:35 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 13:50:45 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:50:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 188 Main menu Fri Jun 30 13:51:04 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 13:51:39 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 13:51:52 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:51:55 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 227 Main menu Fri Jun 30 13:52:14 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 16: 000011101 test 17: 000011111 test 18: 000100001 test 19: 000100011 test 20: 000100101 test 21: 000100111 test 22: 000101001 test 23: 000101011 test 24: 000101101 test 25: 000101111 test 26: 000110001 test 27: 000110011 test 28: 000110101 test 29: 000110111 test 30: 000111001 test 31: 000111011 test 32: 000111101 test 33: 000111111 test 34: 001000001 test 35: 001000011 test 36: 001000101 test 37: 001000111 test 38: 001001001 test 39: 001001011 test 40: 001001101 test 41: 001001111 test 42: 001010001 test 43: 001010011 test 44: 001010101 test 45: 001010111 test 46: 001011001 test 47: 001011011 test 48: 001011101 test 49: 001011111 test 50: 001100001 test 51: 001100011 test 52: 001100101 test 53: 001100111 test 54: 001101001 test 55: 001101011 test 56: 001101101 test 57: 001101111 test 58: 001110001 test 59: 001110011 test 60: 001110101 test 61: 001110111 test 62: 001111001 test 63: 001111011 test 64: 001111101 test 65: 001111111 test 66: 010000001 test 67: 010000011 test 68: 010000101 test 69: 010000111 test 70: 010001001 test 71: 010001011 test 72: 010001101 test 73: 010001111 test 74: 010010001 test 75: 010010011 test 76: 010010101 test 77: 010010111 test 78: 010011001 test 79: 010011011 test 80: 010011101 test 81: 010011111 test 82: 010100001 test 83: 010100011 test 84: 010100101 test 85: 010100111 test 86: 010101001 test 87: 010101011 test 88: 010101101 test 89: 010101111 test 90: 010110001 test 91: 010110011 test 92: 010110101 test 93: 010110111 test 94: 010111001 test 95: 010111011 test 96: 010111101 test 97: 010111111 test 98: 011000001 test 99: 011000011 test 100: 011000101 test 101: 011000111 test 102: 011001001 test 103: 011001011 test 104: 011001101 test 105: 011001111 test 106: 011010001 test 107: 011010011 test 108: 011010101 test 109: 011010111 test 110: 011011001 test 111: 011011011 test 112: 011011101 test 113: 011011111 test 114: 011100001 test 115: 011100011 test 116: 011100101 test 117: 011100111 test 118: 011101001 test 119: 011101011 test 120: 011101101 test 121: 011101111 test 122: 011110001 test 123: 011110011 test 124: 011110101 test 125: 011110111 test 126: 011111001 test 127: 011111011 test 128: 011111101 test 129: 011111111 test 130: 100000001 test 131: 100000011 test 132: 100000101 test 133: 100000111 test 134: 100001001 test 135: 100001011 test 136: 100001101 test 137: 100001111 test 138: 100010001 test 139: 100010011 test 140: 100010101 test 141: 100010111 test 142: 100011001 test 143: 100011011 test 144: 100011101 test 145: 100011111 test 146: 100100001 test 147: 100100011 test 148: 100100101 test 149: 100100111 test 150: 100101001 test 151: 100101011 test 152: 100101101 test 153: 100101111 test 154: 100110001 test 155: 100110011 test 156: 100110101 test 157: 100110111 test 158: 100111001 test 159: 100111011 test 160: 100111101 test 161: 100111111 test 162: 101000001 test 163: 101000011 test 164: 101000101 test 165: 101000111 test 166: 101001001 test 167: 101001011 test 168: 101001101 test 169: 101001111 test 170: 101010001 test 171: 101010011 test 172: 101010101 test 173: 101010111 test 174: 101011001 test 175: 101011011 test 176: 101011101 test 177: 101011111 test 178: 101100001 test 179: 101100011 test 180: 101100101 test 181: 101100111 test 182: 101101001 test 183: 101101011 test 184: 101101101 test 185: 101101111 test 186: 101110001 test 187: 101110011 test 188: 101110101 test 189: 101110111 test 190: 101111001 test 191: 101111011 test 192: 101111101 test 193: 101111111 test 194: 110000001 test 195: 110000011 test 196: 110000101 test 197: 110000111 test 198: 110001001 test 199: 110001011 test 200: 110001101 test 201: 110001111 test 202: 110010001 test 203: 110010011 test 204: 110010101 test 205: 110010111 test 206: 110011001 test 207: 110011011 test 208: 110011101 test 209: 110011111 test 210: 110100001 test 211: 110100011 test 212: 110100101 test 213: 110100111 test 214: 110101001 test 215: 110101011 test 216: 110101101 test 217: 110101111 test 218: 110110001 test 219: 110110011 test 220: 110110101 test 221: 110110111 test 222: 110111001 test 223: 110111011 test 224: 110111101 test 225: 110111111 test 226: 111000001 test 227: 111000011 test 228: 111000101 test 229: 111000111 test 230: 111001001 test 231: 111001011 test 232: 111001101 test 233: 111001111 test 234: 111010001 test 235: 111010011 test 236: 111010101 test 237: 111010111 test 238: 111011001 test 239: 111011011 test 240: 111011101 test 241: 111011111 test 242: 111100001 test 243: 111100011 test 244: 111100101 test 245: 111100111 test 246: 111101001 test 247: 111101011 test 248: 111101101 test 249: 111101111 test 250: 111110001 test 251: 111110011 test 252: 111110101 test 253: 111110111 test 254: 111111001 test 255: 111111011 test 256: 111111101 test 257: 111111110 test 258: 000000001 test 259: 000000001 test 260: 000000011 test 261: 000000101 test 262: 000000111 test 263: 000001001 test 264: 000001011 test 265: 000001101 test 266: 000001111 test 267: 000010001 test 268: 000010011 test 269: 000010101 test 270: 000010111 test 271: 000011001 test 272: 000011011 test 273: 000011101 test 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011100011 test 1401: 011100101 test 1402: 011100111 test 1403: 011101001 test 1404: 011101011 test 1405: 011101101 test 1406: 011101111 test 1407: 011110001 test 1408: 011110011 test 1409: 011110101 test 1410: 011110111 test 1411: 011111001 test 1412: 011111011 test 1413: 011111101 test 1414: 011111111 test 1415: 100000001 test 1416: 100000011 test 1417: 100000101 test 1418: 100000111 test 1419: 100001001 test 1420: 100001011 test 1421: 100001101 test 1422: 100001111 test 1423: 100010001 test 1424: 100010011 test 1425: 100010101 test 1426: 100010111 test 1427: 100011001 test 1428: 100011011 test 1429: 100011101 test 1430: 100011111 test 1431: 100100001 test 1432: 100100011 test 1433: 100100101 test 1434: 100100111 test 1435: 100101001 test 1436: 100101011 test 1437: 100101101 test 1438: 100101111 test 1439: 100110001 test 1440: 100110011 test 1441: 100110101 test 1442: 100110111 test 1443: 100111001 test 1444: 100111011 test 1445: 100111101 test 1446: 100111111 test 1447: 101000001 test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 0x0005 0x0010 0x0002 0x0000 0x0000 5: 0x0007 0x0010 0x0002 0x0000 0x0000 6: 0x0009 0x0010 0x0002 0x0000 0x0000 7: 0x000B 0x0010 0x0002 0x0000 0x0000 8: 0x000D 0x0010 0x0002 0x0000 0x0000 9: 0x000F 0x0010 0x0002 0x0000 0x0000 10: 0x0011 0x0010 0x0002 0x0000 0x0000 11: 0x0013 0x0010 0x0002 0x0000 0x0000 12: 0x0015 0x0010 0x0002 0x0000 0x0000 13: 0x0017 0x0010 0x0002 0x0000 0x0000 14: 0x0019 0x0010 0x0002 0x0000 0x0000 15: 0x001B 0x0010 0x0002 0x0000 0x0000 16: 0x001D 0x0010 0x0002 0x0000 0x0000 17: 0x001F 0x0010 0x0002 0x0000 0x0000 18: 0x1001 0x0010 0x0002 0x0000 0x0000 19: 0x1003 0x0010 0x0002 0x0000 0x0000 20: 0x1005 0x0010 0x0002 0x0000 0x0000 21: 0x1007 0x0010 0x0002 0x0000 0x0000 22: 0x1009 0x0010 0x0002 0x0000 0x0000 23: 0x100B 0x0010 0x0002 0x0000 0x0000 24: 0x100D 0x0010 0x0002 0x0000 0x0000 25: 0x100F 0x0010 0x0002 0x0000 0x0000 26: 0x1011 0x0010 0x0002 0x0000 0x0000 27: 0x1013 0x0010 0x0002 0x0000 0x0000 28: 0x1015 0x0010 0x0002 0x0000 0x0000 29: 0x1017 0x0010 0x0002 0x0000 0x0000 30: 0x1019 0x0010 0x0002 0x0000 0x0000 31: 0x101B 0x0010 0x0002 0x0000 0x0000 32: 0x101D 0x0010 0x0002 0x0000 0x0000 33: 0x101F 0x0010 0x0002 0x0000 0x0000 34: 0x2001 0x0010 0x0002 0x0000 0x0000 35: 0x2003 0x0010 0x0002 0x0000 0x0000 36: 0x2005 0x0010 0x0002 0x0000 0x0000 37: 0x2007 0x0010 0x0002 0x0000 0x0000 38: 0x2009 0x0010 0x0002 0x0000 0x0000 39: 0x200B 0x0010 0x0002 0x0000 0x0000 40: 0x200D 0x0010 0x0002 0x0000 0x0000 41: 0x200F 0x0010 0x0002 0x0000 0x0000 42: 0x2011 0x0010 0x0002 0x0000 0x0000 43: 0x2013 0x0010 0x0002 0x0000 0x0000 44: 0x2015 0x0010 0x0002 0x0000 0x0000 45: 0x2017 0x0010 0x0002 0x0000 0x0000 46: 0x2019 0x0010 0x0002 0x0000 0x0000 47: 0x201B 0x0010 0x0002 0x0000 0x0000 48: 0x201D 0x0010 0x0002 0x0000 0x0000 49: 0x201F 0x0010 0x0002 0x0000 0x0000 50: 0x3001 0x0010 0x0002 0x0000 0x0000 51: 0x3003 0x0010 0x0002 0x0000 0x0000 52: 0x3005 0x0010 0x0002 0x0000 0x0000 53: 0x3007 0x0010 0x0002 0x0000 0x0000 54: 0x3009 0x0010 0x0002 0x0000 0x0000 55: 0x300B 0x0010 0x0002 0x0000 0x0000 56: 0x300D 0x0010 0x0002 0x0000 0x0000 57: 0x300F 0x0010 0x0002 0x0000 0x0000 58: 0x3011 0x0010 0x0002 0x0000 0x0000 59: 0x3013 0x0010 0x0002 0x0000 0x0000 60: 0x3015 0x0010 0x0002 0x0000 0x0000 61: 0x3017 0x0010 0x0002 0x0000 0x0000 62: 0x3019 0x0010 0x0002 0x0000 0x0000 63: 0x301B 0x0010 0x0002 0x0000 0x0000 64: 0x301D 0x0010 0x0002 0x0000 0x0000 65: 0x301F 0x0010 0x0002 0x0000 0x0000 66: 0x4001 0x0010 0x0002 0x0000 0x0000 67: 0x4003 0x0010 0x0002 0x0000 0x0000 68: 0x4005 0x0010 0x0002 0x0000 0x0000 69: 0x4007 0x0010 0x0002 0x0000 0x0000 70: 0x4009 0x0010 0x0002 0x0000 0x0000 71: 0x400B 0x0010 0x0002 0x0000 0x0000 72: 0x400D 0x0010 0x0002 0x0000 0x0000 73: 0x400F 0x0010 0x0002 0x0000 0x0000 74: 0x4011 0x0010 0x0002 0x0000 0x0000 75: 0x4013 0x0010 0x0002 0x0000 0x0000 76: 0x4015 0x0010 0x0002 0x0000 0x0000 77: 0x4017 0x0010 0x0002 0x0000 0x0000 78: 0x4019 0x0010 0x0002 0x0000 0x0000 79: 0x401B 0x0010 0x0002 0x0000 0x0000 80: 0x401D 0x0010 0x0002 0x0000 0x0000 81: 0x401F 0x0010 0x0002 0x0000 0x0000 82: 0x5001 0x0010 0x0002 0x0000 0x0000 83: 0x5003 0x0010 0x0002 0x0000 0x0000 84: 0x5005 0x0010 0x0002 0x0000 0x0000 85: 0x5007 0x0010 0x0002 0x0000 0x0000 86: 0x5009 0x0010 0x0002 0x0000 0x0000 87: 0x500B 0x0010 0x0002 0x0000 0x0000 88: 0x500D 0x0010 0x0002 0x0000 0x0000 89: 0x500F 0x0010 0x0002 0x0000 0x0000 90: 0x5011 0x0010 0x0002 0x0000 0x0000 91: 0x5013 0x0010 0x0002 0x0000 0x0000 92: 0x5015 0x0010 0x0002 0x0000 0x0000 93: 0x5017 0x0010 0x0002 0x0000 0x0000 94: 0x5019 0x0010 0x0002 0x0000 0x0000 95: 0x501B 0x0010 0x0002 0x0000 0x0000 96: 0x501D 0x0010 0x0002 0x0000 0x0000 97: 0x501F 0x0010 0x0002 0x0000 0x0000 98: 0x6001 0x0010 0x0002 0x0000 0x0000 99: 0x6003 0x0010 0x0002 0x0000 0x0000 100: 0x6005 0x0010 0x0002 0x0000 0x0000 101: 0x6007 0x0010 0x0002 0x0000 0x0000 102: 0x6009 0x0010 0x0002 0x0000 0x0000 103: 0x600B 0x0010 0x0002 0x0000 0x0000 104: 0x600D 0x0010 0x0002 0x0000 0x0000 105: 0x600F 0x0010 0x0002 0x0000 0x0000 106: 0x6011 0x0010 0x0002 0x0000 0x0000 107: 0x6013 0x0010 0x0002 0x0000 0x0000 108: 0x6015 0x0010 0x0002 0x0000 0x0000 109: 0x6017 0x0010 0x0002 0x0000 0x0000 110: 0x6019 0x0010 0x0002 0x0000 0x0000 111: 0x601B 0x0010 0x0002 0x0000 0x0000 112: 0x601D 0x0010 0x0002 0x0000 0x0000 113: 0x601F 0x0010 0x0002 0x0000 0x0000 114: 0x7001 0x0010 0x0002 0x0000 0x0000 115: 0x7003 0x0010 0x0002 0x0000 0x0000 116: 0x7005 0x0010 0x0002 0x0000 0x0000 117: 0x7007 0x0010 0x0002 0x0000 0x0000 118: 0x7009 0x0010 0x0002 0x0000 0x0000 119: 0x700B 0x0010 0x0002 0x0000 0x0000 120: 0x700D 0x0010 0x0002 0x0000 0x0000 121: 0x700F 0x0010 0x0002 0x0000 0x0000 122: 0x7011 0x0010 0x0002 0x0000 0x0000 123: 0x7013 0x0010 0x0002 0x0000 0x0000 124: 0x7015 0x0010 0x0002 0x0000 0x0000 125: 0x7017 0x0010 0x0002 0x0000 0x0000 126: 0x7019 0x0010 0x0002 0x0000 0x0000 127: 0x701B 0x0010 0x0002 0x0000 0x0000 128: 0x701D 0x0010 0x0002 0x0000 0x0000 129: 0x701F 0x0010 0x0002 0x0000 0x0000 130: 0x8001 0x0010 0x0002 0x0000 0x0000 131: 0x8003 0x0010 0x0002 0x0000 0x0000 132: 0x8005 0x0010 0x0002 0x0000 0x0000 133: 0x8007 0x0010 0x0002 0x0000 0x0000 134: 0x8009 0x0010 0x0002 0x0000 0x0000 135: 0x800B 0x0010 0x0002 0x0000 0x0000 136: 0x800D 0x0010 0x0002 0x0000 0x0000 137: 0x800F 0x0010 0x0002 0x0000 0x0000 138: 0x8011 0x0010 0x0002 0x0000 0x0000 139: 0x8013 0x0010 0x0002 0x0000 0x0000 140: 0x8015 0x0010 0x0002 0x0000 0x0000 141: 0x8017 0x0010 0x0002 0x0000 0x0000 142: 0x8019 0x0010 0x0002 0x0000 0x0000 143: 0x801B 0x0010 0x0002 0x0000 0x0000 144: 0x801D 0x0010 0x0002 0x0000 0x0000 145: 0x801F 0x0010 0x0002 0x0000 0x0000 146: 0x9001 0x0010 0x0002 0x0000 0x0000 147: 0x9003 0x0010 0x0002 0x0000 0x0000 148: 0x9005 0x0010 0x0002 0x0000 0x0000 149: 0x9007 0x0010 0x0002 0x0000 0x0000 150: 0x9009 0x0010 0x0002 0x0000 0x0000 151: 0x900B 0x0010 0x0002 0x0000 0x0000 152: 0x900D 0x0010 0x0002 0x0000 0x0000 153: 0x900F 0x0010 0x0002 0x0000 0x0000 154: 0x9011 0x0010 0x0002 0x0000 0x0000 155: 0x9013 0x0010 0x0002 0x0000 0x0000 156: 0x9015 0x0010 0x0002 0x0000 0x0000 157: 0x9017 0x0010 0x0002 0x0000 0x0000 158: 0x9019 0x0010 0x0002 0x0000 0x0000 159: 0x901B 0x0010 0x0002 0x0000 0x0000 160: 0x901D 0x0010 0x0002 0x0000 0x0000 161: 0x901F 0x0010 0x0002 0x0000 0x0000 162: 0xA001 0x0010 0x0002 0x0000 0x0000 163: 0xA003 0x0010 0x0002 0x0000 0x0000 164: 0xA005 0x0010 0x0002 0x0000 0x0000 165: 0xA007 0x0010 0x0002 0x0000 0x0000 166: 0xA009 0x0010 0x0002 0x0000 0x0000 167: 0xA00B 0x0010 0x0002 0x0000 0x0000 168: 0xA00D 0x0010 0x0002 0x0000 0x0000 169: 0xA00F 0x0010 0x0002 0x0000 0x0000 170: 0xA011 0x0010 0x0002 0x0000 0x0000 171: 0xA013 0x0010 0x0002 0x0000 0x0000 172: 0xA015 0x0010 0x0002 0x0000 0x0000 173: 0xA017 0x0010 0x0002 0x0000 0x0000 174: 0xA019 0x0010 0x0002 0x0000 0x0000 175: 0xA01B 0x0010 0x0002 0x0000 0x0000 176: 0xA01D 0x0010 0x0002 0x0000 0x0000 177: 0xA01F 0x0010 0x0002 0x0000 0x0000 178: 0xB001 0x0010 0x0002 0x0000 0x0000 179: 0xB003 0x0010 0x0002 0x0000 0x0000 180: 0xB005 0x0010 0x0002 0x0000 0x0000 181: 0xB007 0x0010 0x0002 0x0000 0x0000 182: 0xB009 0x0010 0x0002 0x0000 0x0000 183: 0xB00B 0x0010 0x0002 0x0000 0x0000 184: 0xB00D 0x0010 0x0002 0x0000 0x0000 185: 0xB00F 0x0010 0x0002 0x0000 0x0000 186: 0xB011 0x0010 0x0002 0x0000 0x0000 187: 0xB013 0x0010 0x0002 0x0000 0x0000 188: 0xB015 0x0010 0x0002 0x0000 0x0000 189: 0xB017 0x0010 0x0002 0x0000 0x0000 190: 0xB019 0x0010 0x0002 0x0000 0x0000 191: 0xB01B 0x0010 0x0002 0x0000 0x0000 192: 0xB01D 0x0010 0x0002 0x0000 0x0000 193: 0xB01F 0x0010 0x0002 0x0000 0x0000 194: 0xC001 0x0010 0x0002 0x0000 0x0000 195: 0xC003 0x0010 0x0002 0x0000 0x0000 196: 0xC005 0x0010 0x0002 0x0000 0x0000 197: 0xC007 0x0010 0x0002 0x0000 0x0000 198: 0xC009 0x0010 0x0002 0x0000 0x0000 199: 0xC00B 0x0010 0x0002 0x0000 0x0000 200: 0xC00D 0x0010 0x0002 0x0000 0x0000 201: 0xC00F 0x0010 0x0002 0x0000 0x0000 202: 0xC011 0x0010 0x0002 0x0000 0x0000 203: 0xC013 0x0010 0x0002 0x0000 0x0000 204: 0xC015 0x0010 0x0002 0x0000 0x0000 205: 0xC017 0x0010 0x0002 0x0000 0x0000 206: 0xC019 0x0010 0x0002 0x0000 0x0000 207: 0xC01B 0x0010 0x0002 0x0000 0x0000 208: 0xC01D 0x0010 0x0002 0x0000 0x0000 209: 0xC01F 0x0010 0x0002 0x0000 0x0000 210: 0xD001 0x0010 0x0002 0x0000 0x0000 211: 0xD003 0x0010 0x0002 0x0000 0x0000 212: 0xD005 0x0010 0x0002 0x0000 0x0000 213: 0xD007 0x0010 0x0002 0x0000 0x0000 214: 0xD009 0x0010 0x0002 0x0000 0x0000 215: 0xD00B 0x0010 0x0002 0x0000 0x0000 216: 0xD00D 0x0010 0x0002 0x0000 0x0000 217: 0xD00F 0x0010 0x0002 0x0000 0x0000 218: 0xD011 0x0010 0x0002 0x0000 0x0000 219: 0xD013 0x0010 0x0002 0x0000 0x0000 220: 0xD015 0x0010 0x0002 0x0000 0x0000 221: 0xD017 0x0010 0x0002 0x0000 0x0000 222: 0xD019 0x0010 0x0002 0x0000 0x0000 223: 0xD01B 0x0010 0x0002 0x0000 0x0000 224: 0xD01D 0x0010 0x0002 0x0000 0x0000 225: 0xD01F 0x0010 0x0002 0x0000 0x0000 226: 0xE001 0x0010 0x0002 0x0000 0x0000 227: 0xE003 0x0010 0x0002 0x0000 0x0000 228: 0xE005 0x0010 0x0002 0x0000 0x0000 229: 0xE007 0x0010 0x0002 0x0000 0x0000 230: 0xE009 0x0010 0x0002 0x0000 0x0000 231: 0xE00B 0x0010 0x0002 0x0000 0x0000 232: 0xE00D 0x0010 0x0002 0x0000 0x0000 233: 0xE00F 0x0010 0x0002 0x0000 0x0000 234: 0xE011 0x0010 0x0002 0x0000 0x0000 235: 0xE013 0x0010 0x0002 0x0000 0x0000 236: 0xE015 0x0010 0x0002 0x0000 0x0000 237: 0xE017 0x0010 0x0002 0x0000 0x0000 238: 0xE019 0x0010 0x0002 0x0000 0x0000 239: 0xE01B 0x0010 0x0002 0x0000 0x0000 240: 0xE01D 0x0010 0x0002 0x0000 0x0000 241: 0xE01F 0x0010 0x0002 0x0000 0x0000 242: 0xF001 0x0010 0x0002 0x0000 0x0000 243: 0xF003 0x0010 0x0002 0x0000 0x0000 244: 0xF005 0x0010 0x0002 0x0000 0x0000 245: 0xF007 0x0010 0x0002 0x0000 0x0000 246: 0xF009 0x0010 0x0002 0x0000 0x0000 247: 0xF00B 0x0010 0x0002 0x0000 0x0000 248: 0xF00D 0x0010 0x0002 0x0000 0x0000 249: 0xF00F 0x0010 0x0002 0x0000 0x0000 250: 0xF011 0x0010 0x0002 0x0000 0x0000 251: 0xF013 0x0010 0x0002 0x0000 0x0000 252: 0xF015 0x0010 0x0002 0x0000 0x0000 253: 0xF017 0x0010 0x0002 0x0000 0x0000 254: 0xF019 0x0010 0x0002 0x0000 0x0000 255: 0xF01B 0x0010 0x0002 0x0000 0x0000 256: 0xF01D 0x0010 0x0002 0x0000 0x0000 257: 0xF01E 0x0010 0x0002 0x0000 0x0000 258: 0x0001 0x0010 0x0002 0x0000 0x0000 259: 0x0001 0x0010 0x0002 0x0000 0x0000 260: 0x0001 0x0018 0x0002 0x0000 0x0000 261: 0x0001 0x0014 0x0002 0x0000 0x0000 262: 0x0001 0x001C 0x0002 0x0000 0x0000 263: 0x0001 0x0012 0x0002 0x0000 0x0000 264: 0x0001 0x001A 0x0002 0x0000 0x0000 265: 0x0001 0x0016 0x0002 0x0000 0x0000 266: 0x0001 0x001E 0x0002 0x0000 0x0000 267: 0x0001 0x0011 0x0002 0x0000 0x0000 268: 0x0001 0x0019 0x0002 0x0000 0x0000 269: 0x0001 0x0015 0x0002 0x0000 0x0000 270: 0x0001 0x001D 0x0002 0x0000 0x0000 271: 0x0001 0x0013 0x0002 0x0000 0x0000 272: 0x0001 0x001B 0x0002 0x0000 0x0000 273: 0x0001 0x0017 0x0002 0x0000 0x0000 274: 0x0001 0x001F 0x0002 0x0000 0x0000 275: 0x0001 0x8010 0x0002 0x0000 0x0000 276: 0x0001 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0x0003 0x0000 0x0000 1391: 0xF71E 0x982F 0x0002 0x0000 0x0000 1392: 0xF71E 0x982F 0x0003 0x0000 0x0000 1393: 0xF71E 0x98AF 0x0002 0x0000 0x0000 1394: 0xF71E 0x98AF 0x0003 0x0000 0x0000 1395: 0xF71E 0x986F 0x0002 0x0000 0x0000 1396: 0xF71E 0x986F 0x0003 0x0000 0x0000 1397: 0xF71E 0x98EF 0x0002 0x0000 0x0000 1398: 0xF71E 0x98EF 0x0003 0x0000 0x0000 1399: 0xF71E 0x9C0F 0x0002 0x0000 0x0000 1400: 0xF71E 0x9C0F 0x0003 0x0000 0x0000 1401: 0xF71E 0x9C8F 0x0002 0x0000 0x0000 1402: 0xF71E 0x9C8F 0x0003 0x0000 0x0000 1403: 0xF71E 0x9C4F 0x0002 0x0000 0x0000 1404: 0xF71E 0x9C4F 0x0003 0x0000 0x0000 1405: 0xF71E 0x9CCF 0x0002 0x0000 0x0000 1406: 0xF71E 0x9CCF 0x0003 0x0000 0x0000 1407: 0xF71E 0x9C2F 0x0002 0x0000 0x0000 1408: 0xF71E 0x9C2F 0x0003 0x0000 0x0000 1409: 0xF71E 0x9CAF 0x0002 0x0000 0x0000 1410: 0xF71E 0x9CAF 0x0003 0x0000 0x0000 1411: 0xF71E 0x9C6F 0x0002 0x0000 0x0000 1412: 0xF71E 0x9C6F 0x0003 0x0000 0x0000 1413: 0xF71E 0x9CEF 0x0002 0x0000 0x0000 1414: 0xF71E 0x9CEF 0x0003 0x0000 0x0000 1415: 0xF71E 0xA00F 0x0002 0x0000 0x0000 1416: 0xF71E 0xA00F 0x0003 0x0000 0x0000 1417: 0xF71E 0xA08F 0x0002 0x0000 0x0000 1418: 0xF71E 0xA08F 0x0003 0x0000 0x0000 1419: 0xF71E 0xA04F 0x0002 0x0000 0x0000 1420: 0xF71E 0xA04F 0x0003 0x0000 0x0000 1421: 0xF71E 0xA0CF 0x0002 0x0000 0x0000 1422: 0xF71E 0xA0CF 0x0003 0x0000 0x0000 1423: 0xF71E 0xA02F 0x0002 0x0000 0x0000 1424: 0xF71E 0xA02F 0x0003 0x0000 0x0000 1425: 0xF71E 0xA0AF 0x0002 0x0000 0x0000 1426: 0xF71E 0xA0AF 0x0003 0x0000 0x0000 1427: 0xF71E 0xA06F 0x0002 0x0000 0x0000 1428: 0xF71E 0xA06F 0x0003 0x0000 0x0000 1429: 0xF71E 0xA0EF 0x0002 0x0000 0x0000 1430: 0xF71E 0xA0EF 0x0003 0x0000 0x0000 1431: 0xF71E 0xA40F 0x0002 0x0000 0x0000 1432: 0xF71E 0xA40F 0x0003 0x0000 0x0000 1433: 0xF71E 0xA48F 0x0002 0x0000 0x0000 1434: 0xF71E 0xA48F 0x0003 0x0000 0x0000 1435: 0xF71E 0xA44F 0x0002 0x0000 0x0000 1436: 0xF71E 0xA44F 0x0003 0x0000 0x0000 1437: 0xF71E 0xA4CF 0x0002 0x0000 0x0000 1438: 0xF71E 0xA4CF 0x0003 0x0000 0x0000 1439: 0xF71E 0xA42F 0x0002 0x0000 0x0000 1440: 0xF71E 0xA42F 0x0003 0x0000 0x0000 1441: 0xF71E 0xA4AF 0x0002 0x0000 0x0000 1442: 0xF71E 0xA4AF 0x0003 0x0000 0x0000 1443: 0xF71E 0xA46F 0x0002 0x0000 0x0000 1444: 0xF71E 0xA46F 0x0003 0x0000 0x0000 1445: 0xF71E 0xA4EF 0x0002 0x0000 0x0000 1446: 0xF71E 0xA4EF 0x0003 0x0000 0x0000 1447: 0xF71E 0xA80F 0x0002 0x0000 0x0000 1448: 0xF71E 0xA80F 0x0003 0x0000 0x0000 1449: 0xF71E 0xA88F 0x0002 0x0000 0x0000 1450: 0xF71E 0xA88F 0x0003 0x0000 0x0000 1451: 0xF71E 0xA84F 0x0002 0x0000 0x0000 1452: 0xF71E 0xA84F 0x0003 0x0000 0x0000 1453: 0xF71E 0xA8CF 0x0002 0x0000 0x0000 1454: 0xF71E 0xA8CF 0x0003 0x0000 0x0000 1455: 0xF71E 0xA82F 0x0002 0x0000 0x0000 1456: 0xF71E 0xA82F 0x0003 0x0000 0x0000 1457: 0xF71E 0xA8AF 0x0002 0x0000 0x0000 1458: 0xF71E 0xA8AF 0x0003 0x0000 0x0000 1459: 0xF71E 0xA86F 0x0002 0x0000 0x0000 1460: 0xF71E 0xA86F 0x0003 0x0000 0x0000 1461: 0xF71E 0xA8EF 0x0002 0x0000 0x0000 1462: 0xF71E 0xA8EF 0x0003 0x0000 0x0000 1463: 0xF71E 0xAC0F 0x0002 0x0000 0x0000 1464: 0xF71E 0xAC0F 0x0003 0x0000 0x0000 1465: 0xF71E 0xAC8F 0x0002 0x0000 0x0000 1466: 0xF71E 0xAC8F 0x0003 0x0000 0x0000 1467: 0xF71E 0xAC4F 0x0002 0x0000 0x0000 1468: 0xF71E 0xAC4F 0x0003 0x0000 0x0000 1469: 0xF71E 0xACCF 0x0002 0x0000 0x0000 1470: 0xF71E 0xACCF 0x0003 0x0000 0x0000 1471: 0xF71E 0xAC2F 0x0002 0x0000 0x0000 1472: 0xF71E 0xAC2F 0x0003 0x0000 0x0000 1473: 0xF71E 0xACAF 0x0002 0x0000 0x0000 1474: 0xF71E 0xACAF 0x0003 0x0000 0x0000 1475: 0xF71E 0xAC6F 0x0002 0x0000 0x0000 1476: 0xF71E 0xAC6F 0x0003 0x0000 0x0000 1477: 0xF71E 0xACEF 0x0002 0x0000 0x0000 1478: 0xF71E 0xACEF 0x0003 0x0000 0x0000 1479: 0xF71E 0xB00F 0x0002 0x0000 0x0000 1480: 0xF71E 0xB00F 0x0003 0x0000 0x0000 1481: 0xF71E 0xB08F 0x0002 0x0000 0x0000 1482: 0xF71E 0xB08F 0x0003 0x0000 0x0000 1483: 0xF71E 0xB04F 0x0002 0x0000 0x0000 1484: 0xF71E 0xB04F 0x0003 0x0000 0x0000 1485: 0xF71E 0xB0CF 0x0002 0x0000 0x0000 1486: 0xF71E 0xB0CF 0x0003 0x0000 0x0000 1487: 0xF71E 0xB02F 0x0002 0x0000 0x0000 1488: 0xF71E 0xB02F 0x0003 0x0000 0x0000 1489: 0xF71E 0xB0AF 0x0002 0x0000 0x0000 1490: 0xF71E 0xB0AF 0x0003 0x0000 0x0000 1491: 0xF71E 0xB06F 0x0002 0x0000 0x0000 1492: 0xF71E 0xB06F 0x0003 0x0000 0x0000 1493: 0xF71E 0xB0EF 0x0002 0x0000 0x0000 1494: 0xF71E 0xB0EF 0x0003 0x0000 0x0000 1495: 0xF71E 0xB40F 0x0002 0x0000 0x0000 1496: 0xF71E 0xB40F 0x0003 0x0000 0x0000 1497: 0xF71E 0xB48F 0x0002 0x0000 0x0000 1498: 0xF71E 0xB48F 0x0003 0x0000 0x0000 1499: 0xF71E 0xB44F 0x0002 0x0000 0x0000 1500: 0xF71E 0xB44F 0x0003 0x0000 0x0000 1501: 0xF71E 0xB4CF 0x0002 0x0000 0x0000 1502: 0xF71E 0xB4CF 0x0003 0x0000 0x0000 1503: 0xF71E 0xB42F 0x0002 0x0000 0x0000 1504: 0xF71E 0xB42F 0x0003 0x0000 0x0000 1505: 0xF71E 0xB4AF 0x0002 0x0000 0x0000 1506: 0xF71E 0xB4AF 0x0003 0x0000 0x0000 1507: 0xF71E 0xB46F 0x0002 0x0000 0x0000 1508: 0xF71E 0xB46F 0x0003 0x0000 0x0000 1509: 0xF71E 0xB4EF 0x0002 0x0000 0x0000 1510: 0xF71E 0xB4EF 0x0003 0x0000 0x0000 1511: 0xF71E 0xB80F 0x0002 0x0000 0x0000 1512: 0xF71E 0xB80F 0x0003 0x0000 0x0000 1513: 0xF71E 0xB88F 0x0002 0x0000 0x0000 1514: 0xF71E 0xB88F 0x0003 0x0000 0x0000 1515: 0xF71E 0xB84F 0x0002 0x0000 0x0000 1516: 0xF71E 0xB84F 0x0003 0x0000 0x0000 1517: 0xF71E 0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 3 pins used: 27 not used: 39 1543 'test steps' 1576 lines M119 REV B 3 8-input NAND PINS Main menu Fri Jun 30 13:52:41 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:52:44 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 9 Main menu Fri Jun 30 13:52:53 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 13:53:14 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:53:18 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 11 Main menu Fri Jun 30 13:53:36 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 13:54:17 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:54:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 15 Main menu Fri Jun 30 13:54:21 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 13:54:43 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:54:45 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 31 Main menu Fri Jun 30 13:54:49 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m112.tst reading test file: tests\m112.tst comment: M112 PCB REV D SCHEMATIC REV D 10 2-input NOR comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 O AC1 E1-13 pins: 4 I AD1 E1-5 pins: 5 I AE1 E1-6 pins: 6 O AF1 E1-4 pins: 7 I AD2 E1-9 pins: 8 I AE2 E1-8 pins: 9 O AF2 E1-10 pins: 10 I AH1 E1-3 pins: 11 I AJ1 E1-2 pins: 12 O AK1 E1-1 pins: 13 I AH2 E2-3 pins: 14 I AJ2 E2-2 pins: 15 O AK2 E2-1 pins: 16 I AL1 E2-6 pins: 17 I AM1 E2-5 pins: 18 O AN1 E2-4 pins: 19 I AL2 E3-9 pins: 20 I AM2 E3-8 pins: 21 O AN2 E3-10 pins: 22 I AP1 E3-12 pins: 23 I AR1 E3-11 pins: 24 O AS1 E3-13 pins: 25 I AP2 E3-6 pins: 26 I AR2 E3-5 pins: 27 O AS2 E3-4 pins: 28 I AT2 E3-3 pins: 29 I AU2 E3-2 pins: 30 O AV2 E3-1 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 010 test 3: 110 test 4: 100 test 5: 001 test 6: 010 test 7: 110 test 8: 100 test 9: 001 test 10: 010 test 11: 110 test 12: 100 test 13: 001 test 14: 010 test 15: 110 test 16: 100 test 17: 001 test 18: 010 test 19: 110 test 20: 100 test 21: 001 test 22: 010 test 23: 110 test 24: 100 test 25: 001 test 26: 010 test 27: 110 test 28: 100 test 29: 001 test 30: 010 test 31: 110 test 32: 100 test 33: 001 test 34: 010 test 35: 110 test 36: 100 test 37: 001 test 38: 010 test 39: 110 test 40: 100 test 41: 001 test 42: 001001001001001001001001001001 test 43: 110110110110110110110110110110 test 44: 010 test 45: 001 test 46: 100 test 47: 110 test 48: 010 test 49: 001 test 50: 100 test 51: 110 test 52: 010 test 53: 001 test 54: 100 test 55: 110 test 56: 010 test 57: 001 test 58: 100 test 59: 110 test 60: 010 test 61: 001 test 62: 100 test 63: 110 test 64: 010 test 65: 001 test 66: 100 test 67: 110 test 68: 010 test 69: 001 test 70: 100 test 71: 110 test 72: 010 test 73: 001 test 74: 100 test 75: 110 test 76: 010 test 77: 001 test 78: 100 test 79: 110 test 80: 010 test 81: 001 test 82: 100 test 83: 110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0x4404 0x9249 0x0002 0x0000 0x0000 3: 0xC404 0x9249 0x0002 0x0000 0x0000 4: 0x8404 0x9249 0x0002 0x0000 0x0000 5: 0x2404 0x9249 0x0002 0x0000 0x0000 6: 0x2804 0x9249 0x0002 0x0000 0x0000 7: 0x3804 0x9249 0x0002 0x0000 0x0000 8: 0x3004 0x9249 0x0002 0x0000 0x0000 9: 0x2404 0x9249 0x0002 0x0000 0x0000 10: 0x2408 0x9249 0x0002 0x0000 0x0000 11: 0x2418 0x9249 0x0002 0x0000 0x0000 12: 0x2410 0x9249 0x0002 0x0000 0x0000 13: 0x2404 0x9249 0x0002 0x0000 0x0000 14: 0x2504 0x1249 0x0002 0x0000 0x0000 15: 0x2704 0x1249 0x0002 0x0000 0x0000 16: 0x2604 0x1249 0x0002 0x0000 0x0000 17: 0x2404 0x9249 0x0002 0x0000 0x0000 18: 0x2405 0x9248 0x0002 0x0000 0x0000 19: 0x2407 0x9248 0x0002 0x0000 0x0000 20: 0x2406 0x9248 0x0002 0x0000 0x0000 21: 0x2404 0x9249 0x0002 0x0000 0x0000 22: 0x2404 0xA249 0x0002 0x0000 0x0000 23: 0x2404 0xE249 0x0002 0x0000 0x0000 24: 0x2404 0xC249 0x0002 0x0000 0x0000 25: 0x2404 0x9249 0x0002 0x0000 0x0000 26: 0x2404 0x9245 0x0002 0x0000 0x0000 27: 0x2404 0x9247 0x0002 0x0000 0x0000 28: 0x2404 0x9243 0x0002 0x0000 0x0000 29: 0x2404 0x9249 0x0002 0x0000 0x0000 30: 0x2404 0x9449 0x0002 0x0000 0x0000 31: 0x2404 0x9C49 0x0002 0x0000 0x0000 32: 0x2404 0x9849 0x0002 0x0000 0x0000 33: 0x2404 0x9249 0x0002 0x0000 0x0000 34: 0x2404 0x9229 0x0002 0x0000 0x0000 35: 0x2404 0x9239 0x0002 0x0000 0x0000 36: 0x2404 0x9219 0x0002 0x0000 0x0000 37: 0x2404 0x9249 0x0002 0x0000 0x0000 38: 0x2404 0x9249 0x0001 0x0000 0x0000 39: 0x2404 0x92C9 0x0001 0x0000 0x0000 40: 0x2404 0x92C9 0x0000 0x0000 0x0000 41: 0x2404 0x9249 0x0002 0x0000 0x0000 42: 0x2404 0x9249 0x0002 0x0000 0x0000 43: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 44: 0x5B1B 0x6CB6 0x0001 0x0000 0x0000 45: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 46: 0x9B1B 0x6CB6 0x0001 0x0000 0x0000 47: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 48: 0xCB1B 0x6CB6 0x0001 0x0000 0x0000 49: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 50: 0xD31B 0x6CB6 0x0001 0x0000 0x0000 51: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 52: 0xDB0B 0x6CB6 0x0001 0x0000 0x0000 53: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 54: 0xDB13 0x6CB6 0x0001 0x0000 0x0000 55: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 56: 0xD91B 0x6CB6 0x0001 0x0000 0x0000 57: 0xD81B 0xECB6 0x0001 0x0000 0x0000 58: 0xDA1B 0x6CB6 0x0001 0x0000 0x0000 59: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 60: 0xDB19 0x6CB6 0x0001 0x0000 0x0000 61: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 62: 0xDB1A 0x6CB6 0x0001 0x0000 0x0000 63: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 64: 0xDB1B 0x2CB6 0x0001 0x0000 0x0000 65: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 66: 0xDB1B 0x4CB6 0x0001 0x0000 0x0000 67: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 68: 0xDB1B 0x6CB4 0x0001 0x0000 0x0000 69: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 70: 0xDB1B 0x6CB2 0x0001 0x0000 0x0000 71: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 72: 0xDB1B 0x64B6 0x0001 0x0000 0x0000 73: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 74: 0xDB1B 0x68B6 0x0001 0x0000 0x0000 75: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 76: 0xDB1B 0x6CA6 0x0001 0x0000 0x0000 77: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 78: 0xDB1B 0x6C96 0x0001 0x0000 0x0000 79: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 80: 0xDB1B 0x6C36 0x0001 0x0000 0x0000 81: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 82: 0xDB1B 0x6CB6 0x0000 0x0000 0x0000 83: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M112 PCB REV D SCHEMATIC REV D 10 2-input NOR PINS Main menu Fri Jun 30 13:55:10 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:55:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 168 Main menu Fri Jun 30 13:55:33 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 13:55:47 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:55:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O O O O O O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvv vvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^ was hi 111111111111111111111111 1111 total fails 14, total passes 0 Main menu Fri Jun 30 13:55:59 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 13:56:28 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:56:43 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 23 Main menu Fri Jun 30 13:56:46 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:57:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Fri Jun 30 13:57:01 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 13:57:04 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:57:05 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 39 Main menu Fri Jun 30 13:57:07 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 13:57:22 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:57:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 36 Main menu Fri Jun 30 13:57:29 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 13:57:46 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:57:47 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 43 Main menu Fri Jun 30 13:57:50 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 13:58:05 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 13:58:06 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 13:58:06 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:58:08 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 23 Main menu Fri Jun 30 13:58:10 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 13:58:34 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:58:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 20 Main menu Fri Jun 30 13:58:41 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst could not open test file. valid test files are: reverting back to test file: tests\m617.tst Main menu Fri Jun 30 13:59:00 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:59:02 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails OI OI O IO OI O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 14, total passes 0 Main menu Fri Jun 30 13:59:12 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst could not open test file. valid test files are: reverting back to test file: tests\m617.tst Main menu Fri Jun 30 13:59:20 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 13:59:31 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 13:59:35 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:59:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 59 Main menu Fri Jun 30 13:59:40 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 13:59:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 36 Main menu Fri Jun 30 14:11:42 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m212.tst reading test file: tests\m212.tst comment: ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER comment: comment: ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) comment: pins: PINS pins: 1 I AB1 E3-4,10;E6-4,10;E9-4,10 CLEAR-N CLEARS FF0 THRU FF5 pins: 2 I AL2 E1-3 INA0-N pins: 3 I AM2 E2-2 INA1-N pins: 4 I AN2 E4-2 INA2-N pins: 5 I AR2 E5-2 INA3-N pins: 6 I AV1 E7-2 INA4-N pins: 7 I AV2 E8-2 INA5-N pins: 8 I AN1 ENABLE_INPUT_A pins: 9 I AP2 E1-4 INB0-N pins: 10 I AR1 E2-4 INB1-N pins: 11 I AS1 E4-4 INB2-N pins: 12 I AU1 E5-4 INB3-N pins: 13 I AA1 E7-4 INB4-N pins: 14 I AT2 E8-4 INB5-N pins: 15 I AU2 ENABLE_INPUT_B pins: 16 I AM1 E1-1 SHIFT_R_INSERT-N RIGHT SHIFTS INTO FF0 pins: 17 I AL1 ENABLE_R_SHIFT pins: 18 I AS2 E8-9 SHIFT_L_INSERT-N LEFT SHIFTS INTO FF5 pins: 19 I AP1 ENABLE_L_SHIFT pins: 20 I AC1 E3-3,11;E6-3,11;E9-3,11 CLOCK (RISING EDGE) pins: 21 O AD1 E3-6 FF0 pins: 22 O AD2 E3-5 FF0-N pins: 23 O AF1 E3-8 FF1 pins: 24 O AE1 E3-9 FF1-N pins: 25 O AH2 E6-6 FF2 pins: 26 O AE2 E6-5 FF2-N pins: 27 O AH1 E6-8 FF3 pins: 28 O AF2 E6-9 FF3-N pins: 29 O AK2 E9-6 FF4 pins: 30 O AJ2 E9-5 FF4-N pins: 31 O AK1 E9-8 FF5 pins: 32 O AJ1 A9-9 FF5-N pins: direction: IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO comment: ; CLEAR-N, NO ENABLES test 1: 01111110111111010100010101010101 test 2: 1 comment: comment: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM comment: ; see mk_m212_ld_shift.c comment: comment: comment: ; TEST A INPUTS, GRAY CODE PATTERN comment: comment: ; ENABLE A INPUTS test 3: 1 comment: ; LOAD FFs FROM INPUT A comment: test 4: 000001 test 5: 1010101010110 test 6: 0 test 7: 000011 test 8: 1010101011010 test 9: 0 test 10: 000010 test 11: 1010101011001 test 12: 0 test 13: 000110 test 14: 1010101101001 test 15: 0 test 16: 000111 test 17: 1010101101010 test 18: 0 test 19: 000101 test 20: 1010101100110 test 21: 0 test 22: 000100 test 23: 1010101100101 test 24: 0 test 25: 001100 test 26: 1010110100101 test 27: 0 test 28: 001101 test 29: 1010110100110 test 30: 0 test 31: 001111 test 32: 1010110101010 test 33: 0 test 34: 001110 test 35: 1010110101001 test 36: 0 test 37: 001010 test 38: 1010110011001 test 39: 0 test 40: 001011 test 41: 1010110011010 test 42: 0 test 43: 001001 test 44: 1010110010110 test 45: 0 test 46: 001000 test 47: 1010110010101 test 48: 0 test 49: 011000 test 50: 1011010010101 test 51: 0 test 52: 011001 test 53: 1011010010110 test 54: 0 test 55: 011011 test 56: 1011010011010 test 57: 0 test 58: 011010 test 59: 1011010011001 test 60: 0 test 61: 011110 test 62: 1011010101001 test 63: 0 test 64: 011111 test 65: 1011010101010 test 66: 0 test 67: 011101 test 68: 1011010100110 test 69: 0 test 70: 011100 test 71: 1011010100101 test 72: 0 test 73: 010100 test 74: 1011001100101 test 75: 0 test 76: 010101 test 77: 1011001100110 test 78: 0 test 79: 010111 test 80: 1011001101010 test 81: 0 test 82: 010110 test 83: 1011001101001 test 84: 0 test 85: 010010 test 86: 1011001011001 test 87: 0 test 88: 010011 test 89: 1011001011010 test 90: 0 test 91: 010001 test 92: 1011001010110 test 93: 0 test 94: 010000 test 95: 1011001010101 test 96: 0 test 97: 110000 test 98: 1101001010101 test 99: 0 test 100: 110001 test 101: 1101001010110 test 102: 0 test 103: 110011 test 104: 1101001011010 test 105: 0 test 106: 110010 test 107: 1101001011001 test 108: 0 test 109: 110110 test 110: 1101001101001 test 111: 0 test 112: 110111 test 113: 1101001101010 test 114: 0 test 115: 110101 test 116: 1101001100110 test 117: 0 test 118: 110100 test 119: 1101001100101 test 120: 0 test 121: 111100 test 122: 1101010100101 test 123: 0 test 124: 111101 test 125: 1101010100110 test 126: 0 test 127: 111111 test 128: 1101010101010 test 129: 0 test 130: 111110 test 131: 1101010101001 test 132: 0 test 133: 111010 test 134: 1101010011001 test 135: 0 test 136: 111011 test 137: 1101010011010 test 138: 0 test 139: 111001 test 140: 1101010010110 test 141: 0 test 142: 111000 test 143: 1101010010101 test 144: 0 test 145: 101000 test 146: 1100110010101 test 147: 0 test 148: 101001 test 149: 1100110010110 test 150: 0 test 151: 101011 test 152: 1100110011010 test 153: 0 test 154: 101010 test 155: 1100110011001 test 156: 0 test 157: 101110 test 158: 1100110101001 test 159: 0 test 160: 101111 test 161: 1100110101010 test 162: 0 test 163: 101101 test 164: 1100110100110 test 165: 0 test 166: 101100 test 167: 1100110100101 test 168: 0 test 169: 100100 test 170: 1100101100101 test 171: 0 test 172: 100101 test 173: 1100101100110 test 174: 0 test 175: 100111 test 176: 1100101101010 test 177: 0 test 178: 100110 test 179: 1100101101001 test 180: 0 test 181: 100010 test 182: 1100101011001 test 183: 0 test 184: 100011 test 185: 1100101011010 test 186: 0 test 187: 100001 test 188: 1100101010110 test 189: 0 test 190: 100000 test 191: 1100101010101 test 192: 0 test 193: 000000 test 194: 1010101010101 test 195: 0 comment: comment: ; DISABLE A INPUTS test 196: 0 comment: comment: comment: ; TEST B INPUTS comment: comment: ; ENABLE B INPUTS test 197: 1 comment: ; LOAD FFs FROM INPUT B comment: test 198: 000001 test 199: 1010101010110 test 200: 0 test 201: 000011 test 202: 1010101011010 test 203: 0 test 204: 000010 test 205: 1010101011001 test 206: 0 test 207: 000110 test 208: 1010101101001 test 209: 0 test 210: 000111 test 211: 1010101101010 test 212: 0 test 213: 000101 test 214: 1010101100110 test 215: 0 test 216: 000100 test 217: 1010101100101 test 218: 0 test 219: 001100 test 220: 1010110100101 test 221: 0 test 222: 001101 test 223: 1010110100110 test 224: 0 test 225: 001111 test 226: 1010110101010 test 227: 0 test 228: 001110 test 229: 1010110101001 test 230: 0 test 231: 001010 test 232: 1010110011001 test 233: 0 test 234: 001011 test 235: 1010110011010 test 236: 0 test 237: 001001 test 238: 1010110010110 test 239: 0 test 240: 001000 test 241: 1010110010101 test 242: 0 test 243: 011000 test 244: 1011010010101 test 245: 0 test 246: 011001 test 247: 1011010010110 test 248: 0 test 249: 011011 test 250: 1011010011010 test 251: 0 test 252: 011010 test 253: 1011010011001 test 254: 0 test 255: 011110 test 256: 1011010101001 test 257: 0 test 258: 011111 test 259: 1011010101010 test 260: 0 test 261: 011101 test 262: 1011010100110 test 263: 0 test 264: 011100 test 265: 1011010100101 test 266: 0 test 267: 010100 test 268: 1011001100101 test 269: 0 test 270: 010101 test 271: 1011001100110 test 272: 0 test 273: 010111 test 274: 1011001101010 test 275: 0 test 276: 010110 test 277: 1011001101001 test 278: 0 test 279: 010010 test 280: 1011001011001 test 281: 0 test 282: 010011 test 283: 1011001011010 test 284: 0 test 285: 010001 test 286: 1011001010110 test 287: 0 test 288: 010000 test 289: 1011001010101 test 290: 0 test 291: 110000 test 292: 1101001010101 test 293: 0 test 294: 110001 test 295: 1101001010110 test 296: 0 test 297: 110011 test 298: 1101001011010 test 299: 0 test 300: 110010 test 301: 1101001011001 test 302: 0 test 303: 110110 test 304: 1101001101001 test 305: 0 test 306: 110111 test 307: 1101001101010 test 308: 0 test 309: 110101 test 310: 1101001100110 test 311: 0 test 312: 110100 test 313: 1101001100101 test 314: 0 test 315: 111100 test 316: 1101010100101 test 317: 0 test 318: 111101 test 319: 1101010100110 test 320: 0 test 321: 111111 test 322: 1101010101010 test 323: 0 test 324: 111110 test 325: 1101010101001 test 326: 0 test 327: 111010 test 328: 1101010011001 test 329: 0 test 330: 111011 test 331: 1101010011010 test 332: 0 test 333: 111001 test 334: 1101010010110 test 335: 0 test 336: 111000 test 337: 1101010010101 test 338: 0 test 339: 101000 test 340: 1100110010101 test 341: 0 test 342: 101001 test 343: 1100110010110 test 344: 0 test 345: 101011 test 346: 1100110011010 test 347: 0 test 348: 101010 test 349: 1100110011001 test 350: 0 test 351: 101110 test 352: 1100110101001 test 353: 0 test 354: 101111 test 355: 1100110101010 test 356: 0 test 357: 101101 test 358: 1100110100110 test 359: 0 test 360: 101100 test 361: 1100110100101 test 362: 0 test 363: 100100 test 364: 1100101100101 test 365: 0 test 366: 100101 test 367: 1100101100110 test 368: 0 test 369: 100111 test 370: 1100101101010 test 371: 0 test 372: 100110 test 373: 1100101101001 test 374: 0 test 375: 100010 test 376: 1100101011001 test 377: 0 test 378: 100011 test 379: 1100101011010 test 380: 0 test 381: 100001 test 382: 1100101010110 test 383: 0 test 384: 100000 test 385: 1100101010101 test 386: 0 test 387: 000000 test 388: 1010101010101 test 389: 0 comment: comment: ; DISABLE B INPUTS test 390: 0 comment: comment: comment: ; TEST SHIFT R (LOAD VIA A INPUTS) comment: comment: ; SHIFT IN A ZERO test 391: 0 comment: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS comment: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT test 392: 0000011 test 393: 1010101010110 test 394: 0 1 0 test 395: 1010101010101 test 396: 0 0 test 397: 0000111 test 398: 1010101011010 test 399: 0 1 0 test 400: 1010101010110 test 401: 0 0 test 402: 0000101 test 403: 1010101011001 test 404: 0 1 0 test 405: 1010101010110 test 406: 0 0 test 407: 0001101 test 408: 1010101101001 test 409: 0 1 0 test 410: 1010101011010 test 411: 0 0 test 412: 0001111 test 413: 1010101101010 test 414: 0 1 0 test 415: 1010101011010 test 416: 0 0 test 417: 0001011 test 418: 1010101100110 test 419: 0 1 0 test 420: 1010101011001 test 421: 0 0 test 422: 0001001 test 423: 1010101100101 test 424: 0 1 0 test 425: 1010101011001 test 426: 0 0 test 427: 0011001 test 428: 1010110100101 test 429: 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test 1371: 1010101101001 test 1372: 0 10 test 1373: 1010110100110 test 1374: 00 test 1375: 0001111 test 1376: 1010101101010 test 1377: 0 10 test 1378: 1010110101010 test 1379: 00 test 1380: 0001011 test 1381: 1010101100110 test 1382: 0 10 test 1383: 1010110011010 test 1384: 00 test 1385: 0001001 test 1386: 1010101100101 test 1387: 0 10 test 1388: 1010110010110 test 1389: 00 test 1390: 0011001 test 1391: 1010110100101 test 1392: 0 10 test 1393: 1011010010110 test 1394: 00 test 1395: 0011011 test 1396: 1010110100110 test 1397: 0 10 test 1398: 1011010011010 test 1399: 00 test 1400: 0011111 test 1401: 1010110101010 test 1402: 0 10 test 1403: 1011010101010 test 1404: 00 test 1405: 0011101 test 1406: 1010110101001 test 1407: 0 10 test 1408: 1011010100110 test 1409: 00 test 1410: 0010101 test 1411: 1010110011001 test 1412: 0 10 test 1413: 1011001100110 test 1414: 00 test 1415: 0010111 test 1416: 1010110011010 test 1417: 0 10 test 1418: 1011001101010 test 1419: 00 test 1420: 0010011 test 1421: 1010110010110 test 1422: 0 10 test 1423: 1011001011010 test 1424: 00 test 1425: 0010001 test 1426: 1010110010101 test 1427: 0 10 test 1428: 1011001010110 test 1429: 00 test 1430: 0110001 test 1431: 1011010010101 test 1432: 0 10 test 1433: 1101001010110 test 1434: 00 test 1435: 0110011 test 1436: 1011010010110 test 1437: 0 10 test 1438: 1101001011010 test 1439: 00 test 1440: 0110111 test 1441: 1011010011010 test 1442: 0 10 test 1443: 1101001101010 test 1444: 00 test 1445: 0110101 test 1446: 1011010011001 test 1447: 0 10 test 1448: 1101001100110 test 1449: 00 test 1450: 0111101 test 1451: 1011010101001 test 1452: 0 10 test 1453: 1101010100110 test 1454: 00 test 1455: 0111111 test 1456: 1011010101010 test 1457: 0 10 test 1458: 1101010101010 test 1459: 00 test 1460: 0111011 test 1461: 1011010100110 test 1462: 0 10 test 1463: 1101010011010 test 1464: 00 test 1465: 0111001 test 1466: 1011010100101 test 1467: 0 10 test 1468: 1101010010110 test 1469: 00 test 1470: 0101001 test 1471: 1011001100101 test 1472: 0 10 test 1473: 1100110010110 test 1474: 00 test 1475: 0101011 test 1476: 1011001100110 test 1477: 0 10 test 1478: 1100110011010 test 1479: 00 test 1480: 0101111 test 1481: 1011001101010 test 1482: 0 10 test 1483: 1100110101010 test 1484: 00 test 1485: 0101101 test 1486: 1011001101001 test 1487: 0 10 test 1488: 1100110100110 test 1489: 00 test 1490: 0100101 test 1491: 1011001011001 test 1492: 0 10 test 1493: 1100101100110 test 1494: 00 test 1495: 0100111 test 1496: 1011001011010 test 1497: 0 10 test 1498: 1100101101010 test 1499: 00 test 1500: 0100011 test 1501: 1011001010110 test 1502: 0 10 test 1503: 1100101011010 test 1504: 00 test 1505: 0100001 test 1506: 1011001010101 test 1507: 0 10 test 1508: 1100101010110 test 1509: 00 test 1510: 1100001 test 1511: 1101001010101 test 1512: 0 10 test 1513: 1100101010110 test 1514: 00 test 1515: 1100011 test 1516: 1101001010110 test 1517: 0 10 test 1518: 1100101011010 test 1519: 00 test 1520: 1100111 test 1521: 1101001011010 test 1522: 0 10 test 1523: 1100101101010 test 1524: 00 test 1525: 1100101 test 1526: 1101001011001 test 1527: 0 10 test 1528: 1100101100110 test 1529: 00 test 1530: 1101101 test 1531: 1101001101001 test 1532: 0 10 test 1533: 1100110100110 test 1534: 00 test 1535: 1101111 test 1536: 1101001101010 test 1537: 0 10 test 1538: 1100110101010 test 1539: 00 test 1540: 1101011 test 1541: 1101001100110 test 1542: 0 10 test 1543: 1100110011010 test 1544: 00 test 1545: 1101001 test 1546: 1101001100101 test 1547: 0 10 test 1548: 1100110010110 test 1549: 00 test 1550: 1111001 test 1551: 1101010100101 test 1552: 0 10 test 1553: 1101010010110 test 1554: 00 test 1555: 1111011 test 1556: 1101010100110 test 1557: 0 10 test 1558: 1101010011010 test 1559: 00 test 1560: 1111111 test 1561: 1101010101010 test 1562: 0 10 test 1563: 1101010101010 test 1564: 00 test 1565: 1111101 test 1566: 1101010101001 test 1567: 0 10 test 1568: 1101010100110 test 1569: 00 test 1570: 1110101 test 1571: 1101010011001 test 1572: 0 10 test 1573: 1101001100110 test 1574: 00 test 1575: 1110111 test 1576: 1101010011010 test 1577: 0 10 test 1578: 1101001101010 test 1579: 00 test 1580: 1110011 test 1581: 1101010010110 test 1582: 0 10 test 1583: 1101001011010 test 1584: 00 test 1585: 1110001 test 1586: 1101010010101 test 1587: 0 10 test 1588: 1101001010110 test 1589: 00 test 1590: 1010001 test 1591: 1100110010101 test 1592: 0 10 test 1593: 1011001010110 test 1594: 00 test 1595: 1010011 test 1596: 1100110010110 test 1597: 0 10 test 1598: 1011001011010 test 1599: 00 test 1600: 1010111 test 1601: 1100110011010 test 1602: 0 10 test 1603: 1011001101010 test 1604: 00 test 1605: 1010101 test 1606: 1100110011001 test 1607: 0 10 test 1608: 1011001100110 test 1609: 00 test 1610: 1011101 test 1611: 1100110101001 test 1612: 0 10 test 1613: 1011010100110 test 1614: 00 test 1615: 1011111 test 1616: 1100110101010 test 1617: 0 10 test 1618: 1011010101010 test 1619: 00 test 1620: 1011011 test 1621: 1100110100110 test 1622: 0 10 test 1623: 1011010011010 test 1624: 00 test 1625: 1011001 test 1626: 1100110100101 test 1627: 0 10 test 1628: 1011010010110 test 1629: 00 test 1630: 1001001 test 1631: 1100101100101 test 1632: 0 10 test 1633: 1010110010110 test 1634: 00 test 1635: 1001011 test 1636: 1100101100110 test 1637: 0 10 test 1638: 1010110011010 test 1639: 00 test 1640: 1001111 test 1641: 1100101101010 test 1642: 0 10 test 1643: 1010110101010 test 1644: 00 test 1645: 1001101 test 1646: 1100101101001 test 1647: 0 10 test 1648: 1010110100110 test 1649: 00 test 1650: 1000101 test 1651: 1100101011001 test 1652: 0 10 test 1653: 1010101100110 test 1654: 00 test 1655: 1000111 test 1656: 1100101011010 test 1657: 0 10 test 1658: 1010101101010 test 1659: 00 test 1660: 1000011 test 1661: 1100101010110 test 1662: 0 10 test 1663: 1010101011010 test 1664: 00 test 1665: 1000001 test 1666: 1100101010101 test 1667: 0 10 test 1668: 1010101010110 test 1669: 00 test 1670: 0000001 test 1671: 1010101010101 test 1672: 0 10 test 1673: 1010101010110 test 1674: 00 comment: comment: comment: ; end of SECTION GENERATED BY A PROGRAM comment: comment: comment: ; CLEAR FFs test 1675: 0 010101010101 test 1676: 1 comment: test 1677: 11111110111111010100010101010101 comment: end: END summary column 1: offset 0, mask 0x4000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0020 column 6: offset 2, mask 0x4000 column 7: offset 2, mask 0x0002 column 8: offset 1, mask 0x1000 column 9: offset 1, mask 0x0010 column 10: offset 1, mask 0x0400 column 11: offset 1, mask 0x0200 column 12: offset 2, mask 0x8000 column 13: offset 0, mask 0x8000 column 14: offset 1, mask 0x0080 column 15: offset 2, mask 0x0001 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x4000 column 18: offset 1, mask 0x0040 column 19: offset 1, mask 0x0800 column 20: offset 0, mask 0x2000 column 21: offset 0, mask 0x1000 column 22: offset 0, mask 0x0010 column 23: offset 0, mask 0x0400 column 24: offset 0, mask 0x0800 column 25: offset 0, mask 0x0002 column 26: offset 0, mask 0x0008 column 27: offset 0, mask 0x0200 column 28: offset 0, mask 0x0004 column 29: offset 1, mask 0x0001 column 30: offset 0, mask 0x0001 column 31: offset 1, mask 0x8000 column 32: offset 0, mask 0x0100 direction bits (1=input) 0x1FFF 0x8101 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x891D 0x26FE 0xC002 0x0000 0x0000 2: 0xC91D 0x26FE 0xC002 0x0000 0x0000 3: 0xC91D 0x36FE 0xC002 0x0000 0x0000 4: 0xC91D 0x36D0 0x8002 0x0000 0x0000 5: 0xE81D 0xB6D0 0x8002 0x0000 0x0000 6: 0xC81D 0xB6D0 0x8002 0x0000 0x0000 7: 0xC81D 0xB6D0 0xC002 0x0000 0x0000 8: 0xE81C 0xB6D1 0xC002 0x0000 0x0000 9: 0xC81C 0xB6D1 0xC002 0x0000 0x0000 10: 0xC81C 0xB6D1 0xC000 0x0000 0x0000 11: 0xE91C 0x36D1 0xC000 0x0000 0x0000 12: 0xC91C 0x36D1 0xC000 0x0000 0x0000 13: 0xC91C 0x36F1 0xC000 0x0000 0x0000 14: 0xEB18 0x36F1 0xC000 0x0000 0x0000 15: 0xCB18 0x36F1 0xC000 0x0000 0x0000 16: 0xCB18 0x36F1 0xC002 0x0000 0x0000 17: 0xEA18 0xB6F1 0xC002 0x0000 0x0000 18: 0xCA18 0xB6F1 0xC002 0x0000 0x0000 19: 0xCA18 0xB6F1 0x8002 0x0000 0x0000 20: 0xEA19 0xB6F0 0x8002 0x0000 0x0000 21: 0xCA19 0xB6F0 0x8002 0x0000 0x0000 22: 0xCA19 0xB6F0 0x8000 0x0000 0x0000 23: 0xEB19 0x36F0 0x8000 0x0000 0x0000 24: 0xCB19 0x36F0 0x8000 0x0000 0x0000 25: 0xCB19 0x36F8 0x8000 0x0000 0x0000 26: 0xEB13 0x36F8 0x8000 0x0000 0x0000 27: 0xCB13 0x36F8 0x8000 0x0000 0x0000 28: 0xCB13 0x36F8 0x8002 0x0000 0x0000 29: 0xEA13 0xB6F8 0x8002 0x0000 0x0000 30: 0xCA13 0xB6F8 0x8002 0x0000 0x0000 31: 0xCA13 0xB6F8 0xC002 0x0000 0x0000 32: 0xEA12 0xB6F9 0xC002 0x0000 0x0000 33: 0xCA12 0xB6F9 0xC002 0x0000 0x0000 34: 0xCA12 0xB6F9 0xC000 0x0000 0x0000 35: 0xEB12 0x36F9 0xC000 0x0000 0x0000 36: 0xCB12 0x36F9 0xC000 0x0000 0x0000 37: 0xCB12 0x36D9 0xC000 0x0000 0x0000 38: 0xE916 0x36D9 0xC000 0x0000 0x0000 39: 0xC916 0x36D9 0xC000 0x0000 0x0000 40: 0xC916 0x36D9 0xC002 0x0000 0x0000 41: 0xE816 0xB6D9 0xC002 0x0000 0x0000 42: 0xC816 0xB6D9 0xC002 0x0000 0x0000 43: 0xC816 0xB6D9 0x8002 0x0000 0x0000 44: 0xE817 0xB6D8 0x8002 0x0000 0x0000 45: 0xC817 0xB6D8 0x8002 0x0000 0x0000 46: 0xC817 0xB6D8 0x8000 0x0000 0x0000 47: 0xE917 0x36D8 0x8000 0x0000 0x0000 48: 0xC917 0x36D8 0x8000 0x0000 0x0000 49: 0xC917 0x36DC 0x8000 0x0000 0x0000 50: 0xE517 0x36DC 0x8000 0x0000 0x0000 51: 0xC517 0x36DC 0x8000 0x0000 0x0000 52: 0xC517 0x36DC 0x8002 0x0000 0x0000 53: 0xE417 0xB6DC 0x8002 0x0000 0x0000 54: 0xC417 0xB6DC 0x8002 0x0000 0x0000 55: 0xC417 0xB6DC 0xC002 0x0000 0x0000 56: 0xE416 0xB6DD 0xC002 0x0000 0x0000 57: 0xC416 0xB6DD 0xC002 0x0000 0x0000 58: 0xC416 0xB6DD 0xC000 0x0000 0x0000 59: 0xE516 0x36DD 0xC000 0x0000 0x0000 60: 0xC516 0x36DD 0xC000 0x0000 0x0000 61: 0xC516 0x36FD 0xC000 0x0000 0x0000 62: 0xE712 0x36FD 0xC000 0x0000 0x0000 63: 0xC712 0x36FD 0xC000 0x0000 0x0000 64: 0xC712 0x36FD 0xC002 0x0000 0x0000 65: 0xE612 0xB6FD 0xC002 0x0000 0x0000 66: 0xC612 0xB6FD 0xC002 0x0000 0x0000 67: 0xC612 0xB6FD 0x8002 0x0000 0x0000 68: 0xE613 0xB6FC 0x8002 0x0000 0x0000 69: 0xC613 0xB6FC 0x8002 0x0000 0x0000 70: 0xC613 0xB6FC 0x8000 0x0000 0x0000 71: 0xE713 0x36FC 0x8000 0x0000 0x0000 72: 0xC713 0x36FC 0x8000 0x0000 0x0000 73: 0xC713 0x36F4 0x8000 0x0000 0x0000 74: 0xE719 0x36F4 0x8000 0x0000 0x0000 75: 0xC719 0x36F4 0x8000 0x0000 0x0000 76: 0xC719 0x36F4 0x8002 0x0000 0x0000 77: 0xE619 0xB6F4 0x8002 0x0000 0x0000 78: 0xC619 0xB6F4 0x8002 0x0000 0x0000 79: 0xC619 0xB6F4 0xC002 0x0000 0x0000 80: 0xE618 0xB6F5 0xC002 0x0000 0x0000 81: 0xC618 0xB6F5 0xC002 0x0000 0x0000 82: 0xC618 0xB6F5 0xC000 0x0000 0x0000 83: 0xE718 0x36F5 0xC000 0x0000 0x0000 84: 0xC718 0x36F5 0xC000 0x0000 0x0000 85: 0xC718 0x36D5 0xC000 0x0000 0x0000 86: 0xE51C 0x36D5 0xC000 0x0000 0x0000 87: 0xC51C 0x36D5 0xC000 0x0000 0x0000 88: 0xC51C 0x36D5 0xC002 0x0000 0x0000 89: 0xE41C 0xB6D5 0xC002 0x0000 0x0000 90: 0xC41C 0xB6D5 0xC002 0x0000 0x0000 91: 0xC41C 0xB6D5 0x8002 0x0000 0x0000 92: 0xE41D 0xB6D4 0x8002 0x0000 0x0000 93: 0xC41D 0xB6D4 0x8002 0x0000 0x0000 94: 0xC41D 0xB6D4 0x8000 0x0000 0x0000 95: 0xE51D 0x36D4 0x8000 0x0000 0x0000 96: 0xC51D 0x36D4 0x8000 0x0000 0x0000 97: 0xC51D 0x36D6 0x8000 0x0000 0x0000 98: 0xF50D 0x36D6 0x8000 0x0000 0x0000 99: 0xD50D 0x36D6 0x8000 0x0000 0x0000 100: 0xD50D 0x36D6 0x8002 0x0000 0x0000 101: 0xF40D 0xB6D6 0x8002 0x0000 0x0000 102: 0xD40D 0xB6D6 0x8002 0x0000 0x0000 103: 0xD40D 0xB6D6 0xC002 0x0000 0x0000 104: 0xF40C 0xB6D7 0xC002 0x0000 0x0000 105: 0xD40C 0xB6D7 0xC002 0x0000 0x0000 106: 0xD40C 0xB6D7 0xC000 0x0000 0x0000 107: 0xF50C 0x36D7 0xC000 0x0000 0x0000 108: 0xD50C 0x36D7 0xC000 0x0000 0x0000 109: 0xD50C 0x36F7 0xC000 0x0000 0x0000 110: 0xF708 0x36F7 0xC000 0x0000 0x0000 111: 0xD708 0x36F7 0xC000 0x0000 0x0000 112: 0xD708 0x36F7 0xC002 0x0000 0x0000 113: 0xF608 0xB6F7 0xC002 0x0000 0x0000 114: 0xD608 0xB6F7 0xC002 0x0000 0x0000 115: 0xD608 0xB6F7 0x8002 0x0000 0x0000 116: 0xF609 0xB6F6 0x8002 0x0000 0x0000 117: 0xD609 0xB6F6 0x8002 0x0000 0x0000 118: 0xD609 0xB6F6 0x8000 0x0000 0x0000 119: 0xF709 0x36F6 0x8000 0x0000 0x0000 120: 0xD709 0x36F6 0x8000 0x0000 0x0000 121: 0xD709 0x36FE 0x8000 0x0000 0x0000 122: 0xF703 0x36FE 0x8000 0x0000 0x0000 123: 0xD703 0x36FE 0x8000 0x0000 0x0000 124: 0xD703 0x36FE 0x8002 0x0000 0x0000 125: 0xF603 0xB6FE 0x8002 0x0000 0x0000 126: 0xD603 0xB6FE 0x8002 0x0000 0x0000 127: 0xD603 0xB6FE 0xC002 0x0000 0x0000 128: 0xF602 0xB6FF 0xC002 0x0000 0x0000 129: 0xD602 0xB6FF 0xC002 0x0000 0x0000 130: 0xD602 0xB6FF 0xC000 0x0000 0x0000 131: 0xF702 0x36FF 0xC000 0x0000 0x0000 132: 0xD702 0x36FF 0xC000 0x0000 0x0000 133: 0xD702 0x36DF 0xC000 0x0000 0x0000 134: 0xF506 0x36DF 0xC000 0x0000 0x0000 135: 0xD506 0x36DF 0xC000 0x0000 0x0000 136: 0xD506 0x36DF 0xC002 0x0000 0x0000 137: 0xF406 0xB6DF 0xC002 0x0000 0x0000 138: 0xD406 0xB6DF 0xC002 0x0000 0x0000 139: 0xD406 0xB6DF 0x8002 0x0000 0x0000 140: 0xF407 0xB6DE 0x8002 0x0000 0x0000 141: 0xD407 0xB6DE 0x8002 0x0000 0x0000 142: 0xD407 0xB6DE 0x8000 0x0000 0x0000 143: 0xF507 0x36DE 0x8000 0x0000 0x0000 144: 0xD507 0x36DE 0x8000 0x0000 0x0000 145: 0xD507 0x36DA 0x8000 0x0000 0x0000 146: 0xF907 0x36DA 0x8000 0x0000 0x0000 147: 0xD907 0x36DA 0x8000 0x0000 0x0000 148: 0xD907 0x36DA 0x8002 0x0000 0x0000 149: 0xF807 0xB6DA 0x8002 0x0000 0x0000 150: 0xD807 0xB6DA 0x8002 0x0000 0x0000 151: 0xD807 0xB6DA 0xC002 0x0000 0x0000 152: 0xF806 0xB6DB 0xC002 0x0000 0x0000 153: 0xD806 0xB6DB 0xC002 0x0000 0x0000 154: 0xD806 0xB6DB 0xC000 0x0000 0x0000 155: 0xF906 0x36DB 0xC000 0x0000 0x0000 156: 0xD906 0x36DB 0xC000 0x0000 0x0000 157: 0xD906 0x36FB 0xC000 0x0000 0x0000 158: 0xFB02 0x36FB 0xC000 0x0000 0x0000 159: 0xDB02 0x36FB 0xC000 0x0000 0x0000 160: 0xDB02 0x36FB 0xC002 0x0000 0x0000 161: 0xFA02 0xB6FB 0xC002 0x0000 0x0000 162: 0xDA02 0xB6FB 0xC002 0x0000 0x0000 163: 0xDA02 0xB6FB 0x8002 0x0000 0x0000 164: 0xFA03 0xB6FA 0x8002 0x0000 0x0000 165: 0xDA03 0xB6FA 0x8002 0x0000 0x0000 166: 0xDA03 0xB6FA 0x8000 0x0000 0x0000 167: 0xFB03 0x36FA 0x8000 0x0000 0x0000 168: 0xDB03 0x36FA 0x8000 0x0000 0x0000 169: 0xDB03 0x36F2 0x8000 0x0000 0x0000 170: 0xFB09 0x36F2 0x8000 0x0000 0x0000 171: 0xDB09 0x36F2 0x8000 0x0000 0x0000 172: 0xDB09 0x36F2 0x8002 0x0000 0x0000 173: 0xFA09 0xB6F2 0x8002 0x0000 0x0000 174: 0xDA09 0xB6F2 0x8002 0x0000 0x0000 175: 0xDA09 0xB6F2 0xC002 0x0000 0x0000 176: 0xFA08 0xB6F3 0xC002 0x0000 0x0000 177: 0xDA08 0xB6F3 0xC002 0x0000 0x0000 178: 0xDA08 0xB6F3 0xC000 0x0000 0x0000 179: 0xFB08 0x36F3 0xC000 0x0000 0x0000 180: 0xDB08 0x36F3 0xC000 0x0000 0x0000 181: 0xDB08 0x36D3 0xC000 0x0000 0x0000 182: 0xF90C 0x36D3 0xC000 0x0000 0x0000 183: 0xD90C 0x36D3 0xC000 0x0000 0x0000 184: 0xD90C 0x36D3 0xC002 0x0000 0x0000 185: 0xF80C 0xB6D3 0xC002 0x0000 0x0000 186: 0xD80C 0xB6D3 0xC002 0x0000 0x0000 187: 0xD80C 0xB6D3 0x8002 0x0000 0x0000 188: 0xF80D 0xB6D2 0x8002 0x0000 0x0000 189: 0xD80D 0xB6D2 0x8002 0x0000 0x0000 190: 0xD80D 0xB6D2 0x8000 0x0000 0x0000 191: 0xF90D 0x36D2 0x8000 0x0000 0x0000 192: 0xD90D 0x36D2 0x8000 0x0000 0x0000 193: 0xD90D 0x36D0 0x8000 0x0000 0x0000 194: 0xE91D 0x36D0 0x8000 0x0000 0x0000 195: 0xC91D 0x36D0 0x8000 0x0000 0x0000 196: 0xC91D 0x26D0 0x8000 0x0000 0x0000 197: 0xC91D 0x26D0 0x8001 0x0000 0x0000 198: 0x491D 0x20C0 0x0001 0x0000 0x0000 199: 0x681D 0xA0C0 0x0001 0x0000 0x0000 200: 0x481D 0xA0C0 0x0001 0x0000 0x0000 201: 0xC81D 0xA0C0 0x0001 0x0000 0x0000 202: 0xE81C 0xA0C1 0x0001 0x0000 0x0000 203: 0xC81C 0xA0C1 0x0001 0x0000 0x0000 204: 0xC81C 0xA041 0x0001 0x0000 0x0000 205: 0xE91C 0x2041 0x0001 0x0000 0x0000 206: 0xC91C 0x2041 0x0001 0x0000 0x0000 207: 0xC91C 0x2041 0x8001 0x0000 0x0000 208: 0xEB18 0x2041 0x8001 0x0000 0x0000 209: 0xCB18 0x2041 0x8001 0x0000 0x0000 210: 0xCB18 0x20C1 0x8001 0x0000 0x0000 211: 0xEA18 0xA0C1 0x8001 0x0000 0x0000 212: 0xCA18 0xA0C1 0x8001 0x0000 0x0000 213: 0x4A18 0xA0C1 0x8001 0x0000 0x0000 214: 0x6A19 0xA0C0 0x8001 0x0000 0x0000 215: 0x4A19 0xA0C0 0x8001 0x0000 0x0000 216: 0x4A19 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0x4000 0x0000 0x0000 1649: 0x4A13 0xA062 0x4000 0x0000 0x0000 1650: 0x4A13 0xB042 0x4000 0x0000 0x0000 1651: 0x790C 0x3043 0x4000 0x0000 0x0000 1652: 0x590C 0x2843 0x4000 0x0000 0x0000 1653: 0x6A19 0xA842 0x4000 0x0000 0x0000 1654: 0x4A19 0xA042 0x4000 0x0000 0x0000 1655: 0x4A19 0xB042 0x4002 0x0000 0x0000 1656: 0x780C 0xB043 0x4002 0x0000 0x0000 1657: 0x580C 0xA843 0x4002 0x0000 0x0000 1658: 0x6A18 0xA843 0x4002 0x0000 0x0000 1659: 0x4A18 0xA043 0x4002 0x0000 0x0000 1660: 0x4A18 0xB043 0x0002 0x0000 0x0000 1661: 0x780D 0xB042 0x0002 0x0000 0x0000 1662: 0x580D 0xA842 0x0002 0x0000 0x0000 1663: 0x681C 0xA843 0x0002 0x0000 0x0000 1664: 0x481C 0xA043 0x0002 0x0000 0x0000 1665: 0x481C 0xB043 0x0000 0x0000 0x0000 1666: 0x790D 0x3042 0x0000 0x0000 0x0000 1667: 0x590D 0x2842 0x0000 0x0000 0x0000 1668: 0x681D 0xA842 0x0000 0x0000 0x0000 1669: 0x481D 0xA042 0x0000 0x0000 0x0000 1670: 0x481D 0xB040 0x0000 0x0000 0x0000 1671: 0x691D 0x3040 0x0000 0x0000 0x0000 1672: 0x491D 0x2840 0x0000 0x0000 0x0000 1673: 0x681D 0xA840 0x0000 0x0000 0x0000 1674: 0x481D 0xA040 0x0000 0x0000 0x0000 1675: 0x091D 0x2040 0x0000 0x0000 0x0000 1676: 0x491D 0x2040 0x0000 0x0000 0x0000 1677: 0xC91D 0x26FE 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOOOOOOIIIIIIGIIP GOOOOOOIIIIIIIII G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 1677 'test steps' 1775 lines ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) PINS Main menu Fri Jun 30 14:11:50 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 14:11:52 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 8 Main menu Fri Jun 30 14:12:03 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 14:13:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 9 Main menu Fri Jun 30 14:13:26 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 14:18:59 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 2 Main menu Fri Jun 30 14:19:03 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 14:22:20 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 14:22:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 170 111101111011110111100000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 171 111101111011110111100001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 172 111101111011110111100010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 173 111101111011110111100011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 174 111101111011110111100100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 175 111101111011110111100101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 176 111101111011110111100110011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 177 111101111011110111100111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 178 111101111011110111101000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 179 111101111011110111101001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 180 111101111011110111101010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 181 111101111011110111101011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 182 111101111011110111101100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 183 111101111011110111101101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 184 111101111011110111101110011110 fail ^ step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 15: *** FAIL *************************** 134 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111 11111111111111 11111 rising ^^^^^^^^^ ^^^^^^^^^^^^^^ ^^^^^ falling vvvvvvvvv vvvvvvvvvvvvvv vvvvv was lo 000000000000000000000000000000 total fails 15, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 000010000 00001000010000 00001 step 1 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 17 111100000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 18 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000010001000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000010010000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000010011000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000010100000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000010101000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000010110000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000010111000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000011000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000011001000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000011010000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000011011000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000011100000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000011101000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000011110000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000011111000001000010000000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 35 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000010000000011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000010000000101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000010000000111000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000010000001001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000010000001011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000010000001101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000010000001111000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000010000010001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000010000010011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000010000010101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000010000010111000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000010000011001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000010000011011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000010000011101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000010000011110000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000010000000001000110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000010000000001001010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000010000000001001110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000010000000001010010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000010000000001010110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000010000000001011010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000010000000001011110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000010000000001100010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000010000000001100110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000010000000001101010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000010000000001101110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000010000000001110010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000010000000001110110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000010000000001111010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000010000000001111100000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000010000000001000010001000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000010000000001000010010000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000010000000001000010011000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000010000000001000010100000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000010000000001000010101000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000010000000001000010110000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000010000000001000010111000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000010000000001000011000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000010000000001000011001000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000010000000001000011010000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000010000000001000011011000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000010000000001000011100000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000010000000001000011101000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000010000000001000011110000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 85 000010000000001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 86 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000010000000001000010000000011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000010000000001000010000000101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000010000000001000010000000111 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000010000000001000010000001001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000010000000001000010000001011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000010000000001000010000001101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000010000000001000010000001111 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000010000000001000010000010001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000010000000001000010000010011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000010000000001000010000010101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000010000000001000010000010111 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000010000000001000010000011001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000010000000001000010000011011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000010000000001000010000011101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000010000000001000010000011110 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000010000000001000010000000001 fail ^ ^ step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 step 109 001111111011110111101111011110 step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 step 113 011111111011110111101111011110 step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 step 117 101111111011110111101111011110 step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 122 111100000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 123 111100001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 124 111100010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 125 111100011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 126 111100100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 127 111100101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 128 111100110011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 129 111100111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 130 111101000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 131 111101001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 132 111101010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 133 111101011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 134 111101100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 135 111101101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 136 111101110011110111101111011110 fail ^ step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 170 111101111011110111100000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 171 111101111011110111100001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 172 111101111011110111100010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 173 111101111011110111100011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 174 111101111011110111100100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 175 111101111011110111100101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 176 111101111011110111100110011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 177 111101111011110111100111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 178 111101111011110111101000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 179 111101111011110111101001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 180 111101111011110111101010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 181 111101111011110111101011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 182 111101111011110111101100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 183 111101111011110111101101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 184 111101111011110111101110011110 fail ^ step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 16: *** FAIL *************************** 134 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111 11111111111111 11111 rising ^^^^^^^^^ ^^^^^^^^^^^^^^ ^^^^^ falling vvvvvvvvv vvvvvvvvvvvvvv vvvvv was lo 000000000000000000000000000000 total fails 16, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O O was lo 000000000000000000000000000000 falling vvvvvvvvv vvvvvvvvvvvvvv vvvvv rising ^^^^^^^^^ ^^^^^^^^^^^^^^ ^^^^^ was hi 111111111 11111111111111 11111 total fails 16, total passes 0 Main menu Fri Jun 30 14:35:08 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 14:35:13 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 14:35:29 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 1 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 2 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 3 000110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 4 001010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 5 001110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 6 010010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 7 010110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 8 011010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 9 011110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 10 100010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 11 100110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 12 101010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 13 101110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 14 110010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 15 110110000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 16 111010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 17 111100000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 18 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 19 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 20 000010001000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 21 000010010000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 22 000010011000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 23 000010100000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 24 000010101000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 25 000010110000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 26 000010111000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 27 000011000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 28 000011001000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 29 000011010000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 30 000011011000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 31 000011100000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 32 000011101000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 33 000011110000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 34 000011111000001000010000000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 35 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 36 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 37 000010000000011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 38 000010000000101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 39 000010000000111000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 40 000010000001001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 41 000010000001011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 42 000010000001101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 43 000010000001111000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 44 000010000010001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 45 000010000010011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 46 000010000010101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 47 000010000010111000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 48 000010000011001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 49 000010000011011000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 50 000010000011101000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 51 000010000011110000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 52 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 53 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 54 000010000000001000110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 55 000010000000001001010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 56 000010000000001001110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 57 000010000000001010010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 58 000010000000001010110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 59 000010000000001011010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 60 000010000000001011110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 61 000010000000001100010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 62 000010000000001100110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 63 000010000000001101010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 64 000010000000001101110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 65 000010000000001110010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 66 000010000000001110110000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 67 000010000000001111010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 68 000010000000001111100000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 69 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 70 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 71 000010000000001000010001000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 72 000010000000001000010010000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 73 000010000000001000010011000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 74 000010000000001000010100000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 75 000010000000001000010101000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 76 000010000000001000010110000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 77 000010000000001000010111000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 78 000010000000001000011000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 79 000010000000001000011001000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 80 000010000000001000011010000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 81 000010000000001000011011000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 82 000010000000001000011100000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 83 000010000000001000011101000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 84 000010000000001000011110000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 85 000010000000001000011111000001 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 86 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 87 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 88 000010000000001000010000000011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 89 000010000000001000010000000101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 90 000010000000001000010000000111 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 91 000010000000001000010000001001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 92 000010000000001000010000001011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 93 000010000000001000010000001101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 94 000010000000001000010000001111 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 95 000010000000001000010000010001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 96 000010000000001000010000010011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 97 000010000000001000010000010101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 98 000010000000001000010000010111 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 99 000010000000001000010000011001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 100 000010000000001000010000011011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 101 000010000000001000010000011101 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 102 000010000000001000010000011110 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 00001 step 103 000010000000001000010000000001 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: step 104 000010000000001000010000000001 fail ^ ^ step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 step 109 001111111011110111101111011110 step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 step 113 011111111011110111101111011110 step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 step 117 101111111011110111101111011110 step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 step 120 111011111011110111101111011110 step 121 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 122 111100000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 123 111100001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 124 111100010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 125 111100011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 126 111100100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 127 111100101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 128 111100110011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 129 111100111011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 130 111101000011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 131 111101001011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 132 111101010011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 133 111101011011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 134 111101100011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 135 111101101011110111101111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 136 111101110011110111101111011110 fail ^ step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 0000 step 170 111101111011110111100000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 171 111101111011110111100001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 172 111101111011110111100010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 173 111101111011110111100011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 174 111101111011110111100100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 175 111101111011110111100101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 176 111101111011110111100110011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 177 111101111011110111100111011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1000 step 178 111101111011110111101000011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 179 111101111011110111101001011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 180 111101111011110111101010011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 181 111101111011110111101011011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 182 111101111011110111101100011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 1 step 183 111101111011110111101101011110 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 10 step 184 111101111011110111101110011110 fail ^ step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 1: *** FAIL *************************** 134 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O O all fails O O was hi 111111111 11111111111111 11111 rising ^^^^^^^^^ ^^^^^^^^^^^^^^ ^^^^^ falling vvvvvvvvv vvvvvvvvvvvvvv vvvvv was lo 000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 10 O AL1 E2-8 25 O AP2 E2-6 PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 10 O AL1 E2-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 111111111 11111111111111 11111 fails LO: 000000000 00000000000000000000 fails HI: fails HI: pin: 25 O AP2 E2-6 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 111111111 11111111111111 11111 fails LO: 000000000000000000000000 00000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O O was lo 000000000000000000000000000000 falling vvvvvvvvv vvvvvvvvvvvvvv vvvvv rising ^^^^^^^^^ ^^^^^^^^^^^^^^ ^^^^^ was hi 111111111 11111111111111 11111 total fails 1, total passes 0 Main menu Fri Jun 30 14:49:01 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7440.tst could not open test file. valid test files are: reverting back to test file: tests\m617.tst Main menu Fri Jun 30 14:49:08 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:06:30 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Fri Jun 30 15:06:31 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7440.tst reading test file: tests\7440.tst comment: 7440 DUAL 4-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 7440 PIN 1 1A pins: 2 I AB2 E1-2 7440 PIN 2 1B pins: 3 I AD2 E1-4 7440 PIN 4 1C pins: 4 I AE2 E1-5 7440 PIN 5 1D pins: 5 O AF2 E1-6 7440 PIN 6 1Y = 1A NAND 1B NAND 1C NAND 1D pins: 6 I AM2 E1-11 7440 PIN 9 2A pins: 7 I AN2 E1-12 7440 PIN 10 2B pins: 8 I AR2 E1-14 7440 PIN 12 2C pins: 9 I AS2 E1-15 7440 PIN 13 2D pins: 10 O AL2 E1-10 7440 PIN 8 2Y = 1A NAND 2B NAND 2C NAND 2D pins: 11 I AC1 E1-3 7440 PIN 3 N.C. pins: 12 I AP2 E1-13 7440 PIN 11 N.C. pins: 13 I AH2 E1-7 7440 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7440 PIN 14 VCC pins: direction: IIIIOIIIIOIIIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 000010000100000 error: the first 'test step' is too short error: it must set EVERY column expected 'test step' (16 columns of '0','1','X', or ' ') bad test file Main menu Fri Jun 30 15:06:37 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7440.tst reading test file: tests\7440.tst comment: 7440 DUAL 4-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 7440 PIN 1 1A pins: 2 I AB2 E1-2 7440 PIN 2 1B pins: 3 I AD2 E1-4 7440 PIN 4 1C pins: 4 I AE2 E1-5 7440 PIN 5 1D pins: 5 O AF2 E1-6 7440 PIN 6 1Y = 1A NAND 1B NAND 1C NAND 1D pins: 6 I AM2 E1-11 7440 PIN 9 2A pins: 7 I AN2 E1-12 7440 PIN 10 2B pins: 8 I AR2 E1-14 7440 PIN 12 2C pins: 9 I AS2 E1-15 7440 PIN 13 2D pins: 10 O AL2 E1-10 7440 PIN 8 2Y = 1A NAND 2B NAND 2C NAND 2D pins: 11 I AC1 E1-3 7440 PIN 3 N.C. pins: 12 I AP2 E1-13 7440 PIN 11 N.C. pins: 13 I AH2 E1-7 7440 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7440 PIN 14 VCC pins: direction: IIIIOIIIIOIIIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000100001000000 comment: comment: ; ALL INPUTS ONES test 2: 1111011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 11101 test 4: 11001 test 5: 11011 test 6: 10011 test 7: 10001 test 8: 10101 test 9: 10111 test 10: 00111 test 11: 00101 test 12: 00001 test 13: 00011 test 14: 01011 test 15: 01001 test 16: 01101 test 17: 01111 test 18: 11110 test 19: 11101 test 20: 11001 test 21: 11011 test 22: 10011 test 23: 10001 test 24: 10101 test 25: 10111 test 26: 00111 test 27: 00101 test 28: 00001 test 29: 00011 test 30: 01011 test 31: 01001 test 32: 01101 test 33: 01111 test 34: 11110 comment: comment: ; ALL INPUTS LO test 35: 000100010001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0008 column 5: offset 0, mask 0x0004 column 6: offset 1, mask 0x0004 column 7: offset 1, mask 0x0008 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0002 column 11: offset 0, mask 0x2000 column 12: offset 1, mask 0x0010 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF02 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 2: 0x8058 0x006C 0x0000 0x0000 0x0000 3: 0x8054 0x006C 0x0000 0x0000 0x0000 4: 0x8044 0x006C 0x0000 0x0000 0x0000 5: 0x804C 0x006C 0x0000 0x0000 0x0000 6: 0x800C 0x006C 0x0000 0x0000 0x0000 7: 0x8004 0x006C 0x0000 0x0000 0x0000 8: 0x8014 0x006C 0x0000 0x0000 0x0000 9: 0x801C 0x006C 0x0000 0x0000 0x0000 10: 0x001C 0x006C 0x0000 0x0000 0x0000 11: 0x0014 0x006C 0x0000 0x0000 0x0000 12: 0x0004 0x006C 0x0000 0x0000 0x0000 13: 0x000C 0x006C 0x0000 0x0000 0x0000 14: 0x004C 0x006C 0x0000 0x0000 0x0000 15: 0x0044 0x006C 0x0000 0x0000 0x0000 16: 0x0054 0x006C 0x0000 0x0000 0x0000 17: 0x005C 0x006C 0x0000 0x0000 0x0000 18: 0x8058 0x006C 0x0000 0x0000 0x0000 19: 0x8058 0x002E 0x0000 0x0000 0x0000 20: 0x8058 0x000E 0x0000 0x0000 0x0000 21: 0x8058 0x004E 0x0000 0x0000 0x0000 22: 0x8058 0x0046 0x0000 0x0000 0x0000 23: 0x8058 0x0006 0x0000 0x0000 0x0000 24: 0x8058 0x0026 0x0000 0x0000 0x0000 25: 0x8058 0x0066 0x0000 0x0000 0x0000 26: 0x8058 0x0062 0x0000 0x0000 0x0000 27: 0x8058 0x0022 0x0000 0x0000 0x0000 28: 0x8058 0x0002 0x0000 0x0000 0x0000 29: 0x8058 0x0042 0x0000 0x0000 0x0000 30: 0x8058 0x004A 0x0000 0x0000 0x0000 31: 0x8058 0x000A 0x0000 0x0000 0x0000 32: 0x8058 0x002A 0x0000 0x0000 0x0000 33: 0x8058 0x006A 0x0000 0x0000 0x0000 34: 0x8058 0x006C 0x0000 0x0000 0x0000 35: 0x0008 0x0030 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIIIII G P G UUT inputs: 14 UUT outputs: 2 pins used: 16 not used: 50 35 'test steps' 81 lines 7440 DUAL 4-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V PINS Main menu Fri Jun 30 15:07:19 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:07:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 000 100 01 1 step 35 0001100101010000 fail ^ ^ test 53: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O O all fails O O was hi 1111111111 1 rising ^^^^^^^^^^ ^ falling vvvvvvvvvv v was lo 0000000000000000 total fails 53, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 000 100 01 1 step 35 0001100101010000 fail ^ ^ test 54: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O O all fails O O was hi 1111111111 1 rising ^^^^^^^^^^ ^ falling vvvvvvvvvv v was lo 0000000000000000 total fails 54, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 000 100 01 1 step 35 0001100101010000 fail ^ ^ test 55: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O O all fails O O was hi 1111111111 1 rising ^^^^^^^^^^ ^ falling vvvvvvvvvv v was lo 0000000000000000 total fails 55, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 000 100 01 1 step 35 0001100101010000 fail ^ ^ test 56: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O O all fails O O was hi 1111111111 1 rising ^^^^^^^^^^ ^ falling vvvvvvvvvv v was lo 0000000000000000 total fails 56, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; START WITH ALL INPUTS ZERO source: 0000100001000000 changed: 0 0 0 step 1 0000100001000000 source: source: ; ALL INPUTS ONES source: 1111011110 changed: 1111011110 step 2 1111011110000000 source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: 11101 changed: 01 step 3 1110111110000000 source: 11001 changed: 0 step 4 1100111110000000 source: 11011 changed: 1 step 5 1101111110000000 source: 10011 changed: 0 step 6 1001111110000000 source: 10001 changed: 0 step 7 1000111110000000 source: 10101 changed: 1 step 8 1010111110000000 source: 10111 changed: 1 step 9 1011111110000000 source: 00111 changed: 0 step 10 0011111110000000 source: 00101 changed: 0 step 11 0010111110000000 source: 00001 changed: 0 step 12 0000111110000000 source: 00011 changed: 1 step 13 0001111110000000 source: 01011 changed: 1 step 14 0101111110000000 source: 01001 changed: 0 step 15 0100111110000000 source: 01101 changed: 1 step 16 0110111110000000 source: 01111 changed: 1 step 17 0111111110000000 source: 11110 changed: 1 0 step 18 1111011110000000 source: 11101 changed: 01 step 19 1111011101000000 source: 11001 changed: 0 step 20 1111011001000000 source: 11011 changed: 1 step 21 1111011011000000 source: 10011 changed: 0 step 22 1111010011000000 source: 10001 changed: 0 step 23 1111010001000000 source: 10101 changed: 1 step 24 1111010101000000 source: 10111 changed: 1 step 25 1111010111000000 source: 00111 changed: 0 step 26 1111000111000000 source: 00101 changed: 0 step 27 1111000101000000 source: 00001 changed: 0 step 28 1111000001000000 source: 00011 changed: 1 step 29 1111000011000000 source: 01011 changed: 1 step 30 1111001011000000 source: 01001 changed: 0 step 31 1111001001000000 source: 01101 changed: 1 step 32 1111001101000000 source: 01111 changed: 1 step 33 1111001111000000 source: 11110 changed: 1 0 step 34 1111011110000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: source: ; ALL INPUTS LO source: 000100010001 changed: 000 100 01 1 step 35 0001100101010000 fail ^ ^ test 57: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O O all fails O O was hi 1111111111 1 rising ^^^^^^^^^^ ^ falling vvvvvvvvvv v was lo 0000000000000000 total fails 57, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; START WITH ALL INPUTS ZERO source: 0000100001000000 changed: 0 0 0 step 1 0000100001000000 source: source: ; ALL INPUTS ONES source: 1111011110 changed: 1111011110 step 2 1111011110000000 source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: 11101 changed: 01 step 3 1110111110000000 source: 11001 changed: 0 step 4 1100111110000000 source: 11011 changed: 1 step 5 1101111110000000 source: 10011 changed: 0 step 6 1001111110000000 source: 10001 changed: 0 step 7 1000111110000000 source: 10101 changed: 1 step 8 1010111110000000 source: 10111 changed: 1 step 9 1011111110000000 source: 00111 changed: 0 step 10 0011111110000000 source: 00101 changed: 0 step 11 0010111110000000 source: 00001 changed: 0 step 12 0000111110000000 source: 00011 changed: 1 step 13 0001111110000000 source: 01011 changed: 1 step 14 0101111110000000 source: 01001 changed: 0 step 15 0100111110000000 source: 01101 changed: 1 step 16 0110111110000000 source: 01111 changed: 1 step 17 0111111110000000 source: 11110 changed: 1 0 step 18 1111011110000000 source: 11101 changed: 01 step 19 1111011101000000 source: 11001 changed: 0 step 20 1111011001000000 source: 11011 changed: 1 step 21 1111011011000000 source: 10011 changed: 0 step 22 1111010011000000 source: 10001 changed: 0 step 23 1111010001000000 source: 10101 changed: 1 step 24 1111010101000000 source: 10111 changed: 1 step 25 1111010111000000 source: 00111 changed: 0 step 26 1111000111000000 source: 00101 changed: 0 step 27 1111000101000000 source: 00001 changed: 0 step 28 1111000001000000 source: 00011 changed: 1 step 29 1111000011000000 source: 01011 changed: 1 step 30 1111001011000000 source: 01001 changed: 0 step 31 1111001001000000 source: 01101 changed: 1 step 32 1111001101000000 source: 01111 changed: 1 step 33 1111001111000000 source: 11110 changed: 1 0 step 34 1111011110000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: source: ; ALL INPUTS LO source: 000100010001 changed: 000 100 01 1 step 35 0001100101010000 fail ^ ^ test 58: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O O all fails O O was hi 1111111111 1 rising ^^^^^^^^^^ ^ falling vvvvvvvvvv v was lo 0000000000000000 total fails 58, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails O O was lo 0000000000000000 falling vvvvvvvvvv v rising ^^^^^^^^^^ ^ was hi 1111111111 1 total fails 58, total passes 0 Main menu Fri Jun 30 15:09:17 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7440.tst reading test file: tests\7440.tst comment: 7440 DUAL 4-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 7440 PIN 1 1A pins: 2 I AB2 E1-2 7440 PIN 2 1B pins: 3 I AD2 E1-4 7440 PIN 4 1C pins: 4 I AE2 E1-5 7440 PIN 5 1D pins: 5 O AF2 E1-6 7440 PIN 6 1Y = 1A NAND 1B NAND 1C NAND 1D pins: 6 I AM2 E1-11 7440 PIN 9 2A pins: 7 I AN2 E1-12 7440 PIN 10 2B pins: 8 I AR2 E1-14 7440 PIN 12 2C pins: 9 I AS2 E1-15 7440 PIN 13 2D pins: 10 O AL2 E1-10 7440 PIN 8 2Y = 1A NAND 2B NAND 2C NAND 2D pins: 11 I AC1 E1-3 7440 PIN 3 N.C. pins: 12 I AP2 E1-13 7440 PIN 11 N.C. pins: 13 I AH2 E1-7 7440 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7440 PIN 14 VCC pins: direction: IIIIOIIIIOIIIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000100001000000 comment: comment: ; ALL INPUTS ONES test 2: 1111011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 11101 test 4: 11001 test 5: 11011 test 6: 10011 test 7: 10001 test 8: 10101 test 9: 10111 test 10: 00111 test 11: 00101 test 12: 00001 test 13: 00011 test 14: 01011 test 15: 01001 test 16: 01101 test 17: 01111 test 18: 11110 test 19: 11101 test 20: 11001 test 21: 11011 test 22: 10011 test 23: 10001 test 24: 10101 test 25: 10111 test 26: 00111 test 27: 00101 test 28: 00001 test 29: 00011 test 30: 01011 test 31: 01001 test 32: 01101 test 33: 01111 test 34: 11110 comment: comment: ; ALL INPUTS LO test 35: 0000100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0008 column 5: offset 0, mask 0x0004 column 6: offset 1, mask 0x0004 column 7: offset 1, mask 0x0008 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0002 column 11: offset 0, mask 0x2000 column 12: offset 1, mask 0x0010 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF02 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 2: 0x8058 0x006C 0x0000 0x0000 0x0000 3: 0x8054 0x006C 0x0000 0x0000 0x0000 4: 0x8044 0x006C 0x0000 0x0000 0x0000 5: 0x804C 0x006C 0x0000 0x0000 0x0000 6: 0x800C 0x006C 0x0000 0x0000 0x0000 7: 0x8004 0x006C 0x0000 0x0000 0x0000 8: 0x8014 0x006C 0x0000 0x0000 0x0000 9: 0x801C 0x006C 0x0000 0x0000 0x0000 10: 0x001C 0x006C 0x0000 0x0000 0x0000 11: 0x0014 0x006C 0x0000 0x0000 0x0000 12: 0x0004 0x006C 0x0000 0x0000 0x0000 13: 0x000C 0x006C 0x0000 0x0000 0x0000 14: 0x004C 0x006C 0x0000 0x0000 0x0000 15: 0x0044 0x006C 0x0000 0x0000 0x0000 16: 0x0054 0x006C 0x0000 0x0000 0x0000 17: 0x005C 0x006C 0x0000 0x0000 0x0000 18: 0x8058 0x006C 0x0000 0x0000 0x0000 19: 0x8058 0x002E 0x0000 0x0000 0x0000 20: 0x8058 0x000E 0x0000 0x0000 0x0000 21: 0x8058 0x004E 0x0000 0x0000 0x0000 22: 0x8058 0x0046 0x0000 0x0000 0x0000 23: 0x8058 0x0006 0x0000 0x0000 0x0000 24: 0x8058 0x0026 0x0000 0x0000 0x0000 25: 0x8058 0x0066 0x0000 0x0000 0x0000 26: 0x8058 0x0062 0x0000 0x0000 0x0000 27: 0x8058 0x0022 0x0000 0x0000 0x0000 28: 0x8058 0x0002 0x0000 0x0000 0x0000 29: 0x8058 0x0042 0x0000 0x0000 0x0000 30: 0x8058 0x004A 0x0000 0x0000 0x0000 31: 0x8058 0x000A 0x0000 0x0000 0x0000 32: 0x8058 0x002A 0x0000 0x0000 0x0000 33: 0x8058 0x006A 0x0000 0x0000 0x0000 34: 0x8058 0x006C 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIIIII G P G UUT inputs: 14 UUT outputs: 2 pins used: 16 not used: 50 35 'test steps' 81 lines 7440 DUAL 4-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V PINS Main menu Fri Jun 30 15:09:21 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:09:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails was lo 0000000000000000 falling vvvvvvvvvv rising ^^^^^^^^^^ was hi 1111111111 total fails 0, total passes 79 Main menu Fri Jun 30 15:12:49 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7440.tst reading test file: tests\7440.tst comment: 7440 DUAL 4-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 7440 PIN 1 1A pins: 2 I AB2 E1-2 7440 PIN 2 1B pins: 3 I AD2 E1-4 7440 PIN 4 1C pins: 4 I AE2 E1-5 7440 PIN 5 1D pins: 5 O AF2 E1-6 7440 PIN 6 1Y = 1A NAND 1B NAND 1C NAND 1D pins: 6 I AM2 E1-11 7440 PIN 9 2A pins: 7 I AN2 E1-12 7440 PIN 10 2B pins: 8 I AR2 E1-14 7440 PIN 12 2C pins: 9 I AS2 E1-15 7440 PIN 13 2D pins: 10 O AL2 E1-10 7440 PIN 8 2Y = 1A NAND 2B NAND 2C NAND 2D pins: 11 I AC1 E1-3 7440 PIN 3 N.C. pins: 12 I AP2 E1-13 7440 PIN 11 N.C. pins: 13 I AH2 E1-7 7440 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7440 PIN 14 VCC pins: direction: IIIIOIIIIOIIIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000100001000000 comment: comment: ; ALL INPUTS ONES test 2: 1111011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 11101 test 4: 11001 test 5: 11011 test 6: 10011 test 7: 10001 test 8: 10101 test 9: 10111 test 10: 00111 test 11: 00101 test 12: 00001 test 13: 00011 test 14: 01011 test 15: 01001 test 16: 01101 test 17: 01111 test 18: 11110 test 19: 11101 test 20: 11001 test 21: 11011 test 22: 10011 test 23: 10001 test 24: 10101 test 25: 10111 test 26: 00111 test 27: 00101 test 28: 00001 test 29: 00011 test 30: 01011 test 31: 01001 test 32: 01101 test 33: 01111 test 34: 11110 comment: comment: ; ALL INPUTS LO test 35: 0000100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 36: 00011 test 37: 00111 test 38: 00101 test 39: 01101 test 40: 01111 test 41: 01011 test 42: 01001 test 43: 11001 test 44: 11011 test 45: 11110 test 46: 11100 test 47: 10100 test 48: 10110 test 49: 10010 test 50: 10000 test 51: 10000 comment: comment: comment: comment: comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0008 column 5: offset 0, mask 0x0004 column 6: offset 1, mask 0x0004 column 7: offset 1, mask 0x0008 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0002 column 11: offset 0, mask 0x2000 column 12: offset 1, mask 0x0010 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF02 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 2: 0x8058 0x006C 0x0000 0x0000 0x0000 3: 0x8054 0x006C 0x0000 0x0000 0x0000 4: 0x8044 0x006C 0x0000 0x0000 0x0000 5: 0x804C 0x006C 0x0000 0x0000 0x0000 6: 0x800C 0x006C 0x0000 0x0000 0x0000 7: 0x8004 0x006C 0x0000 0x0000 0x0000 8: 0x8014 0x006C 0x0000 0x0000 0x0000 9: 0x801C 0x006C 0x0000 0x0000 0x0000 10: 0x001C 0x006C 0x0000 0x0000 0x0000 11: 0x0014 0x006C 0x0000 0x0000 0x0000 12: 0x0004 0x006C 0x0000 0x0000 0x0000 13: 0x000C 0x006C 0x0000 0x0000 0x0000 14: 0x004C 0x006C 0x0000 0x0000 0x0000 15: 0x0044 0x006C 0x0000 0x0000 0x0000 16: 0x0054 0x006C 0x0000 0x0000 0x0000 17: 0x005C 0x006C 0x0000 0x0000 0x0000 18: 0x8058 0x006C 0x0000 0x0000 0x0000 19: 0x8058 0x002E 0x0000 0x0000 0x0000 20: 0x8058 0x000E 0x0000 0x0000 0x0000 21: 0x8058 0x004E 0x0000 0x0000 0x0000 22: 0x8058 0x0046 0x0000 0x0000 0x0000 23: 0x8058 0x0006 0x0000 0x0000 0x0000 24: 0x8058 0x0026 0x0000 0x0000 0x0000 25: 0x8058 0x0066 0x0000 0x0000 0x0000 26: 0x8058 0x0062 0x0000 0x0000 0x0000 27: 0x8058 0x0022 0x0000 0x0000 0x0000 28: 0x8058 0x0002 0x0000 0x0000 0x0000 29: 0x8058 0x0042 0x0000 0x0000 0x0000 30: 0x8058 0x004A 0x0000 0x0000 0x0000 31: 0x8058 0x000A 0x0000 0x0000 0x0000 32: 0x8058 0x002A 0x0000 0x0000 0x0000 33: 0x8058 0x006A 0x0000 0x0000 0x0000 34: 0x8058 0x006C 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 36: 0x000C 0x0002 0x0000 0x0000 0x0000 37: 0x001C 0x0002 0x0000 0x0000 0x0000 38: 0x0014 0x0002 0x0000 0x0000 0x0000 39: 0x0054 0x0002 0x0000 0x0000 0x0000 40: 0x005C 0x0002 0x0000 0x0000 0x0000 41: 0x004C 0x0002 0x0000 0x0000 0x0000 42: 0x0044 0x0002 0x0000 0x0000 0x0000 43: 0x8044 0x0002 0x0000 0x0000 0x0000 44: 0x804C 0x0002 0x0000 0x0000 0x0000 45: 0x8058 0x0002 0x0000 0x0000 0x0000 46: 0x8050 0x0002 0x0000 0x0000 0x0000 47: 0x8010 0x0002 0x0000 0x0000 0x0000 48: 0x8018 0x0002 0x0000 0x0000 0x0000 49: 0x8008 0x0002 0x0000 0x0000 0x0000 50: 0x8000 0x0002 0x0000 0x0000 0x0000 51: 0x8000 0x0002 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIIIII G P G UUT inputs: 14 UUT outputs: 2 pins used: 16 not used: 50 51 'test steps' 103 lines 7440 DUAL 4-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V PINS Main menu Fri Jun 30 15:12:52 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:12:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 step 35 0000100001000000 step 36 0001100001000000 step 37 0011100001000000 step 38 0010100001000000 step 39 0110100001000000 step 40 0111100001000000 step 41 0101100001000000 step 42 0100100001000000 step 43 1100100001000000 step 44 1101100001000000 step 45 1111000001000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 01 step 46 1110100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 0 step 47 1010100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 1 step 48 1011100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 0 step 49 1001100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 0 step 50 1000100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: step 51 1000100001000000 fail ^ test 43: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O all fails O was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 43, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 step 35 0000100001000000 step 36 0001100001000000 step 37 0011100001000000 step 38 0010100001000000 step 39 0110100001000000 step 40 0111100001000000 step 41 0101100001000000 step 42 0100100001000000 step 43 1100100001000000 step 44 1101100001000000 step 45 1111000001000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 01 step 46 1110100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 0 step 47 1010100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 1 step 48 1011100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 0 step 49 1001100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 0 step 50 1000100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: step 51 1000100001000000 fail ^ test 44: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O all fails O was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 44, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 step 35 0000100001000000 step 36 0001100001000000 step 37 0011100001000000 step 38 0010100001000000 step 39 0110100001000000 step 40 0111100001000000 step 41 0101100001000000 step 42 0100100001000000 step 43 1100100001000000 step 44 1101100001000000 step 45 1111000001000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII changed: 01 step 46 1110100001000000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10100 changed: 0 step 47 1010100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10110 changed: 1 step 48 1011100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10010 changed: 0 step 49 1001100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10000 changed: 0 step 50 1000100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10000 changed: step 51 1000100001000000 fail ^ test 45: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O all fails O was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 45, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; START WITH ALL INPUTS ZERO source: 0000100001000000 changed: 0 step 1 0000100001000000 source: source: ; ALL INPUTS ONES source: 1111011110 changed: 1111011110 step 2 1111011110000000 source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: 11101 changed: 01 step 3 1110111110000000 source: 11001 changed: 0 step 4 1100111110000000 source: 11011 changed: 1 step 5 1101111110000000 source: 10011 changed: 0 step 6 1001111110000000 source: 10001 changed: 0 step 7 1000111110000000 source: 10101 changed: 1 step 8 1010111110000000 source: 10111 changed: 1 step 9 1011111110000000 source: 00111 changed: 0 step 10 0011111110000000 source: 00101 changed: 0 step 11 0010111110000000 source: 00001 changed: 0 step 12 0000111110000000 source: 00011 changed: 1 step 13 0001111110000000 source: 01011 changed: 1 step 14 0101111110000000 source: 01001 changed: 0 step 15 0100111110000000 source: 01101 changed: 1 step 16 0110111110000000 source: 01111 changed: 1 step 17 0111111110000000 source: 11110 changed: 1 0 step 18 1111011110000000 source: 11101 changed: 01 step 19 1111011101000000 source: 11001 changed: 0 step 20 1111011001000000 source: 11011 changed: 1 step 21 1111011011000000 source: 10011 changed: 0 step 22 1111010011000000 source: 10001 changed: 0 step 23 1111010001000000 source: 10101 changed: 1 step 24 1111010101000000 source: 10111 changed: 1 step 25 1111010111000000 source: 00111 changed: 0 step 26 1111000111000000 source: 00101 changed: 0 step 27 1111000101000000 source: 00001 changed: 0 step 28 1111000001000000 source: 00011 changed: 1 step 29 1111000011000000 source: 01011 changed: 1 step 30 1111001011000000 source: 01001 changed: 0 step 31 1111001001000000 source: 01101 changed: 1 step 32 1111001101000000 source: 01111 changed: 1 step 33 1111001111000000 source: 11110 changed: 1 0 step 34 1111011110000000 source: source: ; ALL INPUTS LO source: 0000100001 changed: 0000100001 step 35 0000100001000000 source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: 00011 changed: 1 step 36 0001100001000000 source: 00111 changed: 1 step 37 0011100001000000 source: 00101 changed: 0 step 38 0010100001000000 source: 01101 changed: 1 step 39 0110100001000000 source: 01111 changed: 1 step 40 0111100001000000 source: 01011 changed: 0 step 41 0101100001000000 source: 01001 changed: 0 step 42 0100100001000000 source: 11001 changed: 1 step 43 1100100001000000 source: 11011 changed: 1 step 44 1101100001000000 source: 11110 changed: 1 0 step 45 1111000001000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 11100 changed: 01 step 46 1110100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10100 changed: 0 step 47 1010100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10110 changed: 1 step 48 1011100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10010 changed: 0 step 49 1001100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10000 changed: 0 step 50 1000100001000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 10000 changed: step 51 1000100001000000 fail ^ test 46: *** FAIL *************************** 6 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail O all fails O was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 46, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; START WITH ALL INPUTS ZERO source: 0000100001000000 changed: 0 step 1 0000100001000000 source: source: ; ALL INPUTS ONES source: 1111011110 changed: 1111011110 step 2 1111011110000000 source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: 11101 changed: 01 step 3 1110111110000000 source: 11001 changed: 0 step 4 1100111110000000 source: 11011 changed: 1 step 5 1101111110000000 source: 10011 changed: 0 step 6 1001111110000000 source: 10001 changed: 0 step 7 1000111110000000 source: 10101 changed: 1 step 8 1010111110000000 source: 10111 changed: 1 step 9 1011111110000000 source: 00111 changed: 0 step 10 0011111110000000 source: 00101 changed: 0 step 11 0010111110000000 source: 00001 changed: 0 step 12 0000111110000000 source: 00011 changed: 1 step 13 0001111110000000 source: 01011 changed: 1 step 14 0101111110000000 source: 01001 changed: 0 step 15 0100111110000000 source: 01101 changed: 1 step 16 0110111110000000 source: 01111 changed: 1 step 17 0111111110000000 source: 11110 changed: 1 0 step 18 1111011110000000 source: 11101 changed: 01 step 19 1111011101000000 source: 11001 changed: 0 step 20 1111011001000000 source: 11011 changed: 1 step 21 1111011011000000 source: 10011 changed: 0 step 22 1111010011000000 source: 10001 changed: 0 step 23 1111010001000000 source: 10101 changed: 1 step 24 1111010101000000 source: 10111 changed: 1 step 25 1111010111000000 source: 00111 changed: 0 step 26 1111000111000000 source: 00101 changed: 0 step 27 1111000101000000 source: 00001 changed: 0 step 28 1111000001000000 source: 00011 changed: 1 step 29 1111000011000000 source: 01011 changed: 1 step 30 1111001011000000 source: 01001 changed: 0 step 31 1111001001000000 source: 01101 changed: 1 step 32 1111001101000000 source: 01111 changed: 1 step 33 1111001111000000 source: 11110 changed: 1 0 step 34 1111011110000000 source: source: ; ALL INPUTS LO source: 0000100001 changed: 0000100001 step 35 0000100001000000 source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: 00011 changed: 1 step 36 0001100001000000 source: 00111 changed: 1 step 37 0011100001000000 source: 00101 changed: 0 step 38 0010100001000000 source: 01101 changed: 1 step 39 0110100001000000 source: 01111 changed: 1 step 40 0111100001000000 source: 01011 changed: 0 step 41 0101100001000000 source: 01001 changed: 0 step 42 0100100001000000 source: 11001 changed: 1 step 43 1100100001000000 source: 11011 changed: 1 step 44 1101100001000000 source: 11110 changed: 1 0 step 45 1111000001000000 SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII source: 11100 changed: 01 step 46 1110100001000000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails O was lo 0000000000000000 falling vvvvvvvvvv rising ^^^^^^^^^^ was hi 1111111111 total fails 46, total passes 0 Main menu Fri Jun 30 15:13:45 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7440.tst reading test file: tests\7440.tst comment: 7440 DUAL 4-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 7440 PIN 1 1A pins: 2 I AB2 E1-2 7440 PIN 2 1B pins: 3 I AD2 E1-4 7440 PIN 4 1C pins: 4 I AE2 E1-5 7440 PIN 5 1D pins: 5 O AF2 E1-6 7440 PIN 6 1Y = 1A NAND 1B NAND 1C NAND 1D pins: 6 I AM2 E1-11 7440 PIN 9 2A pins: 7 I AN2 E1-12 7440 PIN 10 2B pins: 8 I AR2 E1-14 7440 PIN 12 2C pins: 9 I AS2 E1-15 7440 PIN 13 2D pins: 10 O AL2 E1-10 7440 PIN 8 2Y = 1A NAND 2B NAND 2C NAND 2D pins: 11 I AC1 E1-3 7440 PIN 3 N.C. pins: 12 I AP2 E1-13 7440 PIN 11 N.C. pins: 13 I AH2 E1-7 7440 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7440 PIN 14 VCC pins: direction: IIIIOIIIIOIIIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000100001000000 comment: comment: ; ALL INPUTS ONES test 2: 1111011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 11101 test 4: 11001 test 5: 11011 test 6: 10011 test 7: 10001 test 8: 10101 test 9: 10111 test 10: 00111 test 11: 00101 test 12: 00001 test 13: 00011 test 14: 01011 test 15: 01001 test 16: 01101 test 17: 01111 test 18: 11110 test 19: 11101 test 20: 11001 test 21: 11011 test 22: 10011 test 23: 10001 test 24: 10101 test 25: 10111 test 26: 00111 test 27: 00101 test 28: 00001 test 29: 00011 test 30: 01011 test 31: 01001 test 32: 01101 test 33: 01111 test 34: 11110 comment: comment: ; ALL INPUTS LO test 35: 0000100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 36: 00011 test 37: 00111 test 38: 00101 test 39: 01101 test 40: 01111 test 41: 01011 test 42: 01001 test 43: 11001 test 44: 11011 test 45: 11110 test 46: 11101 test 47: 10101 test 48: 10111 test 49: 10011 test 50: 10001 test 51: 10001 comment: comment: comment: comment: comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0008 column 5: offset 0, mask 0x0004 column 6: offset 1, mask 0x0004 column 7: offset 1, mask 0x0008 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0002 column 11: offset 0, mask 0x2000 column 12: offset 1, mask 0x0010 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF02 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 2: 0x8058 0x006C 0x0000 0x0000 0x0000 3: 0x8054 0x006C 0x0000 0x0000 0x0000 4: 0x8044 0x006C 0x0000 0x0000 0x0000 5: 0x804C 0x006C 0x0000 0x0000 0x0000 6: 0x800C 0x006C 0x0000 0x0000 0x0000 7: 0x8004 0x006C 0x0000 0x0000 0x0000 8: 0x8014 0x006C 0x0000 0x0000 0x0000 9: 0x801C 0x006C 0x0000 0x0000 0x0000 10: 0x001C 0x006C 0x0000 0x0000 0x0000 11: 0x0014 0x006C 0x0000 0x0000 0x0000 12: 0x0004 0x006C 0x0000 0x0000 0x0000 13: 0x000C 0x006C 0x0000 0x0000 0x0000 14: 0x004C 0x006C 0x0000 0x0000 0x0000 15: 0x0044 0x006C 0x0000 0x0000 0x0000 16: 0x0054 0x006C 0x0000 0x0000 0x0000 17: 0x005C 0x006C 0x0000 0x0000 0x0000 18: 0x8058 0x006C 0x0000 0x0000 0x0000 19: 0x8058 0x002E 0x0000 0x0000 0x0000 20: 0x8058 0x000E 0x0000 0x0000 0x0000 21: 0x8058 0x004E 0x0000 0x0000 0x0000 22: 0x8058 0x0046 0x0000 0x0000 0x0000 23: 0x8058 0x0006 0x0000 0x0000 0x0000 24: 0x8058 0x0026 0x0000 0x0000 0x0000 25: 0x8058 0x0066 0x0000 0x0000 0x0000 26: 0x8058 0x0062 0x0000 0x0000 0x0000 27: 0x8058 0x0022 0x0000 0x0000 0x0000 28: 0x8058 0x0002 0x0000 0x0000 0x0000 29: 0x8058 0x0042 0x0000 0x0000 0x0000 30: 0x8058 0x004A 0x0000 0x0000 0x0000 31: 0x8058 0x000A 0x0000 0x0000 0x0000 32: 0x8058 0x002A 0x0000 0x0000 0x0000 33: 0x8058 0x006A 0x0000 0x0000 0x0000 34: 0x8058 0x006C 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 36: 0x000C 0x0002 0x0000 0x0000 0x0000 37: 0x001C 0x0002 0x0000 0x0000 0x0000 38: 0x0014 0x0002 0x0000 0x0000 0x0000 39: 0x0054 0x0002 0x0000 0x0000 0x0000 40: 0x005C 0x0002 0x0000 0x0000 0x0000 41: 0x004C 0x0002 0x0000 0x0000 0x0000 42: 0x0044 0x0002 0x0000 0x0000 0x0000 43: 0x8044 0x0002 0x0000 0x0000 0x0000 44: 0x804C 0x0002 0x0000 0x0000 0x0000 45: 0x8058 0x0002 0x0000 0x0000 0x0000 46: 0x8054 0x0002 0x0000 0x0000 0x0000 47: 0x8014 0x0002 0x0000 0x0000 0x0000 48: 0x801C 0x0002 0x0000 0x0000 0x0000 49: 0x800C 0x0002 0x0000 0x0000 0x0000 50: 0x8004 0x0002 0x0000 0x0000 0x0000 51: 0x8004 0x0002 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIIIII G P G UUT inputs: 14 UUT outputs: 2 pins used: 16 not used: 50 51 'test steps' 103 lines 7440 DUAL 4-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V PINS Main menu Fri Jun 30 15:13:48 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:13:49 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails was lo 0000000000000000 falling vvvvvvvvvv rising ^^^^^^^^^^ was hi 1111111111 total fails 0, total passes 50 Main menu Fri Jun 30 15:13:52 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7440.tst reading test file: tests\7440.tst comment: 7440 DUAL 4-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 7440 PIN 1 1A pins: 2 I AB2 E1-2 7440 PIN 2 1B pins: 3 I AD2 E1-4 7440 PIN 4 1C pins: 4 I AE2 E1-5 7440 PIN 5 1D pins: 5 O AF2 E1-6 7440 PIN 6 1Y = 1A NAND 1B NAND 1C NAND 1D pins: 6 I AM2 E1-11 7440 PIN 9 2A pins: 7 I AN2 E1-12 7440 PIN 10 2B pins: 8 I AR2 E1-14 7440 PIN 12 2C pins: 9 I AS2 E1-15 7440 PIN 13 2D pins: 10 O AL2 E1-10 7440 PIN 8 2Y = 1A NAND 2B NAND 2C NAND 2D pins: 11 I AC1 E1-3 7440 PIN 3 N.C. pins: 12 I AP2 E1-13 7440 PIN 11 N.C. pins: 13 I AH2 E1-7 7440 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7440 PIN 14 VCC pins: direction: IIIIOIIIIOIIIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 0000100001000000 comment: comment: ; ALL INPUTS ONES test 2: 1111011110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 11101 test 4: 11001 test 5: 11011 test 6: 10011 test 7: 10001 test 8: 10101 test 9: 10111 test 10: 00111 test 11: 00101 test 12: 00001 test 13: 00011 test 14: 01011 test 15: 01001 test 16: 01101 test 17: 01111 test 18: 11110 test 19: 11101 test 20: 11001 test 21: 11011 test 22: 10011 test 23: 10001 test 24: 10101 test 25: 10111 test 26: 00111 test 27: 00101 test 28: 00001 test 29: 00011 test 30: 01011 test 31: 01001 test 32: 01101 test 33: 01111 test 34: 11110 comment: comment: ; ALL INPUTS LO test 35: 0000100001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 36: 00011 test 37: 00111 test 38: 00101 test 39: 01101 test 40: 01111 test 41: 01011 test 42: 01001 test 43: 11001 test 44: 11011 test 45: 11110 test 46: 11101 test 47: 10101 test 48: 10111 test 49: 10011 test 50: 10001 test 51: 00001 test 52: 00011 test 53: 00111 test 54: 00101 test 55: 01101 test 56: 01111 test 57: 01011 test 58: 01001 test 59: 11001 test 60: 11011 test 61: 11110 test 62: 11101 test 63: 10101 test 64: 10111 test 65: 10011 test 66: 10001 test 67: 00001 comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0008 column 5: offset 0, mask 0x0004 column 6: offset 1, mask 0x0004 column 7: offset 1, mask 0x0008 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0040 column 10: offset 1, mask 0x0002 column 11: offset 0, mask 0x2000 column 12: offset 1, mask 0x0010 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA4 0xFF02 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0004 0x0002 0x0000 0x0000 0x0000 2: 0x8058 0x006C 0x0000 0x0000 0x0000 3: 0x8054 0x006C 0x0000 0x0000 0x0000 4: 0x8044 0x006C 0x0000 0x0000 0x0000 5: 0x804C 0x006C 0x0000 0x0000 0x0000 6: 0x800C 0x006C 0x0000 0x0000 0x0000 7: 0x8004 0x006C 0x0000 0x0000 0x0000 8: 0x8014 0x006C 0x0000 0x0000 0x0000 9: 0x801C 0x006C 0x0000 0x0000 0x0000 10: 0x001C 0x006C 0x0000 0x0000 0x0000 11: 0x0014 0x006C 0x0000 0x0000 0x0000 12: 0x0004 0x006C 0x0000 0x0000 0x0000 13: 0x000C 0x006C 0x0000 0x0000 0x0000 14: 0x004C 0x006C 0x0000 0x0000 0x0000 15: 0x0044 0x006C 0x0000 0x0000 0x0000 16: 0x0054 0x006C 0x0000 0x0000 0x0000 17: 0x005C 0x006C 0x0000 0x0000 0x0000 18: 0x8058 0x006C 0x0000 0x0000 0x0000 19: 0x8058 0x002E 0x0000 0x0000 0x0000 20: 0x8058 0x000E 0x0000 0x0000 0x0000 21: 0x8058 0x004E 0x0000 0x0000 0x0000 22: 0x8058 0x0046 0x0000 0x0000 0x0000 23: 0x8058 0x0006 0x0000 0x0000 0x0000 24: 0x8058 0x0026 0x0000 0x0000 0x0000 25: 0x8058 0x0066 0x0000 0x0000 0x0000 26: 0x8058 0x0062 0x0000 0x0000 0x0000 27: 0x8058 0x0022 0x0000 0x0000 0x0000 28: 0x8058 0x0002 0x0000 0x0000 0x0000 29: 0x8058 0x0042 0x0000 0x0000 0x0000 30: 0x8058 0x004A 0x0000 0x0000 0x0000 31: 0x8058 0x000A 0x0000 0x0000 0x0000 32: 0x8058 0x002A 0x0000 0x0000 0x0000 33: 0x8058 0x006A 0x0000 0x0000 0x0000 34: 0x8058 0x006C 0x0000 0x0000 0x0000 35: 0x0004 0x0002 0x0000 0x0000 0x0000 36: 0x000C 0x0002 0x0000 0x0000 0x0000 37: 0x001C 0x0002 0x0000 0x0000 0x0000 38: 0x0014 0x0002 0x0000 0x0000 0x0000 39: 0x0054 0x0002 0x0000 0x0000 0x0000 40: 0x005C 0x0002 0x0000 0x0000 0x0000 41: 0x004C 0x0002 0x0000 0x0000 0x0000 42: 0x0044 0x0002 0x0000 0x0000 0x0000 43: 0x8044 0x0002 0x0000 0x0000 0x0000 44: 0x804C 0x0002 0x0000 0x0000 0x0000 45: 0x8058 0x0002 0x0000 0x0000 0x0000 46: 0x8054 0x0002 0x0000 0x0000 0x0000 47: 0x8014 0x0002 0x0000 0x0000 0x0000 48: 0x801C 0x0002 0x0000 0x0000 0x0000 49: 0x800C 0x0002 0x0000 0x0000 0x0000 50: 0x8004 0x0002 0x0000 0x0000 0x0000 51: 0x0004 0x0002 0x0000 0x0000 0x0000 52: 0x0004 0x0042 0x0000 0x0000 0x0000 53: 0x0004 0x0062 0x0000 0x0000 0x0000 54: 0x0004 0x0022 0x0000 0x0000 0x0000 55: 0x0004 0x002A 0x0000 0x0000 0x0000 56: 0x0004 0x006A 0x0000 0x0000 0x0000 57: 0x0004 0x004A 0x0000 0x0000 0x0000 58: 0x0004 0x000A 0x0000 0x0000 0x0000 59: 0x0004 0x000E 0x0000 0x0000 0x0000 60: 0x0004 0x004E 0x0000 0x0000 0x0000 61: 0x0004 0x006C 0x0000 0x0000 0x0000 62: 0x0004 0x002E 0x0000 0x0000 0x0000 63: 0x0004 0x0026 0x0000 0x0000 0x0000 64: 0x0004 0x0066 0x0000 0x0000 0x0000 65: 0x0004 0x0046 0x0000 0x0000 0x0000 66: 0x0004 0x0006 0x0000 0x0000 0x0000 67: 0x0004 0x0002 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIOIIIOIIIIII G P G UUT inputs: 14 UUT outputs: 2 pins used: 16 not used: 50 67 'test steps' 114 lines 7440 DUAL 4-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V PINS Main menu Fri Jun 30 15:15:26 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:15:27 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 50 1000100001000000 step 51 0000100001000000 step 52 0000100011000000 step 53 0000100111000000 step 54 0000100101000000 step 55 0000101101000000 step 56 0000101111000000 step 57 0000101011000000 step 58 0000101001000000 step 59 0000111001000000 step 60 0000111011000000 step 61 0000111110000000 step 62 0000111101000000 step 63 0000110101000000 step 64 0000110111000000 step 65 0000110011000000 step 66 0000110001000000 step 67 0000100001000000 test 47: pass SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail all fails was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 47 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 step 35 0000100001000000 step 36 0001100001000000 step 37 0011100001000000 step 38 0010100001000000 step 39 0110100001000000 step 40 0111100001000000 step 41 0101100001000000 step 42 0100100001000000 step 43 1100100001000000 step 44 1101100001000000 step 45 1111000001000000 step 46 1110100001000000 step 47 1010100001000000 step 48 1011100001000000 step 49 1001100001000000 step 50 1000100001000000 step 51 0000100001000000 step 52 0000100011000000 step 53 0000100111000000 step 54 0000100101000000 step 55 0000101101000000 step 56 0000101111000000 step 57 0000101011000000 step 58 0000101001000000 step 59 0000111001000000 step 60 0000111011000000 step 61 0000111110000000 step 62 0000111101000000 step 63 0000110101000000 step 64 0000110111000000 step 65 0000110011000000 step 66 0000110001000000 step 67 0000100001000000 test 48: pass SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail all fails was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 48 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 step 35 0000100001000000 step 36 0001100001000000 step 37 0011100001000000 step 38 0010100001000000 step 39 0110100001000000 step 40 0111100001000000 step 41 0101100001000000 step 42 0100100001000000 step 43 1100100001000000 step 44 1101100001000000 step 45 1111000001000000 step 46 1110100001000000 step 47 1010100001000000 step 48 1011100001000000 step 49 1001100001000000 step 50 1000100001000000 step 51 0000100001000000 step 52 0000100011000000 step 53 0000100111000000 step 54 0000100101000000 step 55 0000101101000000 step 56 0000101111000000 step 57 0000101011000000 step 58 0000101001000000 step 59 0000111001000000 step 60 0000111011000000 step 61 0000111110000000 step 62 0000111101000000 step 63 0000110101000000 step 64 0000110111000000 step 65 0000110011000000 step 66 0000110001000000 step 67 0000100001000000 test 49: pass SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail all fails was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 49 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 step 35 0000100001000000 step 36 0001100001000000 step 37 0011100001000000 step 38 0010100001000000 step 39 0110100001000000 step 40 0111100001000000 step 41 0101100001000000 step 42 0100100001000000 step 43 1100100001000000 step 44 1101100001000000 step 45 1111000001000000 step 46 1110100001000000 step 47 1010100001000000 step 48 1011100001000000 step 49 1001100001000000 step 50 1000100001000000 step 51 0000100001000000 step 52 0000100011000000 step 53 0000100111000000 step 54 0000100101000000 step 55 0000101101000000 step 56 0000101111000000 step 57 0000101011000000 step 58 0000101001000000 step 59 0000111001000000 step 60 0000111011000000 step 61 0000111110000000 step 62 0000111101000000 step 63 0000110101000000 step 64 0000110111000000 step 65 0000110011000000 step 66 0000110001000000 step 67 0000100001000000 test 50: pass SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail all fails was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 50 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000100001000000 step 2 1111011110000000 step 3 1110111110000000 step 4 1100111110000000 step 5 1101111110000000 step 6 1001111110000000 step 7 1000111110000000 step 8 1010111110000000 step 9 1011111110000000 step 10 0011111110000000 step 11 0010111110000000 step 12 0000111110000000 step 13 0001111110000000 step 14 0101111110000000 step 15 0100111110000000 step 16 0110111110000000 step 17 0111111110000000 step 18 1111011110000000 step 19 1111011101000000 step 20 1111011001000000 step 21 1111011011000000 step 22 1111010011000000 step 23 1111010001000000 step 24 1111010101000000 step 25 1111010111000000 step 26 1111000111000000 step 27 1111000101000000 step 28 1111000001000000 step 29 1111000011000000 step 30 1111001011000000 step 31 1111001001000000 step 32 1111001101000000 step 33 1111001111000000 step 34 1111011110000000 step 35 0000100001000000 step 36 0001100001000000 step 37 0011100001000000 step 38 0010100001000000 step 39 0110100001000000 step 40 0111100001000000 step 41 0101100001000000 step 42 0100100001000000 step 43 1100100001000000 step 44 1101100001000000 step 45 1111000001000000 step 46 1110100001000000 step 47 1010100001000000 step 48 1011100001000000 step 49 1001100001000000 step 50 1000100001000000 step 51 0000100001000000 step 52 0000100011000000 step 53 0000100111000000 step 54 0000100101000000 step 55 0000101101000000 step 56 0000101111000000 step 57 0000101011000000 step 58 0000101001000000 step 59 0000111001000000 step 60 0000111011000000 step 61 0000111110000000 step 62 0000111101000000 step 63 0000110101000000 step 64 0000110111000000 step 65 0000110011000000 step 66 0000110001000000 step 67 0000100001000000 test 51: pass SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII this fail all fails was hi 1111111111 rising ^^^^^^^^^^ falling vvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 51 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 6 I AM2 E1-11 7440 PIN 9 2A space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails was lo 0000000000000000 falling vvvvvvvvvv rising ^^^^^^^^^^ was hi 1111111111 total fails 0, total passes 51 Main menu Fri Jun 30 15:15:41 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:16:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails was lo 0000000000000000 falling vvvvvvvvvv rising ^^^^^^^^^^ was hi 1111111111 total fails 0, total passes 40 Main menu Fri Jun 30 15:17:31 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:17:33 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails was lo 0000000000000000 falling vvvvvvvvvv rising ^^^^^^^^^^ was hi 1111111111 total fails 0, total passes 37 Main menu Fri Jun 30 15:17:35 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:18:18 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABDEFMNRSLCPHJKT SIDE 1222222222122222 DIRECTION IIIIOIIIIOIIIIII all fails was lo 0000000000000000 falling vvvvvvvvvv rising ^^^^^^^^^^ was hi 1111111111 total fails 0, total passes 42 Main menu Fri Jun 30 15:18:21 2017 test file is: tests\7440.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 15:21:34 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:21:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 17 Main menu Fri Jun 30 15:21:37 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m304.tst reading test file: tests\m304.tst comment: M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. comment: comment: USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. comment: comment: PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AF1 OUT-A, comment: NEGATIVE PULSE ON AH1 OUT-A-N comment: PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AJ1 OUT-B, comment: NEGATIVE PULSE ON AK1 OUT-B-N. comment: PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AL1 OUT-C, comment: NEGATIVE PULSE ON AM1 OUT-C-N. comment: PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AP1 OUT-D, comment: NEGATIVE PULSE ON AN1 OUT-D-N. comment: comment: TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE comment: INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE comment: TRIGGER. comment: pins: PINS pins: 1 I AD1 E2-13 INPUT A1 (LOW TRIGGERS) pins: 2 I AD2 E2-12 INPUT A2 (LOW TRIGGERS) pins: 3 O AF1 E1-08 OUTPUT A POSITIVE PULSE pins: 4 O AH1 E1-06 OUTPUT A-N NEGATIVE PULSE pins: 5 I AE1 E2-10 INPUT B1 (LOW TRIGGERS) pins: 6 I AE2 E2-09 INPUT B2 (LOW TRIGGERS) pins: 7 O AJ1 E3-08 OUTPUT B POSITIVE PULSE pins: 8 O AK1 E3-06 OUTPUT B-N NEGATIVE PULSE pins: 9 I AS1 E7-01 INPUT C1 (LOW TRIGGERS) pins: 10 I AS2 E7-02 INPUT C2 (LOW TRIGGERS) pins: 11 O AL1 E5-08 OUTPUT C POSITIVE PULSE pins: 12 O AM1 E5-06 OUTPUT C-N NEGATIVE PULSE pins: 13 I AR1 E7-04 INPUT D1 (LOW TRIGGERS) pins: 14 I AR2 E7-05 INPUT D2 (LOW TRIGGERS) pins: 15 O AP1 E6-06 OUTPUT D POSITIVE PULSE pins: 16 O AN1 E6-08 OUTPUT D-N NEGATIVE PULSE pins: direction: IIOOIIOOIIOOIIOO test 1: 1101110111011101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 2: 0101 test 3: 1101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 4: 1001 test 5: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 6: 0101 test 7: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 8: 1001 test 9: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 10: 0101 test 11: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 12: 1001 test 13: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 14: 0101 test 15: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 16: 1001 test 17: 1101 test 18: 1101110111011101 end: END summary column 1: offset 0, mask 0x1000 column 2: offset 0, mask 0x0010 column 3: offset 0, mask 0x0400 column 4: offset 0, mask 0x0200 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0100 column 8: offset 1, mask 0x8000 column 9: offset 1, mask 0x0200 column 10: offset 1, mask 0x0040 column 11: offset 1, mask 0x4000 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x0400 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0800 column 16: offset 1, mask 0x1000 direction bits (1=input) 0xE7E7 0xF99F 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1A18 0xB660 0x0000 0x0000 0x0000 2: 0x0A18 0xB660 0x0000 0x0000 0x0000 3: 0x1A18 0xB660 0x0000 0x0000 0x0000 4: 0x1A08 0xB660 0x0000 0x0000 0x0000 5: 0x1A18 0xB660 0x0000 0x0000 0x0000 6: 0x1218 0xB660 0x0000 0x0000 0x0000 7: 0x1A18 0xB660 0x0000 0x0000 0x0000 8: 0x1A10 0xB660 0x0000 0x0000 0x0000 9: 0x1A18 0xB660 0x0000 0x0000 0x0000 10: 0x1A18 0xB460 0x0000 0x0000 0x0000 11: 0x1A18 0xB660 0x0000 0x0000 0x0000 12: 0x1A18 0xB620 0x0000 0x0000 0x0000 13: 0x1A18 0xB660 0x0000 0x0000 0x0000 14: 0x1A18 0xB260 0x0000 0x0000 0x0000 15: 0x1A18 0xB660 0x0000 0x0000 0x0000 16: 0x1A18 0xB640 0x0000 0x0000 0x0000 17: 0x1A18 0xB660 0x0000 0x0000 0x0000 18: 0x1A18 0xB660 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOOOOOOOOIIG P GII II G P G UUT inputs: 8 UUT outputs: 8 pins used: 16 not used: 50 18 'test steps' 67 lines M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) POSITIVE PULSE ON AF1 OUT-A, NEGATIVE PULSE ON AH1 OUT-A-N PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) POSITIVE PULSE ON AJ1 OUT-B, NEGATIVE PULSE ON AK1 OUT-B-N. PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) POSITIVE PULSE ON AL1 OUT-C, NEGATIVE PULSE ON AM1 OUT-C-N. PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) POSITIVE PULSE ON AP1 OUT-D, NEGATIVE PULSE ON AN1 OUT-D-N. TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE TRIGGER. PINS Main menu Fri Jun 30 15:26:50 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 15:27:09 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 15:27:20 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 15:27:20 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 15:27:22 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:27:26 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 117: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 117, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 118: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 118, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 119: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 119, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 120: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 120, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101110111011101 changed: step 1 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO all fails O was lo 0000000 000 000 falling vv vv vv vv rising ^^ ^^ ^^ ^^ was hi 11 11 111 111 1 total fails 120, total passes 0 Main menu Fri Jun 30 15:32:58 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:33:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO all fails O was lo 00 0 0 0 falling rising was hi 11 11 111 111 1 total fails 0, total passes 0 Main menu Fri Jun 30 15:46:56 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 15:47:01 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:47:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 58 Main menu Fri Jun 30 15:47:13 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 15:47:29 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:47:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 43: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 43 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 1 001001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 3 011110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 4 001110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 5 101110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 6 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 7 110011110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 8 110001110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 9 110101110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 10 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 11 110110011110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 12 110110001110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 13 110110101110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 14 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 15 110110110011110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 16 110110110001110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 17 110110110101110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 18 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 19 110110110110011110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 20 110110110110001110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 21 110110110110101110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 22 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 23 110110110110110011110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 24 110110110110110001110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 25 110110110110110101110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 26 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 27 110110110110110110011110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 28 110110110110110110001110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 29 110110110110110110101110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 30 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 31 110110110110110110110011110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 32 110110110110110110110001110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 step 33 110110110110110110110101110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 43 Main menu Fri Jun 30 15:47:54 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 15:48:12 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:48:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 40 Main menu Fri Jun 30 15:48:21 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst could not open test file. valid test files are: reverting back to test file: tests\m115.tst Main menu Fri Jun 30 15:48:37 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 15:48:38 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:48:39 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails O OI OI O I O I O IO IO was lo 000000000000000000000000000 000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv vvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^ was hi 11111111111111111111111111111111 total fails 34, total passes 0 Main menu Fri Jun 30 15:48:55 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst could not open test file. valid test files are: reverting back to test file: tests\m115.tst Main menu Fri Jun 30 15:49:00 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 15:49:49 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 15:49:54 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:49:57 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 28 Main menu Fri Jun 30 15:50:01 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:50:11 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 15 Main menu Fri Jun 30 15:50:13 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m627.tst could not open test file. valid test files are: reverting back to test file: tests\m617.tst Main menu Fri Jun 30 15:50:43 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 15:50:49 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:50:51 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 53 Main menu Fri Jun 30 15:51:00 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 15:51:29 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:51:32 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 82 Main menu Fri Jun 30 15:51:38 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m112.tst reading test file: tests\m112.tst comment: M112 PCB REV D SCHEMATIC REV D 10 2-input NOR comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 O AC1 E1-13 pins: 4 I AD1 E1-5 pins: 5 I AE1 E1-6 pins: 6 O AF1 E1-4 pins: 7 I AD2 E1-9 pins: 8 I AE2 E1-8 pins: 9 O AF2 E1-10 pins: 10 I AH1 E1-3 pins: 11 I AJ1 E1-2 pins: 12 O AK1 E1-1 pins: 13 I AH2 E2-3 pins: 14 I AJ2 E2-2 pins: 15 O AK2 E2-1 pins: 16 I AL1 E2-6 pins: 17 I AM1 E2-5 pins: 18 O AN1 E2-4 pins: 19 I AL2 E3-9 pins: 20 I AM2 E3-8 pins: 21 O AN2 E3-10 pins: 22 I AP1 E3-12 pins: 23 I AR1 E3-11 pins: 24 O AS1 E3-13 pins: 25 I AP2 E3-6 pins: 26 I AR2 E3-5 pins: 27 O AS2 E3-4 pins: 28 I AT2 E3-3 pins: 29 I AU2 E3-2 pins: 30 O AV2 E3-1 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 010 test 3: 110 test 4: 100 test 5: 001 test 6: 010 test 7: 110 test 8: 100 test 9: 001 test 10: 010 test 11: 110 test 12: 100 test 13: 001 test 14: 010 test 15: 110 test 16: 100 test 17: 001 test 18: 010 test 19: 110 test 20: 100 test 21: 001 test 22: 010 test 23: 110 test 24: 100 test 25: 001 test 26: 010 test 27: 110 test 28: 100 test 29: 001 test 30: 010 test 31: 110 test 32: 100 test 33: 001 test 34: 010 test 35: 110 test 36: 100 test 37: 001 test 38: 010 test 39: 110 test 40: 100 test 41: 001 test 42: 001001001001001001001001001001 test 43: 110110110110110110110110110110 test 44: 010 test 45: 001 test 46: 100 test 47: 110 test 48: 010 test 49: 001 test 50: 100 test 51: 110 test 52: 010 test 53: 001 test 54: 100 test 55: 110 test 56: 010 test 57: 001 test 58: 100 test 59: 110 test 60: 010 test 61: 001 test 62: 100 test 63: 110 test 64: 010 test 65: 001 test 66: 100 test 67: 110 test 68: 010 test 69: 001 test 70: 100 test 71: 110 test 72: 010 test 73: 001 test 74: 100 test 75: 110 test 76: 010 test 77: 001 test 78: 100 test 79: 110 test 80: 010 test 81: 001 test 82: 100 test 83: 110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0x4404 0x9249 0x0002 0x0000 0x0000 3: 0xC404 0x9249 0x0002 0x0000 0x0000 4: 0x8404 0x9249 0x0002 0x0000 0x0000 5: 0x2404 0x9249 0x0002 0x0000 0x0000 6: 0x2804 0x9249 0x0002 0x0000 0x0000 7: 0x3804 0x9249 0x0002 0x0000 0x0000 8: 0x3004 0x9249 0x0002 0x0000 0x0000 9: 0x2404 0x9249 0x0002 0x0000 0x0000 10: 0x2408 0x9249 0x0002 0x0000 0x0000 11: 0x2418 0x9249 0x0002 0x0000 0x0000 12: 0x2410 0x9249 0x0002 0x0000 0x0000 13: 0x2404 0x9249 0x0002 0x0000 0x0000 14: 0x2504 0x1249 0x0002 0x0000 0x0000 15: 0x2704 0x1249 0x0002 0x0000 0x0000 16: 0x2604 0x1249 0x0002 0x0000 0x0000 17: 0x2404 0x9249 0x0002 0x0000 0x0000 18: 0x2405 0x9248 0x0002 0x0000 0x0000 19: 0x2407 0x9248 0x0002 0x0000 0x0000 20: 0x2406 0x9248 0x0002 0x0000 0x0000 21: 0x2404 0x9249 0x0002 0x0000 0x0000 22: 0x2404 0xA249 0x0002 0x0000 0x0000 23: 0x2404 0xE249 0x0002 0x0000 0x0000 24: 0x2404 0xC249 0x0002 0x0000 0x0000 25: 0x2404 0x9249 0x0002 0x0000 0x0000 26: 0x2404 0x9245 0x0002 0x0000 0x0000 27: 0x2404 0x9247 0x0002 0x0000 0x0000 28: 0x2404 0x9243 0x0002 0x0000 0x0000 29: 0x2404 0x9249 0x0002 0x0000 0x0000 30: 0x2404 0x9449 0x0002 0x0000 0x0000 31: 0x2404 0x9C49 0x0002 0x0000 0x0000 32: 0x2404 0x9849 0x0002 0x0000 0x0000 33: 0x2404 0x9249 0x0002 0x0000 0x0000 34: 0x2404 0x9229 0x0002 0x0000 0x0000 35: 0x2404 0x9239 0x0002 0x0000 0x0000 36: 0x2404 0x9219 0x0002 0x0000 0x0000 37: 0x2404 0x9249 0x0002 0x0000 0x0000 38: 0x2404 0x9249 0x0001 0x0000 0x0000 39: 0x2404 0x92C9 0x0001 0x0000 0x0000 40: 0x2404 0x92C9 0x0000 0x0000 0x0000 41: 0x2404 0x9249 0x0002 0x0000 0x0000 42: 0x2404 0x9249 0x0002 0x0000 0x0000 43: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 44: 0x5B1B 0x6CB6 0x0001 0x0000 0x0000 45: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 46: 0x9B1B 0x6CB6 0x0001 0x0000 0x0000 47: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 48: 0xCB1B 0x6CB6 0x0001 0x0000 0x0000 49: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 50: 0xD31B 0x6CB6 0x0001 0x0000 0x0000 51: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 52: 0xDB0B 0x6CB6 0x0001 0x0000 0x0000 53: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 54: 0xDB13 0x6CB6 0x0001 0x0000 0x0000 55: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 56: 0xD91B 0x6CB6 0x0001 0x0000 0x0000 57: 0xD81B 0xECB6 0x0001 0x0000 0x0000 58: 0xDA1B 0x6CB6 0x0001 0x0000 0x0000 59: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 60: 0xDB19 0x6CB6 0x0001 0x0000 0x0000 61: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 62: 0xDB1A 0x6CB6 0x0001 0x0000 0x0000 63: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 64: 0xDB1B 0x2CB6 0x0001 0x0000 0x0000 65: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 66: 0xDB1B 0x4CB6 0x0001 0x0000 0x0000 67: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 68: 0xDB1B 0x6CB4 0x0001 0x0000 0x0000 69: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 70: 0xDB1B 0x6CB2 0x0001 0x0000 0x0000 71: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 72: 0xDB1B 0x64B6 0x0001 0x0000 0x0000 73: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 74: 0xDB1B 0x68B6 0x0001 0x0000 0x0000 75: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 76: 0xDB1B 0x6CA6 0x0001 0x0000 0x0000 77: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 78: 0xDB1B 0x6C96 0x0001 0x0000 0x0000 79: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 80: 0xDB1B 0x6C36 0x0001 0x0000 0x0000 81: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 82: 0xDB1B 0x6CB6 0x0000 0x0000 0x0000 83: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M112 PCB REV D SCHEMATIC REV D 10 2-input NOR PINS Main menu Fri Jun 30 15:51:58 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:52:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 69 Main menu Fri Jun 30 15:52:05 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 15:52:19 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:52:22 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 43 Main menu Fri Jun 30 15:52:25 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 15:52:55 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:52:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 49 Main menu Fri Jun 30 15:52:59 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 15:53:12 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:53:14 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 35 Main menu Fri Jun 30 15:53:17 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 15:53:32 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:53:33 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 25 Main menu Fri Jun 30 15:53:36 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:53:53 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 23 Main menu Fri Jun 30 15:53:57 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 15:54:18 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:54:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 27 Main menu Fri Jun 30 15:54:23 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 15:54:39 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:54:40 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 23 Main menu Fri Jun 30 15:54:43 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 15:55:04 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:55:05 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 132 Main menu Fri Jun 30 15:55:20 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 15:55:34 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:55:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 54 Main menu Fri Jun 30 15:55:40 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 15:55:58 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:56:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 44 Main menu Fri Jun 30 15:56:03 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:56:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 33 Main menu Fri Jun 30 15:56:18 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:56:44 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 52 Main menu Fri Jun 30 15:56:48 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 15:57:18 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:57:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 51 Main menu Fri Jun 30 15:57:24 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 15:57:51 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:57:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails IOO OO I OO I OO OO OO was lo 00000000000000000000000000000000 falling vvvv vvvv vvv vvvv vvv vvvv v rising ^^^^ ^^^^ ^^^ ^^^^ ^^^ ^^^^ ^ was hi 1111 1111 111 1111 111 1111 1 total fails 51, total passes 0 Main menu Fri Jun 30 15:58:25 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 15:58:31 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 15:58:45 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 15:58:49 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:58:52 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 38 Main menu Fri Jun 30 15:58:55 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 15:59:10 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:59:11 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 64 Main menu Fri Jun 30 15:59:15 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 16: 000011101 test 17: 000011111 test 18: 000100001 test 19: 000100011 test 20: 000100101 test 21: 000100111 test 22: 000101001 test 23: 000101011 test 24: 000101101 test 25: 000101111 test 26: 000110001 test 27: 000110011 test 28: 000110101 test 29: 000110111 test 30: 000111001 test 31: 000111011 test 32: 000111101 test 33: 000111111 test 34: 001000001 test 35: 001000011 test 36: 001000101 test 37: 001000111 test 38: 001001001 test 39: 001001011 test 40: 001001101 test 41: 001001111 test 42: 001010001 test 43: 001010011 test 44: 001010101 test 45: 001010111 test 46: 001011001 test 47: 001011011 test 48: 001011101 test 49: 001011111 test 50: 001100001 test 51: 001100011 test 52: 001100101 test 53: 001100111 test 54: 001101001 test 55: 001101011 test 56: 001101101 test 57: 001101111 test 58: 001110001 test 59: 001110011 test 60: 001110101 test 61: 001110111 test 62: 001111001 test 63: 001111011 test 64: 001111101 test 65: 001111111 test 66: 010000001 test 67: 010000011 test 68: 010000101 test 69: 010000111 test 70: 010001001 test 71: 010001011 test 72: 010001101 test 73: 010001111 test 74: 010010001 test 75: 010010011 test 76: 010010101 test 77: 010010111 test 78: 010011001 test 79: 010011011 test 80: 010011101 test 81: 010011111 test 82: 010100001 test 83: 010100011 test 84: 010100101 test 85: 010100111 test 86: 010101001 test 87: 010101011 test 88: 010101101 test 89: 010101111 test 90: 010110001 test 91: 010110011 test 92: 010110101 test 93: 010110111 test 94: 010111001 test 95: 010111011 test 96: 010111101 test 97: 010111111 test 98: 011000001 test 99: 011000011 test 100: 011000101 test 101: 011000111 test 102: 011001001 test 103: 011001011 test 104: 011001101 test 105: 011001111 test 106: 011010001 test 107: 011010011 test 108: 011010101 test 109: 011010111 test 110: 011011001 test 111: 011011011 test 112: 011011101 test 113: 011011111 test 114: 011100001 test 115: 011100011 test 116: 011100101 test 117: 011100111 test 118: 011101001 test 119: 011101011 test 120: 011101101 test 121: 011101111 test 122: 011110001 test 123: 011110011 test 124: 011110101 test 125: 011110111 test 126: 011111001 test 127: 011111011 test 128: 011111101 test 129: 011111111 test 130: 100000001 test 131: 100000011 test 132: 100000101 test 133: 100000111 test 134: 100001001 test 135: 100001011 test 136: 100001101 test 137: 100001111 test 138: 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101110101 test 189: 101110111 test 190: 101111001 test 191: 101111011 test 192: 101111101 test 193: 101111111 test 194: 110000001 test 195: 110000011 test 196: 110000101 test 197: 110000111 test 198: 110001001 test 199: 110001011 test 200: 110001101 test 201: 110001111 test 202: 110010001 test 203: 110010011 test 204: 110010101 test 205: 110010111 test 206: 110011001 test 207: 110011011 test 208: 110011101 test 209: 110011111 test 210: 110100001 test 211: 110100011 test 212: 110100101 test 213: 110100111 test 214: 110101001 test 215: 110101011 test 216: 110101101 test 217: 110101111 test 218: 110110001 test 219: 110110011 test 220: 110110101 test 221: 110110111 test 222: 110111001 test 223: 110111011 test 224: 110111101 test 225: 110111111 test 226: 111000001 test 227: 111000011 test 228: 111000101 test 229: 111000111 test 230: 111001001 test 231: 111001011 test 232: 111001101 test 233: 111001111 test 234: 111010001 test 235: 111010011 test 236: 111010101 test 237: 111010111 test 238: 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001000001 test 1320: 001000011 test 1321: 001000101 test 1322: 001000111 test 1323: 001001001 test 1324: 001001011 test 1325: 001001101 test 1326: 001001111 test 1327: 001010001 test 1328: 001010011 test 1329: 001010101 test 1330: 001010111 test 1331: 001011001 test 1332: 001011011 test 1333: 001011101 test 1334: 001011111 test 1335: 001100001 test 1336: 001100011 test 1337: 001100101 test 1338: 001100111 test 1339: 001101001 test 1340: 001101011 test 1341: 001101101 test 1342: 001101111 test 1343: 001110001 test 1344: 001110011 test 1345: 001110101 test 1346: 001110111 test 1347: 001111001 test 1348: 001111011 test 1349: 001111101 test 1350: 001111111 test 1351: 010000001 test 1352: 010000011 test 1353: 010000101 test 1354: 010000111 test 1355: 010001001 test 1356: 010001011 test 1357: 010001101 test 1358: 010001111 test 1359: 010010001 test 1360: 010010011 test 1361: 010010101 test 1362: 010010111 test 1363: 010011001 test 1364: 010011011 test 1365: 010011101 test 1366: 010011111 test 1367: 010100001 test 1368: 010100011 test 1369: 010100101 test 1370: 010100111 test 1371: 010101001 test 1372: 010101011 test 1373: 010101101 test 1374: 010101111 test 1375: 010110001 test 1376: 010110011 test 1377: 010110101 test 1378: 010110111 test 1379: 010111001 test 1380: 010111011 test 1381: 010111101 test 1382: 010111111 test 1383: 011000001 test 1384: 011000011 test 1385: 011000101 test 1386: 011000111 test 1387: 011001001 test 1388: 011001011 test 1389: 011001101 test 1390: 011001111 test 1391: 011010001 test 1392: 011010011 test 1393: 011010101 test 1394: 011010111 test 1395: 011011001 test 1396: 011011011 test 1397: 011011101 test 1398: 011011111 test 1399: 011100001 test 1400: 011100011 test 1401: 011100101 test 1402: 011100111 test 1403: 011101001 test 1404: 011101011 test 1405: 011101101 test 1406: 011101111 test 1407: 011110001 test 1408: 011110011 test 1409: 011110101 test 1410: 011110111 test 1411: 011111001 test 1412: 011111011 test 1413: 011111101 test 1414: 011111111 test 1415: 100000001 test 1416: 100000011 test 1417: 100000101 test 1418: 100000111 test 1419: 100001001 test 1420: 100001011 test 1421: 100001101 test 1422: 100001111 test 1423: 100010001 test 1424: 100010011 test 1425: 100010101 test 1426: 100010111 test 1427: 100011001 test 1428: 100011011 test 1429: 100011101 test 1430: 100011111 test 1431: 100100001 test 1432: 100100011 test 1433: 100100101 test 1434: 100100111 test 1435: 100101001 test 1436: 100101011 test 1437: 100101101 test 1438: 100101111 test 1439: 100110001 test 1440: 100110011 test 1441: 100110101 test 1442: 100110111 test 1443: 100111001 test 1444: 100111011 test 1445: 100111101 test 1446: 100111111 test 1447: 101000001 test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 0x0005 0x0010 0x0002 0x0000 0x0000 5: 0x0007 0x0010 0x0002 0x0000 0x0000 6: 0x0009 0x0010 0x0002 0x0000 0x0000 7: 0x000B 0x0010 0x0002 0x0000 0x0000 8: 0x000D 0x0010 0x0002 0x0000 0x0000 9: 0x000F 0x0010 0x0002 0x0000 0x0000 10: 0x0011 0x0010 0x0002 0x0000 0x0000 11: 0x0013 0x0010 0x0002 0x0000 0x0000 12: 0x0015 0x0010 0x0002 0x0000 0x0000 13: 0x0017 0x0010 0x0002 0x0000 0x0000 14: 0x0019 0x0010 0x0002 0x0000 0x0000 15: 0x001B 0x0010 0x0002 0x0000 0x0000 16: 0x001D 0x0010 0x0002 0x0000 0x0000 17: 0x001F 0x0010 0x0002 0x0000 0x0000 18: 0x1001 0x0010 0x0002 0x0000 0x0000 19: 0x1003 0x0010 0x0002 0x0000 0x0000 20: 0x1005 0x0010 0x0002 0x0000 0x0000 21: 0x1007 0x0010 0x0002 0x0000 0x0000 22: 0x1009 0x0010 0x0002 0x0000 0x0000 23: 0x100B 0x0010 0x0002 0x0000 0x0000 24: 0x100D 0x0010 0x0002 0x0000 0x0000 25: 0x100F 0x0010 0x0002 0x0000 0x0000 26: 0x1011 0x0010 0x0002 0x0000 0x0000 27: 0x1013 0x0010 0x0002 0x0000 0x0000 28: 0x1015 0x0010 0x0002 0x0000 0x0000 29: 0x1017 0x0010 0x0002 0x0000 0x0000 30: 0x1019 0x0010 0x0002 0x0000 0x0000 31: 0x101B 0x0010 0x0002 0x0000 0x0000 32: 0x101D 0x0010 0x0002 0x0000 0x0000 33: 0x101F 0x0010 0x0002 0x0000 0x0000 34: 0x2001 0x0010 0x0002 0x0000 0x0000 35: 0x2003 0x0010 0x0002 0x0000 0x0000 36: 0x2005 0x0010 0x0002 0x0000 0x0000 37: 0x2007 0x0010 0x0002 0x0000 0x0000 38: 0x2009 0x0010 0x0002 0x0000 0x0000 39: 0x200B 0x0010 0x0002 0x0000 0x0000 40: 0x200D 0x0010 0x0002 0x0000 0x0000 41: 0x200F 0x0010 0x0002 0x0000 0x0000 42: 0x2011 0x0010 0x0002 0x0000 0x0000 43: 0x2013 0x0010 0x0002 0x0000 0x0000 44: 0x2015 0x0010 0x0002 0x0000 0x0000 45: 0x2017 0x0010 0x0002 0x0000 0x0000 46: 0x2019 0x0010 0x0002 0x0000 0x0000 47: 0x201B 0x0010 0x0002 0x0000 0x0000 48: 0x201D 0x0010 0x0002 0x0000 0x0000 49: 0x201F 0x0010 0x0002 0x0000 0x0000 50: 0x3001 0x0010 0x0002 0x0000 0x0000 51: 0x3003 0x0010 0x0002 0x0000 0x0000 52: 0x3005 0x0010 0x0002 0x0000 0x0000 53: 0x3007 0x0010 0x0002 0x0000 0x0000 54: 0x3009 0x0010 0x0002 0x0000 0x0000 55: 0x300B 0x0010 0x0002 0x0000 0x0000 56: 0x300D 0x0010 0x0002 0x0000 0x0000 57: 0x300F 0x0010 0x0002 0x0000 0x0000 58: 0x3011 0x0010 0x0002 0x0000 0x0000 59: 0x3013 0x0010 0x0002 0x0000 0x0000 60: 0x3015 0x0010 0x0002 0x0000 0x0000 61: 0x3017 0x0010 0x0002 0x0000 0x0000 62: 0x3019 0x0010 0x0002 0x0000 0x0000 63: 0x301B 0x0010 0x0002 0x0000 0x0000 64: 0x301D 0x0010 0x0002 0x0000 0x0000 65: 0x301F 0x0010 0x0002 0x0000 0x0000 66: 0x4001 0x0010 0x0002 0x0000 0x0000 67: 0x4003 0x0010 0x0002 0x0000 0x0000 68: 0x4005 0x0010 0x0002 0x0000 0x0000 69: 0x4007 0x0010 0x0002 0x0000 0x0000 70: 0x4009 0x0010 0x0002 0x0000 0x0000 71: 0x400B 0x0010 0x0002 0x0000 0x0000 72: 0x400D 0x0010 0x0002 0x0000 0x0000 73: 0x400F 0x0010 0x0002 0x0000 0x0000 74: 0x4011 0x0010 0x0002 0x0000 0x0000 75: 0x4013 0x0010 0x0002 0x0000 0x0000 76: 0x4015 0x0010 0x0002 0x0000 0x0000 77: 0x4017 0x0010 0x0002 0x0000 0x0000 78: 0x4019 0x0010 0x0002 0x0000 0x0000 79: 0x401B 0x0010 0x0002 0x0000 0x0000 80: 0x401D 0x0010 0x0002 0x0000 0x0000 81: 0x401F 0x0010 0x0002 0x0000 0x0000 82: 0x5001 0x0010 0x0002 0x0000 0x0000 83: 0x5003 0x0010 0x0002 0x0000 0x0000 84: 0x5005 0x0010 0x0002 0x0000 0x0000 85: 0x5007 0x0010 0x0002 0x0000 0x0000 86: 0x5009 0x0010 0x0002 0x0000 0x0000 87: 0x500B 0x0010 0x0002 0x0000 0x0000 88: 0x500D 0x0010 0x0002 0x0000 0x0000 89: 0x500F 0x0010 0x0002 0x0000 0x0000 90: 0x5011 0x0010 0x0002 0x0000 0x0000 91: 0x5013 0x0010 0x0002 0x0000 0x0000 92: 0x5015 0x0010 0x0002 0x0000 0x0000 93: 0x5017 0x0010 0x0002 0x0000 0x0000 94: 0x5019 0x0010 0x0002 0x0000 0x0000 95: 0x501B 0x0010 0x0002 0x0000 0x0000 96: 0x501D 0x0010 0x0002 0x0000 0x0000 97: 0x501F 0x0010 0x0002 0x0000 0x0000 98: 0x6001 0x0010 0x0002 0x0000 0x0000 99: 0x6003 0x0010 0x0002 0x0000 0x0000 100: 0x6005 0x0010 0x0002 0x0000 0x0000 101: 0x6007 0x0010 0x0002 0x0000 0x0000 102: 0x6009 0x0010 0x0002 0x0000 0x0000 103: 0x600B 0x0010 0x0002 0x0000 0x0000 104: 0x600D 0x0010 0x0002 0x0000 0x0000 105: 0x600F 0x0010 0x0002 0x0000 0x0000 106: 0x6011 0x0010 0x0002 0x0000 0x0000 107: 0x6013 0x0010 0x0002 0x0000 0x0000 108: 0x6015 0x0010 0x0002 0x0000 0x0000 109: 0x6017 0x0010 0x0002 0x0000 0x0000 110: 0x6019 0x0010 0x0002 0x0000 0x0000 111: 0x601B 0x0010 0x0002 0x0000 0x0000 112: 0x601D 0x0010 0x0002 0x0000 0x0000 113: 0x601F 0x0010 0x0002 0x0000 0x0000 114: 0x7001 0x0010 0x0002 0x0000 0x0000 115: 0x7003 0x0010 0x0002 0x0000 0x0000 116: 0x7005 0x0010 0x0002 0x0000 0x0000 117: 0x7007 0x0010 0x0002 0x0000 0x0000 118: 0x7009 0x0010 0x0002 0x0000 0x0000 119: 0x700B 0x0010 0x0002 0x0000 0x0000 120: 0x700D 0x0010 0x0002 0x0000 0x0000 121: 0x700F 0x0010 0x0002 0x0000 0x0000 122: 0x7011 0x0010 0x0002 0x0000 0x0000 123: 0x7013 0x0010 0x0002 0x0000 0x0000 124: 0x7015 0x0010 0x0002 0x0000 0x0000 125: 0x7017 0x0010 0x0002 0x0000 0x0000 126: 0x7019 0x0010 0x0002 0x0000 0x0000 127: 0x701B 0x0010 0x0002 0x0000 0x0000 128: 0x701D 0x0010 0x0002 0x0000 0x0000 129: 0x701F 0x0010 0x0002 0x0000 0x0000 130: 0x8001 0x0010 0x0002 0x0000 0x0000 131: 0x8003 0x0010 0x0002 0x0000 0x0000 132: 0x8005 0x0010 0x0002 0x0000 0x0000 133: 0x8007 0x0010 0x0002 0x0000 0x0000 134: 0x8009 0x0010 0x0002 0x0000 0x0000 135: 0x800B 0x0010 0x0002 0x0000 0x0000 136: 0x800D 0x0010 0x0002 0x0000 0x0000 137: 0x800F 0x0010 0x0002 0x0000 0x0000 138: 0x8011 0x0010 0x0002 0x0000 0x0000 139: 0x8013 0x0010 0x0002 0x0000 0x0000 140: 0x8015 0x0010 0x0002 0x0000 0x0000 141: 0x8017 0x0010 0x0002 0x0000 0x0000 142: 0x8019 0x0010 0x0002 0x0000 0x0000 143: 0x801B 0x0010 0x0002 0x0000 0x0000 144: 0x801D 0x0010 0x0002 0x0000 0x0000 145: 0x801F 0x0010 0x0002 0x0000 0x0000 146: 0x9001 0x0010 0x0002 0x0000 0x0000 147: 0x9003 0x0010 0x0002 0x0000 0x0000 148: 0x9005 0x0010 0x0002 0x0000 0x0000 149: 0x9007 0x0010 0x0002 0x0000 0x0000 150: 0x9009 0x0010 0x0002 0x0000 0x0000 151: 0x900B 0x0010 0x0002 0x0000 0x0000 152: 0x900D 0x0010 0x0002 0x0000 0x0000 153: 0x900F 0x0010 0x0002 0x0000 0x0000 154: 0x9011 0x0010 0x0002 0x0000 0x0000 155: 0x9013 0x0010 0x0002 0x0000 0x0000 156: 0x9015 0x0010 0x0002 0x0000 0x0000 157: 0x9017 0x0010 0x0002 0x0000 0x0000 158: 0x9019 0x0010 0x0002 0x0000 0x0000 159: 0x901B 0x0010 0x0002 0x0000 0x0000 160: 0x901D 0x0010 0x0002 0x0000 0x0000 161: 0x901F 0x0010 0x0002 0x0000 0x0000 162: 0xA001 0x0010 0x0002 0x0000 0x0000 163: 0xA003 0x0010 0x0002 0x0000 0x0000 164: 0xA005 0x0010 0x0002 0x0000 0x0000 165: 0xA007 0x0010 0x0002 0x0000 0x0000 166: 0xA009 0x0010 0x0002 0x0000 0x0000 167: 0xA00B 0x0010 0x0002 0x0000 0x0000 168: 0xA00D 0x0010 0x0002 0x0000 0x0000 169: 0xA00F 0x0010 0x0002 0x0000 0x0000 170: 0xA011 0x0010 0x0002 0x0000 0x0000 171: 0xA013 0x0010 0x0002 0x0000 0x0000 172: 0xA015 0x0010 0x0002 0x0000 0x0000 173: 0xA017 0x0010 0x0002 0x0000 0x0000 174: 0xA019 0x0010 0x0002 0x0000 0x0000 175: 0xA01B 0x0010 0x0002 0x0000 0x0000 176: 0xA01D 0x0010 0x0002 0x0000 0x0000 177: 0xA01F 0x0010 0x0002 0x0000 0x0000 178: 0xB001 0x0010 0x0002 0x0000 0x0000 179: 0xB003 0x0010 0x0002 0x0000 0x0000 180: 0xB005 0x0010 0x0002 0x0000 0x0000 181: 0xB007 0x0010 0x0002 0x0000 0x0000 182: 0xB009 0x0010 0x0002 0x0000 0x0000 183: 0xB00B 0x0010 0x0002 0x0000 0x0000 184: 0xB00D 0x0010 0x0002 0x0000 0x0000 185: 0xB00F 0x0010 0x0002 0x0000 0x0000 186: 0xB011 0x0010 0x0002 0x0000 0x0000 187: 0xB013 0x0010 0x0002 0x0000 0x0000 188: 0xB015 0x0010 0x0002 0x0000 0x0000 189: 0xB017 0x0010 0x0002 0x0000 0x0000 190: 0xB019 0x0010 0x0002 0x0000 0x0000 191: 0xB01B 0x0010 0x0002 0x0000 0x0000 192: 0xB01D 0x0010 0x0002 0x0000 0x0000 193: 0xB01F 0x0010 0x0002 0x0000 0x0000 194: 0xC001 0x0010 0x0002 0x0000 0x0000 195: 0xC003 0x0010 0x0002 0x0000 0x0000 196: 0xC005 0x0010 0x0002 0x0000 0x0000 197: 0xC007 0x0010 0x0002 0x0000 0x0000 198: 0xC009 0x0010 0x0002 0x0000 0x0000 199: 0xC00B 0x0010 0x0002 0x0000 0x0000 200: 0xC00D 0x0010 0x0002 0x0000 0x0000 201: 0xC00F 0x0010 0x0002 0x0000 0x0000 202: 0xC011 0x0010 0x0002 0x0000 0x0000 203: 0xC013 0x0010 0x0002 0x0000 0x0000 204: 0xC015 0x0010 0x0002 0x0000 0x0000 205: 0xC017 0x0010 0x0002 0x0000 0x0000 206: 0xC019 0x0010 0x0002 0x0000 0x0000 207: 0xC01B 0x0010 0x0002 0x0000 0x0000 208: 0xC01D 0x0010 0x0002 0x0000 0x0000 209: 0xC01F 0x0010 0x0002 0x0000 0x0000 210: 0xD001 0x0010 0x0002 0x0000 0x0000 211: 0xD003 0x0010 0x0002 0x0000 0x0000 212: 0xD005 0x0010 0x0002 0x0000 0x0000 213: 0xD007 0x0010 0x0002 0x0000 0x0000 214: 0xD009 0x0010 0x0002 0x0000 0x0000 215: 0xD00B 0x0010 0x0002 0x0000 0x0000 216: 0xD00D 0x0010 0x0002 0x0000 0x0000 217: 0xD00F 0x0010 0x0002 0x0000 0x0000 218: 0xD011 0x0010 0x0002 0x0000 0x0000 219: 0xD013 0x0010 0x0002 0x0000 0x0000 220: 0xD015 0x0010 0x0002 0x0000 0x0000 221: 0xD017 0x0010 0x0002 0x0000 0x0000 222: 0xD019 0x0010 0x0002 0x0000 0x0000 223: 0xD01B 0x0010 0x0002 0x0000 0x0000 224: 0xD01D 0x0010 0x0002 0x0000 0x0000 225: 0xD01F 0x0010 0x0002 0x0000 0x0000 226: 0xE001 0x0010 0x0002 0x0000 0x0000 227: 0xE003 0x0010 0x0002 0x0000 0x0000 228: 0xE005 0x0010 0x0002 0x0000 0x0000 229: 0xE007 0x0010 0x0002 0x0000 0x0000 230: 0xE009 0x0010 0x0002 0x0000 0x0000 231: 0xE00B 0x0010 0x0002 0x0000 0x0000 232: 0xE00D 0x0010 0x0002 0x0000 0x0000 233: 0xE00F 0x0010 0x0002 0x0000 0x0000 234: 0xE011 0x0010 0x0002 0x0000 0x0000 235: 0xE013 0x0010 0x0002 0x0000 0x0000 236: 0xE015 0x0010 0x0002 0x0000 0x0000 237: 0xE017 0x0010 0x0002 0x0000 0x0000 238: 0xE019 0x0010 0x0002 0x0000 0x0000 239: 0xE01B 0x0010 0x0002 0x0000 0x0000 240: 0xE01D 0x0010 0x0002 0x0000 0x0000 241: 0xE01F 0x0010 0x0002 0x0000 0x0000 242: 0xF001 0x0010 0x0002 0x0000 0x0000 243: 0xF003 0x0010 0x0002 0x0000 0x0000 244: 0xF005 0x0010 0x0002 0x0000 0x0000 245: 0xF007 0x0010 0x0002 0x0000 0x0000 246: 0xF009 0x0010 0x0002 0x0000 0x0000 247: 0xF00B 0x0010 0x0002 0x0000 0x0000 248: 0xF00D 0x0010 0x0002 0x0000 0x0000 249: 0xF00F 0x0010 0x0002 0x0000 0x0000 250: 0xF011 0x0010 0x0002 0x0000 0x0000 251: 0xF013 0x0010 0x0002 0x0000 0x0000 252: 0xF015 0x0010 0x0002 0x0000 0x0000 253: 0xF017 0x0010 0x0002 0x0000 0x0000 254: 0xF019 0x0010 0x0002 0x0000 0x0000 255: 0xF01B 0x0010 0x0002 0x0000 0x0000 256: 0xF01D 0x0010 0x0002 0x0000 0x0000 257: 0xF01E 0x0010 0x0002 0x0000 0x0000 258: 0x0001 0x0010 0x0002 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0x94CF 0x0002 0x0000 0x0000 1374: 0xF71E 0x94CF 0x0003 0x0000 0x0000 1375: 0xF71E 0x942F 0x0002 0x0000 0x0000 1376: 0xF71E 0x942F 0x0003 0x0000 0x0000 1377: 0xF71E 0x94AF 0x0002 0x0000 0x0000 1378: 0xF71E 0x94AF 0x0003 0x0000 0x0000 1379: 0xF71E 0x946F 0x0002 0x0000 0x0000 1380: 0xF71E 0x946F 0x0003 0x0000 0x0000 1381: 0xF71E 0x94EF 0x0002 0x0000 0x0000 1382: 0xF71E 0x94EF 0x0003 0x0000 0x0000 1383: 0xF71E 0x980F 0x0002 0x0000 0x0000 1384: 0xF71E 0x980F 0x0003 0x0000 0x0000 1385: 0xF71E 0x988F 0x0002 0x0000 0x0000 1386: 0xF71E 0x988F 0x0003 0x0000 0x0000 1387: 0xF71E 0x984F 0x0002 0x0000 0x0000 1388: 0xF71E 0x984F 0x0003 0x0000 0x0000 1389: 0xF71E 0x98CF 0x0002 0x0000 0x0000 1390: 0xF71E 0x98CF 0x0003 0x0000 0x0000 1391: 0xF71E 0x982F 0x0002 0x0000 0x0000 1392: 0xF71E 0x982F 0x0003 0x0000 0x0000 1393: 0xF71E 0x98AF 0x0002 0x0000 0x0000 1394: 0xF71E 0x98AF 0x0003 0x0000 0x0000 1395: 0xF71E 0x986F 0x0002 0x0000 0x0000 1396: 0xF71E 0x986F 0x0003 0x0000 0x0000 1397: 0xF71E 0x98EF 0x0002 0x0000 0x0000 1398: 0xF71E 0x98EF 0x0003 0x0000 0x0000 1399: 0xF71E 0x9C0F 0x0002 0x0000 0x0000 1400: 0xF71E 0x9C0F 0x0003 0x0000 0x0000 1401: 0xF71E 0x9C8F 0x0002 0x0000 0x0000 1402: 0xF71E 0x9C8F 0x0003 0x0000 0x0000 1403: 0xF71E 0x9C4F 0x0002 0x0000 0x0000 1404: 0xF71E 0x9C4F 0x0003 0x0000 0x0000 1405: 0xF71E 0x9CCF 0x0002 0x0000 0x0000 1406: 0xF71E 0x9CCF 0x0003 0x0000 0x0000 1407: 0xF71E 0x9C2F 0x0002 0x0000 0x0000 1408: 0xF71E 0x9C2F 0x0003 0x0000 0x0000 1409: 0xF71E 0x9CAF 0x0002 0x0000 0x0000 1410: 0xF71E 0x9CAF 0x0003 0x0000 0x0000 1411: 0xF71E 0x9C6F 0x0002 0x0000 0x0000 1412: 0xF71E 0x9C6F 0x0003 0x0000 0x0000 1413: 0xF71E 0x9CEF 0x0002 0x0000 0x0000 1414: 0xF71E 0x9CEF 0x0003 0x0000 0x0000 1415: 0xF71E 0xA00F 0x0002 0x0000 0x0000 1416: 0xF71E 0xA00F 0x0003 0x0000 0x0000 1417: 0xF71E 0xA08F 0x0002 0x0000 0x0000 1418: 0xF71E 0xA08F 0x0003 0x0000 0x0000 1419: 0xF71E 0xA04F 0x0002 0x0000 0x0000 1420: 0xF71E 0xA04F 0x0003 0x0000 0x0000 1421: 0xF71E 0xA0CF 0x0002 0x0000 0x0000 1422: 0xF71E 0xA0CF 0x0003 0x0000 0x0000 1423: 0xF71E 0xA02F 0x0002 0x0000 0x0000 1424: 0xF71E 0xA02F 0x0003 0x0000 0x0000 1425: 0xF71E 0xA0AF 0x0002 0x0000 0x0000 1426: 0xF71E 0xA0AF 0x0003 0x0000 0x0000 1427: 0xF71E 0xA06F 0x0002 0x0000 0x0000 1428: 0xF71E 0xA06F 0x0003 0x0000 0x0000 1429: 0xF71E 0xA0EF 0x0002 0x0000 0x0000 1430: 0xF71E 0xA0EF 0x0003 0x0000 0x0000 1431: 0xF71E 0xA40F 0x0002 0x0000 0x0000 1432: 0xF71E 0xA40F 0x0003 0x0000 0x0000 1433: 0xF71E 0xA48F 0x0002 0x0000 0x0000 1434: 0xF71E 0xA48F 0x0003 0x0000 0x0000 1435: 0xF71E 0xA44F 0x0002 0x0000 0x0000 1436: 0xF71E 0xA44F 0x0003 0x0000 0x0000 1437: 0xF71E 0xA4CF 0x0002 0x0000 0x0000 1438: 0xF71E 0xA4CF 0x0003 0x0000 0x0000 1439: 0xF71E 0xA42F 0x0002 0x0000 0x0000 1440: 0xF71E 0xA42F 0x0003 0x0000 0x0000 1441: 0xF71E 0xA4AF 0x0002 0x0000 0x0000 1442: 0xF71E 0xA4AF 0x0003 0x0000 0x0000 1443: 0xF71E 0xA46F 0x0002 0x0000 0x0000 1444: 0xF71E 0xA46F 0x0003 0x0000 0x0000 1445: 0xF71E 0xA4EF 0x0002 0x0000 0x0000 1446: 0xF71E 0xA4EF 0x0003 0x0000 0x0000 1447: 0xF71E 0xA80F 0x0002 0x0000 0x0000 1448: 0xF71E 0xA80F 0x0003 0x0000 0x0000 1449: 0xF71E 0xA88F 0x0002 0x0000 0x0000 1450: 0xF71E 0xA88F 0x0003 0x0000 0x0000 1451: 0xF71E 0xA84F 0x0002 0x0000 0x0000 1452: 0xF71E 0xA84F 0x0003 0x0000 0x0000 1453: 0xF71E 0xA8CF 0x0002 0x0000 0x0000 1454: 0xF71E 0xA8CF 0x0003 0x0000 0x0000 1455: 0xF71E 0xA82F 0x0002 0x0000 0x0000 1456: 0xF71E 0xA82F 0x0003 0x0000 0x0000 1457: 0xF71E 0xA8AF 0x0002 0x0000 0x0000 1458: 0xF71E 0xA8AF 0x0003 0x0000 0x0000 1459: 0xF71E 0xA86F 0x0002 0x0000 0x0000 1460: 0xF71E 0xA86F 0x0003 0x0000 0x0000 1461: 0xF71E 0xA8EF 0x0002 0x0000 0x0000 1462: 0xF71E 0xA8EF 0x0003 0x0000 0x0000 1463: 0xF71E 0xAC0F 0x0002 0x0000 0x0000 1464: 0xF71E 0xAC0F 0x0003 0x0000 0x0000 1465: 0xF71E 0xAC8F 0x0002 0x0000 0x0000 1466: 0xF71E 0xAC8F 0x0003 0x0000 0x0000 1467: 0xF71E 0xAC4F 0x0002 0x0000 0x0000 1468: 0xF71E 0xAC4F 0x0003 0x0000 0x0000 1469: 0xF71E 0xACCF 0x0002 0x0000 0x0000 1470: 0xF71E 0xACCF 0x0003 0x0000 0x0000 1471: 0xF71E 0xAC2F 0x0002 0x0000 0x0000 1472: 0xF71E 0xAC2F 0x0003 0x0000 0x0000 1473: 0xF71E 0xACAF 0x0002 0x0000 0x0000 1474: 0xF71E 0xACAF 0x0003 0x0000 0x0000 1475: 0xF71E 0xAC6F 0x0002 0x0000 0x0000 1476: 0xF71E 0xAC6F 0x0003 0x0000 0x0000 1477: 0xF71E 0xACEF 0x0002 0x0000 0x0000 1478: 0xF71E 0xACEF 0x0003 0x0000 0x0000 1479: 0xF71E 0xB00F 0x0002 0x0000 0x0000 1480: 0xF71E 0xB00F 0x0003 0x0000 0x0000 1481: 0xF71E 0xB08F 0x0002 0x0000 0x0000 1482: 0xF71E 0xB08F 0x0003 0x0000 0x0000 1483: 0xF71E 0xB04F 0x0002 0x0000 0x0000 1484: 0xF71E 0xB04F 0x0003 0x0000 0x0000 1485: 0xF71E 0xB0CF 0x0002 0x0000 0x0000 1486: 0xF71E 0xB0CF 0x0003 0x0000 0x0000 1487: 0xF71E 0xB02F 0x0002 0x0000 0x0000 1488: 0xF71E 0xB02F 0x0003 0x0000 0x0000 1489: 0xF71E 0xB0AF 0x0002 0x0000 0x0000 1490: 0xF71E 0xB0AF 0x0003 0x0000 0x0000 1491: 0xF71E 0xB06F 0x0002 0x0000 0x0000 1492: 0xF71E 0xB06F 0x0003 0x0000 0x0000 1493: 0xF71E 0xB0EF 0x0002 0x0000 0x0000 1494: 0xF71E 0xB0EF 0x0003 0x0000 0x0000 1495: 0xF71E 0xB40F 0x0002 0x0000 0x0000 1496: 0xF71E 0xB40F 0x0003 0x0000 0x0000 1497: 0xF71E 0xB48F 0x0002 0x0000 0x0000 1498: 0xF71E 0xB48F 0x0003 0x0000 0x0000 1499: 0xF71E 0xB44F 0x0002 0x0000 0x0000 1500: 0xF71E 0xB44F 0x0003 0x0000 0x0000 1501: 0xF71E 0xB4CF 0x0002 0x0000 0x0000 1502: 0xF71E 0xB4CF 0x0003 0x0000 0x0000 1503: 0xF71E 0xB42F 0x0002 0x0000 0x0000 1504: 0xF71E 0xB42F 0x0003 0x0000 0x0000 1505: 0xF71E 0xB4AF 0x0002 0x0000 0x0000 1506: 0xF71E 0xB4AF 0x0003 0x0000 0x0000 1507: 0xF71E 0xB46F 0x0002 0x0000 0x0000 1508: 0xF71E 0xB46F 0x0003 0x0000 0x0000 1509: 0xF71E 0xB4EF 0x0002 0x0000 0x0000 1510: 0xF71E 0xB4EF 0x0003 0x0000 0x0000 1511: 0xF71E 0xB80F 0x0002 0x0000 0x0000 1512: 0xF71E 0xB80F 0x0003 0x0000 0x0000 1513: 0xF71E 0xB88F 0x0002 0x0000 0x0000 1514: 0xF71E 0xB88F 0x0003 0x0000 0x0000 1515: 0xF71E 0xB84F 0x0002 0x0000 0x0000 1516: 0xF71E 0xB84F 0x0003 0x0000 0x0000 1517: 0xF71E 0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 3 pins used: 27 not used: 39 1543 'test steps' 1576 lines M119 REV B 3 8-input NAND PINS Main menu Fri Jun 30 15:59:38 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 15:59:39 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 7 Main menu Fri Jun 30 15:59:47 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:00:00 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:00:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 47 Main menu Fri Jun 30 16:00:04 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m161.tst reading test file: tests\m161.tst comment: ; M161 PCB REV C SCHEMATIC REV B BINARY TO OCAL/DECIMAL DECODER comment: ; comment: ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES). comment: ; comment: ; ALL 3 ENABLES MUST BE HIGH TO ENABLE OUTPUTS comment: comment: pins: PINS pins: 1 I AS2 E8-2,E8-12 EN_1 ENABLE 1 (HI TO ENABLE) pins: 2 I AS1 E8-4,E8-10 EN_2 ENABLE 2 (HI TO ENABLE) pins: 3 I AT2 E8-5,E8-9 EN_3 ENABLE 3 (HI TO ENABLE) pins: 4 I AU1 E9-2 A8 pins: 5 I AV2 E9-9 A4 pins: 6 I AU2 E9-12 A2 pins: 7 I AV1 E9-5 A1 pins: 8 O AR2 E10-8 OUT9 pins: 9 O AR1 E7-8 OUT9-N pins: 10 O AP2 E10-11 OUT8 pins: 11 O AP1 E7-6 OUT8-N pins: 12 O AL2 E5-8 OUT7 pins: 13 O AL1 E4-6 OUT7-N pins: 14 O AH2 E1-3 OUT6 pins: 15 O AH1 E4-8 OUT6-N pins: 16 O AM2 E5-6 OUT5 pins: 17 O AM1 E3-6 OUT5-N pins: 18 O AF2 E1-6 OUT4 pins: 19 O AF1 E3-8 OUT4-N pins: 20 O AN2 E5-3 OUT3 pins: 21 O AN1 E6-6 OUT3-N pins: 22 O AJ2 E5-11 OUT2 pins: 23 O AJ1 E6-8 OUT2-N pins: 24 O AE2 E1-8 OUT1 pins: 25 O AE1 E2-6 OUT1-N pins: 26 O AD2 E1-11 OUT0 pins: 27 O AD1 E2-8 OUT0-N pins: direction: IIIIIIIOOOOOOOOOOOOOOOOOOOO test 1: 000000001010101010101010101 comment: test 2: 0000000 test 3: 0000001 test 4: 0000010 test 5: 0000011 test 6: 0000100 test 7: 0000101 test 8: 0000110 test 9: 0000111 test 10: 0001000 test 11: 0001001 test 12: 0001010 test 13: 0001011 test 14: 0001100 test 15: 0001101 test 16: 0001110 test 17: 0001111 comment: test 18: 0010000 test 19: 0010001 test 20: 0010010 test 21: 0010011 test 22: 0010100 test 23: 0010101 test 24: 0010110 test 25: 0010111 test 26: 0011000 test 27: 0011001 test 28: 0011010 test 29: 0011011 test 30: 0011100 test 31: 0011101 test 32: 0011110 test 33: 0011111 comment: test 34: 0100000 test 35: 0100001 test 36: 0100010 test 37: 0100011 test 38: 0100100 test 39: 0100101 test 40: 0100110 test 41: 0100111 test 42: 0101000 test 43: 0101001 test 44: 0101010 test 45: 0101011 test 46: 0101100 test 47: 0101101 test 48: 0101110 test 49: 0101111 comment: test 50: 0110000 test 51: 0110001 test 52: 0110010 test 53: 0110011 test 54: 0110100 test 55: 0110101 test 56: 0110110 test 57: 0110111 test 58: 0111000 test 59: 0111001 test 60: 0111010 test 61: 0111011 test 62: 0111100 test 63: 0111101 test 64: 0111110 test 65: 0111111 comment: test 66: 1000000 test 67: 1000001 test 68: 1000010 test 69: 1000011 test 70: 1000100 test 71: 1000101 test 72: 1000110 test 73: 1000111 test 74: 1001000 test 75: 1001001 test 76: 1001010 test 77: 1001011 test 78: 1001100 test 79: 1001101 test 80: 1001110 test 81: 1001111 comment: test 82: 1010000 test 83: 1010001 test 84: 1010010 test 85: 1010011 test 86: 1010100 test 87: 1010101 test 88: 1010110 test 89: 1010111 test 90: 1011000 test 91: 1011001 test 92: 1011010 test 93: 1011011 test 94: 1011100 test 95: 1011101 test 96: 1011110 test 97: 1011111 comment: test 98: 1100000 test 99: 1100001 test 100: 1100010 test 101: 1100011 test 102: 1100100 test 103: 1100101 test 104: 1100110 test 105: 1100111 test 106: 1101000 test 107: 1101001 test 108: 1101010 test 109: 1101011 test 110: 1101100 test 111: 1101101 test 112: 1101110 test 113: 1101111 comment: test 114: 111000001010101010101010110 test 115: 111000101010101010101011001 test 116: 111001001010101010101100101 test 117: 111001101010101010110010101 test 118: 111010001010101011001010101 test 119: 111010101010101100101010101 test 120: 111011001010110010101010101 test 121: 111011101011001010101010101 test 122: 111100001100101010101010101 test 123: 111100110010101010101010101 test 124: 111101001100101010101010101 test 125: 111101110010101010101010101 test 126: 111110001100101010101010101 test 127: 111110110010101010101010101 test 128: 111111001100101010101010101 test 129: 111111110010101010101010101 comment: test 130: 000000001010101010101010101 end: END summary column 1: offset 1, mask 0x0040 column 2: offset 1, mask 0x0200 column 3: offset 1, mask 0x0080 column 4: offset 2, mask 0x8000 column 5: offset 2, mask 0x0002 column 6: offset 2, mask 0x0001 column 7: offset 2, mask 0x4000 column 8: offset 1, mask 0x0020 column 9: offset 1, mask 0x0400 column 10: offset 1, mask 0x0010 column 11: offset 1, mask 0x0800 column 12: offset 1, mask 0x0002 column 13: offset 1, mask 0x4000 column 14: offset 0, mask 0x0002 column 15: offset 0, mask 0x0200 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x2000 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0400 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x1000 column 22: offset 0, mask 0x0001 column 23: offset 0, mask 0x0100 column 24: offset 0, mask 0x0008 column 25: offset 0, mask 0x0800 column 26: offset 0, mask 0x0010 column 27: offset 0, mask 0x1000 direction bits (1=input) 0xFFFF 0xFD3F 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1F00 0x7C00 0x0000 0x0000 0x0000 2: 0x1F00 0x7C00 0x0000 0x0000 0x0000 3: 0x1F00 0x7C00 0x4000 0x0000 0x0000 4: 0x1F00 0x7C00 0x0001 0x0000 0x0000 5: 0x1F00 0x7C00 0x4001 0x0000 0x0000 6: 0x1F00 0x7C00 0x0002 0x0000 0x0000 7: 0x1F00 0x7C00 0x4002 0x0000 0x0000 8: 0x1F00 0x7C00 0x0003 0x0000 0x0000 9: 0x1F00 0x7C00 0x4003 0x0000 0x0000 10: 0x1F00 0x7C00 0x8000 0x0000 0x0000 11: 0x1F00 0x7C00 0xC000 0x0000 0x0000 12: 0x1F00 0x7C00 0x8001 0x0000 0x0000 13: 0x1F00 0x7C00 0xC001 0x0000 0x0000 14: 0x1F00 0x7C00 0x8002 0x0000 0x0000 15: 0x1F00 0x7C00 0xC002 0x0000 0x0000 16: 0x1F00 0x7C00 0x8003 0x0000 0x0000 17: 0x1F00 0x7C00 0xC003 0x0000 0x0000 18: 0x1F00 0x7C80 0x0000 0x0000 0x0000 19: 0x1F00 0x7C80 0x4000 0x0000 0x0000 20: 0x1F00 0x7C80 0x0001 0x0000 0x0000 21: 0x1F00 0x7C80 0x4001 0x0000 0x0000 22: 0x1F00 0x7C80 0x0002 0x0000 0x0000 23: 0x1F00 0x7C80 0x4002 0x0000 0x0000 24: 0x1F00 0x7C80 0x0003 0x0000 0x0000 25: 0x1F00 0x7C80 0x4003 0x0000 0x0000 26: 0x1F00 0x7C80 0x8000 0x0000 0x0000 27: 0x1F00 0x7C80 0xC000 0x0000 0x0000 28: 0x1F00 0x7C80 0x8001 0x0000 0x0000 29: 0x1F00 0x7C80 0xC001 0x0000 0x0000 30: 0x1F00 0x7C80 0x8002 0x0000 0x0000 31: 0x1F00 0x7C80 0xC002 0x0000 0x0000 32: 0x1F00 0x7C80 0x8003 0x0000 0x0000 33: 0x1F00 0x7C80 0xC003 0x0000 0x0000 34: 0x1F00 0x7E00 0x0000 0x0000 0x0000 35: 0x1F00 0x7E00 0x4000 0x0000 0x0000 36: 0x1F00 0x7E00 0x0001 0x0000 0x0000 37: 0x1F00 0x7E00 0x4001 0x0000 0x0000 38: 0x1F00 0x7E00 0x0002 0x0000 0x0000 39: 0x1F00 0x7E00 0x4002 0x0000 0x0000 40: 0x1F00 0x7E00 0x0003 0x0000 0x0000 41: 0x1F00 0x7E00 0x4003 0x0000 0x0000 42: 0x1F00 0x7E00 0x8000 0x0000 0x0000 43: 0x1F00 0x7E00 0xC000 0x0000 0x0000 44: 0x1F00 0x7E00 0x8001 0x0000 0x0000 45: 0x1F00 0x7E00 0xC001 0x0000 0x0000 46: 0x1F00 0x7E00 0x8002 0x0000 0x0000 47: 0x1F00 0x7E00 0xC002 0x0000 0x0000 48: 0x1F00 0x7E00 0x8003 0x0000 0x0000 49: 0x1F00 0x7E00 0xC003 0x0000 0x0000 50: 0x1F00 0x7E80 0x0000 0x0000 0x0000 51: 0x1F00 0x7E80 0x4000 0x0000 0x0000 52: 0x1F00 0x7E80 0x0001 0x0000 0x0000 53: 0x1F00 0x7E80 0x4001 0x0000 0x0000 54: 0x1F00 0x7E80 0x0002 0x0000 0x0000 55: 0x1F00 0x7E80 0x4002 0x0000 0x0000 56: 0x1F00 0x7E80 0x0003 0x0000 0x0000 57: 0x1F00 0x7E80 0x4003 0x0000 0x0000 58: 0x1F00 0x7E80 0x8000 0x0000 0x0000 59: 0x1F00 0x7E80 0xC000 0x0000 0x0000 60: 0x1F00 0x7E80 0x8001 0x0000 0x0000 61: 0x1F00 0x7E80 0xC001 0x0000 0x0000 62: 0x1F00 0x7E80 0x8002 0x0000 0x0000 63: 0x1F00 0x7E80 0xC002 0x0000 0x0000 64: 0x1F00 0x7E80 0x8003 0x0000 0x0000 65: 0x1F00 0x7E80 0xC003 0x0000 0x0000 66: 0x1F00 0x7C40 0x0000 0x0000 0x0000 67: 0x1F00 0x7C40 0x4000 0x0000 0x0000 68: 0x1F00 0x7C40 0x0001 0x0000 0x0000 69: 0x1F00 0x7C40 0x4001 0x0000 0x0000 70: 0x1F00 0x7C40 0x0002 0x0000 0x0000 71: 0x1F00 0x7C40 0x4002 0x0000 0x0000 72: 0x1F00 0x7C40 0x0003 0x0000 0x0000 73: 0x1F00 0x7C40 0x4003 0x0000 0x0000 74: 0x1F00 0x7C40 0x8000 0x0000 0x0000 75: 0x1F00 0x7C40 0xC000 0x0000 0x0000 76: 0x1F00 0x7C40 0x8001 0x0000 0x0000 77: 0x1F00 0x7C40 0xC001 0x0000 0x0000 78: 0x1F00 0x7C40 0x8002 0x0000 0x0000 79: 0x1F00 0x7C40 0xC002 0x0000 0x0000 80: 0x1F00 0x7C40 0x8003 0x0000 0x0000 81: 0x1F00 0x7C40 0xC003 0x0000 0x0000 82: 0x1F00 0x7CC0 0x0000 0x0000 0x0000 83: 0x1F00 0x7CC0 0x4000 0x0000 0x0000 84: 0x1F00 0x7CC0 0x0001 0x0000 0x0000 85: 0x1F00 0x7CC0 0x4001 0x0000 0x0000 86: 0x1F00 0x7CC0 0x0002 0x0000 0x0000 87: 0x1F00 0x7CC0 0x4002 0x0000 0x0000 88: 0x1F00 0x7CC0 0x0003 0x0000 0x0000 89: 0x1F00 0x7CC0 0x4003 0x0000 0x0000 90: 0x1F00 0x7CC0 0x8000 0x0000 0x0000 91: 0x1F00 0x7CC0 0xC000 0x0000 0x0000 92: 0x1F00 0x7CC0 0x8001 0x0000 0x0000 93: 0x1F00 0x7CC0 0xC001 0x0000 0x0000 94: 0x1F00 0x7CC0 0x8002 0x0000 0x0000 95: 0x1F00 0x7CC0 0xC002 0x0000 0x0000 96: 0x1F00 0x7CC0 0x8003 0x0000 0x0000 97: 0x1F00 0x7CC0 0xC003 0x0000 0x0000 98: 0x1F00 0x7E40 0x0000 0x0000 0x0000 99: 0x1F00 0x7E40 0x4000 0x0000 0x0000 100: 0x1F00 0x7E40 0x0001 0x0000 0x0000 101: 0x1F00 0x7E40 0x4001 0x0000 0x0000 102: 0x1F00 0x7E40 0x0002 0x0000 0x0000 103: 0x1F00 0x7E40 0x4002 0x0000 0x0000 104: 0x1F00 0x7E40 0x0003 0x0000 0x0000 105: 0x1F00 0x7E40 0x4003 0x0000 0x0000 106: 0x1F00 0x7E40 0x8000 0x0000 0x0000 107: 0x1F00 0x7E40 0xC000 0x0000 0x0000 108: 0x1F00 0x7E40 0x8001 0x0000 0x0000 109: 0x1F00 0x7E40 0xC001 0x0000 0x0000 110: 0x1F00 0x7E40 0x8002 0x0000 0x0000 111: 0x1F00 0x7E40 0xC002 0x0000 0x0000 112: 0x1F00 0x7E40 0x8003 0x0000 0x0000 113: 0x1F00 0x7E40 0xC003 0x0000 0x0000 114: 0x0F10 0x7EC0 0x0000 0x0000 0x0000 115: 0x1708 0x7EC0 0x4000 0x0000 0x0000 116: 0x1E01 0x7EC0 0x0001 0x0000 0x0000 117: 0x1F00 0x6EC8 0x4001 0x0000 0x0000 118: 0x1B04 0x7EC0 0x0002 0x0000 0x0000 119: 0x1F00 0x5EC4 0x4002 0x0000 0x0000 120: 0x1D02 0x7EC0 0x0003 0x0000 0x0000 121: 0x1F00 0x3EC2 0x4003 0x0000 0x0000 122: 0x1F00 0x76D0 0x8000 0x0000 0x0000 123: 0x1F00 0x7AE0 0xC000 0x0000 0x0000 124: 0x1F00 0x76D0 0x8001 0x0000 0x0000 125: 0x1F00 0x7AE0 0xC001 0x0000 0x0000 126: 0x1F00 0x76D0 0x8002 0x0000 0x0000 127: 0x1F00 0x7AE0 0xC002 0x0000 0x0000 128: 0x1F00 0x76D0 0x8003 0x0000 0x0000 129: 0x1F00 0x7AE0 0xC003 0x0000 0x0000 130: 0x1F00 0x7C00 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OOOOO OOOOOIGIIP GOOOOO OOOOOIIII G P G UUT inputs: 7 UUT outputs: 20 pins used: 27 not used: 39 130 'test steps' 177 lines ; M161 PCB REV C SCHEMATIC REV B BINARY TO OCAL/DECIMAL DECODER ; ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES). ; ; ALL 3 ENABLES MUST BE HIGH TO ENABLE OUTPUTS PINS Main menu Fri Jun 30 16:00:24 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:00:25 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SSTUVUVRRPPLLHHMMFFNNJJEEDD SIDE 212122121212121212121212121 DIRECTION IIIIIIIOOOOOOOOOOOOOOOOOOOO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 96 Main menu Fri Jun 30 16:00:34 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:00:53 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SSTUVUVRRPPLLHHMMFFNNJJEEDD SIDE 212122121212121212121212121 DIRECTION IIIIIIIOOOOOOOOOOOOOOOOOOOO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 112 Main menu Fri Jun 30 16:01:02 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:01:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SSTUVUVRRPPLLHHMMFFNNJJEEDD SIDE 212122121212121212121212121 DIRECTION IIIIIIIOOOOOOOOOOOOOOOOOOOO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 40 Main menu Fri Jun 30 16:01:21 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:01:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SSTUVUVRRPPLLHHMMFFNNJJEEDD SIDE 212122121212121212121212121 DIRECTION IIIIIIIOOOOOOOOOOOOOOOOOOOO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 39 Main menu Fri Jun 30 16:01:39 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:01:53 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SSTUVUVRRPPLLHHMMFFNNJJEEDD SIDE 212122121212121212121212121 DIRECTION IIIIIIIOOOOOOOOOOOOOOOOOOOO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 28 Main menu Fri Jun 30 16:01:56 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:02:12 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SSTUVUVRRPPLLHHMMFFNNJJEEDD SIDE 212122121212121212121212121 DIRECTION IIIIIIIOOOOOOOOOOOOOOOOOOOO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 34 Main menu Fri Jun 30 16:02:17 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:02:28 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER SSTUVUVRRPPLLHHMMFFNNJJEEDD SIDE 212122121212121212121212121 DIRECTION IIIIIIIOOOOOOOOOOOOOOOOOOOO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 25 Main menu Fri Jun 30 16:02:31 2017 test file is: tests\m161.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:02:57 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:02:59 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 45 Main menu Fri Jun 30 16:03:02 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:03:15 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:03:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 21 Main menu Fri Jun 30 16:03:18 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 16:03:32 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:03:32 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 19 Main menu Fri Jun 30 16:03:35 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 16:03:48 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:03:49 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 46 Main menu Fri Jun 30 16:03:52 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 16:04:08 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:04:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 44 Main menu Fri Jun 30 16:04:12 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:04:29 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:04:30 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 28 Main menu Fri Jun 30 16:04:32 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 16:04:46 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:04:46 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 39 Main menu Fri Jun 30 16:04:49 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 16: 000011101 test 17: 000011111 test 18: 000100001 test 19: 000100011 test 20: 000100101 test 21: 000100111 test 22: 000101001 test 23: 000101011 test 24: 000101101 test 25: 000101111 test 26: 000110001 test 27: 000110011 test 28: 000110101 test 29: 000110111 test 30: 000111001 test 31: 000111011 test 32: 000111101 test 33: 000111111 test 34: 001000001 test 35: 001000011 test 36: 001000101 test 37: 001000111 test 38: 001001001 test 39: 001001011 test 40: 001001101 test 41: 001001111 test 42: 001010001 test 43: 001010011 test 44: 001010101 test 45: 001010111 test 46: 001011001 test 47: 001011011 test 48: 001011101 test 49: 001011111 test 50: 001100001 test 51: 001100011 test 52: 001100101 test 53: 001100111 test 54: 001101001 test 55: 001101011 test 56: 001101101 test 57: 001101111 test 58: 001110001 test 59: 001110011 test 60: 001110101 test 61: 001110111 test 62: 001111001 test 63: 001111011 test 64: 001111101 test 65: 001111111 test 66: 010000001 test 67: 010000011 test 68: 010000101 test 69: 010000111 test 70: 010001001 test 71: 010001011 test 72: 010001101 test 73: 010001111 test 74: 010010001 test 75: 010010011 test 76: 010010101 test 77: 010010111 test 78: 010011001 test 79: 010011011 test 80: 010011101 test 81: 010011111 test 82: 010100001 test 83: 010100011 test 84: 010100101 test 85: 010100111 test 86: 010101001 test 87: 010101011 test 88: 010101101 test 89: 010101111 test 90: 010110001 test 91: 010110011 test 92: 010110101 test 93: 010110111 test 94: 010111001 test 95: 010111011 test 96: 010111101 test 97: 010111111 test 98: 011000001 test 99: 011000011 test 100: 011000101 test 101: 011000111 test 102: 011001001 test 103: 011001011 test 104: 011001101 test 105: 011001111 test 106: 011010001 test 107: 011010011 test 108: 011010101 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test 159: 100111011 test 160: 100111101 test 161: 100111111 test 162: 101000001 test 163: 101000011 test 164: 101000101 test 165: 101000111 test 166: 101001001 test 167: 101001011 test 168: 101001101 test 169: 101001111 test 170: 101010001 test 171: 101010011 test 172: 101010101 test 173: 101010111 test 174: 101011001 test 175: 101011011 test 176: 101011101 test 177: 101011111 test 178: 101100001 test 179: 101100011 test 180: 101100101 test 181: 101100111 test 182: 101101001 test 183: 101101011 test 184: 101101101 test 185: 101101111 test 186: 101110001 test 187: 101110011 test 188: 101110101 test 189: 101110111 test 190: 101111001 test 191: 101111011 test 192: 101111101 test 193: 101111111 test 194: 110000001 test 195: 110000011 test 196: 110000101 test 197: 110000111 test 198: 110001001 test 199: 110001011 test 200: 110001101 test 201: 110001111 test 202: 110010001 test 203: 110010011 test 204: 110010101 test 205: 110010111 test 206: 110011001 test 207: 110011011 test 208: 110011101 test 209: 110011111 test 210: 110100001 test 211: 110100011 test 212: 110100101 test 213: 110100111 test 214: 110101001 test 215: 110101011 test 216: 110101101 test 217: 110101111 test 218: 110110001 test 219: 110110011 test 220: 110110101 test 221: 110110111 test 222: 110111001 test 223: 110111011 test 224: 110111101 test 225: 110111111 test 226: 111000001 test 227: 111000011 test 228: 111000101 test 229: 111000111 test 230: 111001001 test 231: 111001011 test 232: 111001101 test 233: 111001111 test 234: 111010001 test 235: 111010011 test 236: 111010101 test 237: 111010111 test 238: 111011001 test 239: 111011011 test 240: 111011101 test 241: 111011111 test 242: 111100001 test 243: 111100011 test 244: 111100101 test 245: 111100111 test 246: 111101001 test 247: 111101011 test 248: 111101101 test 249: 111101111 test 250: 111110001 test 251: 111110011 test 252: 111110101 test 253: 111110111 test 254: 111111001 test 255: 111111011 test 256: 111111101 test 257: 111111110 test 258: 000000001 test 259: 000000001 test 260: 000000011 test 261: 000000101 test 262: 000000111 test 263: 000001001 test 264: 000001011 test 265: 000001101 test 266: 000001111 test 267: 000010001 test 268: 000010011 test 269: 000010101 test 270: 000010111 test 271: 000011001 test 272: 000011011 test 273: 000011101 test 274: 000011111 test 275: 000100001 test 276: 000100011 test 277: 000100101 test 278: 000100111 test 279: 000101001 test 280: 000101011 test 281: 000101101 test 282: 000101111 test 283: 000110001 test 284: 000110011 test 285: 000110101 test 286: 000110111 test 287: 000111001 test 288: 000111011 test 289: 000111101 test 290: 000111111 test 291: 001000001 test 292: 001000011 test 293: 001000101 test 294: 001000111 test 295: 001001001 test 296: 001001011 test 297: 001001101 test 298: 001001111 test 299: 001010001 test 300: 001010011 test 301: 001010101 test 302: 001010111 test 303: 001011001 test 304: 001011011 test 305: 001011101 test 306: 001011111 test 307: 001100001 test 308: 001100011 test 309: 001100101 test 310: 001100111 test 311: 001101001 test 312: 001101011 test 313: 001101101 test 314: 001101111 test 315: 001110001 test 316: 001110011 test 317: 001110101 test 318: 001110111 test 319: 001111001 test 320: 001111011 test 321: 001111101 test 322: 001111111 test 323: 010000001 test 324: 010000011 test 325: 010000101 test 326: 010000111 test 327: 010001001 test 328: 010001011 test 329: 010001101 test 330: 010001111 test 331: 010010001 test 332: 010010011 test 333: 010010101 test 334: 010010111 test 335: 010011001 test 336: 010011011 test 337: 010011101 test 338: 010011111 test 339: 010100001 test 340: 010100011 test 341: 010100101 test 342: 010100111 test 343: 010101001 test 344: 010101011 test 345: 010101101 test 346: 010101111 test 347: 010110001 test 348: 010110011 test 349: 010110101 test 350: 010110111 test 351: 010111001 test 352: 010111011 test 353: 010111101 test 354: 010111111 test 355: 011000001 test 356: 011000011 test 357: 011000101 test 358: 011000111 test 359: 011001001 test 360: 011001011 test 361: 011001101 test 362: 011001111 test 363: 011010001 test 364: 011010011 test 365: 011010101 test 366: 011010111 test 367: 011011001 test 368: 011011011 test 369: 011011101 test 370: 011011111 test 371: 011100001 test 372: 011100011 test 373: 011100101 test 374: 011100111 test 375: 011101001 test 376: 011101011 test 377: 011101101 test 378: 011101111 test 379: 011110001 test 380: 011110011 test 381: 011110101 test 382: 011110111 test 383: 011111001 test 384: 011111011 test 385: 011111101 test 386: 011111111 test 387: 100000001 test 388: 100000011 test 389: 100000101 test 390: 100000111 test 391: 100001001 test 392: 100001011 test 393: 100001101 test 394: 100001111 test 395: 100010001 test 396: 100010011 test 397: 100010101 test 398: 100010111 test 399: 100011001 test 400: 100011011 test 401: 100011101 test 402: 100011111 test 403: 100100001 test 404: 100100011 test 405: 100100101 test 406: 100100111 test 407: 100101001 test 408: 100101011 test 409: 100101101 test 410: 100101111 test 411: 100110001 test 412: 100110011 test 413: 100110101 test 414: 100110111 test 415: 100111001 test 416: 100111011 test 417: 100111101 test 418: 100111111 test 419: 101000001 test 420: 101000011 test 421: 101000101 test 422: 101000111 test 423: 101001001 test 424: 101001011 test 425: 101001101 test 426: 101001111 test 427: 101010001 test 428: 101010011 test 429: 101010101 test 430: 101010111 test 431: 101011001 test 432: 101011011 test 433: 101011101 test 434: 101011111 test 435: 101100001 test 436: 101100011 test 437: 101100101 test 438: 101100111 test 439: 101101001 test 440: 101101011 test 441: 101101101 test 442: 101101111 test 443: 101110001 test 444: 101110011 test 445: 101110101 test 446: 101110111 test 447: 101111001 test 448: 101111011 test 449: 101111101 test 450: 101111111 test 451: 110000001 test 452: 110000011 test 453: 110000101 test 454: 110000111 test 455: 110001001 test 456: 110001011 test 457: 110001101 test 458: 110001111 test 459: 110010001 test 460: 110010011 test 461: 110010101 test 462: 110010111 test 463: 110011001 test 464: 110011011 test 465: 110011101 test 466: 110011111 test 467: 110100001 test 468: 110100011 test 469: 110100101 test 470: 110100111 test 471: 110101001 test 472: 110101011 test 473: 110101101 test 474: 110101111 test 475: 110110001 test 476: 110110011 test 477: 110110101 test 478: 110110111 test 479: 110111001 test 480: 110111011 test 481: 110111101 test 482: 110111111 test 483: 111000001 test 484: 111000011 test 485: 111000101 test 486: 111000111 test 487: 111001001 test 488: 111001011 test 489: 111001101 test 490: 111001111 test 491: 111010001 test 492: 111010011 test 493: 111010101 test 494: 111010111 test 495: 111011001 test 496: 111011011 test 497: 111011101 test 498: 111011111 test 499: 111100001 test 500: 111100011 test 501: 111100101 test 502: 111100111 test 503: 111101001 test 504: 111101011 test 505: 111101101 test 506: 111101111 test 507: 111110001 test 508: 111110011 test 509: 111110101 test 510: 111110111 test 511: 111111001 test 512: 111111011 test 513: 111111101 test 514: 111111110 test 515: 000000001 test 516: 000000001 test 517: 000000011 test 518: 000000101 test 519: 000000111 test 520: 000001001 test 521: 000001011 test 522: 000001101 test 523: 000001111 test 524: 000010001 test 525: 000010011 test 526: 000010101 test 527: 000010111 test 528: 000011001 test 529: 000011011 test 530: 000011101 test 531: 000011111 test 532: 000100001 test 533: 000100011 test 534: 000100101 test 535: 000100111 test 536: 000101001 test 537: 000101011 test 538: 000101101 test 539: 000101111 test 540: 000110001 test 541: 000110011 test 542: 000110101 test 543: 000110111 test 544: 000111001 test 545: 000111011 test 546: 000111101 test 547: 000111111 test 548: 001000001 test 549: 001000011 test 550: 001000101 test 551: 001000111 test 552: 001001001 test 553: 001001011 test 554: 001001101 test 555: 001001111 test 556: 001010001 test 557: 001010011 test 558: 001010101 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test 659: 100011111 test 660: 100100001 test 661: 100100011 test 662: 100100101 test 663: 100100111 test 664: 100101001 test 665: 100101011 test 666: 100101101 test 667: 100101111 test 668: 100110001 test 669: 100110011 test 670: 100110101 test 671: 100110111 test 672: 100111001 test 673: 100111011 test 674: 100111101 test 675: 100111111 test 676: 101000001 test 677: 101000011 test 678: 101000101 test 679: 101000111 test 680: 101001001 test 681: 101001011 test 682: 101001101 test 683: 101001111 test 684: 101010001 test 685: 101010011 test 686: 101010101 test 687: 101010111 test 688: 101011001 test 689: 101011011 test 690: 101011101 test 691: 101011111 test 692: 101100001 test 693: 101100011 test 694: 101100101 test 695: 101100111 test 696: 101101001 test 697: 101101011 test 698: 101101101 test 699: 101101111 test 700: 101110001 test 701: 101110011 test 702: 101110101 test 703: 101110111 test 704: 101111001 test 705: 101111011 test 706: 101111101 test 707: 101111111 test 708: 110000001 test 709: 110000011 test 710: 110000101 test 711: 110000111 test 712: 110001001 test 713: 110001011 test 714: 110001101 test 715: 110001111 test 716: 110010001 test 717: 110010011 test 718: 110010101 test 719: 110010111 test 720: 110011001 test 721: 110011011 test 722: 110011101 test 723: 110011111 test 724: 110100001 test 725: 110100011 test 726: 110100101 test 727: 110100111 test 728: 110101001 test 729: 110101011 test 730: 110101101 test 731: 110101111 test 732: 110110001 test 733: 110110011 test 734: 110110101 test 735: 110110111 test 736: 110111001 test 737: 110111011 test 738: 110111101 test 739: 110111111 test 740: 111000001 test 741: 111000011 test 742: 111000101 test 743: 111000111 test 744: 111001001 test 745: 111001011 test 746: 111001101 test 747: 111001111 test 748: 111010001 test 749: 111010011 test 750: 111010101 test 751: 111010111 test 752: 111011001 test 753: 111011011 test 754: 111011101 test 755: 111011111 test 756: 111100001 test 757: 111100011 test 758: 111100101 test 759: 111100111 test 760: 111101001 test 761: 111101011 test 762: 111101101 test 763: 111101111 test 764: 111110001 test 765: 111110011 test 766: 111110101 test 767: 111110111 test 768: 111111001 test 769: 111111011 test 770: 111111101 test 771: 111111110 test 772: 000000001 test 773: 000000001000000001000000001 test 774: 111111110111111110111111110 test 775: 000000001 test 776: 000000011 test 777: 000000101 test 778: 000000111 test 779: 000001001 test 780: 000001011 test 781: 000001101 test 782: 000001111 test 783: 000010001 test 784: 000010011 test 785: 000010101 test 786: 000010111 test 787: 000011001 test 788: 000011011 test 789: 000011101 test 790: 000011111 test 791: 000100001 test 792: 000100011 test 793: 000100101 test 794: 000100111 test 795: 000101001 test 796: 000101011 test 797: 000101101 test 798: 000101111 test 799: 000110001 test 800: 000110011 test 801: 000110101 test 802: 000110111 test 803: 000111001 test 804: 000111011 test 805: 000111101 test 806: 000111111 test 807: 001000001 test 808: 001000011 test 809: 001000101 test 810: 001000111 test 811: 001001001 test 812: 001001011 test 813: 001001101 test 814: 001001111 test 815: 001010001 test 816: 001010011 test 817: 001010101 test 818: 001010111 test 819: 001011001 test 820: 001011011 test 821: 001011101 test 822: 001011111 test 823: 001100001 test 824: 001100011 test 825: 001100101 test 826: 001100111 test 827: 001101001 test 828: 001101011 test 829: 001101101 test 830: 001101111 test 831: 001110001 test 832: 001110011 test 833: 001110101 test 834: 001110111 test 835: 001111001 test 836: 001111011 test 837: 001111101 test 838: 001111111 test 839: 010000001 test 840: 010000011 test 841: 010000101 test 842: 010000111 test 843: 010001001 test 844: 010001011 test 845: 010001101 test 846: 010001111 test 847: 010010001 test 848: 010010011 test 849: 010010101 test 850: 010010111 test 851: 010011001 test 852: 010011011 test 853: 010011101 test 854: 010011111 test 855: 010100001 test 856: 010100011 test 857: 010100101 test 858: 010100111 test 859: 010101001 test 860: 010101011 test 861: 010101101 test 862: 010101111 test 863: 010110001 test 864: 010110011 test 865: 010110101 test 866: 010110111 test 867: 010111001 test 868: 010111011 test 869: 010111101 test 870: 010111111 test 871: 011000001 test 872: 011000011 test 873: 011000101 test 874: 011000111 test 875: 011001001 test 876: 011001011 test 877: 011001101 test 878: 011001111 test 879: 011010001 test 880: 011010011 test 881: 011010101 test 882: 011010111 test 883: 011011001 test 884: 011011011 test 885: 011011101 test 886: 011011111 test 887: 011100001 test 888: 011100011 test 889: 011100101 test 890: 011100111 test 891: 011101001 test 892: 011101011 test 893: 011101101 test 894: 011101111 test 895: 011110001 test 896: 011110011 test 897: 011110101 test 898: 011110111 test 899: 011111001 test 900: 011111011 test 901: 011111101 test 902: 011111111 test 903: 100000001 test 904: 100000011 test 905: 100000101 test 906: 100000111 test 907: 100001001 test 908: 100001011 test 909: 100001101 test 910: 100001111 test 911: 100010001 test 912: 100010011 test 913: 100010101 test 914: 100010111 test 915: 100011001 test 916: 100011011 test 917: 100011101 test 918: 100011111 test 919: 100100001 test 920: 100100011 test 921: 100100101 test 922: 100100111 test 923: 100101001 test 924: 100101011 test 925: 100101101 test 926: 100101111 test 927: 100110001 test 928: 100110011 test 929: 100110101 test 930: 100110111 test 931: 100111001 test 932: 100111011 test 933: 100111101 test 934: 100111111 test 935: 101000001 test 936: 101000011 test 937: 101000101 test 938: 101000111 test 939: 101001001 test 940: 101001011 test 941: 101001101 test 942: 101001111 test 943: 101010001 test 944: 101010011 test 945: 101010101 test 946: 101010111 test 947: 101011001 test 948: 101011011 test 949: 101011101 test 950: 101011111 test 951: 101100001 test 952: 101100011 test 953: 101100101 test 954: 101100111 test 955: 101101001 test 956: 101101011 test 957: 101101101 test 958: 101101111 test 959: 101110001 test 960: 101110011 test 961: 101110101 test 962: 101110111 test 963: 101111001 test 964: 101111011 test 965: 101111101 test 966: 101111111 test 967: 110000001 test 968: 110000011 test 969: 110000101 test 970: 110000111 test 971: 110001001 test 972: 110001011 test 973: 110001101 test 974: 110001111 test 975: 110010001 test 976: 110010011 test 977: 110010101 test 978: 110010111 test 979: 110011001 test 980: 110011011 test 981: 110011101 test 982: 110011111 test 983: 110100001 test 984: 110100011 test 985: 110100101 test 986: 110100111 test 987: 110101001 test 988: 110101011 test 989: 110101101 test 990: 110101111 test 991: 110110001 test 992: 110110011 test 993: 110110101 test 994: 110110111 test 995: 110111001 test 996: 110111011 test 997: 110111101 test 998: 110111111 test 999: 111000001 test 1000: 111000011 test 1001: 111000101 test 1002: 111000111 test 1003: 111001001 test 1004: 111001011 test 1005: 111001101 test 1006: 111001111 test 1007: 111010001 test 1008: 111010011 test 1009: 111010101 test 1010: 111010111 test 1011: 111011001 test 1012: 111011011 test 1013: 111011101 test 1014: 111011111 test 1015: 111100001 test 1016: 111100011 test 1017: 111100101 test 1018: 111100111 test 1019: 111101001 test 1020: 111101011 test 1021: 111101101 test 1022: 111101111 test 1023: 111110001 test 1024: 111110011 test 1025: 111110101 test 1026: 111110111 test 1027: 111111001 test 1028: 111111011 test 1029: 111111101 test 1030: 111111110 test 1031: 000000001 test 1032: 000000011 test 1033: 000000101 test 1034: 000000111 test 1035: 000001001 test 1036: 000001011 test 1037: 000001101 test 1038: 000001111 test 1039: 000010001 test 1040: 000010011 test 1041: 000010101 test 1042: 000010111 test 1043: 000011001 test 1044: 000011011 test 1045: 000011101 test 1046: 000011111 test 1047: 000100001 test 1048: 000100011 test 1049: 000100101 test 1050: 000100111 test 1051: 000101001 test 1052: 000101011 test 1053: 000101101 test 1054: 000101111 test 1055: 000110001 test 1056: 000110011 test 1057: 000110101 test 1058: 000110111 test 1059: 000111001 test 1060: 000111011 test 1061: 000111101 test 1062: 000111111 test 1063: 001000001 test 1064: 001000011 test 1065: 001000101 test 1066: 001000111 test 1067: 001001001 test 1068: 001001011 test 1069: 001001101 test 1070: 001001111 test 1071: 001010001 test 1072: 001010011 test 1073: 001010101 test 1074: 001010111 test 1075: 001011001 test 1076: 001011011 test 1077: 001011101 test 1078: 001011111 test 1079: 001100001 test 1080: 001100011 test 1081: 001100101 test 1082: 001100111 test 1083: 001101001 test 1084: 001101011 test 1085: 001101101 test 1086: 001101111 test 1087: 001110001 test 1088: 001110011 test 1089: 001110101 test 1090: 001110111 test 1091: 001111001 test 1092: 001111011 test 1093: 001111101 test 1094: 001111111 test 1095: 010000001 test 1096: 010000011 test 1097: 010000101 test 1098: 010000111 test 1099: 010001001 test 1100: 010001011 test 1101: 010001101 test 1102: 010001111 test 1103: 010010001 test 1104: 010010011 test 1105: 010010101 test 1106: 010010111 test 1107: 010011001 test 1108: 010011011 test 1109: 010011101 test 1110: 010011111 test 1111: 010100001 test 1112: 010100011 test 1113: 010100101 test 1114: 010100111 test 1115: 010101001 test 1116: 010101011 test 1117: 010101101 test 1118: 010101111 test 1119: 010110001 test 1120: 010110011 test 1121: 010110101 test 1122: 010110111 test 1123: 010111001 test 1124: 010111011 test 1125: 010111101 test 1126: 010111111 test 1127: 011000001 test 1128: 011000011 test 1129: 011000101 test 1130: 011000111 test 1131: 011001001 test 1132: 011001011 test 1133: 011001101 test 1134: 011001111 test 1135: 011010001 test 1136: 011010011 test 1137: 011010101 test 1138: 011010111 test 1139: 011011001 test 1140: 011011011 test 1141: 011011101 test 1142: 011011111 test 1143: 011100001 test 1144: 011100011 test 1145: 011100101 test 1146: 011100111 test 1147: 011101001 test 1148: 011101011 test 1149: 011101101 test 1150: 011101111 test 1151: 011110001 test 1152: 011110011 test 1153: 011110101 test 1154: 011110111 test 1155: 011111001 test 1156: 011111011 test 1157: 011111101 test 1158: 011111111 test 1159: 100000001 test 1160: 100000011 test 1161: 100000101 test 1162: 100000111 test 1163: 100001001 test 1164: 100001011 test 1165: 100001101 test 1166: 100001111 test 1167: 100010001 test 1168: 100010011 test 1169: 100010101 test 1170: 100010111 test 1171: 100011001 test 1172: 100011011 test 1173: 100011101 test 1174: 100011111 test 1175: 100100001 test 1176: 100100011 test 1177: 100100101 test 1178: 100100111 test 1179: 100101001 test 1180: 100101011 test 1181: 100101101 test 1182: 100101111 test 1183: 100110001 test 1184: 100110011 test 1185: 100110101 test 1186: 100110111 test 1187: 100111001 test 1188: 100111011 test 1189: 100111101 test 1190: 100111111 test 1191: 101000001 test 1192: 101000011 test 1193: 101000101 test 1194: 101000111 test 1195: 101001001 test 1196: 101001011 test 1197: 101001101 test 1198: 101001111 test 1199: 101010001 test 1200: 101010011 test 1201: 101010101 test 1202: 101010111 test 1203: 101011001 test 1204: 101011011 test 1205: 101011101 test 1206: 101011111 test 1207: 101100001 test 1208: 101100011 test 1209: 101100101 test 1210: 101100111 test 1211: 101101001 test 1212: 101101011 test 1213: 101101101 test 1214: 101101111 test 1215: 101110001 test 1216: 101110011 test 1217: 101110101 test 1218: 101110111 test 1219: 101111001 test 1220: 101111011 test 1221: 101111101 test 1222: 101111111 test 1223: 110000001 test 1224: 110000011 test 1225: 110000101 test 1226: 110000111 test 1227: 110001001 test 1228: 110001011 test 1229: 110001101 test 1230: 110001111 test 1231: 110010001 test 1232: 110010011 test 1233: 110010101 test 1234: 110010111 test 1235: 110011001 test 1236: 110011011 test 1237: 110011101 test 1238: 110011111 test 1239: 110100001 test 1240: 110100011 test 1241: 110100101 test 1242: 110100111 test 1243: 110101001 test 1244: 110101011 test 1245: 110101101 test 1246: 110101111 test 1247: 110110001 test 1248: 110110011 test 1249: 110110101 test 1250: 110110111 test 1251: 110111001 test 1252: 110111011 test 1253: 110111101 test 1254: 110111111 test 1255: 111000001 test 1256: 111000011 test 1257: 111000101 test 1258: 111000111 test 1259: 111001001 test 1260: 111001011 test 1261: 111001101 test 1262: 111001111 test 1263: 111010001 test 1264: 111010011 test 1265: 111010101 test 1266: 111010111 test 1267: 111011001 test 1268: 111011011 test 1269: 111011101 test 1270: 111011111 test 1271: 111100001 test 1272: 111100011 test 1273: 111100101 test 1274: 111100111 test 1275: 111101001 test 1276: 111101011 test 1277: 111101101 test 1278: 111101111 test 1279: 111110001 test 1280: 111110011 test 1281: 111110101 test 1282: 111110111 test 1283: 111111001 test 1284: 111111011 test 1285: 111111101 test 1286: 111111110 test 1287: 000000001 test 1288: 000000011 test 1289: 000000101 test 1290: 000000111 test 1291: 000001001 test 1292: 000001011 test 1293: 000001101 test 1294: 000001111 test 1295: 000010001 test 1296: 000010011 test 1297: 000010101 test 1298: 000010111 test 1299: 000011001 test 1300: 000011011 test 1301: 000011101 test 1302: 000011111 test 1303: 000100001 test 1304: 000100011 test 1305: 000100101 test 1306: 000100111 test 1307: 000101001 test 1308: 000101011 test 1309: 000101101 test 1310: 000101111 test 1311: 000110001 test 1312: 000110011 test 1313: 000110101 test 1314: 000110111 test 1315: 000111001 test 1316: 000111011 test 1317: 000111101 test 1318: 000111111 test 1319: 001000001 test 1320: 001000011 test 1321: 001000101 test 1322: 001000111 test 1323: 001001001 test 1324: 001001011 test 1325: 001001101 test 1326: 001001111 test 1327: 001010001 test 1328: 001010011 test 1329: 001010101 test 1330: 001010111 test 1331: 001011001 test 1332: 001011011 test 1333: 001011101 test 1334: 001011111 test 1335: 001100001 test 1336: 001100011 test 1337: 001100101 test 1338: 001100111 test 1339: 001101001 test 1340: 001101011 test 1341: 001101101 test 1342: 001101111 test 1343: 001110001 test 1344: 001110011 test 1345: 001110101 test 1346: 001110111 test 1347: 001111001 test 1348: 001111011 test 1349: 001111101 test 1350: 001111111 test 1351: 010000001 test 1352: 010000011 test 1353: 010000101 test 1354: 010000111 test 1355: 010001001 test 1356: 010001011 test 1357: 010001101 test 1358: 010001111 test 1359: 010010001 test 1360: 010010011 test 1361: 010010101 test 1362: 010010111 test 1363: 010011001 test 1364: 010011011 test 1365: 010011101 test 1366: 010011111 test 1367: 010100001 test 1368: 010100011 test 1369: 010100101 test 1370: 010100111 test 1371: 010101001 test 1372: 010101011 test 1373: 010101101 test 1374: 010101111 test 1375: 010110001 test 1376: 010110011 test 1377: 010110101 test 1378: 010110111 test 1379: 010111001 test 1380: 010111011 test 1381: 010111101 test 1382: 010111111 test 1383: 011000001 test 1384: 011000011 test 1385: 011000101 test 1386: 011000111 test 1387: 011001001 test 1388: 011001011 test 1389: 011001101 test 1390: 011001111 test 1391: 011010001 test 1392: 011010011 test 1393: 011010101 test 1394: 011010111 test 1395: 011011001 test 1396: 011011011 test 1397: 011011101 test 1398: 011011111 test 1399: 011100001 test 1400: 011100011 test 1401: 011100101 test 1402: 011100111 test 1403: 011101001 test 1404: 011101011 test 1405: 011101101 test 1406: 011101111 test 1407: 011110001 test 1408: 011110011 test 1409: 011110101 test 1410: 011110111 test 1411: 011111001 test 1412: 011111011 test 1413: 011111101 test 1414: 011111111 test 1415: 100000001 test 1416: 100000011 test 1417: 100000101 test 1418: 100000111 test 1419: 100001001 test 1420: 100001011 test 1421: 100001101 test 1422: 100001111 test 1423: 100010001 test 1424: 100010011 test 1425: 100010101 test 1426: 100010111 test 1427: 100011001 test 1428: 100011011 test 1429: 100011101 test 1430: 100011111 test 1431: 100100001 test 1432: 100100011 test 1433: 100100101 test 1434: 100100111 test 1435: 100101001 test 1436: 100101011 test 1437: 100101101 test 1438: 100101111 test 1439: 100110001 test 1440: 100110011 test 1441: 100110101 test 1442: 100110111 test 1443: 100111001 test 1444: 100111011 test 1445: 100111101 test 1446: 100111111 test 1447: 101000001 test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 0x0005 0x0010 0x0002 0x0000 0x0000 5: 0x0007 0x0010 0x0002 0x0000 0x0000 6: 0x0009 0x0010 0x0002 0x0000 0x0000 7: 0x000B 0x0010 0x0002 0x0000 0x0000 8: 0x000D 0x0010 0x0002 0x0000 0x0000 9: 0x000F 0x0010 0x0002 0x0000 0x0000 10: 0x0011 0x0010 0x0002 0x0000 0x0000 11: 0x0013 0x0010 0x0002 0x0000 0x0000 12: 0x0015 0x0010 0x0002 0x0000 0x0000 13: 0x0017 0x0010 0x0002 0x0000 0x0000 14: 0x0019 0x0010 0x0002 0x0000 0x0000 15: 0x001B 0x0010 0x0002 0x0000 0x0000 16: 0x001D 0x0010 0x0002 0x0000 0x0000 17: 0x001F 0x0010 0x0002 0x0000 0x0000 18: 0x1001 0x0010 0x0002 0x0000 0x0000 19: 0x1003 0x0010 0x0002 0x0000 0x0000 20: 0x1005 0x0010 0x0002 0x0000 0x0000 21: 0x1007 0x0010 0x0002 0x0000 0x0000 22: 0x1009 0x0010 0x0002 0x0000 0x0000 23: 0x100B 0x0010 0x0002 0x0000 0x0000 24: 0x100D 0x0010 0x0002 0x0000 0x0000 25: 0x100F 0x0010 0x0002 0x0000 0x0000 26: 0x1011 0x0010 0x0002 0x0000 0x0000 27: 0x1013 0x0010 0x0002 0x0000 0x0000 28: 0x1015 0x0010 0x0002 0x0000 0x0000 29: 0x1017 0x0010 0x0002 0x0000 0x0000 30: 0x1019 0x0010 0x0002 0x0000 0x0000 31: 0x101B 0x0010 0x0002 0x0000 0x0000 32: 0x101D 0x0010 0x0002 0x0000 0x0000 33: 0x101F 0x0010 0x0002 0x0000 0x0000 34: 0x2001 0x0010 0x0002 0x0000 0x0000 35: 0x2003 0x0010 0x0002 0x0000 0x0000 36: 0x2005 0x0010 0x0002 0x0000 0x0000 37: 0x2007 0x0010 0x0002 0x0000 0x0000 38: 0x2009 0x0010 0x0002 0x0000 0x0000 39: 0x200B 0x0010 0x0002 0x0000 0x0000 40: 0x200D 0x0010 0x0002 0x0000 0x0000 41: 0x200F 0x0010 0x0002 0x0000 0x0000 42: 0x2011 0x0010 0x0002 0x0000 0x0000 43: 0x2013 0x0010 0x0002 0x0000 0x0000 44: 0x2015 0x0010 0x0002 0x0000 0x0000 45: 0x2017 0x0010 0x0002 0x0000 0x0000 46: 0x2019 0x0010 0x0002 0x0000 0x0000 47: 0x201B 0x0010 0x0002 0x0000 0x0000 48: 0x201D 0x0010 0x0002 0x0000 0x0000 49: 0x201F 0x0010 0x0002 0x0000 0x0000 50: 0x3001 0x0010 0x0002 0x0000 0x0000 51: 0x3003 0x0010 0x0002 0x0000 0x0000 52: 0x3005 0x0010 0x0002 0x0000 0x0000 53: 0x3007 0x0010 0x0002 0x0000 0x0000 54: 0x3009 0x0010 0x0002 0x0000 0x0000 55: 0x300B 0x0010 0x0002 0x0000 0x0000 56: 0x300D 0x0010 0x0002 0x0000 0x0000 57: 0x300F 0x0010 0x0002 0x0000 0x0000 58: 0x3011 0x0010 0x0002 0x0000 0x0000 59: 0x3013 0x0010 0x0002 0x0000 0x0000 60: 0x3015 0x0010 0x0002 0x0000 0x0000 61: 0x3017 0x0010 0x0002 0x0000 0x0000 62: 0x3019 0x0010 0x0002 0x0000 0x0000 63: 0x301B 0x0010 0x0002 0x0000 0x0000 64: 0x301D 0x0010 0x0002 0x0000 0x0000 65: 0x301F 0x0010 0x0002 0x0000 0x0000 66: 0x4001 0x0010 0x0002 0x0000 0x0000 67: 0x4003 0x0010 0x0002 0x0000 0x0000 68: 0x4005 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0x0000 1481: 0xF71E 0xB08F 0x0002 0x0000 0x0000 1482: 0xF71E 0xB08F 0x0003 0x0000 0x0000 1483: 0xF71E 0xB04F 0x0002 0x0000 0x0000 1484: 0xF71E 0xB04F 0x0003 0x0000 0x0000 1485: 0xF71E 0xB0CF 0x0002 0x0000 0x0000 1486: 0xF71E 0xB0CF 0x0003 0x0000 0x0000 1487: 0xF71E 0xB02F 0x0002 0x0000 0x0000 1488: 0xF71E 0xB02F 0x0003 0x0000 0x0000 1489: 0xF71E 0xB0AF 0x0002 0x0000 0x0000 1490: 0xF71E 0xB0AF 0x0003 0x0000 0x0000 1491: 0xF71E 0xB06F 0x0002 0x0000 0x0000 1492: 0xF71E 0xB06F 0x0003 0x0000 0x0000 1493: 0xF71E 0xB0EF 0x0002 0x0000 0x0000 1494: 0xF71E 0xB0EF 0x0003 0x0000 0x0000 1495: 0xF71E 0xB40F 0x0002 0x0000 0x0000 1496: 0xF71E 0xB40F 0x0003 0x0000 0x0000 1497: 0xF71E 0xB48F 0x0002 0x0000 0x0000 1498: 0xF71E 0xB48F 0x0003 0x0000 0x0000 1499: 0xF71E 0xB44F 0x0002 0x0000 0x0000 1500: 0xF71E 0xB44F 0x0003 0x0000 0x0000 1501: 0xF71E 0xB4CF 0x0002 0x0000 0x0000 1502: 0xF71E 0xB4CF 0x0003 0x0000 0x0000 1503: 0xF71E 0xB42F 0x0002 0x0000 0x0000 1504: 0xF71E 0xB42F 0x0003 0x0000 0x0000 1505: 0xF71E 0xB4AF 0x0002 0x0000 0x0000 1506: 0xF71E 0xB4AF 0x0003 0x0000 0x0000 1507: 0xF71E 0xB46F 0x0002 0x0000 0x0000 1508: 0xF71E 0xB46F 0x0003 0x0000 0x0000 1509: 0xF71E 0xB4EF 0x0002 0x0000 0x0000 1510: 0xF71E 0xB4EF 0x0003 0x0000 0x0000 1511: 0xF71E 0xB80F 0x0002 0x0000 0x0000 1512: 0xF71E 0xB80F 0x0003 0x0000 0x0000 1513: 0xF71E 0xB88F 0x0002 0x0000 0x0000 1514: 0xF71E 0xB88F 0x0003 0x0000 0x0000 1515: 0xF71E 0xB84F 0x0002 0x0000 0x0000 1516: 0xF71E 0xB84F 0x0003 0x0000 0x0000 1517: 0xF71E 0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 3 pins used: 27 not used: 39 1543 'test steps' 1576 lines M119 REV B 3 8-input NAND PINS Main menu Fri Jun 30 16:05:06 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:05:07 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 8 Main menu Fri Jun 30 16:05:15 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 16:05:29 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:05:30 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 54 Main menu Fri Jun 30 16:05:33 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 16:05:49 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 16:06:07 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 16:06:14 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:06:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 37 Main menu Fri Jun 30 16:06:24 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:12:40 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:12:42 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 20 Main menu Fri Jun 30 16:12:44 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:13:11 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:13:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 30 Main menu Fri Jun 30 16:13:15 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m169.tst reading test file: tests\m169.tst comment: ; M169 PCB REV B SCHEMATIC REV A comment: ; 4 AND-OR TREES (2-2-2-2) WITH 2 SETS OF ENABLES; EXTRA OR ON OUTPUT. comment: comment: ; PINS HEADER comment: ; PIN HEADER A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2D3D4 comment: ; EX EQUATION: A = A5-N OR (EN_A1B1 AND A1) comment: ; OR (EN_A2B2 AND A2) comment: ; OR (EN_A3B3 AND A3) comment: ; OR (EN_A4B4 AND A4) comment: pins: PINS pins: 1 I AC1 E1-13,E2-13 EN_A1B1 1-X-X-X 1-X-X-X pins: 2 I AD1 E1-1 A1 1-X-X-X pins: 3 I AD2 E1-10,E2-10 EN_A2B2 X-1-X-X X-1-X-X pins: 4 I AE1 E1-9 A2 X-1-X-X pins: 5 I AE2 E1-4,E2-4 EN_A3B3 X-X-1-X X-X-1-X pins: 6 I AF1 E1-5 A3 X-X-1-X pins: 7 I AF2 E1-2,E2-2 EN_A4B4 X-X-X-1 X-X-X-1 pins: 8 I AH1 E1-3 A4 X-X-X-1 pins: 9 I AB1 E3-12 A5-N pins: 10 O AA1 E3-11 OUTPUT A pins: 11 I AH2 E2-1 B1 1-X-X-X pins: 12 I AJ2 E2-9 B2 X-1-X-X pins: 13 I AK2 E2-5 B3 X-X-1-X pins: 14 I AL2 E2-3 B4 X-X-X-1 pins: 15 I AJ1 E3-9 B5-N pins: 16 O AK1 E3-8 OUTPUT B pins: 17 I AM2 E5-13,E4-13 EN_C1D1 1-X-X-X 1-X-X-X pins: 18 I AN1 E5-1 C1 1-X-X-X pins: 19 I AN2 E5-10,E4-10 EN_C2D2 X-1-X-X X-1-X-X pins: 20 I AP1 E5-9 C2 X-1-X-X pins: 21 I AP2 E5-4,E4-4 EN_C3D3 X-X-1-X X-X-1-X pins: 22 I AR1 E5-5 C3 X-X-1-X pins: 23 I AR2 E5-2,E4-2 EN_C4D4 X-X-X-1 X-X-X-1 pins: 24 I AS1 E1-3 C4 X-X-X-1 pins: 25 I AL1 E3-5 C5-N pins: 26 O AM1 E3-6 OUTPUT C pins: 27 I AS2 E4-1 D1 1-X-X-X pins: 28 I AT2 E4-9 D2 X-1-X-X pins: 29 I AU1 E4-5 D3 X-X-1-X pins: 30 I AV1 E4-3 D4 X-X-X-1 pins: 31 I AU2 E3-1 D5-N pins: 32 O AV2 E3-3 OUTPUT D pins: direction: IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO test 1: 00000000100000100000000010000010 comment: comment: ; TEST OUTPUT A TURNING ON test 2: 01 0 test 3: 11 1 test 4: 10 0 test 5: 00 0 test 6: 01 0 test 7: 11 1 test 8: 10 0 test 9: 00 0 test 10: 01 0 test 11: 11 1 test 12: 10 0 test 13: 00 0 test 14: 01 0 test 15: 11 1 test 16: 10 0 test 17: 00 0 test 18: 01 test 19: 11 1 test 20: 00 1 test 21: 10 test 22: 00000000100000100000000010000010 comment: ; TEST OUTPUT A NOT TURNING ON test 23: 1 0 test 24: 1 0 test 25: 1 0 test 26: 1 0 test 27: 0 0 test 28: 0 0 test 29: 0 0 test 30: 0 0 test 31: 1 0 test 32: 0 0 test 33: 00000000100000100000000010000010 comment: ;TEST OUTPUT B TURNING ON test 34: 0 1 0 test 35: 1 1 1 test 36: 1 0 0 test 37: 0 0 0 test 38: 0 1 0 test 39: 1 1 1 test 40: 1 0 0 test 41: 0 0 0 comment: test 42: 0 1 0 test 43: 1 1 1 test 44: 1 0 0 test 45: 0 0 0 comment: test 46: 0 1 0 test 47: 1 1 1 test 48: 1 0 0 test 49: 0 0 0 test 50: 01 test 51: 1 1 1 test 52: 0 0 1 test 53: 10 test 54: 00000000100000100000000010000010 comment: ; TEST OUTPUT B NOT TURNING ON test 55: 1 0 test 56: 1 0 test 57: 1 0 test 58: 1 0 test 59: 0 0 test 60: 0 0 test 61: 0 0 test 62: 0 0 test 63: 1 0 test 64: 0 0 test 65: 00000000100000100000000010000010 comment: ; TEST EN_A1B1 test 66: 10 00 0 test 67: 11 10 0 test 68: 11 11 1 test 69: 01 01 0 test 70: 11 11 1 test 71: 10 01 1 test 72: 10 00 0 test 73: 00 00 0 test 74: 00000000100000100000000010000010 comment: ; TEST EN_A2B2 test 75: 10 0 0 0 test 76: 11 1 0 0 test 77: 11 1 1 1 test 78: 01 0 1 0 test 79: 11 1 1 1 test 80: 10 0 1 1 test 81: 10 0 0 0 test 82: 00 0 0 0 test 83: 00000000100000100000000010000010 comment: ; TEST EN_A3B3 test 84: 10 0 0 0 test 85: 11 1 0 0 test 86: 11 1 1 1 test 87: 01 0 1 0 test 88: 11 1 1 1 test 89: 10 0 1 1 test 90: 10 0 0 0 test 91: 00 0 0 0 test 92: 00000000100000100000000010000010 comment: ; TEST EN_A4B4 test 93: 10 0 0 0 test 94: 11 1 0 0 test 95: 11 1 1 1 test 96: 01 0 1 0 test 97: 11 1 1 1 test 98: 10 0 1 1 test 99: 10 0 0 0 test 100: 00 0 0 0 test 101: 00000000100000100000000010000010 comment: ; TEST OUTPUT C TURNING ON test 102: 01 0 test 103: 11 1 test 104: 10 0 test 105: 00 0 test 106: 01 0 test 107: 11 1 test 108: 10 0 test 109: 00 0 test 110: 01 0 test 111: 11 1 test 112: 10 0 test 113: 00 0 test 114: 01 0 test 115: 11 1 test 116: 10 0 test 117: 00 0 test 118: 01 test 119: 11 1 test 120: 00 1 test 121: 10 test 122: 00000000100000100000000010000010 comment: ; TEST OUTPUT C NOT TURNING ON test 123: 1 0 test 124: 1 0 test 125: 1 0 test 126: 1 0 test 127: 0 0 test 128: 0 0 test 129: 0 0 test 130: 0 0 test 131: 1 0 test 132: 0 0 test 133: 00000000100000100000000010000010 comment: ; TEST OUTPUT D TURNING ON test 134: 0 1 0 test 135: 1 1 1 test 136: 1 0 0 test 137: 0 0 0 test 138: 0 1 0 test 139: 1 1 1 test 140: 1 0 0 test 141: 0 0 0 test 142: 0 1 0 test 143: 1 1 1 test 144: 1 0 0 test 145: 0 0 0 test 146: 0 1 0 test 147: 1 1 1 test 148: 1 0 0 test 149: 0 0 0 test 150: 01 test 151: 1 1 1 test 152: 0 0 1 test 153: 10 test 154: 00000000100000100000000010000010 comment: ; TEST OUTPUT D NOT TURNING ON test 155: 1 0 test 156: 1 0 test 157: 1 0 test 158: 1 0 test 159: 0 0 test 160: 0 0 test 161: 0 0 test 162: 0 0 test 163: 1 0 test 164: 0 0 test 165: 00000000100000100000000010000010 comment: ; TEST EN_C1D1 test 166: 10 00 0 test 167: 11 10 0 test 168: 11 11 1 test 169: 01 01 0 test 170: 11 11 1 test 171: 10 01 1 test 172: 10 00 0 test 173: 00 00 0 test 174: 00000000100000100000000010000010 comment: ; TEST EN_C2D2 test 175: 10 0 0 0 test 176: 11 1 0 0 test 177: 11 1 1 1 test 178: 01 0 1 0 test 179: 11 1 1 1 test 180: 10 0 1 1 test 181: 10 0 0 0 test 182: 00 0 0 0 test 183: 00000000100000100000000010000010 comment: ; TEST EN_C3D3 test 184: 10 0 0 0 test 185: 11 1 0 0 test 186: 11 1 1 1 test 187: 01 0 1 0 test 188: 11 1 1 1 test 189: 10 0 1 1 test 190: 10 0 0 0 test 191: 00 0 0 0 test 192: 00000000100000100000000010000010 comment: ; TEST EN_C4D4 test 193: 10 0 0 0 test 194: 11 1 0 0 test 195: 11 1 1 1 test 196: 01 0 1 0 test 197: 11 1 1 1 test 198: 10 0 1 1 test 199: 10 0 0 0 test 200: 00 0 0 0 test 201: 00000000100000100000000010000010 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x1000 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0800 column 5: offset 0, mask 0x0008 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0200 column 9: offset 0, mask 0x4000 column 10: offset 0, mask 0x8000 column 11: offset 0, mask 0x0002 column 12: offset 0, mask 0x0001 column 13: offset 1, mask 0x0001 column 14: offset 1, mask 0x0002 column 15: offset 0, mask 0x0100 column 16: offset 1, mask 0x8000 column 17: offset 1, mask 0x0004 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0800 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x4000 column 26: offset 1, mask 0x2000 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x80E0 0xA100 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4100 0x4000 0x0001 0x0000 0x0000 2: 0x5100 0x4000 0x0001 0x0000 0x0000 3: 0xF100 0x4000 0x0001 0x0000 0x0000 4: 0x6100 0x4000 0x0001 0x0000 0x0000 5: 0x4100 0x4000 0x0001 0x0000 0x0000 6: 0x4900 0x4000 0x0001 0x0000 0x0000 7: 0xC910 0x4000 0x0001 0x0000 0x0000 8: 0x4110 0x4000 0x0001 0x0000 0x0000 9: 0x4100 0x4000 0x0001 0x0000 0x0000 10: 0x4500 0x4000 0x0001 0x0000 0x0000 11: 0xC508 0x4000 0x0001 0x0000 0x0000 12: 0x4108 0x4000 0x0001 0x0000 0x0000 13: 0x4100 0x4000 0x0001 0x0000 0x0000 14: 0x4300 0x4000 0x0001 0x0000 0x0000 15: 0xC304 0x4000 0x0001 0x0000 0x0000 16: 0x4104 0x4000 0x0001 0x0000 0x0000 17: 0x4100 0x4000 0x0001 0x0000 0x0000 18: 0x8100 0x4000 0x0001 0x0000 0x0000 19: 0x8304 0x4000 0x0001 0x0000 0x0000 20: 0x8100 0x4000 0x0001 0x0000 0x0000 21: 0x4100 0x4000 0x0001 0x0000 0x0000 22: 0x4100 0x4000 0x0001 0x0000 0x0000 23: 0x5100 0x4000 0x0001 0x0000 0x0000 24: 0x5900 0x4000 0x0001 0x0000 0x0000 25: 0x5D00 0x4000 0x0001 0x0000 0x0000 26: 0x5F00 0x4000 0x0001 0x0000 0x0000 27: 0x5D00 0x4000 0x0001 0x0000 0x0000 28: 0x5900 0x4000 0x0001 0x0000 0x0000 29: 0x5100 0x4000 0x0001 0x0000 0x0000 30: 0x4100 0x4000 0x0001 0x0000 0x0000 31: 0x6100 0x4000 0x0001 0x0000 0x0000 32: 0x4100 0x4000 0x0001 0x0000 0x0000 33: 0x4100 0x4000 0x0001 0x0000 0x0000 34: 0x4102 0x4000 0x0001 0x0000 0x0000 35: 0x6102 0xC000 0x0001 0x0000 0x0000 36: 0x6100 0x4000 0x0001 0x0000 0x0000 37: 0x4100 0x4000 0x0001 0x0000 0x0000 38: 0x4101 0x4000 0x0001 0x0000 0x0000 39: 0x4111 0xC000 0x0001 0x0000 0x0000 40: 0x4110 0x4000 0x0001 0x0000 0x0000 41: 0x4100 0x4000 0x0001 0x0000 0x0000 42: 0x4100 0x4001 0x0001 0x0000 0x0000 43: 0x4108 0xC001 0x0001 0x0000 0x0000 44: 0x4108 0x4000 0x0001 0x0000 0x0000 45: 0x4100 0x4000 0x0001 0x0000 0x0000 46: 0x4100 0x4002 0x0001 0x0000 0x0000 47: 0x4104 0xC002 0x0001 0x0000 0x0000 48: 0x4104 0x4000 0x0001 0x0000 0x0000 49: 0x4100 0x4000 0x0001 0x0000 0x0000 50: 0x4000 0xC000 0x0001 0x0000 0x0000 51: 0x4004 0xC002 0x0001 0x0000 0x0000 52: 0x4000 0xC000 0x0001 0x0000 0x0000 53: 0x4100 0x4000 0x0001 0x0000 0x0000 54: 0x4100 0x4000 0x0001 0x0000 0x0000 55: 0x4102 0x4000 0x0001 0x0000 0x0000 56: 0x4103 0x4000 0x0001 0x0000 0x0000 57: 0x4103 0x4001 0x0001 0x0000 0x0000 58: 0x4103 0x4003 0x0001 0x0000 0x0000 59: 0x4103 0x4001 0x0001 0x0000 0x0000 60: 0x4103 0x4000 0x0001 0x0000 0x0000 61: 0x4102 0x4000 0x0001 0x0000 0x0000 62: 0x4100 0x4000 0x0001 0x0000 0x0000 63: 0x6100 0x4000 0x0001 0x0000 0x0000 64: 0x4100 0x4000 0x0001 0x0000 0x0000 65: 0x4100 0x4000 0x0001 0x0000 0x0000 66: 0x6100 0x4000 0x0001 0x0000 0x0000 67: 0xF100 0x4000 0x0001 0x0000 0x0000 68: 0xF102 0xC000 0x0001 0x0000 0x0000 69: 0x5102 0x4000 0x0001 0x0000 0x0000 70: 0xF102 0xC000 0x0001 0x0000 0x0000 71: 0x6102 0xC000 0x0001 0x0000 0x0000 72: 0x6100 0x4000 0x0001 0x0000 0x0000 73: 0x4100 0x4000 0x0001 0x0000 0x0000 74: 0x4100 0x4000 0x0001 0x0000 0x0000 75: 0x4110 0x4000 0x0001 0x0000 0x0000 76: 0xC910 0x4000 0x0001 0x0000 0x0000 77: 0xC911 0xC000 0x0001 0x0000 0x0000 78: 0x4901 0x4000 0x0001 0x0000 0x0000 79: 0xC911 0xC000 0x0001 0x0000 0x0000 80: 0x4111 0xC000 0x0001 0x0000 0x0000 81: 0x4110 0x4000 0x0001 0x0000 0x0000 82: 0x4100 0x4000 0x0001 0x0000 0x0000 83: 0x4100 0x4000 0x0001 0x0000 0x0000 84: 0x4108 0x4000 0x0001 0x0000 0x0000 85: 0xC508 0x4000 0x0001 0x0000 0x0000 86: 0xC508 0xC001 0x0001 0x0000 0x0000 87: 0x4500 0x4001 0x0001 0x0000 0x0000 88: 0xC508 0xC001 0x0001 0x0000 0x0000 89: 0x4108 0xC001 0x0001 0x0000 0x0000 90: 0x4108 0x4000 0x0001 0x0000 0x0000 91: 0x4100 0x4000 0x0001 0x0000 0x0000 92: 0x4100 0x4000 0x0001 0x0000 0x0000 93: 0x4104 0x4000 0x0001 0x0000 0x0000 94: 0xC304 0x4000 0x0001 0x0000 0x0000 95: 0xC304 0xC002 0x0001 0x0000 0x0000 96: 0x4300 0x4002 0x0001 0x0000 0x0000 97: 0xC304 0xC002 0x0001 0x0000 0x0000 98: 0x4104 0xC002 0x0001 0x0000 0x0000 99: 0x4104 0x4000 0x0001 0x0000 0x0000 100: 0x4100 0x4000 0x0001 0x0000 0x0000 101: 0x4100 0x4000 0x0001 0x0000 0x0000 102: 0x4100 0x5000 0x0001 0x0000 0x0000 103: 0x4100 0x7004 0x0001 0x0000 0x0000 104: 0x4100 0x4004 0x0001 0x0000 0x0000 105: 0x4100 0x4000 0x0001 0x0000 0x0000 106: 0x4100 0x4800 0x0001 0x0000 0x0000 107: 0x4100 0x6808 0x0001 0x0000 0x0000 108: 0x4100 0x4008 0x0001 0x0000 0x0000 109: 0x4100 0x4000 0x0001 0x0000 0x0000 110: 0x4100 0x4400 0x0001 0x0000 0x0000 111: 0x4100 0x6410 0x0001 0x0000 0x0000 112: 0x4100 0x4010 0x0001 0x0000 0x0000 113: 0x4100 0x4000 0x0001 0x0000 0x0000 114: 0x4100 0x4200 0x0001 0x0000 0x0000 115: 0x4100 0x6220 0x0001 0x0000 0x0000 116: 0x4100 0x4020 0x0001 0x0000 0x0000 117: 0x4100 0x4000 0x0001 0x0000 0x0000 118: 0x4100 0x2000 0x0001 0x0000 0x0000 119: 0x4100 0x2220 0x0001 0x0000 0x0000 120: 0x4100 0x2000 0x0001 0x0000 0x0000 121: 0x4100 0x4000 0x0001 0x0000 0x0000 122: 0x4100 0x4000 0x0001 0x0000 0x0000 123: 0x4100 0x5000 0x0001 0x0000 0x0000 124: 0x4100 0x5800 0x0001 0x0000 0x0000 125: 0x4100 0x5C00 0x0001 0x0000 0x0000 126: 0x4100 0x5E00 0x0001 0x0000 0x0000 127: 0x4100 0x5C00 0x0001 0x0000 0x0000 128: 0x4100 0x5800 0x0001 0x0000 0x0000 129: 0x4100 0x5000 0x0001 0x0000 0x0000 130: 0x4100 0x4000 0x0001 0x0000 0x0000 131: 0x4100 0x4004 0x0001 0x0000 0x0000 132: 0x4100 0x4000 0x0001 0x0000 0x0000 133: 0x4100 0x4000 0x0001 0x0000 0x0000 134: 0x4100 0x4040 0x0001 0x0000 0x0000 135: 0x4100 0x4044 0x0003 0x0000 0x0000 136: 0x4100 0x4004 0x0001 0x0000 0x0000 137: 0x4100 0x4000 0x0001 0x0000 0x0000 138: 0x4100 0x4080 0x0001 0x0000 0x0000 139: 0x4100 0x4088 0x0003 0x0000 0x0000 140: 0x4100 0x4008 0x0001 0x0000 0x0000 141: 0x4100 0x4000 0x0001 0x0000 0x0000 142: 0x4100 0x4000 0x8001 0x0000 0x0000 143: 0x4100 0x4010 0x8003 0x0000 0x0000 144: 0x4100 0x4010 0x0001 0x0000 0x0000 145: 0x4100 0x4000 0x0001 0x0000 0x0000 146: 0x4100 0x4000 0x4001 0x0000 0x0000 147: 0x4100 0x4020 0x4003 0x0000 0x0000 148: 0x4100 0x4020 0x0001 0x0000 0x0000 149: 0x4100 0x4000 0x0001 0x0000 0x0000 150: 0x4100 0x4000 0x0002 0x0000 0x0000 151: 0x4100 0x4020 0x4002 0x0000 0x0000 152: 0x4100 0x4000 0x0002 0x0000 0x0000 153: 0x4100 0x4000 0x0001 0x0000 0x0000 154: 0x4100 0x4000 0x0001 0x0000 0x0000 155: 0x4100 0x4040 0x0001 0x0000 0x0000 156: 0x4100 0x40C0 0x0001 0x0000 0x0000 157: 0x4100 0x40C0 0x8001 0x0000 0x0000 158: 0x4100 0x40C0 0xC001 0x0000 0x0000 159: 0x4100 0x40C0 0x8001 0x0000 0x0000 160: 0x4100 0x40C0 0x0001 0x0000 0x0000 161: 0x4100 0x4040 0x0001 0x0000 0x0000 162: 0x4100 0x4000 0x0001 0x0000 0x0000 163: 0x4100 0x4004 0x0001 0x0000 0x0000 164: 0x4100 0x4000 0x0001 0x0000 0x0000 165: 0x4100 0x4000 0x0001 0x0000 0x0000 166: 0x4100 0x4004 0x0001 0x0000 0x0000 167: 0x4100 0x7004 0x0001 0x0000 0x0000 168: 0x4100 0x7044 0x0003 0x0000 0x0000 169: 0x4100 0x5040 0x0001 0x0000 0x0000 170: 0x4100 0x7044 0x0003 0x0000 0x0000 171: 0x4100 0x4044 0x0003 0x0000 0x0000 172: 0x4100 0x4004 0x0001 0x0000 0x0000 173: 0x4100 0x4000 0x0001 0x0000 0x0000 174: 0x4100 0x4000 0x0001 0x0000 0x0000 175: 0x4100 0x4008 0x0001 0x0000 0x0000 176: 0x4100 0x6808 0x0001 0x0000 0x0000 177: 0x4100 0x6888 0x0003 0x0000 0x0000 178: 0x4100 0x4880 0x0001 0x0000 0x0000 179: 0x4100 0x6888 0x0003 0x0000 0x0000 180: 0x4100 0x4088 0x0003 0x0000 0x0000 181: 0x4100 0x4008 0x0001 0x0000 0x0000 182: 0x4100 0x4000 0x0001 0x0000 0x0000 183: 0x4100 0x4000 0x0001 0x0000 0x0000 184: 0x4100 0x4010 0x0001 0x0000 0x0000 185: 0x4100 0x6410 0x0001 0x0000 0x0000 186: 0x4100 0x6410 0x8003 0x0000 0x0000 187: 0x4100 0x4400 0x8001 0x0000 0x0000 188: 0x4100 0x6410 0x8003 0x0000 0x0000 189: 0x4100 0x4010 0x8003 0x0000 0x0000 190: 0x4100 0x4010 0x0001 0x0000 0x0000 191: 0x4100 0x4000 0x0001 0x0000 0x0000 192: 0x4100 0x4000 0x0001 0x0000 0x0000 193: 0x4100 0x4020 0x0001 0x0000 0x0000 194: 0x4100 0x6220 0x0001 0x0000 0x0000 195: 0x4100 0x6220 0x4003 0x0000 0x0000 196: 0x4100 0x4200 0x4001 0x0000 0x0000 197: 0x4100 0x6220 0x4003 0x0000 0x0000 198: 0x4100 0x4020 0x4003 0x0000 0x0000 199: 0x4100 0x4020 0x0001 0x0000 0x0000 200: 0x4100 0x4000 0x0001 0x0000 0x0000 201: 0x4100 0x4000 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OIIIIIIIOIOIIIIGIIP GIIIIIIIIIIIIIIO G P G UUT inputs: 28 UUT outputs: 4 pins used: 32 not used: 34 201 'test steps' 266 lines ; M169 PCB REV B SCHEMATIC REV A ; 4 AND-OR TREES (2-2-2-2) WITH 2 SETS OF ENABLES; EXTRA OR ON OUTPUT. ; PINS HEADER ; PIN HEADER A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2D3D4 ; EX EQUATION: A = A5-N OR (EN_A1B1 AND A1) ; OR (EN_A2B2 AND A2) ; OR (EN_A3B3 AND A3) ; OR (EN_A4B4 AND A4) PINS Main menu Fri Jun 30 16:13:36 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:13:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDDEEFFHBAHJKLJKMNNPPRRSLMSTUVUV SIDE 11212121112222112121212111221122 DIRECTION IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 35 Main menu Fri Jun 30 16:13:42 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:13:53 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDDEEFFHBAHJKLJKMNNPPRRSLMSTUVUV SIDE 11212121112222112121212111221122 DIRECTION IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 33 Main menu Fri Jun 30 16:13:57 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:14:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDDEEFFHBAHJKLJKMNNPPRRSLMSTUVUV SIDE 11212121112222112121212111221122 DIRECTION IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 28 Main menu Fri Jun 30 16:14:22 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m169.tst reading test file: tests\m169.tst comment: ; M169 PCB REV B SCHEMATIC REV A comment: ; 4 AND-OR TREES (2-2-2-2) WITH 2 SETS OF ENABLES; EXTRA OR ON OUTPUT. comment: comment: ; PINS HEADER comment: ; PIN HEADER A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2D3D4 comment: ; EX EQUATION: A = A5-N OR (EN_A1B1 AND A1) comment: ; OR (EN_A2B2 AND A2) comment: ; OR (EN_A3B3 AND A3) comment: ; OR (EN_A4B4 AND A4) comment: pins: PINS pins: 1 I AC1 E1-13,E2-13 EN_A1B1 1-X-X-X 1-X-X-X pins: 2 I AD1 E1-1 A1 1-X-X-X pins: 3 I AD2 E1-10,E2-10 EN_A2B2 X-1-X-X X-1-X-X pins: 4 I AE1 E1-9 A2 X-1-X-X pins: 5 I AE2 E1-4,E2-4 EN_A3B3 X-X-1-X X-X-1-X pins: 6 I AF1 E1-5 A3 X-X-1-X pins: 7 I AF2 E1-2,E2-2 EN_A4B4 X-X-X-1 X-X-X-1 pins: 8 I AH1 E1-3 A4 X-X-X-1 pins: 9 I AB1 E3-12 A5-N pins: 10 O AA1 E3-11 OUTPUT A pins: 11 I AH2 E2-1 B1 1-X-X-X pins: 12 I AJ2 E2-9 B2 X-1-X-X pins: 13 I AK2 E2-5 B3 X-X-1-X pins: 14 I AL2 E2-3 B4 X-X-X-1 pins: 15 I AJ1 E3-9 B5-N pins: 16 O AK1 E3-8 OUTPUT B pins: 17 I AM2 E5-13,E4-13 EN_C1D1 1-X-X-X 1-X-X-X pins: 18 I AN1 E5-1 C1 1-X-X-X pins: 19 I AN2 E5-10,E4-10 EN_C2D2 X-1-X-X X-1-X-X pins: 20 I AP1 E5-9 C2 X-1-X-X pins: 21 I AP2 E5-4,E4-4 EN_C3D3 X-X-1-X X-X-1-X pins: 22 I AR1 E5-5 C3 X-X-1-X pins: 23 I AR2 E5-2,E4-2 EN_C4D4 X-X-X-1 X-X-X-1 pins: 24 I AS1 E1-3 C4 X-X-X-1 pins: 25 I AL1 E3-5 C5-N pins: 26 O AM1 E3-6 OUTPUT C pins: 27 I AS2 E4-1 D1 1-X-X-X pins: 28 I AT2 E4-9 D2 X-1-X-X pins: 29 I AU1 E4-5 D3 X-X-1-X pins: 30 I AV1 E4-3 D4 X-X-X-1 pins: 31 I AU2 E3-1 D5-N pins: 32 O AV2 E3-3 OUTPUT D pins: direction: IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO test 1: 00000000100000100000000010000010 comment: comment: ; TEST OUTPUT A TURNING ON test 2: 01 0 test 3: 11 1 test 4: 10 0 test 5: 00 0 test 6: 01 0 test 7: 11 1 test 8: 10 0 test 9: 00 0 test 10: 01 0 test 11: 11 1 test 12: 10 0 test 13: 00 0 test 14: 01 0 test 15: 11 1 test 16: 10 0 test 17: 00 0 test 18: 01 test 19: 11 1 test 20: 00 1 test 21: 10 test 22: 00000000100000100000000010000010 comment: ; TEST OUTPUT A NOT TURNING ON test 23: 1 0 test 24: 1 0 test 25: 1 0 test 26: 1 0 test 27: 0 0 test 28: 0 0 test 29: 0 0 test 30: 0 0 test 31: 1 0 test 32: 0 0 test 33: 00000000100000100000000010000010 comment: ;TEST OUTPUT B TURNING ON test 34: 0 1 0 test 35: 1 1 1 test 36: 1 0 0 test 37: 0 0 0 test 38: 0 1 0 test 39: 1 1 1 test 40: 1 0 0 test 41: 0 0 0 comment: test 42: 0 1 0 test 43: 1 1 1 test 44: 1 0 0 test 45: 0 0 0 comment: test 46: 0 1 0 test 47: 1 1 1 test 48: 1 0 0 test 49: 0 0 0 test 50: 01 test 51: 1 1 1 test 52: 0 0 1 test 53: 10 test 54: 00000000100000100000000010000010 comment: ; TEST OUTPUT B NOT TURNING ON test 55: 1 0 test 56: 1 0 test 57: 1 0 test 58: 1 0 test 59: 0 0 test 60: 0 0 test 61: 0 0 test 62: 0 0 test 63: 1 0 test 64: 0 0 test 65: 00000000100000100000000010000010 comment: ; TEST EN_A1B1 test 66: 10 00 0 test 67: 11 10 0 test 68: 11 11 1 test 69: 01 01 0 test 70: 11 11 1 test 71: 10 01 1 test 72: 10 00 0 test 73: 00 00 0 test 74: 00000000100000100000000010000010 comment: ; TEST EN_A2B2 test 75: 10 0 0 0 test 76: 11 1 0 0 test 77: 11 1 1 1 test 78: 01 0 1 0 test 79: 11 1 1 1 test 80: 10 0 1 1 test 81: 10 0 0 0 test 82: 00 0 0 0 test 83: 00000000100000100000000010000010 comment: ; TEST EN_A3B3 test 84: 10 0 0 0 test 85: 11 1 0 0 test 86: 11 1 1 1 test 87: 01 0 1 0 test 88: 11 1 1 1 test 89: 10 0 1 1 test 90: 10 0 0 0 test 91: 00 0 0 0 test 92: 00000000100000100000000010000010 comment: ; TEST EN_A4B4 test 93: 10 0 0 0 test 94: 11 1 0 0 test 95: 11 1 1 1 test 96: 01 0 1 0 test 97: 11 1 1 1 test 98: 10 0 1 1 test 99: 10 0 0 0 test 100: 00 0 0 0 test 101: 00000000100000100000000010000010 comment: ; TEST OUTPUT C TURNING ON test 102: 01 0 test 103: 11 1 test 104: 10 0 test 105: 00 0 test 106: 01 0 test 107: 11 1 test 108: 10 0 test 109: 00 0 test 110: 01 0 test 111: 11 1 test 112: 10 0 test 113: 00 0 test 114: 01 0 test 115: 11 1 test 116: 10 0 test 117: 00 0 test 118: 01 test 119: 11 1 test 120: 00 1 test 121: 10 test 122: 00000000100000100000000010000010 comment: ; TEST OUTPUT C NOT TURNING ON test 123: 1 0 test 124: 1 0 test 125: 1 0 test 126: 1 0 test 127: 0 0 test 128: 0 0 test 129: 0 0 test 130: 0 0 test 131: 1 0 test 132: 0 0 test 133: 00000000100000100000000010000010 comment: ; TEST OUTPUT D TURNING ON test 134: 0 1 0 test 135: 1 1 1 test 136: 1 0 0 test 137: 0 0 0 test 138: 0 1 0 test 139: 1 1 1 test 140: 1 0 0 test 141: 0 0 0 test 142: 0 1 0 test 143: 1 1 1 test 144: 1 0 0 test 145: 0 0 0 test 146: 0 1 0 test 147: 1 1 1 test 148: 1 0 0 test 149: 0 0 0 test 150: 01 test 151: 1 1 1 test 152: 0 0 1 test 153: 10 test 154: 00000000100000100000000010000010 comment: ; TEST OUTPUT D NOT TURNING ON test 155: 1 0 test 156: 1 0 test 157: 1 0 test 158: 1 0 test 159: 0 0 test 160: 0 0 test 161: 0 0 test 162: 0 0 test 163: 1 0 test 164: 0 0 test 165: 00000000100000100000000010000010 comment: ; TEST EN_C1D1 test 166: 10 00 0 test 167: 11 10 0 test 168: 11 11 1 test 169: 01 01 0 test 170: 11 11 1 test 171: 10 01 1 test 172: 10 00 0 test 173: 00 00 0 test 174: 00000000100000100000000010000010 comment: ; TEST EN_C2D2 test 175: 10 0 0 0 test 176: 11 1 0 0 test 177: 11 1 1 1 test 178: 01 0 1 0 test 179: 11 1 1 1 test 180: 10 0 1 1 test 181: 10 0 0 0 test 182: 00 0 0 0 test 183: 00000000100000100000000010000010 comment: ; TEST EN_C3D3 test 184: 10 0 0 0 test 185: 11 1 0 0 test 186: 11 1 1 1 test 187: 01 0 1 0 test 188: 11 1 1 1 test 189: 10 0 1 1 test 190: 10 0 0 0 test 191: 00 0 0 0 test 192: 00000000100000100000000010000010 comment: ; TEST EN_C4D4 test 193: 10 0 0 0 test 194: 11 1 0 0 test 195: 11 1 1 1 test 196: 01 0 1 0 test 197: 11 1 1 1 test 198: 10 0 1 1 test 199: 10 0 0 0 test 200: 00 0 0 0 test 201: 00000000100000100000000010000010 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x1000 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0800 column 5: offset 0, mask 0x0008 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0200 column 9: offset 0, mask 0x4000 column 10: offset 0, mask 0x8000 column 11: offset 0, mask 0x0002 column 12: offset 0, mask 0x0001 column 13: offset 1, mask 0x0001 column 14: offset 1, mask 0x0002 column 15: offset 0, mask 0x0100 column 16: offset 1, mask 0x8000 column 17: offset 1, mask 0x0004 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0800 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x4000 column 26: offset 1, mask 0x2000 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x80E0 0xA100 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4100 0x4000 0x0001 0x0000 0x0000 2: 0x5100 0x4000 0x0001 0x0000 0x0000 3: 0xF100 0x4000 0x0001 0x0000 0x0000 4: 0x6100 0x4000 0x0001 0x0000 0x0000 5: 0x4100 0x4000 0x0001 0x0000 0x0000 6: 0x4900 0x4000 0x0001 0x0000 0x0000 7: 0xC910 0x4000 0x0001 0x0000 0x0000 8: 0x4110 0x4000 0x0001 0x0000 0x0000 9: 0x4100 0x4000 0x0001 0x0000 0x0000 10: 0x4500 0x4000 0x0001 0x0000 0x0000 11: 0xC508 0x4000 0x0001 0x0000 0x0000 12: 0x4108 0x4000 0x0001 0x0000 0x0000 13: 0x4100 0x4000 0x0001 0x0000 0x0000 14: 0x4300 0x4000 0x0001 0x0000 0x0000 15: 0xC304 0x4000 0x0001 0x0000 0x0000 16: 0x4104 0x4000 0x0001 0x0000 0x0000 17: 0x4100 0x4000 0x0001 0x0000 0x0000 18: 0x8100 0x4000 0x0001 0x0000 0x0000 19: 0x8304 0x4000 0x0001 0x0000 0x0000 20: 0x8100 0x4000 0x0001 0x0000 0x0000 21: 0x4100 0x4000 0x0001 0x0000 0x0000 22: 0x4100 0x4000 0x0001 0x0000 0x0000 23: 0x5100 0x4000 0x0001 0x0000 0x0000 24: 0x5900 0x4000 0x0001 0x0000 0x0000 25: 0x5D00 0x4000 0x0001 0x0000 0x0000 26: 0x5F00 0x4000 0x0001 0x0000 0x0000 27: 0x5D00 0x4000 0x0001 0x0000 0x0000 28: 0x5900 0x4000 0x0001 0x0000 0x0000 29: 0x5100 0x4000 0x0001 0x0000 0x0000 30: 0x4100 0x4000 0x0001 0x0000 0x0000 31: 0x6100 0x4000 0x0001 0x0000 0x0000 32: 0x4100 0x4000 0x0001 0x0000 0x0000 33: 0x4100 0x4000 0x0001 0x0000 0x0000 34: 0x4102 0x4000 0x0001 0x0000 0x0000 35: 0x6102 0xC000 0x0001 0x0000 0x0000 36: 0x6100 0x4000 0x0001 0x0000 0x0000 37: 0x4100 0x4000 0x0001 0x0000 0x0000 38: 0x4101 0x4000 0x0001 0x0000 0x0000 39: 0x4111 0xC000 0x0001 0x0000 0x0000 40: 0x4110 0x4000 0x0001 0x0000 0x0000 41: 0x4100 0x4000 0x0001 0x0000 0x0000 42: 0x4100 0x4001 0x0001 0x0000 0x0000 43: 0x4108 0xC001 0x0001 0x0000 0x0000 44: 0x4108 0x4000 0x0001 0x0000 0x0000 45: 0x4100 0x4000 0x0001 0x0000 0x0000 46: 0x4100 0x4002 0x0001 0x0000 0x0000 47: 0x4104 0xC002 0x0001 0x0000 0x0000 48: 0x4104 0x4000 0x0001 0x0000 0x0000 49: 0x4100 0x4000 0x0001 0x0000 0x0000 50: 0x4000 0xC000 0x0001 0x0000 0x0000 51: 0x4004 0xC002 0x0001 0x0000 0x0000 52: 0x4000 0xC000 0x0001 0x0000 0x0000 53: 0x4100 0x4000 0x0001 0x0000 0x0000 54: 0x4100 0x4000 0x0001 0x0000 0x0000 55: 0x4102 0x4000 0x0001 0x0000 0x0000 56: 0x4103 0x4000 0x0001 0x0000 0x0000 57: 0x4103 0x4001 0x0001 0x0000 0x0000 58: 0x4103 0x4003 0x0001 0x0000 0x0000 59: 0x4103 0x4001 0x0001 0x0000 0x0000 60: 0x4103 0x4000 0x0001 0x0000 0x0000 61: 0x4102 0x4000 0x0001 0x0000 0x0000 62: 0x4100 0x4000 0x0001 0x0000 0x0000 63: 0x6100 0x4000 0x0001 0x0000 0x0000 64: 0x4100 0x4000 0x0001 0x0000 0x0000 65: 0x4100 0x4000 0x0001 0x0000 0x0000 66: 0x6100 0x4000 0x0001 0x0000 0x0000 67: 0xF100 0x4000 0x0001 0x0000 0x0000 68: 0xF102 0xC000 0x0001 0x0000 0x0000 69: 0x5102 0x4000 0x0001 0x0000 0x0000 70: 0xF102 0xC000 0x0001 0x0000 0x0000 71: 0x6102 0xC000 0x0001 0x0000 0x0000 72: 0x6100 0x4000 0x0001 0x0000 0x0000 73: 0x4100 0x4000 0x0001 0x0000 0x0000 74: 0x4100 0x4000 0x0001 0x0000 0x0000 75: 0x4110 0x4000 0x0001 0x0000 0x0000 76: 0xC910 0x4000 0x0001 0x0000 0x0000 77: 0xC911 0xC000 0x0001 0x0000 0x0000 78: 0x4901 0x4000 0x0001 0x0000 0x0000 79: 0xC911 0xC000 0x0001 0x0000 0x0000 80: 0x4111 0xC000 0x0001 0x0000 0x0000 81: 0x4110 0x4000 0x0001 0x0000 0x0000 82: 0x4100 0x4000 0x0001 0x0000 0x0000 83: 0x4100 0x4000 0x0001 0x0000 0x0000 84: 0x4108 0x4000 0x0001 0x0000 0x0000 85: 0xC508 0x4000 0x0001 0x0000 0x0000 86: 0xC508 0xC001 0x0001 0x0000 0x0000 87: 0x4500 0x4001 0x0001 0x0000 0x0000 88: 0xC508 0xC001 0x0001 0x0000 0x0000 89: 0x4108 0xC001 0x0001 0x0000 0x0000 90: 0x4108 0x4000 0x0001 0x0000 0x0000 91: 0x4100 0x4000 0x0001 0x0000 0x0000 92: 0x4100 0x4000 0x0001 0x0000 0x0000 93: 0x4104 0x4000 0x0001 0x0000 0x0000 94: 0xC304 0x4000 0x0001 0x0000 0x0000 95: 0xC304 0xC002 0x0001 0x0000 0x0000 96: 0x4300 0x4002 0x0001 0x0000 0x0000 97: 0xC304 0xC002 0x0001 0x0000 0x0000 98: 0x4104 0xC002 0x0001 0x0000 0x0000 99: 0x4104 0x4000 0x0001 0x0000 0x0000 100: 0x4100 0x4000 0x0001 0x0000 0x0000 101: 0x4100 0x4000 0x0001 0x0000 0x0000 102: 0x4100 0x5000 0x0001 0x0000 0x0000 103: 0x4100 0x7004 0x0001 0x0000 0x0000 104: 0x4100 0x4004 0x0001 0x0000 0x0000 105: 0x4100 0x4000 0x0001 0x0000 0x0000 106: 0x4100 0x4800 0x0001 0x0000 0x0000 107: 0x4100 0x6808 0x0001 0x0000 0x0000 108: 0x4100 0x4008 0x0001 0x0000 0x0000 109: 0x4100 0x4000 0x0001 0x0000 0x0000 110: 0x4100 0x4400 0x0001 0x0000 0x0000 111: 0x4100 0x6410 0x0001 0x0000 0x0000 112: 0x4100 0x4010 0x0001 0x0000 0x0000 113: 0x4100 0x4000 0x0001 0x0000 0x0000 114: 0x4100 0x4200 0x0001 0x0000 0x0000 115: 0x4100 0x6220 0x0001 0x0000 0x0000 116: 0x4100 0x4020 0x0001 0x0000 0x0000 117: 0x4100 0x4000 0x0001 0x0000 0x0000 118: 0x4100 0x2000 0x0001 0x0000 0x0000 119: 0x4100 0x2220 0x0001 0x0000 0x0000 120: 0x4100 0x2000 0x0001 0x0000 0x0000 121: 0x4100 0x4000 0x0001 0x0000 0x0000 122: 0x4100 0x4000 0x0001 0x0000 0x0000 123: 0x4100 0x5000 0x0001 0x0000 0x0000 124: 0x4100 0x5800 0x0001 0x0000 0x0000 125: 0x4100 0x5C00 0x0001 0x0000 0x0000 126: 0x4100 0x5E00 0x0001 0x0000 0x0000 127: 0x4100 0x5C00 0x0001 0x0000 0x0000 128: 0x4100 0x5800 0x0001 0x0000 0x0000 129: 0x4100 0x5000 0x0001 0x0000 0x0000 130: 0x4100 0x4000 0x0001 0x0000 0x0000 131: 0x4100 0x4004 0x0001 0x0000 0x0000 132: 0x4100 0x4000 0x0001 0x0000 0x0000 133: 0x4100 0x4000 0x0001 0x0000 0x0000 134: 0x4100 0x4040 0x0001 0x0000 0x0000 135: 0x4100 0x4044 0x0003 0x0000 0x0000 136: 0x4100 0x4004 0x0001 0x0000 0x0000 137: 0x4100 0x4000 0x0001 0x0000 0x0000 138: 0x4100 0x4080 0x0001 0x0000 0x0000 139: 0x4100 0x4088 0x0003 0x0000 0x0000 140: 0x4100 0x4008 0x0001 0x0000 0x0000 141: 0x4100 0x4000 0x0001 0x0000 0x0000 142: 0x4100 0x4000 0x8001 0x0000 0x0000 143: 0x4100 0x4010 0x8003 0x0000 0x0000 144: 0x4100 0x4010 0x0001 0x0000 0x0000 145: 0x4100 0x4000 0x0001 0x0000 0x0000 146: 0x4100 0x4000 0x4001 0x0000 0x0000 147: 0x4100 0x4020 0x4003 0x0000 0x0000 148: 0x4100 0x4020 0x0001 0x0000 0x0000 149: 0x4100 0x4000 0x0001 0x0000 0x0000 150: 0x4100 0x4000 0x0002 0x0000 0x0000 151: 0x4100 0x4020 0x4002 0x0000 0x0000 152: 0x4100 0x4000 0x0002 0x0000 0x0000 153: 0x4100 0x4000 0x0001 0x0000 0x0000 154: 0x4100 0x4000 0x0001 0x0000 0x0000 155: 0x4100 0x4040 0x0001 0x0000 0x0000 156: 0x4100 0x40C0 0x0001 0x0000 0x0000 157: 0x4100 0x40C0 0x8001 0x0000 0x0000 158: 0x4100 0x40C0 0xC001 0x0000 0x0000 159: 0x4100 0x40C0 0x8001 0x0000 0x0000 160: 0x4100 0x40C0 0x0001 0x0000 0x0000 161: 0x4100 0x4040 0x0001 0x0000 0x0000 162: 0x4100 0x4000 0x0001 0x0000 0x0000 163: 0x4100 0x4004 0x0001 0x0000 0x0000 164: 0x4100 0x4000 0x0001 0x0000 0x0000 165: 0x4100 0x4000 0x0001 0x0000 0x0000 166: 0x4100 0x4004 0x0001 0x0000 0x0000 167: 0x4100 0x7004 0x0001 0x0000 0x0000 168: 0x4100 0x7044 0x0003 0x0000 0x0000 169: 0x4100 0x5040 0x0001 0x0000 0x0000 170: 0x4100 0x7044 0x0003 0x0000 0x0000 171: 0x4100 0x4044 0x0003 0x0000 0x0000 172: 0x4100 0x4004 0x0001 0x0000 0x0000 173: 0x4100 0x4000 0x0001 0x0000 0x0000 174: 0x4100 0x4000 0x0001 0x0000 0x0000 175: 0x4100 0x4008 0x0001 0x0000 0x0000 176: 0x4100 0x6808 0x0001 0x0000 0x0000 177: 0x4100 0x6888 0x0003 0x0000 0x0000 178: 0x4100 0x4880 0x0001 0x0000 0x0000 179: 0x4100 0x6888 0x0003 0x0000 0x0000 180: 0x4100 0x4088 0x0003 0x0000 0x0000 181: 0x4100 0x4008 0x0001 0x0000 0x0000 182: 0x4100 0x4000 0x0001 0x0000 0x0000 183: 0x4100 0x4000 0x0001 0x0000 0x0000 184: 0x4100 0x4010 0x0001 0x0000 0x0000 185: 0x4100 0x6410 0x0001 0x0000 0x0000 186: 0x4100 0x6410 0x8003 0x0000 0x0000 187: 0x4100 0x4400 0x8001 0x0000 0x0000 188: 0x4100 0x6410 0x8003 0x0000 0x0000 189: 0x4100 0x4010 0x8003 0x0000 0x0000 190: 0x4100 0x4010 0x0001 0x0000 0x0000 191: 0x4100 0x4000 0x0001 0x0000 0x0000 192: 0x4100 0x4000 0x0001 0x0000 0x0000 193: 0x4100 0x4020 0x0001 0x0000 0x0000 194: 0x4100 0x6220 0x0001 0x0000 0x0000 195: 0x4100 0x6220 0x4003 0x0000 0x0000 196: 0x4100 0x4200 0x4001 0x0000 0x0000 197: 0x4100 0x6220 0x4003 0x0000 0x0000 198: 0x4100 0x4020 0x4003 0x0000 0x0000 199: 0x4100 0x4020 0x0001 0x0000 0x0000 200: 0x4100 0x4000 0x0001 0x0000 0x0000 201: 0x4100 0x4000 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OIIIIIIIOIOIIIIGIIP GIIIIIIIIIIIIIIO G P G UUT inputs: 28 UUT outputs: 4 pins used: 32 not used: 34 201 'test steps' 266 lines ; M169 PCB REV B SCHEMATIC REV A ; 4 AND-OR TREES (2-2-2-2) WITH 2 SETS OF ENABLES; EXTRA OR ON OUTPUT. ; PINS HEADER ; PIN HEADER A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2D3D4 ; EX EQUATION: A = A5-N OR (EN_A1B1 AND A1) ; OR (EN_A2B2 AND A2) ; OR (EN_A3B3 AND A3) ; OR (EN_A4B4 AND A4) PINS Main menu Fri Jun 30 16:14:45 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:14:52 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDDEEFFHBAHJKLJKMNNPPRRSLMSTUVUV SIDE 11212121112222112121212111221122 DIRECTION IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 29 Main menu Fri Jun 30 16:14:56 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:15:07 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDDEEFFHBAHJKLJKMNNPPRRSLMSTUVUV SIDE 11212121112222112121212111221122 DIRECTION IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 19 Main menu Fri Jun 30 16:15:09 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:15:26 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDDEEFFHBAHJKLJKMNNPPRRSLMSTUVUV SIDE 11212121112222112121212111221122 DIRECTION IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 29 Main menu Fri Jun 30 16:15:29 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:15:51 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:15:58 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:16:02 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 97 Main menu Fri Jun 30 16:16:08 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:16:25 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:16:28 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 16:16:28 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:16:32 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 92 Main menu Fri Jun 30 16:16:37 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 16:16:55 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:16:58 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 60 Main menu Fri Jun 30 16:17:06 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m212.tst reading test file: tests\m212.tst comment: ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER comment: comment: ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) comment: pins: PINS pins: 1 I AB1 E3-4,10;E6-4,10;E9-4,10 CLEAR-N CLEARS FF0 THRU FF5 pins: 2 I AL2 E1-3 INA0-N pins: 3 I AM2 E2-2 INA1-N pins: 4 I AN2 E4-2 INA2-N pins: 5 I AR2 E5-2 INA3-N pins: 6 I AV1 E7-2 INA4-N pins: 7 I AV2 E8-2 INA5-N pins: 8 I AN1 ENABLE_INPUT_A pins: 9 I AP2 E1-4 INB0-N pins: 10 I AR1 E2-4 INB1-N pins: 11 I AS1 E4-4 INB2-N pins: 12 I AU1 E5-4 INB3-N pins: 13 I AA1 E7-4 INB4-N pins: 14 I AT2 E8-4 INB5-N pins: 15 I AU2 ENABLE_INPUT_B pins: 16 I AM1 E1-1 SHIFT_R_INSERT-N RIGHT SHIFTS INTO FF0 pins: 17 I AL1 ENABLE_R_SHIFT pins: 18 I AS2 E8-9 SHIFT_L_INSERT-N LEFT SHIFTS INTO FF5 pins: 19 I AP1 ENABLE_L_SHIFT pins: 20 I AC1 E3-3,11;E6-3,11;E9-3,11 CLOCK (RISING EDGE) pins: 21 O AD1 E3-6 FF0 pins: 22 O AD2 E3-5 FF0-N pins: 23 O AF1 E3-8 FF1 pins: 24 O AE1 E3-9 FF1-N pins: 25 O AH2 E6-6 FF2 pins: 26 O AE2 E6-5 FF2-N pins: 27 O AH1 E6-8 FF3 pins: 28 O AF2 E6-9 FF3-N pins: 29 O AK2 E9-6 FF4 pins: 30 O AJ2 E9-5 FF4-N pins: 31 O AK1 E9-8 FF5 pins: 32 O AJ1 A9-9 FF5-N pins: direction: IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO comment: ; CLEAR-N, NO ENABLES test 1: 01111110111111010100010101010101 test 2: 1 comment: comment: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM comment: ; see mk_m212_ld_shift.c comment: comment: comment: ; TEST A INPUTS, GRAY CODE PATTERN comment: comment: ; ENABLE A INPUTS test 3: 1 comment: ; LOAD FFs FROM INPUT A comment: test 4: 000001 test 5: 1010101010110 test 6: 0 test 7: 000011 test 8: 1010101011010 test 9: 0 test 10: 000010 test 11: 1010101011001 test 12: 0 test 13: 000110 test 14: 1010101101001 test 15: 0 test 16: 000111 test 17: 1010101101010 test 18: 0 test 19: 000101 test 20: 1010101100110 test 21: 0 test 22: 000100 test 23: 1010101100101 test 24: 0 test 25: 001100 test 26: 1010110100101 test 27: 0 test 28: 001101 test 29: 1010110100110 test 30: 0 test 31: 001111 test 32: 1010110101010 test 33: 0 test 34: 001110 test 35: 1010110101001 test 36: 0 test 37: 001010 test 38: 1010110011001 test 39: 0 test 40: 001011 test 41: 1010110011010 test 42: 0 test 43: 001001 test 44: 1010110010110 test 45: 0 test 46: 001000 test 47: 1010110010101 test 48: 0 test 49: 011000 test 50: 1011010010101 test 51: 0 test 52: 011001 test 53: 1011010010110 test 54: 0 test 55: 011011 test 56: 1011010011010 test 57: 0 test 58: 011010 test 59: 1011010011001 test 60: 0 test 61: 011110 test 62: 1011010101001 test 63: 0 test 64: 011111 test 65: 1011010101010 test 66: 0 test 67: 011101 test 68: 1011010100110 test 69: 0 test 70: 011100 test 71: 1011010100101 test 72: 0 test 73: 010100 test 74: 1011001100101 test 75: 0 test 76: 010101 test 77: 1011001100110 test 78: 0 test 79: 010111 test 80: 1011001101010 test 81: 0 test 82: 010110 test 83: 1011001101001 test 84: 0 test 85: 010010 test 86: 1011001011001 test 87: 0 test 88: 010011 test 89: 1011001011010 test 90: 0 test 91: 010001 test 92: 1011001010110 test 93: 0 test 94: 010000 test 95: 1011001010101 test 96: 0 test 97: 110000 test 98: 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1011001101001 test 1166: 0 10 test 1167: 1100110100101 test 1168: 00 test 1169: 0100101 test 1170: 1011001011001 test 1171: 0 10 test 1172: 1100101100101 test 1173: 00 test 1174: 0100111 test 1175: 1011001011010 test 1176: 0 10 test 1177: 1100101101001 test 1178: 00 test 1179: 0100011 test 1180: 1011001010110 test 1181: 0 10 test 1182: 1100101011001 test 1183: 00 test 1184: 0100001 test 1185: 1011001010101 test 1186: 0 10 test 1187: 1100101010101 test 1188: 00 test 1189: 1100001 test 1190: 1101001010101 test 1191: 0 10 test 1192: 1100101010101 test 1193: 00 test 1194: 1100011 test 1195: 1101001010110 test 1196: 0 10 test 1197: 1100101011001 test 1198: 00 test 1199: 1100111 test 1200: 1101001011010 test 1201: 0 10 test 1202: 1100101101001 test 1203: 00 test 1204: 1100101 test 1205: 1101001011001 test 1206: 0 10 test 1207: 1100101100101 test 1208: 00 test 1209: 1101101 test 1210: 1101001101001 test 1211: 0 10 test 1212: 1100110100101 test 1213: 00 test 1214: 1101111 test 1215: 1101001101010 test 1216: 0 10 test 1217: 1100110101001 test 1218: 00 test 1219: 1101011 test 1220: 1101001100110 test 1221: 0 10 test 1222: 1100110011001 test 1223: 00 test 1224: 1101001 test 1225: 1101001100101 test 1226: 0 10 test 1227: 1100110010101 test 1228: 00 test 1229: 1111001 test 1230: 1101010100101 test 1231: 0 10 test 1232: 1101010010101 test 1233: 00 test 1234: 1111011 test 1235: 1101010100110 test 1236: 0 10 test 1237: 1101010011001 test 1238: 00 test 1239: 1111111 test 1240: 1101010101010 test 1241: 0 10 test 1242: 1101010101001 test 1243: 00 test 1244: 1111101 test 1245: 1101010101001 test 1246: 0 10 test 1247: 1101010100101 test 1248: 00 test 1249: 1110101 test 1250: 1101010011001 test 1251: 0 10 test 1252: 1101001100101 test 1253: 00 test 1254: 1110111 test 1255: 1101010011010 test 1256: 0 10 test 1257: 1101001101001 test 1258: 00 test 1259: 1110011 test 1260: 1101010010110 test 1261: 0 10 test 1262: 1101001011001 test 1263: 00 test 1264: 1110001 test 1265: 1101010010101 test 1266: 0 10 test 1267: 1101001010101 test 1268: 00 test 1269: 1010001 test 1270: 1100110010101 test 1271: 0 10 test 1272: 1011001010101 test 1273: 00 test 1274: 1010011 test 1275: 1100110010110 test 1276: 0 10 test 1277: 1011001011001 test 1278: 00 test 1279: 1010111 test 1280: 1100110011010 test 1281: 0 10 test 1282: 1011001101001 test 1283: 00 test 1284: 1010101 test 1285: 1100110011001 test 1286: 0 10 test 1287: 1011001100101 test 1288: 00 test 1289: 1011101 test 1290: 1100110101001 test 1291: 0 10 test 1292: 1011010100101 test 1293: 00 test 1294: 1011111 test 1295: 1100110101010 test 1296: 0 10 test 1297: 1011010101001 test 1298: 00 test 1299: 1011011 test 1300: 1100110100110 test 1301: 0 10 test 1302: 1011010011001 test 1303: 00 test 1304: 1011001 test 1305: 1100110100101 test 1306: 0 10 test 1307: 1011010010101 test 1308: 00 test 1309: 1001001 test 1310: 1100101100101 test 1311: 0 10 test 1312: 1010110010101 test 1313: 00 test 1314: 1001011 test 1315: 1100101100110 test 1316: 0 10 test 1317: 1010110011001 test 1318: 00 test 1319: 1001111 test 1320: 1100101101010 test 1321: 0 10 test 1322: 1010110101001 test 1323: 00 test 1324: 1001101 test 1325: 1100101101001 test 1326: 0 10 test 1327: 1010110100101 test 1328: 00 test 1329: 1000101 test 1330: 1100101011001 test 1331: 0 10 test 1332: 1010101100101 test 1333: 00 test 1334: 1000111 test 1335: 1100101011010 test 1336: 0 10 test 1337: 1010101101001 test 1338: 00 test 1339: 1000011 test 1340: 1100101010110 test 1341: 0 10 test 1342: 1010101011001 test 1343: 00 test 1344: 1000001 test 1345: 1100101010101 test 1346: 0 10 test 1347: 1010101010101 test 1348: 00 test 1349: 0000001 test 1350: 1010101010101 test 1351: 0 10 test 1352: 1010101010101 test 1353: 00 comment: comment: comment: ; TEST SHIFT L (LOAD VIA A INPUTS) comment: comment: ; SHIFT IN A ONE test 1354: 1 comment: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS comment: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT test 1355: 0000011 test 1356: 1010101010110 test 1357: 0 10 test 1358: 1010101011010 test 1359: 00 test 1360: 0000111 test 1361: 1010101011010 test 1362: 0 10 test 1363: 1010101101010 test 1364: 00 test 1365: 0000101 test 1366: 1010101011001 test 1367: 0 10 test 1368: 1010101100110 test 1369: 00 test 1370: 0001101 test 1371: 1010101101001 test 1372: 0 10 test 1373: 1010110100110 test 1374: 00 test 1375: 0001111 test 1376: 1010101101010 test 1377: 0 10 test 1378: 1010110101010 test 1379: 00 test 1380: 0001011 test 1381: 1010101100110 test 1382: 0 10 test 1383: 1010110011010 test 1384: 00 test 1385: 0001001 test 1386: 1010101100101 test 1387: 0 10 test 1388: 1010110010110 test 1389: 00 test 1390: 0011001 test 1391: 1010110100101 test 1392: 0 10 test 1393: 1011010010110 test 1394: 00 test 1395: 0011011 test 1396: 1010110100110 test 1397: 0 10 test 1398: 1011010011010 test 1399: 00 test 1400: 0011111 test 1401: 1010110101010 test 1402: 0 10 test 1403: 1011010101010 test 1404: 00 test 1405: 0011101 test 1406: 1010110101001 test 1407: 0 10 test 1408: 1011010100110 test 1409: 00 test 1410: 0010101 test 1411: 1010110011001 test 1412: 0 10 test 1413: 1011001100110 test 1414: 00 test 1415: 0010111 test 1416: 1010110011010 test 1417: 0 10 test 1418: 1011001101010 test 1419: 00 test 1420: 0010011 test 1421: 1010110010110 test 1422: 0 10 test 1423: 1011001011010 test 1424: 00 test 1425: 0010001 test 1426: 1010110010101 test 1427: 0 10 test 1428: 1011001010110 test 1429: 00 test 1430: 0110001 test 1431: 1011010010101 test 1432: 0 10 test 1433: 1101001010110 test 1434: 00 test 1435: 0110011 test 1436: 1011010010110 test 1437: 0 10 test 1438: 1101001011010 test 1439: 00 test 1440: 0110111 test 1441: 1011010011010 test 1442: 0 10 test 1443: 1101001101010 test 1444: 00 test 1445: 0110101 test 1446: 1011010011001 test 1447: 0 10 test 1448: 1101001100110 test 1449: 00 test 1450: 0111101 test 1451: 1011010101001 test 1452: 0 10 test 1453: 1101010100110 test 1454: 00 test 1455: 0111111 test 1456: 1011010101010 test 1457: 0 10 test 1458: 1101010101010 test 1459: 00 test 1460: 0111011 test 1461: 1011010100110 test 1462: 0 10 test 1463: 1101010011010 test 1464: 00 test 1465: 0111001 test 1466: 1011010100101 test 1467: 0 10 test 1468: 1101010010110 test 1469: 00 test 1470: 0101001 test 1471: 1011001100101 test 1472: 0 10 test 1473: 1100110010110 test 1474: 00 test 1475: 0101011 test 1476: 1011001100110 test 1477: 0 10 test 1478: 1100110011010 test 1479: 00 test 1480: 0101111 test 1481: 1011001101010 test 1482: 0 10 test 1483: 1100110101010 test 1484: 00 test 1485: 0101101 test 1486: 1011001101001 test 1487: 0 10 test 1488: 1100110100110 test 1489: 00 test 1490: 0100101 test 1491: 1011001011001 test 1492: 0 10 test 1493: 1100101100110 test 1494: 00 test 1495: 0100111 test 1496: 1011001011010 test 1497: 0 10 test 1498: 1100101101010 test 1499: 00 test 1500: 0100011 test 1501: 1011001010110 test 1502: 0 10 test 1503: 1100101011010 test 1504: 00 test 1505: 0100001 test 1506: 1011001010101 test 1507: 0 10 test 1508: 1100101010110 test 1509: 00 test 1510: 1100001 test 1511: 1101001010101 test 1512: 0 10 test 1513: 1100101010110 test 1514: 00 test 1515: 1100011 test 1516: 1101001010110 test 1517: 0 10 test 1518: 1100101011010 test 1519: 00 test 1520: 1100111 test 1521: 1101001011010 test 1522: 0 10 test 1523: 1100101101010 test 1524: 00 test 1525: 1100101 test 1526: 1101001011001 test 1527: 0 10 test 1528: 1100101100110 test 1529: 00 test 1530: 1101101 test 1531: 1101001101001 test 1532: 0 10 test 1533: 1100110100110 test 1534: 00 test 1535: 1101111 test 1536: 1101001101010 test 1537: 0 10 test 1538: 1100110101010 test 1539: 00 test 1540: 1101011 test 1541: 1101001100110 test 1542: 0 10 test 1543: 1100110011010 test 1544: 00 test 1545: 1101001 test 1546: 1101001100101 test 1547: 0 10 test 1548: 1100110010110 test 1549: 00 test 1550: 1111001 test 1551: 1101010100101 test 1552: 0 10 test 1553: 1101010010110 test 1554: 00 test 1555: 1111011 test 1556: 1101010100110 test 1557: 0 10 test 1558: 1101010011010 test 1559: 00 test 1560: 1111111 test 1561: 1101010101010 test 1562: 0 10 test 1563: 1101010101010 test 1564: 00 test 1565: 1111101 test 1566: 1101010101001 test 1567: 0 10 test 1568: 1101010100110 test 1569: 00 test 1570: 1110101 test 1571: 1101010011001 test 1572: 0 10 test 1573: 1101001100110 test 1574: 00 test 1575: 1110111 test 1576: 1101010011010 test 1577: 0 10 test 1578: 1101001101010 test 1579: 00 test 1580: 1110011 test 1581: 1101010010110 test 1582: 0 10 test 1583: 1101001011010 test 1584: 00 test 1585: 1110001 test 1586: 1101010010101 test 1587: 0 10 test 1588: 1101001010110 test 1589: 00 test 1590: 1010001 test 1591: 1100110010101 test 1592: 0 10 test 1593: 1011001010110 test 1594: 00 test 1595: 1010011 test 1596: 1100110010110 test 1597: 0 10 test 1598: 1011001011010 test 1599: 00 test 1600: 1010111 test 1601: 1100110011010 test 1602: 0 10 test 1603: 1011001101010 test 1604: 00 test 1605: 1010101 test 1606: 1100110011001 test 1607: 0 10 test 1608: 1011001100110 test 1609: 00 test 1610: 1011101 test 1611: 1100110101001 test 1612: 0 10 test 1613: 1011010100110 test 1614: 00 test 1615: 1011111 test 1616: 1100110101010 test 1617: 0 10 test 1618: 1011010101010 test 1619: 00 test 1620: 1011011 test 1621: 1100110100110 test 1622: 0 10 test 1623: 1011010011010 test 1624: 00 test 1625: 1011001 test 1626: 1100110100101 test 1627: 0 10 test 1628: 1011010010110 test 1629: 00 test 1630: 1001001 test 1631: 1100101100101 test 1632: 0 10 test 1633: 1010110010110 test 1634: 00 test 1635: 1001011 test 1636: 1100101100110 test 1637: 0 10 test 1638: 1010110011010 test 1639: 00 test 1640: 1001111 test 1641: 1100101101010 test 1642: 0 10 test 1643: 1010110101010 test 1644: 00 test 1645: 1001101 test 1646: 1100101101001 test 1647: 0 10 test 1648: 1010110100110 test 1649: 00 test 1650: 1000101 test 1651: 1100101011001 test 1652: 0 10 test 1653: 1010101100110 test 1654: 00 test 1655: 1000111 test 1656: 1100101011010 test 1657: 0 10 test 1658: 1010101101010 test 1659: 00 test 1660: 1000011 test 1661: 1100101010110 test 1662: 0 10 test 1663: 1010101011010 test 1664: 00 test 1665: 1000001 test 1666: 1100101010101 test 1667: 0 10 test 1668: 1010101010110 test 1669: 00 test 1670: 0000001 test 1671: 1010101010101 test 1672: 0 10 test 1673: 1010101010110 test 1674: 00 comment: comment: comment: ; end of SECTION GENERATED BY A PROGRAM comment: comment: comment: ; CLEAR FFs test 1675: 0 010101010101 test 1676: 1 comment: test 1677: 11111110111111010100010101010101 comment: end: END summary column 1: offset 0, mask 0x4000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0020 column 6: offset 2, mask 0x4000 column 7: offset 2, mask 0x0002 column 8: offset 1, mask 0x1000 column 9: offset 1, mask 0x0010 column 10: offset 1, mask 0x0400 column 11: offset 1, mask 0x0200 column 12: offset 2, mask 0x8000 column 13: offset 0, mask 0x8000 column 14: offset 1, mask 0x0080 column 15: offset 2, mask 0x0001 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x4000 column 18: offset 1, mask 0x0040 column 19: offset 1, mask 0x0800 column 20: offset 0, mask 0x2000 column 21: offset 0, mask 0x1000 column 22: offset 0, mask 0x0010 column 23: offset 0, mask 0x0400 column 24: offset 0, mask 0x0800 column 25: offset 0, mask 0x0002 column 26: offset 0, mask 0x0008 column 27: offset 0, mask 0x0200 column 28: offset 0, mask 0x0004 column 29: offset 1, mask 0x0001 column 30: offset 0, mask 0x0001 column 31: offset 1, mask 0x8000 column 32: offset 0, mask 0x0100 direction bits (1=input) 0x1FFF 0x8101 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x891D 0x26FE 0xC002 0x0000 0x0000 2: 0xC91D 0x26FE 0xC002 0x0000 0x0000 3: 0xC91D 0x36FE 0xC002 0x0000 0x0000 4: 0xC91D 0x36D0 0x8002 0x0000 0x0000 5: 0xE81D 0xB6D0 0x8002 0x0000 0x0000 6: 0xC81D 0xB6D0 0x8002 0x0000 0x0000 7: 0xC81D 0xB6D0 0xC002 0x0000 0x0000 8: 0xE81C 0xB6D1 0xC002 0x0000 0x0000 9: 0xC81C 0xB6D1 0xC002 0x0000 0x0000 10: 0xC81C 0xB6D1 0xC000 0x0000 0x0000 11: 0xE91C 0x36D1 0xC000 0x0000 0x0000 12: 0xC91C 0x36D1 0xC000 0x0000 0x0000 13: 0xC91C 0x36F1 0xC000 0x0000 0x0000 14: 0xEB18 0x36F1 0xC000 0x0000 0x0000 15: 0xCB18 0x36F1 0xC000 0x0000 0x0000 16: 0xCB18 0x36F1 0xC002 0x0000 0x0000 17: 0xEA18 0xB6F1 0xC002 0x0000 0x0000 18: 0xCA18 0xB6F1 0xC002 0x0000 0x0000 19: 0xCA18 0xB6F1 0x8002 0x0000 0x0000 20: 0xEA19 0xB6F0 0x8002 0x0000 0x0000 21: 0xCA19 0xB6F0 0x8002 0x0000 0x0000 22: 0xCA19 0xB6F0 0x8000 0x0000 0x0000 23: 0xEB19 0x36F0 0x8000 0x0000 0x0000 24: 0xCB19 0x36F0 0x8000 0x0000 0x0000 25: 0xCB19 0x36F8 0x8000 0x0000 0x0000 26: 0xEB13 0x36F8 0x8000 0x0000 0x0000 27: 0xCB13 0x36F8 0x8000 0x0000 0x0000 28: 0xCB13 0x36F8 0x8002 0x0000 0x0000 29: 0xEA13 0xB6F8 0x8002 0x0000 0x0000 30: 0xCA13 0xB6F8 0x8002 0x0000 0x0000 31: 0xCA13 0xB6F8 0xC002 0x0000 0x0000 32: 0xEA12 0xB6F9 0xC002 0x0000 0x0000 33: 0xCA12 0xB6F9 0xC002 0x0000 0x0000 34: 0xCA12 0xB6F9 0xC000 0x0000 0x0000 35: 0xEB12 0x36F9 0xC000 0x0000 0x0000 36: 0xCB12 0x36F9 0xC000 0x0000 0x0000 37: 0xCB12 0x36D9 0xC000 0x0000 0x0000 38: 0xE916 0x36D9 0xC000 0x0000 0x0000 39: 0xC916 0x36D9 0xC000 0x0000 0x0000 40: 0xC916 0x36D9 0xC002 0x0000 0x0000 41: 0xE816 0xB6D9 0xC002 0x0000 0x0000 42: 0xC816 0xB6D9 0xC002 0x0000 0x0000 43: 0xC816 0xB6D9 0x8002 0x0000 0x0000 44: 0xE817 0xB6D8 0x8002 0x0000 0x0000 45: 0xC817 0xB6D8 0x8002 0x0000 0x0000 46: 0xC817 0xB6D8 0x8000 0x0000 0x0000 47: 0xE917 0x36D8 0x8000 0x0000 0x0000 48: 0xC917 0x36D8 0x8000 0x0000 0x0000 49: 0xC917 0x36DC 0x8000 0x0000 0x0000 50: 0xE517 0x36DC 0x8000 0x0000 0x0000 51: 0xC517 0x36DC 0x8000 0x0000 0x0000 52: 0xC517 0x36DC 0x8002 0x0000 0x0000 53: 0xE417 0xB6DC 0x8002 0x0000 0x0000 54: 0xC417 0xB6DC 0x8002 0x0000 0x0000 55: 0xC417 0xB6DC 0xC002 0x0000 0x0000 56: 0xE416 0xB6DD 0xC002 0x0000 0x0000 57: 0xC416 0xB6DD 0xC002 0x0000 0x0000 58: 0xC416 0xB6DD 0xC000 0x0000 0x0000 59: 0xE516 0x36DD 0xC000 0x0000 0x0000 60: 0xC516 0x36DD 0xC000 0x0000 0x0000 61: 0xC516 0x36FD 0xC000 0x0000 0x0000 62: 0xE712 0x36FD 0xC000 0x0000 0x0000 63: 0xC712 0x36FD 0xC000 0x0000 0x0000 64: 0xC712 0x36FD 0xC002 0x0000 0x0000 65: 0xE612 0xB6FD 0xC002 0x0000 0x0000 66: 0xC612 0xB6FD 0xC002 0x0000 0x0000 67: 0xC612 0xB6FD 0x8002 0x0000 0x0000 68: 0xE613 0xB6FC 0x8002 0x0000 0x0000 69: 0xC613 0xB6FC 0x8002 0x0000 0x0000 70: 0xC613 0xB6FC 0x8000 0x0000 0x0000 71: 0xE713 0x36FC 0x8000 0x0000 0x0000 72: 0xC713 0x36FC 0x8000 0x0000 0x0000 73: 0xC713 0x36F4 0x8000 0x0000 0x0000 74: 0xE719 0x36F4 0x8000 0x0000 0x0000 75: 0xC719 0x36F4 0x8000 0x0000 0x0000 76: 0xC719 0x36F4 0x8002 0x0000 0x0000 77: 0xE619 0xB6F4 0x8002 0x0000 0x0000 78: 0xC619 0xB6F4 0x8002 0x0000 0x0000 79: 0xC619 0xB6F4 0xC002 0x0000 0x0000 80: 0xE618 0xB6F5 0xC002 0x0000 0x0000 81: 0xC618 0xB6F5 0xC002 0x0000 0x0000 82: 0xC618 0xB6F5 0xC000 0x0000 0x0000 83: 0xE718 0x36F5 0xC000 0x0000 0x0000 84: 0xC718 0x36F5 0xC000 0x0000 0x0000 85: 0xC718 0x36D5 0xC000 0x0000 0x0000 86: 0xE51C 0x36D5 0xC000 0x0000 0x0000 87: 0xC51C 0x36D5 0xC000 0x0000 0x0000 88: 0xC51C 0x36D5 0xC002 0x0000 0x0000 89: 0xE41C 0xB6D5 0xC002 0x0000 0x0000 90: 0xC41C 0xB6D5 0xC002 0x0000 0x0000 91: 0xC41C 0xB6D5 0x8002 0x0000 0x0000 92: 0xE41D 0xB6D4 0x8002 0x0000 0x0000 93: 0xC41D 0xB6D4 0x8002 0x0000 0x0000 94: 0xC41D 0xB6D4 0x8000 0x0000 0x0000 95: 0xE51D 0x36D4 0x8000 0x0000 0x0000 96: 0xC51D 0x36D4 0x8000 0x0000 0x0000 97: 0xC51D 0x36D6 0x8000 0x0000 0x0000 98: 0xF50D 0x36D6 0x8000 0x0000 0x0000 99: 0xD50D 0x36D6 0x8000 0x0000 0x0000 100: 0xD50D 0x36D6 0x8002 0x0000 0x0000 101: 0xF40D 0xB6D6 0x8002 0x0000 0x0000 102: 0xD40D 0xB6D6 0x8002 0x0000 0x0000 103: 0xD40D 0xB6D6 0xC002 0x0000 0x0000 104: 0xF40C 0xB6D7 0xC002 0x0000 0x0000 105: 0xD40C 0xB6D7 0xC002 0x0000 0x0000 106: 0xD40C 0xB6D7 0xC000 0x0000 0x0000 107: 0xF50C 0x36D7 0xC000 0x0000 0x0000 108: 0xD50C 0x36D7 0xC000 0x0000 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0x7603 0xA86E 0x4000 0x0000 0x0000 1569: 0x5603 0xA06E 0x4000 0x0000 0x0000 1570: 0x5603 0xB04E 0x4000 0x0000 0x0000 1571: 0x7506 0x304F 0x4000 0x0000 0x0000 1572: 0x5506 0x284F 0x4000 0x0000 0x0000 1573: 0x7609 0xA84E 0x4000 0x0000 0x0000 1574: 0x5609 0xA04E 0x4000 0x0000 0x0000 1575: 0x5609 0xB04E 0x4002 0x0000 0x0000 1576: 0x7406 0xB04F 0x4002 0x0000 0x0000 1577: 0x5406 0xA84F 0x4002 0x0000 0x0000 1578: 0x7608 0xA84F 0x4002 0x0000 0x0000 1579: 0x5608 0xA04F 0x4002 0x0000 0x0000 1580: 0x5608 0xB04F 0x0002 0x0000 0x0000 1581: 0x7407 0xB04E 0x0002 0x0000 0x0000 1582: 0x5407 0xA84E 0x0002 0x0000 0x0000 1583: 0x740C 0xA84F 0x0002 0x0000 0x0000 1584: 0x540C 0xA04F 0x0002 0x0000 0x0000 1585: 0x540C 0xB04F 0x0000 0x0000 0x0000 1586: 0x7507 0x304E 0x0000 0x0000 0x0000 1587: 0x5507 0x284E 0x0000 0x0000 0x0000 1588: 0x740D 0xA84E 0x0000 0x0000 0x0000 1589: 0x540D 0xA04E 0x0000 0x0000 0x0000 1590: 0x540D 0xB04A 0x0000 0x0000 0x0000 1591: 0x7907 0x304A 0x0000 0x0000 0x0000 1592: 0x5907 0x284A 0x0000 0x0000 0x0000 1593: 0x641D 0xA84A 0x0000 0x0000 0x0000 1594: 0x441D 0xA04A 0x0000 0x0000 0x0000 1595: 0x441D 0xB04A 0x0002 0x0000 0x0000 1596: 0x7807 0xB04A 0x0002 0x0000 0x0000 1597: 0x5807 0xA84A 0x0002 0x0000 0x0000 1598: 0x641C 0xA84B 0x0002 0x0000 0x0000 1599: 0x441C 0xA04B 0x0002 0x0000 0x0000 1600: 0x441C 0xB04B 0x4002 0x0000 0x0000 1601: 0x7806 0xB04B 0x4002 0x0000 0x0000 1602: 0x5806 0xA84B 0x4002 0x0000 0x0000 1603: 0x6618 0xA84B 0x4002 0x0000 0x0000 1604: 0x4618 0xA04B 0x4002 0x0000 0x0000 1605: 0x4618 0xB04B 0x4000 0x0000 0x0000 1606: 0x7906 0x304B 0x4000 0x0000 0x0000 1607: 0x5906 0x284B 0x4000 0x0000 0x0000 1608: 0x6619 0xA84A 0x4000 0x0000 0x0000 1609: 0x4619 0xA04A 0x4000 0x0000 0x0000 1610: 0x4619 0xB06A 0x4000 0x0000 0x0000 1611: 0x7B02 0x306B 0x4000 0x0000 0x0000 1612: 0x5B02 0x286B 0x4000 0x0000 0x0000 1613: 0x6613 0xA86A 0x4000 0x0000 0x0000 1614: 0x4613 0xA06A 0x4000 0x0000 0x0000 1615: 0x4613 0xB06A 0x4002 0x0000 0x0000 1616: 0x7A02 0xB06B 0x4002 0x0000 0x0000 1617: 0x5A02 0xA86B 0x4002 0x0000 0x0000 1618: 0x6612 0xA86B 0x4002 0x0000 0x0000 1619: 0x4612 0xA06B 0x4002 0x0000 0x0000 1620: 0x4612 0xB06B 0x0002 0x0000 0x0000 1621: 0x7A03 0xB06A 0x0002 0x0000 0x0000 1622: 0x5A03 0xA86A 0x0002 0x0000 0x0000 1623: 0x6416 0xA86B 0x0002 0x0000 0x0000 1624: 0x4416 0xA06B 0x0002 0x0000 0x0000 1625: 0x4416 0xB06B 0x0000 0x0000 0x0000 1626: 0x7B03 0x306A 0x0000 0x0000 0x0000 1627: 0x5B03 0x286A 0x0000 0x0000 0x0000 1628: 0x6417 0xA86A 0x0000 0x0000 0x0000 1629: 0x4417 0xA06A 0x0000 0x0000 0x0000 1630: 0x4417 0xB062 0x0000 0x0000 0x0000 1631: 0x7B09 0x3062 0x0000 0x0000 0x0000 1632: 0x5B09 0x2862 0x0000 0x0000 0x0000 1633: 0x6817 0xA862 0x0000 0x0000 0x0000 1634: 0x4817 0xA062 0x0000 0x0000 0x0000 1635: 0x4817 0xB062 0x0002 0x0000 0x0000 1636: 0x7A09 0xB062 0x0002 0x0000 0x0000 1637: 0x5A09 0xA862 0x0002 0x0000 0x0000 1638: 0x6816 0xA863 0x0002 0x0000 0x0000 1639: 0x4816 0xA063 0x0002 0x0000 0x0000 1640: 0x4816 0xB063 0x4002 0x0000 0x0000 1641: 0x7A08 0xB063 0x4002 0x0000 0x0000 1642: 0x5A08 0xA863 0x4002 0x0000 0x0000 1643: 0x6A12 0xA863 0x4002 0x0000 0x0000 1644: 0x4A12 0xA063 0x4002 0x0000 0x0000 1645: 0x4A12 0xB063 0x4000 0x0000 0x0000 1646: 0x7B08 0x3063 0x4000 0x0000 0x0000 1647: 0x5B08 0x2863 0x4000 0x0000 0x0000 1648: 0x6A13 0xA862 0x4000 0x0000 0x0000 1649: 0x4A13 0xA062 0x4000 0x0000 0x0000 1650: 0x4A13 0xB042 0x4000 0x0000 0x0000 1651: 0x790C 0x3043 0x4000 0x0000 0x0000 1652: 0x590C 0x2843 0x4000 0x0000 0x0000 1653: 0x6A19 0xA842 0x4000 0x0000 0x0000 1654: 0x4A19 0xA042 0x4000 0x0000 0x0000 1655: 0x4A19 0xB042 0x4002 0x0000 0x0000 1656: 0x780C 0xB043 0x4002 0x0000 0x0000 1657: 0x580C 0xA843 0x4002 0x0000 0x0000 1658: 0x6A18 0xA843 0x4002 0x0000 0x0000 1659: 0x4A18 0xA043 0x4002 0x0000 0x0000 1660: 0x4A18 0xB043 0x0002 0x0000 0x0000 1661: 0x780D 0xB042 0x0002 0x0000 0x0000 1662: 0x580D 0xA842 0x0002 0x0000 0x0000 1663: 0x681C 0xA843 0x0002 0x0000 0x0000 1664: 0x481C 0xA043 0x0002 0x0000 0x0000 1665: 0x481C 0xB043 0x0000 0x0000 0x0000 1666: 0x790D 0x3042 0x0000 0x0000 0x0000 1667: 0x590D 0x2842 0x0000 0x0000 0x0000 1668: 0x681D 0xA842 0x0000 0x0000 0x0000 1669: 0x481D 0xA042 0x0000 0x0000 0x0000 1670: 0x481D 0xB040 0x0000 0x0000 0x0000 1671: 0x691D 0x3040 0x0000 0x0000 0x0000 1672: 0x491D 0x2840 0x0000 0x0000 0x0000 1673: 0x681D 0xA840 0x0000 0x0000 0x0000 1674: 0x481D 0xA040 0x0000 0x0000 0x0000 1675: 0x091D 0x2040 0x0000 0x0000 0x0000 1676: 0x491D 0x2040 0x0000 0x0000 0x0000 1677: 0xC91D 0x26FE 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOOOOOOIIIIIIGIIP GOOOOOOIIIIIIIII G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 1677 'test steps' 1775 lines ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) PINS Main menu Fri Jun 30 16:17:32 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:17:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 11 Main menu Fri Jun 30 16:17:49 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:18:07 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 16:18:08 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:18:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 3, total passes 0 Main menu Fri Jun 30 16:18:15 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m212.tst reading test file: tests\m212.tst comment: ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER comment: comment: ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) comment: pins: PINS pins: 1 I AB1 E3-4,10;E6-4,10;E9-4,10 CLEAR-N CLEARS FF0 THRU FF5 pins: 2 I AL2 E1-3 INA0-N pins: 3 I AM2 E2-2 INA1-N pins: 4 I AN2 E4-2 INA2-N pins: 5 I AR2 E5-2 INA3-N pins: 6 I AV1 E7-2 INA4-N pins: 7 I AV2 E8-2 INA5-N pins: 8 I AN1 ENABLE_INPUT_A pins: 9 I AP2 E1-4 INB0-N pins: 10 I AR1 E2-4 INB1-N pins: 11 I AS1 E4-4 INB2-N pins: 12 I AU1 E5-4 INB3-N pins: 13 I AA1 E7-4 INB4-N pins: 14 I AT2 E8-4 INB5-N pins: 15 I AU2 ENABLE_INPUT_B pins: 16 I AM1 E1-1 SHIFT_R_INSERT-N RIGHT SHIFTS INTO FF0 pins: 17 I AL1 ENABLE_R_SHIFT pins: 18 I AS2 E8-9 SHIFT_L_INSERT-N LEFT SHIFTS INTO FF5 pins: 19 I AP1 ENABLE_L_SHIFT pins: 20 I AC1 E3-3,11;E6-3,11;E9-3,11 CLOCK (RISING EDGE) pins: 21 O AD1 E3-6 FF0 pins: 22 O AD2 E3-5 FF0-N pins: 23 O AF1 E3-8 FF1 pins: 24 O AE1 E3-9 FF1-N pins: 25 O AH2 E6-6 FF2 pins: 26 O AE2 E6-5 FF2-N pins: 27 O AH1 E6-8 FF3 pins: 28 O AF2 E6-9 FF3-N pins: 29 O AK2 E9-6 FF4 pins: 30 O AJ2 E9-5 FF4-N pins: 31 O AK1 E9-8 FF5 pins: 32 O AJ1 A9-9 FF5-N pins: direction: IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO comment: ; CLEAR-N, NO ENABLES test 1: 01111110111111010100010101010101 test 2: 1 comment: comment: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM comment: ; see mk_m212_ld_shift.c comment: comment: comment: ; TEST A INPUTS, GRAY CODE PATTERN comment: comment: ; ENABLE A INPUTS test 3: 1 comment: ; LOAD FFs FROM INPUT A comment: test 4: 000001 test 5: 1010101010110 test 6: 0 test 7: 000011 test 8: 1010101011010 test 9: 0 test 10: 000010 test 11: 1010101011001 test 12: 0 test 13: 000110 test 14: 1010101101001 test 15: 0 test 16: 000111 test 17: 1010101101010 test 18: 0 test 19: 000101 test 20: 1010101100110 test 21: 0 test 22: 000100 test 23: 1010101100101 test 24: 0 test 25: 001100 test 26: 1010110100101 test 27: 0 test 28: 001101 test 29: 1010110100110 test 30: 0 test 31: 001111 test 32: 1010110101010 test 33: 0 test 34: 001110 test 35: 1010110101001 test 36: 0 test 37: 001010 test 38: 1010110011001 test 39: 0 test 40: 001011 test 41: 1010110011010 test 42: 0 test 43: 001001 test 44: 1010110010110 test 45: 0 test 46: 001000 test 47: 1010110010101 test 48: 0 test 49: 011000 test 50: 1011010010101 test 51: 0 test 52: 011001 test 53: 1011010010110 test 54: 0 test 55: 011011 test 56: 1011010011010 test 57: 0 test 58: 011010 test 59: 1011010011001 test 60: 0 test 61: 011110 test 62: 1011010101001 test 63: 0 test 64: 011111 test 65: 1011010101010 test 66: 0 test 67: 011101 test 68: 1011010100110 test 69: 0 test 70: 011100 test 71: 1011010100101 test 72: 0 test 73: 010100 test 74: 1011001100101 test 75: 0 test 76: 010101 test 77: 1011001100110 test 78: 0 test 79: 010111 test 80: 1011001101010 test 81: 0 test 82: 010110 test 83: 1011001101001 test 84: 0 test 85: 010010 test 86: 1011001011001 test 87: 0 test 88: 010011 test 89: 1011001011010 test 90: 0 test 91: 010001 test 92: 1011001010110 test 93: 0 test 94: 010000 test 95: 1011001010101 test 96: 0 test 97: 110000 test 98: 1101001010101 test 99: 0 test 100: 110001 test 101: 1101001010110 test 102: 0 test 103: 110011 test 104: 1101001011010 test 105: 0 test 106: 110010 test 107: 1101001011001 test 108: 0 test 109: 110110 test 110: 1101001101001 test 111: 0 test 112: 110111 test 113: 1101001101010 test 114: 0 test 115: 110101 test 116: 1101001100110 test 117: 0 test 118: 110100 test 119: 1101001100101 test 120: 0 test 121: 111100 test 122: 1101010100101 test 123: 0 test 124: 111101 test 125: 1101010100110 test 126: 0 test 127: 111111 test 128: 1101010101010 test 129: 0 test 130: 111110 test 131: 1101010101001 test 132: 0 test 133: 111010 test 134: 1101010011001 test 135: 0 test 136: 111011 test 137: 1101010011010 test 138: 0 test 139: 111001 test 140: 1101010010110 test 141: 0 test 142: 111000 test 143: 1101010010101 test 144: 0 test 145: 101000 test 146: 1100110010101 test 147: 0 test 148: 101001 test 149: 1100110010110 test 150: 0 test 151: 101011 test 152: 1100110011010 test 153: 0 test 154: 101010 test 155: 1100110011001 test 156: 0 test 157: 101110 test 158: 1100110101001 test 159: 0 test 160: 101111 test 161: 1100110101010 test 162: 0 test 163: 101101 test 164: 1100110100110 test 165: 0 test 166: 101100 test 167: 1100110100101 test 168: 0 test 169: 100100 test 170: 1100101100101 test 171: 0 test 172: 100101 test 173: 1100101100110 test 174: 0 test 175: 100111 test 176: 1100101101010 test 177: 0 test 178: 100110 test 179: 1100101101001 test 180: 0 test 181: 100010 test 182: 1100101011001 test 183: 0 test 184: 100011 test 185: 1100101011010 test 186: 0 test 187: 100001 test 188: 1100101010110 test 189: 0 test 190: 100000 test 191: 1100101010101 test 192: 0 test 193: 000000 test 194: 1010101010101 test 195: 0 comment: comment: ; DISABLE A INPUTS test 196: 0 comment: comment: comment: ; TEST B INPUTS comment: comment: ; ENABLE B INPUTS test 197: 1 comment: ; LOAD FFs FROM INPUT B comment: test 198: 000001 test 199: 1010101010110 test 200: 0 test 201: 000011 test 202: 1010101011010 test 203: 0 test 204: 000010 test 205: 1010101011001 test 206: 0 test 207: 000110 test 208: 1010101101001 test 209: 0 test 210: 000111 test 211: 1010101101010 test 212: 0 test 213: 000101 test 214: 1010101100110 test 215: 0 test 216: 000100 test 217: 1010101100101 test 218: 0 test 219: 001100 test 220: 1010110100101 test 221: 0 test 222: 001101 test 223: 1010110100110 test 224: 0 test 225: 001111 test 226: 1010110101010 test 227: 0 test 228: 001110 test 229: 1010110101001 test 230: 0 test 231: 001010 test 232: 1010110011001 test 233: 0 test 234: 001011 test 235: 1010110011010 test 236: 0 test 237: 001001 test 238: 1010110010110 test 239: 0 test 240: 001000 test 241: 1010110010101 test 242: 0 test 243: 011000 test 244: 1011010010101 test 245: 0 test 246: 011001 test 247: 1011010010110 test 248: 0 test 249: 011011 test 250: 1011010011010 test 251: 0 test 252: 011010 test 253: 1011010011001 test 254: 0 test 255: 011110 test 256: 1011010101001 test 257: 0 test 258: 011111 test 259: 1011010101010 test 260: 0 test 261: 011101 test 262: 1011010100110 test 263: 0 test 264: 011100 test 265: 1011010100101 test 266: 0 test 267: 010100 test 268: 1011001100101 test 269: 0 test 270: 010101 test 271: 1011001100110 test 272: 0 test 273: 010111 test 274: 1011001101010 test 275: 0 test 276: 010110 test 277: 1011001101001 test 278: 0 test 279: 010010 test 280: 1011001011001 test 281: 0 test 282: 010011 test 283: 1011001011010 test 284: 0 test 285: 010001 test 286: 1011001010110 test 287: 0 test 288: 010000 test 289: 1011001010101 test 290: 0 test 291: 110000 test 292: 1101001010101 test 293: 0 test 294: 110001 test 295: 1101001010110 test 296: 0 test 297: 110011 test 298: 1101001011010 test 299: 0 test 300: 110010 test 301: 1101001011001 test 302: 0 test 303: 110110 test 304: 1101001101001 test 305: 0 test 306: 110111 test 307: 1101001101010 test 308: 0 test 309: 110101 test 310: 1101001100110 test 311: 0 test 312: 110100 test 313: 1101001100101 test 314: 0 test 315: 111100 test 316: 1101010100101 test 317: 0 test 318: 111101 test 319: 1101010100110 test 320: 0 test 321: 111111 test 322: 1101010101010 test 323: 0 test 324: 111110 test 325: 1101010101001 test 326: 0 test 327: 111010 test 328: 1101010011001 test 329: 0 test 330: 111011 test 331: 1101010011010 test 332: 0 test 333: 111001 test 334: 1101010010110 test 335: 0 test 336: 111000 test 337: 1101010010101 test 338: 0 test 339: 101000 test 340: 1100110010101 test 341: 0 test 342: 101001 test 343: 1100110010110 test 344: 0 test 345: 101011 test 346: 1100110011010 test 347: 0 test 348: 101010 test 349: 1100110011001 test 350: 0 test 351: 101110 test 352: 1100110101001 test 353: 0 test 354: 101111 test 355: 1100110101010 test 356: 0 test 357: 101101 test 358: 1100110100110 test 359: 0 test 360: 101100 test 361: 1100110100101 test 362: 0 test 363: 100100 test 364: 1100101100101 test 365: 0 test 366: 100101 test 367: 1100101100110 test 368: 0 test 369: 100111 test 370: 1100101101010 test 371: 0 test 372: 100110 test 373: 1100101101001 test 374: 0 test 375: 100010 test 376: 1100101011001 test 377: 0 test 378: 100011 test 379: 1100101011010 test 380: 0 test 381: 100001 test 382: 1100101010110 test 383: 0 test 384: 100000 test 385: 1100101010101 test 386: 0 test 387: 000000 test 388: 1010101010101 test 389: 0 comment: comment: ; DISABLE B INPUTS test 390: 0 comment: comment: comment: ; TEST SHIFT R (LOAD VIA A INPUTS) comment: comment: ; SHIFT IN A ZERO test 391: 0 comment: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS comment: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT test 392: 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test 1386: 1010101100101 test 1387: 0 10 test 1388: 1010110010110 test 1389: 00 test 1390: 0011001 test 1391: 1010110100101 test 1392: 0 10 test 1393: 1011010010110 test 1394: 00 test 1395: 0011011 test 1396: 1010110100110 test 1397: 0 10 test 1398: 1011010011010 test 1399: 00 test 1400: 0011111 test 1401: 1010110101010 test 1402: 0 10 test 1403: 1011010101010 test 1404: 00 test 1405: 0011101 test 1406: 1010110101001 test 1407: 0 10 test 1408: 1011010100110 test 1409: 00 test 1410: 0010101 test 1411: 1010110011001 test 1412: 0 10 test 1413: 1011001100110 test 1414: 00 test 1415: 0010111 test 1416: 1010110011010 test 1417: 0 10 test 1418: 1011001101010 test 1419: 00 test 1420: 0010011 test 1421: 1010110010110 test 1422: 0 10 test 1423: 1011001011010 test 1424: 00 test 1425: 0010001 test 1426: 1010110010101 test 1427: 0 10 test 1428: 1011001010110 test 1429: 00 test 1430: 0110001 test 1431: 1011010010101 test 1432: 0 10 test 1433: 1101001010110 test 1434: 00 test 1435: 0110011 test 1436: 1011010010110 test 1437: 0 10 test 1438: 1101001011010 test 1439: 00 test 1440: 0110111 test 1441: 1011010011010 test 1442: 0 10 test 1443: 1101001101010 test 1444: 00 test 1445: 0110101 test 1446: 1011010011001 test 1447: 0 10 test 1448: 1101001100110 test 1449: 00 test 1450: 0111101 test 1451: 1011010101001 test 1452: 0 10 test 1453: 1101010100110 test 1454: 00 test 1455: 0111111 test 1456: 1011010101010 test 1457: 0 10 test 1458: 1101010101010 test 1459: 00 test 1460: 0111011 test 1461: 1011010100110 test 1462: 0 10 test 1463: 1101010011010 test 1464: 00 test 1465: 0111001 test 1466: 1011010100101 test 1467: 0 10 test 1468: 1101010010110 test 1469: 00 test 1470: 0101001 test 1471: 1011001100101 test 1472: 0 10 test 1473: 1100110010110 test 1474: 00 test 1475: 0101011 test 1476: 1011001100110 test 1477: 0 10 test 1478: 1100110011010 test 1479: 00 test 1480: 0101111 test 1481: 1011001101010 test 1482: 0 10 test 1483: 1100110101010 test 1484: 00 test 1485: 0101101 test 1486: 1011001101001 test 1487: 0 10 test 1488: 1100110100110 test 1489: 00 test 1490: 0100101 test 1491: 1011001011001 test 1492: 0 10 test 1493: 1100101100110 test 1494: 00 test 1495: 0100111 test 1496: 1011001011010 test 1497: 0 10 test 1498: 1100101101010 test 1499: 00 test 1500: 0100011 test 1501: 1011001010110 test 1502: 0 10 test 1503: 1100101011010 test 1504: 00 test 1505: 0100001 test 1506: 1011001010101 test 1507: 0 10 test 1508: 1100101010110 test 1509: 00 test 1510: 1100001 test 1511: 1101001010101 test 1512: 0 10 test 1513: 1100101010110 test 1514: 00 test 1515: 1100011 test 1516: 1101001010110 test 1517: 0 10 test 1518: 1100101011010 test 1519: 00 test 1520: 1100111 test 1521: 1101001011010 test 1522: 0 10 test 1523: 1100101101010 test 1524: 00 test 1525: 1100101 test 1526: 1101001011001 test 1527: 0 10 test 1528: 1100101100110 test 1529: 00 test 1530: 1101101 test 1531: 1101001101001 test 1532: 0 10 test 1533: 1100110100110 test 1534: 00 test 1535: 1101111 test 1536: 1101001101010 test 1537: 0 10 test 1538: 1100110101010 test 1539: 00 test 1540: 1101011 test 1541: 1101001100110 test 1542: 0 10 test 1543: 1100110011010 test 1544: 00 test 1545: 1101001 test 1546: 1101001100101 test 1547: 0 10 test 1548: 1100110010110 test 1549: 00 test 1550: 1111001 test 1551: 1101010100101 test 1552: 0 10 test 1553: 1101010010110 test 1554: 00 test 1555: 1111011 test 1556: 1101010100110 test 1557: 0 10 test 1558: 1101010011010 test 1559: 00 test 1560: 1111111 test 1561: 1101010101010 test 1562: 0 10 test 1563: 1101010101010 test 1564: 00 test 1565: 1111101 test 1566: 1101010101001 test 1567: 0 10 test 1568: 1101010100110 test 1569: 00 test 1570: 1110101 test 1571: 1101010011001 test 1572: 0 10 test 1573: 1101001100110 test 1574: 00 test 1575: 1110111 test 1576: 1101010011010 test 1577: 0 10 test 1578: 1101001101010 test 1579: 00 test 1580: 1110011 test 1581: 1101010010110 test 1582: 0 10 test 1583: 1101001011010 test 1584: 00 test 1585: 1110001 test 1586: 1101010010101 test 1587: 0 10 test 1588: 1101001010110 test 1589: 00 test 1590: 1010001 test 1591: 1100110010101 test 1592: 0 10 test 1593: 1011001010110 test 1594: 00 test 1595: 1010011 test 1596: 1100110010110 test 1597: 0 10 test 1598: 1011001011010 test 1599: 00 test 1600: 1010111 test 1601: 1100110011010 test 1602: 0 10 test 1603: 1011001101010 test 1604: 00 test 1605: 1010101 test 1606: 1100110011001 test 1607: 0 10 test 1608: 1011001100110 test 1609: 00 test 1610: 1011101 test 1611: 1100110101001 test 1612: 0 10 test 1613: 1011010100110 test 1614: 00 test 1615: 1011111 test 1616: 1100110101010 test 1617: 0 10 test 1618: 1011010101010 test 1619: 00 test 1620: 1011011 test 1621: 1100110100110 test 1622: 0 10 test 1623: 1011010011010 test 1624: 00 test 1625: 1011001 test 1626: 1100110100101 test 1627: 0 10 test 1628: 1011010010110 test 1629: 00 test 1630: 1001001 test 1631: 1100101100101 test 1632: 0 10 test 1633: 1010110010110 test 1634: 00 test 1635: 1001011 test 1636: 1100101100110 test 1637: 0 10 test 1638: 1010110011010 test 1639: 00 test 1640: 1001111 test 1641: 1100101101010 test 1642: 0 10 test 1643: 1010110101010 test 1644: 00 test 1645: 1001101 test 1646: 1100101101001 test 1647: 0 10 test 1648: 1010110100110 test 1649: 00 test 1650: 1000101 test 1651: 1100101011001 test 1652: 0 10 test 1653: 1010101100110 test 1654: 00 test 1655: 1000111 test 1656: 1100101011010 test 1657: 0 10 test 1658: 1010101101010 test 1659: 00 test 1660: 1000011 test 1661: 1100101010110 test 1662: 0 10 test 1663: 1010101011010 test 1664: 00 test 1665: 1000001 test 1666: 1100101010101 test 1667: 0 10 test 1668: 1010101010110 test 1669: 00 test 1670: 0000001 test 1671: 1010101010101 test 1672: 0 10 test 1673: 1010101010110 test 1674: 00 comment: comment: comment: ; end of SECTION GENERATED BY A PROGRAM comment: comment: comment: ; CLEAR FFs test 1675: 0 010101010101 test 1676: 1 comment: test 1677: 11111110111111010100010101010101 comment: end: END summary column 1: offset 0, mask 0x4000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0020 column 6: offset 2, mask 0x4000 column 7: offset 2, mask 0x0002 column 8: offset 1, mask 0x1000 column 9: offset 1, mask 0x0010 column 10: offset 1, mask 0x0400 column 11: offset 1, mask 0x0200 column 12: offset 2, mask 0x8000 column 13: offset 0, mask 0x8000 column 14: offset 1, mask 0x0080 column 15: offset 2, mask 0x0001 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x4000 column 18: offset 1, mask 0x0040 column 19: offset 1, mask 0x0800 column 20: offset 0, mask 0x2000 column 21: offset 0, mask 0x1000 column 22: offset 0, mask 0x0010 column 23: offset 0, mask 0x0400 column 24: offset 0, mask 0x0800 column 25: offset 0, mask 0x0002 column 26: offset 0, mask 0x0008 column 27: offset 0, mask 0x0200 column 28: offset 0, mask 0x0004 column 29: offset 1, mask 0x0001 column 30: offset 0, mask 0x0001 column 31: offset 1, mask 0x8000 column 32: offset 0, mask 0x0100 direction bits (1=input) 0x1FFF 0x8101 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x891D 0x26FE 0xC002 0x0000 0x0000 2: 0xC91D 0x26FE 0xC002 0x0000 0x0000 3: 0xC91D 0x36FE 0xC002 0x0000 0x0000 4: 0xC91D 0x36D0 0x8002 0x0000 0x0000 5: 0xE81D 0xB6D0 0x8002 0x0000 0x0000 6: 0xC81D 0xB6D0 0x8002 0x0000 0x0000 7: 0xC81D 0xB6D0 0xC002 0x0000 0x0000 8: 0xE81C 0xB6D1 0xC002 0x0000 0x0000 9: 0xC81C 0xB6D1 0xC002 0x0000 0x0000 10: 0xC81C 0xB6D1 0xC000 0x0000 0x0000 11: 0xE91C 0x36D1 0xC000 0x0000 0x0000 12: 0xC91C 0x36D1 0xC000 0x0000 0x0000 13: 0xC91C 0x36F1 0xC000 0x0000 0x0000 14: 0xEB18 0x36F1 0xC000 0x0000 0x0000 15: 0xCB18 0x36F1 0xC000 0x0000 0x0000 16: 0xCB18 0x36F1 0xC002 0x0000 0x0000 17: 0xEA18 0xB6F1 0xC002 0x0000 0x0000 18: 0xCA18 0xB6F1 0xC002 0x0000 0x0000 19: 0xCA18 0xB6F1 0x8002 0x0000 0x0000 20: 0xEA19 0xB6F0 0x8002 0x0000 0x0000 21: 0xCA19 0xB6F0 0x8002 0x0000 0x0000 22: 0xCA19 0xB6F0 0x8000 0x0000 0x0000 23: 0xEB19 0x36F0 0x8000 0x0000 0x0000 24: 0xCB19 0x36F0 0x8000 0x0000 0x0000 25: 0xCB19 0x36F8 0x8000 0x0000 0x0000 26: 0xEB13 0x36F8 0x8000 0x0000 0x0000 27: 0xCB13 0x36F8 0x8000 0x0000 0x0000 28: 0xCB13 0x36F8 0x8002 0x0000 0x0000 29: 0xEA13 0xB6F8 0x8002 0x0000 0x0000 30: 0xCA13 0xB6F8 0x8002 0x0000 0x0000 31: 0xCA13 0xB6F8 0xC002 0x0000 0x0000 32: 0xEA12 0xB6F9 0xC002 0x0000 0x0000 33: 0xCA12 0xB6F9 0xC002 0x0000 0x0000 34: 0xCA12 0xB6F9 0xC000 0x0000 0x0000 35: 0xEB12 0x36F9 0xC000 0x0000 0x0000 36: 0xCB12 0x36F9 0xC000 0x0000 0x0000 37: 0xCB12 0x36D9 0xC000 0x0000 0x0000 38: 0xE916 0x36D9 0xC000 0x0000 0x0000 39: 0xC916 0x36D9 0xC000 0x0000 0x0000 40: 0xC916 0x36D9 0xC002 0x0000 0x0000 41: 0xE816 0xB6D9 0xC002 0x0000 0x0000 42: 0xC816 0xB6D9 0xC002 0x0000 0x0000 43: 0xC816 0xB6D9 0x8002 0x0000 0x0000 44: 0xE817 0xB6D8 0x8002 0x0000 0x0000 45: 0xC817 0xB6D8 0x8002 0x0000 0x0000 46: 0xC817 0xB6D8 0x8000 0x0000 0x0000 47: 0xE917 0x36D8 0x8000 0x0000 0x0000 48: 0xC917 0x36D8 0x8000 0x0000 0x0000 49: 0xC917 0x36DC 0x8000 0x0000 0x0000 50: 0xE517 0x36DC 0x8000 0x0000 0x0000 51: 0xC517 0x36DC 0x8000 0x0000 0x0000 52: 0xC517 0x36DC 0x8002 0x0000 0x0000 53: 0xE417 0xB6DC 0x8002 0x0000 0x0000 54: 0xC417 0xB6DC 0x8002 0x0000 0x0000 55: 0xC417 0xB6DC 0xC002 0x0000 0x0000 56: 0xE416 0xB6DD 0xC002 0x0000 0x0000 57: 0xC416 0xB6DD 0xC002 0x0000 0x0000 58: 0xC416 0xB6DD 0xC000 0x0000 0x0000 59: 0xE516 0x36DD 0xC000 0x0000 0x0000 60: 0xC516 0x36DD 0xC000 0x0000 0x0000 61: 0xC516 0x36FD 0xC000 0x0000 0x0000 62: 0xE712 0x36FD 0xC000 0x0000 0x0000 63: 0xC712 0x36FD 0xC000 0x0000 0x0000 64: 0xC712 0x36FD 0xC002 0x0000 0x0000 65: 0xE612 0xB6FD 0xC002 0x0000 0x0000 66: 0xC612 0xB6FD 0xC002 0x0000 0x0000 67: 0xC612 0xB6FD 0x8002 0x0000 0x0000 68: 0xE613 0xB6FC 0x8002 0x0000 0x0000 69: 0xC613 0xB6FC 0x8002 0x0000 0x0000 70: 0xC613 0xB6FC 0x8000 0x0000 0x0000 71: 0xE713 0x36FC 0x8000 0x0000 0x0000 72: 0xC713 0x36FC 0x8000 0x0000 0x0000 73: 0xC713 0x36F4 0x8000 0x0000 0x0000 74: 0xE719 0x36F4 0x8000 0x0000 0x0000 75: 0xC719 0x36F4 0x8000 0x0000 0x0000 76: 0xC719 0x36F4 0x8002 0x0000 0x0000 77: 0xE619 0xB6F4 0x8002 0x0000 0x0000 78: 0xC619 0xB6F4 0x8002 0x0000 0x0000 79: 0xC619 0xB6F4 0xC002 0x0000 0x0000 80: 0xE618 0xB6F5 0xC002 0x0000 0x0000 81: 0xC618 0xB6F5 0xC002 0x0000 0x0000 82: 0xC618 0xB6F5 0xC000 0x0000 0x0000 83: 0xE718 0x36F5 0xC000 0x0000 0x0000 84: 0xC718 0x36F5 0xC000 0x0000 0x0000 85: 0xC718 0x36D5 0xC000 0x0000 0x0000 86: 0xE51C 0x36D5 0xC000 0x0000 0x0000 87: 0xC51C 0x36D5 0xC000 0x0000 0x0000 88: 0xC51C 0x36D5 0xC002 0x0000 0x0000 89: 0xE41C 0xB6D5 0xC002 0x0000 0x0000 90: 0xC41C 0xB6D5 0xC002 0x0000 0x0000 91: 0xC41C 0xB6D5 0x8002 0x0000 0x0000 92: 0xE41D 0xB6D4 0x8002 0x0000 0x0000 93: 0xC41D 0xB6D4 0x8002 0x0000 0x0000 94: 0xC41D 0xB6D4 0x8000 0x0000 0x0000 95: 0xE51D 0x36D4 0x8000 0x0000 0x0000 96: 0xC51D 0x36D4 0x8000 0x0000 0x0000 97: 0xC51D 0x36D6 0x8000 0x0000 0x0000 98: 0xF50D 0x36D6 0x8000 0x0000 0x0000 99: 0xD50D 0x36D6 0x8000 0x0000 0x0000 100: 0xD50D 0x36D6 0x8002 0x0000 0x0000 101: 0xF40D 0xB6D6 0x8002 0x0000 0x0000 102: 0xD40D 0xB6D6 0x8002 0x0000 0x0000 103: 0xD40D 0xB6D6 0xC002 0x0000 0x0000 104: 0xF40C 0xB6D7 0xC002 0x0000 0x0000 105: 0xD40C 0xB6D7 0xC002 0x0000 0x0000 106: 0xD40C 0xB6D7 0xC000 0x0000 0x0000 107: 0xF50C 0x36D7 0xC000 0x0000 0x0000 108: 0xD50C 0x36D7 0xC000 0x0000 0x0000 109: 0xD50C 0x36F7 0xC000 0x0000 0x0000 110: 0xF708 0x36F7 0xC000 0x0000 0x0000 111: 0xD708 0x36F7 0xC000 0x0000 0x0000 112: 0xD708 0x36F7 0xC002 0x0000 0x0000 113: 0xF608 0xB6F7 0xC002 0x0000 0x0000 114: 0xD608 0xB6F7 0xC002 0x0000 0x0000 115: 0xD608 0xB6F7 0x8002 0x0000 0x0000 116: 0xF609 0xB6F6 0x8002 0x0000 0x0000 117: 0xD609 0xB6F6 0x8002 0x0000 0x0000 118: 0xD609 0xB6F6 0x8000 0x0000 0x0000 119: 0xF709 0x36F6 0x8000 0x0000 0x0000 120: 0xD709 0x36F6 0x8000 0x0000 0x0000 121: 0xD709 0x36FE 0x8000 0x0000 0x0000 122: 0xF703 0x36FE 0x8000 0x0000 0x0000 123: 0xD703 0x36FE 0x8000 0x0000 0x0000 124: 0xD703 0x36FE 0x8002 0x0000 0x0000 125: 0xF603 0xB6FE 0x8002 0x0000 0x0000 126: 0xD603 0xB6FE 0x8002 0x0000 0x0000 127: 0xD603 0xB6FE 0xC002 0x0000 0x0000 128: 0xF602 0xB6FF 0xC002 0x0000 0x0000 129: 0xD602 0xB6FF 0xC002 0x0000 0x0000 130: 0xD602 0xB6FF 0xC000 0x0000 0x0000 131: 0xF702 0x36FF 0xC000 0x0000 0x0000 132: 0xD702 0x36FF 0xC000 0x0000 0x0000 133: 0xD702 0x36DF 0xC000 0x0000 0x0000 134: 0xF506 0x36DF 0xC000 0x0000 0x0000 135: 0xD506 0x36DF 0xC000 0x0000 0x0000 136: 0xD506 0x36DF 0xC002 0x0000 0x0000 137: 0xF406 0xB6DF 0xC002 0x0000 0x0000 138: 0xD406 0xB6DF 0xC002 0x0000 0x0000 139: 0xD406 0xB6DF 0x8002 0x0000 0x0000 140: 0xF407 0xB6DE 0x8002 0x0000 0x0000 141: 0xD407 0xB6DE 0x8002 0x0000 0x0000 142: 0xD407 0xB6DE 0x8000 0x0000 0x0000 143: 0xF507 0x36DE 0x8000 0x0000 0x0000 144: 0xD507 0x36DE 0x8000 0x0000 0x0000 145: 0xD507 0x36DA 0x8000 0x0000 0x0000 146: 0xF907 0x36DA 0x8000 0x0000 0x0000 147: 0xD907 0x36DA 0x8000 0x0000 0x0000 148: 0xD907 0x36DA 0x8002 0x0000 0x0000 149: 0xF807 0xB6DA 0x8002 0x0000 0x0000 150: 0xD807 0xB6DA 0x8002 0x0000 0x0000 151: 0xD807 0xB6DA 0xC002 0x0000 0x0000 152: 0xF806 0xB6DB 0xC002 0x0000 0x0000 153: 0xD806 0xB6DB 0xC002 0x0000 0x0000 154: 0xD806 0xB6DB 0xC000 0x0000 0x0000 155: 0xF906 0x36DB 0xC000 0x0000 0x0000 156: 0xD906 0x36DB 0xC000 0x0000 0x0000 157: 0xD906 0x36FB 0xC000 0x0000 0x0000 158: 0xFB02 0x36FB 0xC000 0x0000 0x0000 159: 0xDB02 0x36FB 0xC000 0x0000 0x0000 160: 0xDB02 0x36FB 0xC002 0x0000 0x0000 161: 0xFA02 0xB6FB 0xC002 0x0000 0x0000 162: 0xDA02 0xB6FB 0xC002 0x0000 0x0000 163: 0xDA02 0xB6FB 0x8002 0x0000 0x0000 164: 0xFA03 0xB6FA 0x8002 0x0000 0x0000 165: 0xDA03 0xB6FA 0x8002 0x0000 0x0000 166: 0xDA03 0xB6FA 0x8000 0x0000 0x0000 167: 0xFB03 0x36FA 0x8000 0x0000 0x0000 168: 0xDB03 0x36FA 0x8000 0x0000 0x0000 169: 0xDB03 0x36F2 0x8000 0x0000 0x0000 170: 0xFB09 0x36F2 0x8000 0x0000 0x0000 171: 0xDB09 0x36F2 0x8000 0x0000 0x0000 172: 0xDB09 0x36F2 0x8002 0x0000 0x0000 173: 0xFA09 0xB6F2 0x8002 0x0000 0x0000 174: 0xDA09 0xB6F2 0x8002 0x0000 0x0000 175: 0xDA09 0xB6F2 0xC002 0x0000 0x0000 176: 0xFA08 0xB6F3 0xC002 0x0000 0x0000 177: 0xDA08 0xB6F3 0xC002 0x0000 0x0000 178: 0xDA08 0xB6F3 0xC000 0x0000 0x0000 179: 0xFB08 0x36F3 0xC000 0x0000 0x0000 180: 0xDB08 0x36F3 0xC000 0x0000 0x0000 181: 0xDB08 0x36D3 0xC000 0x0000 0x0000 182: 0xF90C 0x36D3 0xC000 0x0000 0x0000 183: 0xD90C 0x36D3 0xC000 0x0000 0x0000 184: 0xD90C 0x36D3 0xC002 0x0000 0x0000 185: 0xF80C 0xB6D3 0xC002 0x0000 0x0000 186: 0xD80C 0xB6D3 0xC002 0x0000 0x0000 187: 0xD80C 0xB6D3 0x8002 0x0000 0x0000 188: 0xF80D 0xB6D2 0x8002 0x0000 0x0000 189: 0xD80D 0xB6D2 0x8002 0x0000 0x0000 190: 0xD80D 0xB6D2 0x8000 0x0000 0x0000 191: 0xF90D 0x36D2 0x8000 0x0000 0x0000 192: 0xD90D 0x36D2 0x8000 0x0000 0x0000 193: 0xD90D 0x36D0 0x8000 0x0000 0x0000 194: 0xE91D 0x36D0 0x8000 0x0000 0x0000 195: 0xC91D 0x36D0 0x8000 0x0000 0x0000 196: 0xC91D 0x26D0 0x8000 0x0000 0x0000 197: 0xC91D 0x26D0 0x8001 0x0000 0x0000 198: 0x491D 0x20C0 0x0001 0x0000 0x0000 199: 0x681D 0xA0C0 0x0001 0x0000 0x0000 200: 0x481D 0xA0C0 0x0001 0x0000 0x0000 201: 0xC81D 0xA0C0 0x0001 0x0000 0x0000 202: 0xE81C 0xA0C1 0x0001 0x0000 0x0000 203: 0xC81C 0xA0C1 0x0001 0x0000 0x0000 204: 0xC81C 0xA041 0x0001 0x0000 0x0000 205: 0xE91C 0x2041 0x0001 0x0000 0x0000 206: 0xC91C 0x2041 0x0001 0x0000 0x0000 207: 0xC91C 0x2041 0x8001 0x0000 0x0000 208: 0xEB18 0x2041 0x8001 0x0000 0x0000 209: 0xCB18 0x2041 0x8001 0x0000 0x0000 210: 0xCB18 0x20C1 0x8001 0x0000 0x0000 211: 0xEA18 0xA0C1 0x8001 0x0000 0x0000 212: 0xCA18 0xA0C1 0x8001 0x0000 0x0000 213: 0x4A18 0xA0C1 0x8001 0x0000 0x0000 214: 0x6A19 0xA0C0 0x8001 0x0000 0x0000 215: 0x4A19 0xA0C0 0x8001 0x0000 0x0000 216: 0x4A19 0xA040 0x8001 0x0000 0x0000 217: 0x6B19 0x2040 0x8001 0x0000 0x0000 218: 0x4B19 0x2040 0x8001 0x0000 0x0000 219: 0x4B19 0x2240 0x8001 0x0000 0x0000 220: 0x6B13 0x2240 0x8001 0x0000 0x0000 221: 0x4B13 0x2240 0x8001 0x0000 0x0000 222: 0x4B13 0x22C0 0x8001 0x0000 0x0000 223: 0x6A13 0xA2C0 0x8001 0x0000 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0x0000 1656: 0x780C 0xB043 0x4002 0x0000 0x0000 1657: 0x580C 0xA843 0x4002 0x0000 0x0000 1658: 0x6A18 0xA843 0x4002 0x0000 0x0000 1659: 0x4A18 0xA043 0x4002 0x0000 0x0000 1660: 0x4A18 0xB043 0x0002 0x0000 0x0000 1661: 0x780D 0xB042 0x0002 0x0000 0x0000 1662: 0x580D 0xA842 0x0002 0x0000 0x0000 1663: 0x681C 0xA843 0x0002 0x0000 0x0000 1664: 0x481C 0xA043 0x0002 0x0000 0x0000 1665: 0x481C 0xB043 0x0000 0x0000 0x0000 1666: 0x790D 0x3042 0x0000 0x0000 0x0000 1667: 0x590D 0x2842 0x0000 0x0000 0x0000 1668: 0x681D 0xA842 0x0000 0x0000 0x0000 1669: 0x481D 0xA042 0x0000 0x0000 0x0000 1670: 0x481D 0xB040 0x0000 0x0000 0x0000 1671: 0x691D 0x3040 0x0000 0x0000 0x0000 1672: 0x491D 0x2840 0x0000 0x0000 0x0000 1673: 0x681D 0xA840 0x0000 0x0000 0x0000 1674: 0x481D 0xA040 0x0000 0x0000 0x0000 1675: 0x091D 0x2040 0x0000 0x0000 0x0000 1676: 0x491D 0x2040 0x0000 0x0000 0x0000 1677: 0xC91D 0x26FE 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOOOOOOIIIIIIGIIP GOOOOOOIIIIIIIII G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 1677 'test steps' 1775 lines ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) PINS Main menu Fri Jun 30 16:18:43 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:18:48 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 557 11100111000000000100011010010101 step 558 11100111000000000101101001011010 step 559 11100110000000001100101001011010 step 560 11100110000000001101011010010110 step 561 11100110000000000100011010010110 step 562 11100101000000000100011010010110 step 563 11100101000000000101101001011001 step 564 11100100000000001100101001011001 step 565 11100100000000001101011010010110 step 566 11100100000000000100011010010110 step 567 11101101000000000100011010010110 step 568 11101101000000000101101001101001 step 569 11101100000000001100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 570 11101100000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 571 11101100000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 572 11101111000000000100011010101010 fail ^^ step 573 11101111000000000101101001101010 step 574 11101110000000001100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 575 11101110000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 576 11101110000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 577 11101011000000000100011010101010 fail ^^ step 578 11101011000000000101101001100110 step 579 11101010000000001100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 1001 step 580 11101010000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 581 11101010000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 582 11101001000000000100011010101001 fail ^^ step 583 11101001000000000101101001100101 step 584 11101000000000001100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 585 11101000000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 586 11101000000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 587 11111001000000000100011010101001 fail ^^ step 588 11111001000000000101101010100101 step 589 11111000000000001100101010100101 step 590 11111000000000001101011010101001 step 591 11111000000000000100011010101001 step 592 11111011000000000100011010101001 step 593 11111011000000000101101010100110 step 594 11111010000000001100101010100110 step 595 11111010000000001101011010101001 step 596 11111010000000000100011010101001 step 597 11111111000000000100011010101001 step 598 11111111000000000101101010101010 step 599 11111110000000001100101010101010 step 600 11111110000000001101011010101010 step 601 11111110000000000100011010101010 step 602 11111101000000000100011010101010 step 603 11111101000000000101101010101001 step 604 11111100000000001100101010101001 step 605 11111100000000001101011010101010 step 606 11111100000000000100011010101010 step 607 11110101000000000100011010101010 step 608 11110101000000000101101010011001 step 609 11110100000000001100101010011001 step 610 11110100000000001101011010100110 step 611 11110100000000000100011010100110 step 612 11110111000000000100011010100110 step 613 11110111000000000101101010011010 step 614 11110110000000001100101010011010 step 615 11110110000000001101011010100110 step 616 11110110000000000100011010100110 step 617 11110011000000000100011010100110 step 618 11110011000000000101101010010110 step 619 11110010000000001100101010010110 step 620 11110010000000001101011010100101 step 621 11110010000000000100011010100101 step 622 11110001000000000100011010100101 step 623 11110001000000000101101010010101 step 624 11110000000000001100101010010101 step 625 11110000000000001101011010100101 step 626 11110000000000000100011010100101 step 627 11010001000000000100011010100101 step 628 11010001000000000101100110010101 step 629 11010000000000001100100110010101 step 630 11010000000000001101011001100101 step 631 11010000000000000100011001100101 step 632 11010011000000000100011001100101 step 633 11010011000000000101100110010110 step 634 11010010000000001100100110010110 step 635 11010010000000001101011001100101 step 636 11010010000000000100011001100101 step 637 11010111000000000100011001100101 step 638 11010111000000000101100110011010 step 639 11010110000000001100100110011010 step 640 11010110000000001101011001100110 step 641 11010110000000000100011001100110 step 642 11010101000000000100011001100110 step 643 11010101000000000101100110011001 step 644 11010100000000001100100110011001 step 645 11010100000000001101011001100110 step 646 11010100000000000100011001100110 step 647 11011101000000000100011001100110 step 648 11011101000000000101100110101001 step 649 11011100000000001100100110101001 step 650 11011100000000001101011001101010 step 651 11011100000000000100011001101010 step 652 11011111000000000100011001101010 step 653 11011111000000000101100110101010 step 654 11011110000000001100100110101010 step 655 11011110000000001101011001101010 step 656 11011110000000000100011001101010 step 657 11011011000000000100011001101010 step 658 11011011000000000101100110100110 step 659 11011010000000001100100110100110 step 660 11011010000000001101011001101001 step 661 11011010000000000100011001101001 step 662 11011001000000000100011001101001 step 663 11011001000000000101100110100101 step 664 11011000000000001100100110100101 step 665 11011000000000001101011001101001 step 666 11011000000000000100011001101001 step 667 11001001000000000100011001101001 step 668 11001001000000000101100101100101 step 669 11001000000000001100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 670 11001000000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 671 11001000000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 672 11001011000000000100011001101001 fail ^^ step 673 11001011000000000101100101100110 step 674 11001010000000001100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 675 11001010000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 676 11001010000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 677 11001111000000000100011001101001 fail ^^ step 678 11001111000000000101100101101010 step 679 11001110000000001100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 680 11001110000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 681 11001110000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 682 11001101000000000100011001101010 fail ^^ step 683 11001101000000000101100101101001 step 684 11001100000000001100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 685 11001100000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 686 11001100000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 687 11000101000000000100011001101010 fail ^^ step 688 11000101000000000101100101011001 step 689 11000100000000001100100101011001 step 690 11000100000000001101011001010110 step 691 11000100000000000100011001010110 step 692 11000111000000000100011001010110 step 693 11000111000000000101100101011010 step 694 11000110000000001100100101011010 step 695 11000110000000001101011001010110 step 696 11000110000000000100011001010110 step 697 11000011000000000100011001010110 step 698 11000011000000000101100101010110 step 699 11000010000000001100100101010110 step 700 11000010000000001101011001010101 step 701 11000010000000000100011001010101 step 702 11000001000000000100011001010101 step 703 11000001000000000101100101010101 step 704 11000000000000001100100101010101 step 705 11000000000000001101011001010101 step 706 11000000000000000100011001010101 step 707 10000001000000000100011001010101 step 708 10000001000000000101010101010101 step 709 10000000000000001100010101010101 step 710 10000000000000001101010101010101 step 711 10000000000000000100010101010101 step 712 10000000000000010100010101010101 step 713 10000011000000010100010101010101 step 714 10000011000000010101010101010110 step 715 10000010000000011100010101010110 step 716 10000010000000011101100101010101 step 717 10000010000000010100100101010101 step 718 10000111000000010100100101010101 step 719 10000111000000010101010101011010 step 720 10000110000000011100010101011010 step 721 10000110000000011101100101010110 step 722 10000110000000010100100101010110 step 723 10000101000000010100100101010110 step 724 10000101000000010101010101011001 step 725 10000100000000011100010101011001 step 726 10000100000000011101100101010110 step 727 10000100000000010100100101010110 step 728 10001101000000010100100101010110 step 729 10001101000000010101010101101001 step 730 10001100000000011100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 731 10001100000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 732 10001100000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 733 10001111000000010100100101101010 fail ^^ step 734 10001111000000010101010101101010 step 735 10001110000000011100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 736 10001110000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 737 10001110000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 738 10001011000000010100100101101010 fail ^^ step 739 10001011000000010101010101100110 step 740 10001010000000011100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 741 10001010000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 742 10001010000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 743 10001001000000010100100101101001 fail ^^ step 744 10001001000000010101010101100101 step 745 10001000000000011100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 746 10001000000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 747 10001000000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 748 10011001000000010100100101101001 fail ^^ step 749 10011001000000010101010110100101 step 750 10011000000000011100010110100101 step 751 10011000000000011101100101101001 step 752 10011000000000010100100101101001 step 753 10011011000000010100100101101001 step 754 10011011000000010101010110100110 step 755 10011010000000011100010110100110 step 756 10011010000000011101100101101001 step 757 10011010000000010100100101101001 step 758 10011111000000010100100101101001 step 759 10011111000000010101010110101010 step 760 10011110000000011100010110101010 step 761 10011110000000011101100101101010 step 762 10011110000000010100100101101010 step 763 10011101000000010100100101101010 step 764 10011101000000010101010110101001 step 765 10011100000000011100010110101001 step 766 10011100000000011101100101101010 step 767 10011100000000010100100101101010 step 768 10010101000000010100100101101010 step 769 10010101000000010101010110011001 step 770 10010100000000011100010110011001 step 771 10010100000000011101100101100110 step 772 10010100000000010100100101100110 step 773 10010111000000010100100101100110 step 774 10010111000000010101010110011010 step 775 10010110000000011100010110011010 step 776 10010110000000011101100101100110 step 777 10010110000000010100100101100110 step 778 10010011000000010100100101100110 step 779 10010011000000010101010110010110 step 780 10010010000000011100010110010110 step 781 10010010000000011101100101100101 step 782 10010010000000010100100101100101 step 783 10010001000000010100100101100101 step 784 10010001000000010101010110010101 step 785 10010000000000011100010110010101 step 786 10010000000000011101100101100101 step 787 10010000000000010100100101100101 step 788 10110001000000010100100101100101 step 789 10110001000000010101011010010101 step 790 10110000000000011100011010010101 step 791 10110000000000011101100110100101 step 792 10110000000000010100100110100101 step 793 10110011000000010100100110100101 step 794 10110011000000010101011010010110 step 795 10110010000000011100011010010110 step 796 10110010000000011101100110100101 step 797 10110010000000010100100110100101 step 798 10110111000000010100100110100101 step 799 10110111000000010101011010011010 step 800 10110110000000011100011010011010 step 801 10110110000000011101100110100110 step 802 10110110000000010100100110100110 step 803 10110101000000010100100110100110 step 804 10110101000000010101011010011001 step 805 10110100000000011100011010011001 step 806 10110100000000011101100110100110 step 807 10110100000000010100100110100110 step 808 10111101000000010100100110100110 step 809 10111101000000010101011010101001 step 810 10111100000000011100011010101001 step 811 10111100000000011101100110101010 step 812 10111100000000010100100110101010 step 813 10111111000000010100100110101010 step 814 10111111000000010101011010101010 step 815 10111110000000011100011010101010 step 816 10111110000000011101100110101010 step 817 10111110000000010100100110101010 step 818 10111011000000010100100110101010 step 819 10111011000000010101011010100110 step 820 10111010000000011100011010100110 step 821 10111010000000011101100110101001 step 822 10111010000000010100100110101001 step 823 10111001000000010100100110101001 step 824 10111001000000010101011010100101 step 825 10111000000000011100011010100101 step 826 10111000000000011101100110101001 step 827 10111000000000010100100110101001 step 828 10101001000000010100100110101001 step 829 10101001000000010101011001100101 step 830 10101000000000011100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 831 10101000000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 832 10101000000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 833 10101011000000010100100110101001 fail ^^ step 834 10101011000000010101011001100110 step 835 10101010000000011100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 836 10101010000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 837 10101010000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 838 10101111000000010100100110101001 fail ^^ step 839 10101111000000010101011001101010 step 840 10101110000000011100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 841 10101110000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 842 10101110000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 843 10101101000000010100100110101010 fail ^^ step 844 10101101000000010101011001101001 step 845 10101100000000011100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 846 10101100000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 847 10101100000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 848 10100101000000010100100110101010 fail ^^ step 849 10100101000000010101011001011001 step 850 10100100000000011100011001011001 step 851 10100100000000011101100110010110 step 852 10100100000000010100100110010110 step 853 10100111000000010100100110010110 step 854 10100111000000010101011001011010 step 855 10100110000000011100011001011010 step 856 10100110000000011101100110010110 step 857 10100110000000010100100110010110 step 858 10100011000000010100100110010110 step 859 10100011000000010101011001010110 step 860 10100010000000011100011001010110 step 861 10100010000000011101100110010101 step 862 10100010000000010100100110010101 step 863 10100001000000010100100110010101 step 864 10100001000000010101011001010101 step 865 10100000000000011100011001010101 step 866 10100000000000011101100110010101 step 867 10100000000000010100100110010101 step 868 11100001000000010100100110010101 step 869 11100001000000010101101001010101 step 870 11100000000000011100101001010101 step 871 11100000000000011101101010010101 step 872 11100000000000010100101010010101 step 873 11100011000000010100101010010101 step 874 11100011000000010101101001010110 step 875 11100010000000011100101001010110 step 876 11100010000000011101101010010101 step 877 11100010000000010100101010010101 step 878 11100111000000010100101010010101 step 879 11100111000000010101101001011010 step 880 11100110000000011100101001011010 step 881 11100110000000011101101010010110 step 882 11100110000000010100101010010110 step 883 11100101000000010100101010010110 step 884 11100101000000010101101001011001 step 885 11100100000000011100101001011001 step 886 11100100000000011101101010010110 step 887 11100100000000010100101010010110 step 888 11101101000000010100101010010110 step 889 11101101000000010101101001101001 step 890 11101100000000011100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 891 11101100000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 892 11101100000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 893 11101111000000010100101010101010 fail ^^ step 894 11101111000000010101101001101010 step 895 11101110000000011100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 896 11101110000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 897 11101110000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 898 11101011000000010100101010101010 fail ^^ step 899 11101011000000010101101001100110 step 900 11101010000000011100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 901 11101010000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 902 11101010000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 903 11101001000000010100101010101001 fail ^^ step 904 11101001000000010101101001100101 step 905 11101000000000011100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 906 11101000000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 907 11101000000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 908 11111001000000010100101010101001 fail ^^ step 909 11111001000000010101101010100101 step 910 11111000000000011100101010100101 step 911 11111000000000011101101010101001 step 912 11111000000000010100101010101001 step 913 11111011000000010100101010101001 step 914 11111011000000010101101010100110 step 915 11111010000000011100101010100110 step 916 11111010000000011101101010101001 step 917 11111010000000010100101010101001 step 918 11111111000000010100101010101001 step 919 11111111000000010101101010101010 step 920 11111110000000011100101010101010 step 921 11111110000000011101101010101010 step 922 11111110000000010100101010101010 step 923 11111101000000010100101010101010 step 924 11111101000000010101101010101001 step 925 11111100000000011100101010101001 step 926 11111100000000011101101010101010 step 927 11111100000000010100101010101010 step 928 11110101000000010100101010101010 step 929 11110101000000010101101010011001 step 930 11110100000000011100101010011001 step 931 11110100000000011101101010100110 step 932 11110100000000010100101010100110 step 933 11110111000000010100101010100110 step 934 11110111000000010101101010011010 step 935 11110110000000011100101010011010 step 936 11110110000000011101101010100110 step 937 11110110000000010100101010100110 step 938 11110011000000010100101010100110 step 939 11110011000000010101101010010110 step 940 11110010000000011100101010010110 step 941 11110010000000011101101010100101 step 942 11110010000000010100101010100101 step 943 11110001000000010100101010100101 step 944 11110001000000010101101010010101 step 945 11110000000000011100101010010101 step 946 11110000000000011101101010100101 step 947 11110000000000010100101010100101 step 948 11010001000000010100101010100101 step 949 11010001000000010101100110010101 step 950 11010000000000011100100110010101 step 951 11010000000000011101101001100101 step 952 11010000000000010100101001100101 step 953 11010011000000010100101001100101 step 954 11010011000000010101100110010110 step 955 11010010000000011100100110010110 step 956 11010010000000011101101001100101 step 957 11010010000000010100101001100101 step 958 11010111000000010100101001100101 step 959 11010111000000010101100110011010 step 960 11010110000000011100100110011010 step 961 11010110000000011101101001100110 step 962 11010110000000010100101001100110 step 963 11010101000000010100101001100110 step 964 11010101000000010101100110011001 step 965 11010100000000011100100110011001 step 966 11010100000000011101101001100110 step 967 11010100000000010100101001100110 step 968 11011101000000010100101001100110 step 969 11011101000000010101100110101001 step 970 11011100000000011100100110101001 step 971 11011100000000011101101001101010 step 972 11011100000000010100101001101010 step 973 11011111000000010100101001101010 step 974 11011111000000010101100110101010 step 975 11011110000000011100100110101010 step 976 11011110000000011101101001101010 step 977 11011110000000010100101001101010 step 978 11011011000000010100101001101010 step 979 11011011000000010101100110100110 step 980 11011010000000011100100110100110 step 981 11011010000000011101101001101001 step 982 11011010000000010100101001101001 step 983 11011001000000010100101001101001 step 984 11011001000000010101100110100101 step 985 11011000000000011100100110100101 step 986 11011000000000011101101001101001 step 987 11011000000000010100101001101001 step 988 11001001000000010100101001101001 step 989 11001001000000010101100101100101 step 990 11001000000000011100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 991 11001000000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 992 11001000000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 993 11001011000000010100101001101001 fail ^^ step 994 11001011000000010101100101100110 step 995 11001010000000011100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 996 11001010000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 997 11001010000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 998 11001111000000010100101001101001 fail ^^ step 999 11001111000000010101100101101010 step 1000 11001110000000011100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1001 11001110000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1002 11001110000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1003 11001101000000010100101001101010 fail ^^ step 1004 11001101000000010101100101101001 step 1005 11001100000000011100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1006 11001100000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1007 11001100000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1008 11000101000000010100101001101010 fail ^^ step 1009 11000101000000010101100101011001 step 1010 11000100000000011100100101011001 step 1011 11000100000000011101101001010110 step 1012 11000100000000010100101001010110 step 1013 11000111000000010100101001010110 step 1014 11000111000000010101100101011010 step 1015 11000110000000011100100101011010 step 1016 11000110000000011101101001010110 step 1017 11000110000000010100101001010110 step 1018 11000011000000010100101001010110 step 1019 11000011000000010101100101010110 step 1020 11000010000000011100100101010110 step 1021 11000010000000011101101001010101 step 1022 11000010000000010100101001010101 step 1023 11000001000000010100101001010101 step 1024 11000001000000010101100101010101 step 1025 11000000000000011100100101010101 step 1026 11000000000000011101101001010101 step 1027 11000000000000010100101001010101 step 1028 10000001000000010100101001010101 step 1029 10000001000000010101010101010101 step 1030 10000000000000011100010101010101 step 1031 10000000000000011101100101010101 step 1032 10000000000000010100100101010101 step 1033 10000000000000010000100101010101 step 1034 10000011000000010000100101010101 step 1035 10000011000000010001010101010110 step 1036 10000010000000010010010101010110 step 1037 10000010000000010011010101011001 step 1038 10000010000000010000010101011001 step 1039 10000111000000010000010101011001 step 1040 10000111000000010001010101011010 step 1041 10000110000000010010010101011010 step 1042 10000110000000010011010101101001 step 1043 10000110000000010000010101101001 step 1044 10000101000000010000010101101001 step 1045 10000101000000010001010101011001 step 1046 10000100000000010010010101011001 step 1047 10000100000000010011010101100101 step 1048 10000100000000010000010101100101 step 1049 10001101000000010000010101100101 step 1050 10001101000000010001010101101001 step 1051 10001100000000010010010101101001 step 1052 10001100000000010011010110100101 step 1053 10001100000000010000010110100101 step 1054 10001111000000010000010110100101 step 1055 10001111000000010001010101101010 step 1056 10001110000000010010010101101010 step 1057 10001110000000010011010110101001 step 1058 10001110000000010000010110101001 step 1059 10001011000000010000010110101001 step 1060 10001011000000010001010101100110 step 1061 10001010000000010010010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1062 10001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1063 10001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1064 10001001000000010000010110101001 fail ^^ step 1065 10001001000000010001010101100101 step 1066 10001000000000010010010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1067 10001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1068 10001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1069 10011001000000010000010110100101 fail ^^ step 1070 10011001000000010001010110100101 step 1071 10011000000000010010010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1072 10011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1073 10011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1074 10011011000000010000011010100101 fail ^^ step 1075 10011011000000010001010110100110 step 1076 10011010000000010010010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1077 10011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1078 10011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1079 10011111000000010000011010101001 fail ^^ step 1080 10011111000000010001010110101010 step 1081 10011110000000010010010110101010 step 1082 10011110000000010011011010101001 step 1083 10011110000000010000011010101001 step 1084 10011101000000010000011010101001 step 1085 10011101000000010001010110101001 step 1086 10011100000000010010010110101001 step 1087 10011100000000010011011010100101 step 1088 10011100000000010000011010100101 step 1089 10010101000000010000011010100101 step 1090 10010101000000010001010110011001 step 1091 10010100000000010010010110011001 step 1092 10010100000000010011011001100101 step 1093 10010100000000010000011001100101 step 1094 10010111000000010000011001100101 step 1095 10010111000000010001010110011010 step 1096 10010110000000010010010110011010 step 1097 10010110000000010011011001101001 step 1098 10010110000000010000011001101001 step 1099 10010011000000010000011001101001 step 1100 10010011000000010001010110010110 step 1101 10010010000000010010010110010110 step 1102 10010010000000010011011001011001 step 1103 10010010000000010000011001011001 step 1104 10010001000000010000011001011001 step 1105 10010001000000010001010110010101 step 1106 10010000000000010010010110010101 step 1107 10010000000000010011011001010101 step 1108 10010000000000010000011001010101 step 1109 10110001000000010000011001010101 step 1110 10110001000000010001011010010101 step 1111 10110000000000010010011010010101 step 1112 10110000000000010011101001010101 step 1113 10110000000000010000101001010101 step 1114 10110011000000010000101001010101 step 1115 10110011000000010001011010010110 step 1116 10110010000000010010011010010110 step 1117 10110010000000010011101001011001 step 1118 10110010000000010000101001011001 step 1119 10110111000000010000101001011001 step 1120 10110111000000010001011010011010 step 1121 10110110000000010010011010011010 step 1122 10110110000000010011101001101001 step 1123 10110110000000010000101001101001 step 1124 10110101000000010000101001101001 step 1125 10110101000000010001011010011001 step 1126 10110100000000010010011010011001 step 1127 10110100000000010011101001100101 step 1128 10110100000000010000101001100101 step 1129 10111101000000010000101001100101 step 1130 10111101000000010001011010101001 step 1131 10111100000000010010011010101001 step 1132 10111100000000010011101010100101 step 1133 10111100000000010000101010100101 step 1134 10111111000000010000101010100101 step 1135 10111111000000010001011010101010 step 1136 10111110000000010010011010101010 step 1137 10111110000000010011101010101001 step 1138 10111110000000010000101010101001 step 1139 10111011000000010000101010101001 step 1140 10111011000000010001011010100110 step 1141 10111010000000010010011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 1142 10111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1143 10111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1144 10111001000000010000101010101001 fail ^^ step 1145 10111001000000010001011010100101 step 1146 10111000000000010010011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1147 10111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1148 10111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1149 10101001000000010000101010100101 fail ^^ step 1150 10101001000000010001011001100101 step 1151 10101000000000010010011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 1152 10101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1153 10101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1154 10101011000000010000100110100101 fail ^^ step 1155 10101011000000010001011001100110 step 1156 10101010000000010010011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 1157 10101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1158 10101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1159 10101111000000010000100110101001 fail ^^ step 1160 10101111000000010001011001101010 step 1161 10101110000000010010011001101010 step 1162 10101110000000010011100110101001 step 1163 10101110000000010000100110101001 step 1164 10101101000000010000100110101001 step 1165 10101101000000010001011001101001 step 1166 10101100000000010010011001101001 step 1167 10101100000000010011100110100101 step 1168 10101100000000010000100110100101 step 1169 10100101000000010000100110100101 step 1170 10100101000000010001011001011001 step 1171 10100100000000010010011001011001 step 1172 10100100000000010011100101100101 step 1173 10100100000000010000100101100101 step 1174 10100111000000010000100101100101 step 1175 10100111000000010001011001011010 step 1176 10100110000000010010011001011010 step 1177 10100110000000010011100101101001 step 1178 10100110000000010000100101101001 step 1179 10100011000000010000100101101001 step 1180 10100011000000010001011001010110 step 1181 10100010000000010010011001010110 step 1182 10100010000000010011100101011001 step 1183 10100010000000010000100101011001 step 1184 10100001000000010000100101011001 step 1185 10100001000000010001011001010101 step 1186 10100000000000010010011001010101 step 1187 10100000000000010011100101010101 step 1188 10100000000000010000100101010101 step 1189 11100001000000010000100101010101 step 1190 11100001000000010001101001010101 step 1191 11100000000000010010101001010101 step 1192 11100000000000010011100101010101 step 1193 11100000000000010000100101010101 step 1194 11100011000000010000100101010101 step 1195 11100011000000010001101001010110 step 1196 11100010000000010010101001010110 step 1197 11100010000000010011100101011001 step 1198 11100010000000010000100101011001 step 1199 11100111000000010000100101011001 step 1200 11100111000000010001101001011010 step 1201 11100110000000010010101001011010 step 1202 11100110000000010011100101101001 step 1203 11100110000000010000100101101001 step 1204 11100101000000010000100101101001 step 1205 11100101000000010001101001011001 step 1206 11100100000000010010101001011001 step 1207 11100100000000010011100101100101 step 1208 11100100000000010000100101100101 step 1209 11101101000000010000100101100101 step 1210 11101101000000010001101001101001 step 1211 11101100000000010010101001101001 step 1212 11101100000000010011100110100101 step 1213 11101100000000010000100110100101 step 1214 11101111000000010000100110100101 step 1215 11101111000000010001101001101010 step 1216 11101110000000010010101001101010 step 1217 11101110000000010011100110101001 step 1218 11101110000000010000100110101001 step 1219 11101011000000010000100110101001 step 1220 11101011000000010001101001100110 step 1221 11101010000000010010101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 1001 step 1222 11101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1223 11101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1224 11101001000000010000100110101001 fail ^^ step 1225 11101001000000010001101001100101 step 1226 11101000000000010010101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1227 11101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1228 11101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1229 11111001000000010000100110100101 fail ^^ step 1230 11111001000000010001101010100101 step 1231 11111000000000010010101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1232 11111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1233 11111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1234 11111011000000010000101010100101 fail ^^ step 1235 11111011000000010001101010100110 step 1236 11111010000000010010101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 1237 11111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1238 11111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1239 11111111000000010000101010101001 fail ^^ step 1240 11111111000000010001101010101010 step 1241 11111110000000010010101010101010 step 1242 11111110000000010011101010101001 step 1243 11111110000000010000101010101001 step 1244 11111101000000010000101010101001 step 1245 11111101000000010001101010101001 step 1246 11111100000000010010101010101001 step 1247 11111100000000010011101010100101 step 1248 11111100000000010000101010100101 step 1249 11110101000000010000101010100101 step 1250 11110101000000010001101010011001 step 1251 11110100000000010010101010011001 step 1252 11110100000000010011101001100101 step 1253 11110100000000010000101001100101 step 1254 11110111000000010000101001100101 step 1255 11110111000000010001101010011010 step 1256 11110110000000010010101010011010 step 1257 11110110000000010011101001101001 step 1258 11110110000000010000101001101001 step 1259 11110011000000010000101001101001 step 1260 11110011000000010001101010010110 step 1261 11110010000000010010101010010110 step 1262 11110010000000010011101001011001 step 1263 11110010000000010000101001011001 step 1264 11110001000000010000101001011001 step 1265 11110001000000010001101010010101 step 1266 11110000000000010010101010010101 step 1267 11110000000000010011101001010101 step 1268 11110000000000010000101001010101 step 1269 11010001000000010000101001010101 step 1270 11010001000000010001100110010101 step 1271 11010000000000010010100110010101 step 1272 11010000000000010011011001010101 step 1273 11010000000000010000011001010101 step 1274 11010011000000010000011001010101 step 1275 11010011000000010001100110010110 step 1276 11010010000000010010100110010110 step 1277 11010010000000010011011001011001 step 1278 11010010000000010000011001011001 step 1279 11010111000000010000011001011001 step 1280 11010111000000010001100110011010 step 1281 11010110000000010010100110011010 step 1282 11010110000000010011011001101001 step 1283 11010110000000010000011001101001 step 1284 11010101000000010000011001101001 step 1285 11010101000000010001100110011001 step 1286 11010100000000010010100110011001 step 1287 11010100000000010011011001100101 step 1288 11010100000000010000011001100101 step 1289 11011101000000010000011001100101 step 1290 11011101000000010001100110101001 step 1291 11011100000000010010100110101001 step 1292 11011100000000010011011010100101 step 1293 11011100000000010000011010100101 step 1294 11011111000000010000011010100101 step 1295 11011111000000010001100110101010 step 1296 11011110000000010010100110101010 step 1297 11011110000000010011011010101001 step 1298 11011110000000010000011010101001 step 1299 11011011000000010000011010101001 step 1300 11011011000000010001100110100110 step 1301 11011010000000010010100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 1302 11011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1303 11011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1304 11011001000000010000011010101001 fail ^^ step 1305 11011001000000010001100110100101 step 1306 11011000000000010010100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 1307 11011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1308 11011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1309 11001001000000010000011010100101 fail ^^ step 1310 11001001000000010001100101100101 step 1311 11001000000000010010100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 1312 11001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1313 11001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1314 11001011000000010000010110100101 fail ^^ step 1315 11001011000000010001100101100110 step 1316 11001010000000010010100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 1001 step 1317 11001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1318 11001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1319 11001111000000010000010110101001 fail ^^ step 1320 11001111000000010001100101101010 step 1321 11001110000000010010100101101010 step 1322 11001110000000010011010110101001 step 1323 11001110000000010000010110101001 step 1324 11001101000000010000010110101001 step 1325 11001101000000010001100101101001 step 1326 11001100000000010010100101101001 step 1327 11001100000000010011010110100101 step 1328 11001100000000010000010110100101 step 1329 11000101000000010000010110100101 step 1330 11000101000000010001100101011001 step 1331 11000100000000010010100101011001 step 1332 11000100000000010011010101100101 step 1333 11000100000000010000010101100101 step 1334 11000111000000010000010101100101 step 1335 11000111000000010001100101011010 step 1336 11000110000000010010100101011010 step 1337 11000110000000010011010101101001 step 1338 11000110000000010000010101101001 step 1339 11000011000000010000010101101001 step 1340 11000011000000010001100101010110 step 1341 11000010000000010010100101010110 step 1342 11000010000000010011010101011001 step 1343 11000010000000010000010101011001 step 1344 11000001000000010000010101011001 step 1345 11000001000000010001100101010101 step 1346 11000000000000010010100101010101 step 1347 11000000000000010011010101010101 step 1348 11000000000000010000010101010101 step 1349 10000001000000010000010101010101 step 1350 10000001000000010001010101010101 step 1351 10000000000000010010010101010101 step 1352 10000000000000010011010101010101 step 1353 10000000000000010000010101010101 step 1354 10000000000000010100010101010101 step 1355 10000011000000010100010101010101 step 1356 10000011000000010101010101010110 step 1357 10000010000000010110010101010110 step 1358 10000010000000010111010101011010 step 1359 10000010000000010100010101011010 step 1360 10000111000000010100010101011010 step 1361 10000111000000010101010101011010 step 1362 10000110000000010110010101011010 step 1363 10000110000000010111010101101010 step 1364 10000110000000010100010101101010 step 1365 10000101000000010100010101101010 step 1366 10000101000000010101010101011001 step 1367 10000100000000010110010101011001 step 1368 10000100000000010111010101100110 step 1369 10000100000000010100010101100110 step 1370 10001101000000010100010101100110 step 1371 10001101000000010101010101101001 step 1372 10001100000000010110010101101001 step 1373 10001100000000010111010110100110 step 1374 10001100000000010100010110100110 step 1375 10001111000000010100010110100110 step 1376 10001111000000010101010101101010 step 1377 10001110000000010110010101101010 step 1378 10001110000000010111010110101010 step 1379 10001110000000010100010110101010 step 1380 10001011000000010100010110101010 step 1381 10001011000000010101010101100110 step 1382 10001010000000010110010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1383 10001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1384 10001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1385 10001001000000010100010110101010 fail ^^ step 1386 10001001000000010101010101100101 step 1387 10001000000000010110010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1388 10001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1389 10001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1390 10011001000000010100010110100110 fail ^^ step 1391 10011001000000010101010110100101 step 1392 10011000000000010110010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1393 10011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1394 10011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1395 10011011000000010100011010100110 fail ^^ step 1396 10011011000000010101010110100110 step 1397 10011010000000010110010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1398 10011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1399 10011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1400 10011111000000010100011010101010 fail ^^ step 1401 10011111000000010101010110101010 step 1402 10011110000000010110010110101010 step 1403 10011110000000010111011010101010 step 1404 10011110000000010100011010101010 step 1405 10011101000000010100011010101010 step 1406 10011101000000010101010110101001 step 1407 10011100000000010110010110101001 step 1408 10011100000000010111011010100110 step 1409 10011100000000010100011010100110 step 1410 10010101000000010100011010100110 step 1411 10010101000000010101010110011001 step 1412 10010100000000010110010110011001 step 1413 10010100000000010111011001100110 step 1414 10010100000000010100011001100110 step 1415 10010111000000010100011001100110 step 1416 10010111000000010101010110011010 step 1417 10010110000000010110010110011010 step 1418 10010110000000010111011001101010 step 1419 10010110000000010100011001101010 step 1420 10010011000000010100011001101010 step 1421 10010011000000010101010110010110 step 1422 10010010000000010110010110010110 step 1423 10010010000000010111011001011010 step 1424 10010010000000010100011001011010 step 1425 10010001000000010100011001011010 step 1426 10010001000000010101010110010101 step 1427 10010000000000010110010110010101 step 1428 10010000000000010111011001010110 step 1429 10010000000000010100011001010110 step 1430 10110001000000010100011001010110 step 1431 10110001000000010101011010010101 step 1432 10110000000000010110011010010101 step 1433 10110000000000010111101001010110 step 1434 10110000000000010100101001010110 step 1435 10110011000000010100101001010110 step 1436 10110011000000010101011010010110 step 1437 10110010000000010110011010010110 step 1438 10110010000000010111101001011010 step 1439 10110010000000010100101001011010 step 1440 10110111000000010100101001011010 step 1441 10110111000000010101011010011010 step 1442 10110110000000010110011010011010 step 1443 10110110000000010111101001101010 step 1444 10110110000000010100101001101010 step 1445 10110101000000010100101001101010 step 1446 10110101000000010101011010011001 step 1447 10110100000000010110011010011001 step 1448 10110100000000010111101001100110 step 1449 10110100000000010100101001100110 step 1450 10111101000000010100101001100110 step 1451 10111101000000010101011010101001 step 1452 10111100000000010110011010101001 step 1453 10111100000000010111101010100110 step 1454 10111100000000010100101010100110 step 1455 10111111000000010100101010100110 step 1456 10111111000000010101011010101010 step 1457 10111110000000010110011010101010 step 1458 10111110000000010111101010101010 step 1459 10111110000000010100101010101010 step 1460 10111011000000010100101010101010 step 1461 10111011000000010101011010100110 step 1462 10111010000000010110011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1463 10111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1464 10111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1465 10111001000000010100101010101010 fail ^^ step 1466 10111001000000010101011010100101 step 1467 10111000000000010110011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1468 10111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1469 10111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1470 10101001000000010100101010100110 fail ^^ step 1471 10101001000000010101011001100101 step 1472 10101000000000010110011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1473 10101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1474 10101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1475 10101011000000010100100110100110 fail ^^ step 1476 10101011000000010101011001100110 step 1477 10101010000000010110011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1478 10101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1479 10101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1480 10101111000000010100100110101010 fail ^^ step 1481 10101111000000010101011001101010 step 1482 10101110000000010110011001101010 step 1483 10101110000000010111100110101010 step 1484 10101110000000010100100110101010 step 1485 10101101000000010100100110101010 step 1486 10101101000000010101011001101001 step 1487 10101100000000010110011001101001 step 1488 10101100000000010111100110100110 step 1489 10101100000000010100100110100110 step 1490 10100101000000010100100110100110 step 1491 10100101000000010101011001011001 step 1492 10100100000000010110011001011001 step 1493 10100100000000010111100101100110 step 1494 10100100000000010100100101100110 step 1495 10100111000000010100100101100110 step 1496 10100111000000010101011001011010 step 1497 10100110000000010110011001011010 step 1498 10100110000000010111100101101010 step 1499 10100110000000010100100101101010 step 1500 10100011000000010100100101101010 step 1501 10100011000000010101011001010110 step 1502 10100010000000010110011001010110 step 1503 10100010000000010111100101011010 step 1504 10100010000000010100100101011010 step 1505 10100001000000010100100101011010 step 1506 10100001000000010101011001010101 step 1507 10100000000000010110011001010101 step 1508 10100000000000010111100101010110 step 1509 10100000000000010100100101010110 step 1510 11100001000000010100100101010110 step 1511 11100001000000010101101001010101 step 1512 11100000000000010110101001010101 step 1513 11100000000000010111100101010110 step 1514 11100000000000010100100101010110 step 1515 11100011000000010100100101010110 step 1516 11100011000000010101101001010110 step 1517 11100010000000010110101001010110 step 1518 11100010000000010111100101011010 step 1519 11100010000000010100100101011010 step 1520 11100111000000010100100101011010 step 1521 11100111000000010101101001011010 step 1522 11100110000000010110101001011010 step 1523 11100110000000010111100101101010 step 1524 11100110000000010100100101101010 step 1525 11100101000000010100100101101010 step 1526 11100101000000010101101001011001 step 1527 11100100000000010110101001011001 step 1528 11100100000000010111100101100110 step 1529 11100100000000010100100101100110 step 1530 11101101000000010100100101100110 step 1531 11101101000000010101101001101001 step 1532 11101100000000010110101001101001 step 1533 11101100000000010111100110100110 step 1534 11101100000000010100100110100110 step 1535 11101111000000010100100110100110 step 1536 11101111000000010101101001101010 step 1537 11101110000000010110101001101010 step 1538 11101110000000010111100110101010 step 1539 11101110000000010100100110101010 step 1540 11101011000000010100100110101010 step 1541 11101011000000010101101001100110 step 1542 11101010000000010110101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1543 11101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1544 11101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1545 11101001000000010100100110101010 fail ^^ step 1546 11101001000000010101101001100101 step 1547 11101000000000010110101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1548 11101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1549 11101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1550 11111001000000010100100110100110 fail ^^ step 1551 11111001000000010101101010100101 step 1552 11111000000000010110101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1553 11111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1554 11111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1555 11111011000000010100101010100110 fail ^^ step 1556 11111011000000010101101010100110 step 1557 11111010000000010110101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1558 11111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1559 11111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1560 11111111000000010100101010101010 fail ^^ step 1561 11111111000000010101101010101010 step 1562 11111110000000010110101010101010 step 1563 11111110000000010111101010101010 step 1564 11111110000000010100101010101010 step 1565 11111101000000010100101010101010 step 1566 11111101000000010101101010101001 step 1567 11111100000000010110101010101001 step 1568 11111100000000010111101010100110 step 1569 11111100000000010100101010100110 step 1570 11110101000000010100101010100110 step 1571 11110101000000010101101010011001 step 1572 11110100000000010110101010011001 step 1573 11110100000000010111101001100110 step 1574 11110100000000010100101001100110 step 1575 11110111000000010100101001100110 step 1576 11110111000000010101101010011010 step 1577 11110110000000010110101010011010 step 1578 11110110000000010111101001101010 step 1579 11110110000000010100101001101010 step 1580 11110011000000010100101001101010 step 1581 11110011000000010101101010010110 step 1582 11110010000000010110101010010110 step 1583 11110010000000010111101001011010 step 1584 11110010000000010100101001011010 step 1585 11110001000000010100101001011010 step 1586 11110001000000010101101010010101 step 1587 11110000000000010110101010010101 step 1588 11110000000000010111101001010110 step 1589 11110000000000010100101001010110 step 1590 11010001000000010100101001010110 step 1591 11010001000000010101100110010101 step 1592 11010000000000010110100110010101 step 1593 11010000000000010111011001010110 step 1594 11010000000000010100011001010110 step 1595 11010011000000010100011001010110 step 1596 11010011000000010101100110010110 step 1597 11010010000000010110100110010110 step 1598 11010010000000010111011001011010 step 1599 11010010000000010100011001011010 step 1600 11010111000000010100011001011010 step 1601 11010111000000010101100110011010 step 1602 11010110000000010110100110011010 step 1603 11010110000000010111011001101010 step 1604 11010110000000010100011001101010 step 1605 11010101000000010100011001101010 step 1606 11010101000000010101100110011001 step 1607 11010100000000010110100110011001 step 1608 11010100000000010111011001100110 step 1609 11010100000000010100011001100110 step 1610 11011101000000010100011001100110 step 1611 11011101000000010101100110101001 step 1612 11011100000000010110100110101001 step 1613 11011100000000010111011010100110 step 1614 11011100000000010100011010100110 step 1615 11011111000000010100011010100110 step 1616 11011111000000010101100110101010 step 1617 11011110000000010110100110101010 step 1618 11011110000000010111011010101010 step 1619 11011110000000010100011010101010 step 1620 11011011000000010100011010101010 step 1621 11011011000000010101100110100110 step 1622 11011010000000010110100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1623 11011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1624 11011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1625 11011001000000010100011010101010 fail ^^ step 1626 11011001000000010101100110100101 step 1627 11011000000000010110100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1628 11011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1629 11011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1630 11001001000000010100011010100110 fail ^^ step 1631 11001001000000010101100101100101 step 1632 11001000000000010110100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1633 11001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1634 11001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1635 11001011000000010100010110100110 fail ^^ step 1636 11001011000000010101100101100110 step 1637 11001010000000010110100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1638 11001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1639 11001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1640 11001111000000010100010110101010 fail ^^ step 1641 11001111000000010101100101101010 step 1642 11001110000000010110100101101010 step 1643 11001110000000010111010110101010 step 1644 11001110000000010100010110101010 step 1645 11001101000000010100010110101010 step 1646 11001101000000010101100101101001 step 1647 11001100000000010110100101101001 step 1648 11001100000000010111010110100110 step 1649 11001100000000010100010110100110 step 1650 11000101000000010100010110100110 step 1651 11000101000000010101100101011001 step 1652 11000100000000010110100101011001 step 1653 11000100000000010111010101100110 step 1654 11000100000000010100010101100110 step 1655 11000111000000010100010101100110 step 1656 11000111000000010101100101011010 step 1657 11000110000000010110100101011010 step 1658 11000110000000010111010101101010 step 1659 11000110000000010100010101101010 step 1660 11000011000000010100010101101010 step 1661 11000011000000010101100101010110 step 1662 11000010000000010110100101010110 step 1663 11000010000000010111010101011010 step 1664 11000010000000010100010101011010 step 1665 11000001000000010100010101011010 step 1666 11000001000000010101100101010101 step 1667 11000000000000010110100101010101 step 1668 11000000000000010111010101010110 step 1669 11000000000000010100010101010110 step 1670 10000001000000010100010101010110 step 1671 10000001000000010101010101010101 step 1672 10000000000000010110010101010101 step 1673 10000000000000010111010101010110 step 1674 10000000000000010100010101010110 step 1675 00000000000000010100010101010101 step 1676 10000000000000010100010101010101 step 1677 11111110111111010100010101010101 test 6: *** FAIL *************************** 192 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 6, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 01111110111111010100010101010101 step 2 11111110111111010100010101010101 step 3 11111111111111010100010101010101 step 4 10000011111111010100010101010101 step 5 10000011111111010101010101010110 step 6 10000011111111010100010101010110 step 7 10000111111111010100010101010110 step 8 10000111111111010101010101011010 step 9 10000111111111010100010101011010 step 10 10000101111111010100010101011010 step 11 10000101111111010101010101011001 step 12 10000101111111010100010101011001 step 13 10001101111111010100010101011001 step 14 10001101111111010101010101101001 step 15 10001101111111010100010101101001 step 16 10001111111111010100010101101001 step 17 10001111111111010101010101101010 step 18 10001111111111010100010101101010 step 19 10001011111111010100010101101010 step 20 10001011111111010101010101100110 step 21 10001011111111010100010101100110 step 22 10001001111111010100010101100110 step 23 10001001111111010101010101100101 step 24 10001001111111010100010101100101 step 25 10011001111111010100010101100101 step 26 10011001111111010101010110100101 step 27 10011001111111010100010110100101 step 28 10011011111111010100010110100101 step 29 10011011111111010101010110100110 step 30 10011011111111010100010110100110 step 31 10011111111111010100010110100110 step 32 10011111111111010101010110101010 step 33 10011111111111010100010110101010 step 34 10011101111111010100010110101010 step 35 10011101111111010101010110101001 step 36 10011101111111010100010110101001 step 37 10010101111111010100010110101001 step 38 10010101111111010101010110011001 step 39 10010101111111010100010110011001 step 40 10010111111111010100010110011001 step 41 10010111111111010101010110011010 step 42 10010111111111010100010110011010 step 43 10010011111111010100010110011010 step 44 10010011111111010101010110010110 step 45 10010011111111010100010110010110 step 46 10010001111111010100010110010110 step 47 10010001111111010101010110010101 step 48 10010001111111010100010110010101 step 49 10110001111111010100010110010101 step 50 10110001111111010101011010010101 step 51 10110001111111010100011010010101 step 52 10110011111111010100011010010101 step 53 10110011111111010101011010010110 step 54 10110011111111010100011010010110 step 55 10110111111111010100011010010110 step 56 10110111111111010101011010011010 step 57 10110111111111010100011010011010 step 58 10110101111111010100011010011010 step 59 10110101111111010101011010011001 step 60 10110101111111010100011010011001 step 61 10111101111111010100011010011001 step 62 10111101111111010101011010101001 step 63 10111101111111010100011010101001 step 64 10111111111111010100011010101001 step 65 10111111111111010101011010101010 step 66 10111111111111010100011010101010 step 67 10111011111111010100011010101010 step 68 10111011111111010101011010100110 step 69 10111011111111010100011010100110 step 70 10111001111111010100011010100110 step 71 10111001111111010101011010100101 step 72 10111001111111010100011010100101 step 73 10101001111111010100011010100101 step 74 10101001111111010101011001100101 step 75 10101001111111010100011001100101 step 76 10101011111111010100011001100101 step 77 10101011111111010101011001100110 step 78 10101011111111010100011001100110 step 79 10101111111111010100011001100110 step 80 10101111111111010101011001101010 step 81 10101111111111010100011001101010 step 82 10101101111111010100011001101010 step 83 10101101111111010101011001101001 step 84 10101101111111010100011001101001 step 85 10100101111111010100011001101001 step 86 10100101111111010101011001011001 step 87 10100101111111010100011001011001 step 88 10100111111111010100011001011001 step 89 10100111111111010101011001011010 step 90 10100111111111010100011001011010 step 91 10100011111111010100011001011010 step 92 10100011111111010101011001010110 step 93 10100011111111010100011001010110 step 94 10100001111111010100011001010110 step 95 10100001111111010101011001010101 step 96 10100001111111010100011001010101 step 97 11100001111111010100011001010101 step 98 11100001111111010101101001010101 step 99 11100001111111010100101001010101 step 100 11100011111111010100101001010101 step 101 11100011111111010101101001010110 step 102 11100011111111010100101001010110 step 103 11100111111111010100101001010110 step 104 11100111111111010101101001011010 step 105 11100111111111010100101001011010 step 106 11100101111111010100101001011010 step 107 11100101111111010101101001011001 step 108 11100101111111010100101001011001 step 109 11101101111111010100101001011001 step 110 11101101111111010101101001101001 step 111 11101101111111010100101001101001 step 112 11101111111111010100101001101001 step 113 11101111111111010101101001101010 step 114 11101111111111010100101001101010 step 115 11101011111111010100101001101010 step 116 11101011111111010101101001100110 step 117 11101011111111010100101001100110 step 118 11101001111111010100101001100110 step 119 11101001111111010101101001100101 step 120 11101001111111010100101001100101 step 121 11111001111111010100101001100101 step 122 11111001111111010101101010100101 step 123 11111001111111010100101010100101 step 124 11111011111111010100101010100101 step 125 11111011111111010101101010100110 step 126 11111011111111010100101010100110 step 127 11111111111111010100101010100110 step 128 11111111111111010101101010101010 step 129 11111111111111010100101010101010 step 130 11111101111111010100101010101010 step 131 11111101111111010101101010101001 step 132 11111101111111010100101010101001 step 133 11110101111111010100101010101001 step 134 11110101111111010101101010011001 step 135 11110101111111010100101010011001 step 136 11110111111111010100101010011001 step 137 11110111111111010101101010011010 step 138 11110111111111010100101010011010 step 139 11110011111111010100101010011010 step 140 11110011111111010101101010010110 step 141 11110011111111010100101010010110 step 142 11110001111111010100101010010110 step 143 11110001111111010101101010010101 step 144 11110001111111010100101010010101 step 145 11010001111111010100101010010101 step 146 11010001111111010101100110010101 step 147 11010001111111010100100110010101 step 148 11010011111111010100100110010101 step 149 11010011111111010101100110010110 step 150 11010011111111010100100110010110 step 151 11010111111111010100100110010110 step 152 11010111111111010101100110011010 step 153 11010111111111010100100110011010 step 154 11010101111111010100100110011010 step 155 11010101111111010101100110011001 step 156 11010101111111010100100110011001 step 157 11011101111111010100100110011001 step 158 11011101111111010101100110101001 step 159 11011101111111010100100110101001 step 160 11011111111111010100100110101001 step 161 11011111111111010101100110101010 step 162 11011111111111010100100110101010 step 163 11011011111111010100100110101010 step 164 11011011111111010101100110100110 step 165 11011011111111010100100110100110 step 166 11011001111111010100100110100110 step 167 11011001111111010101100110100101 step 168 11011001111111010100100110100101 step 169 11001001111111010100100110100101 step 170 11001001111111010101100101100101 step 171 11001001111111010100100101100101 step 172 11001011111111010100100101100101 step 173 11001011111111010101100101100110 step 174 11001011111111010100100101100110 step 175 11001111111111010100100101100110 step 176 11001111111111010101100101101010 step 177 11001111111111010100100101101010 step 178 11001101111111010100100101101010 step 179 11001101111111010101100101101001 step 180 11001101111111010100100101101001 step 181 11000101111111010100100101101001 step 182 11000101111111010101100101011001 step 183 11000101111111010100100101011001 step 184 11000111111111010100100101011001 step 185 11000111111111010101100101011010 step 186 11000111111111010100100101011010 step 187 11000011111111010100100101011010 step 188 11000011111111010101100101010110 step 189 11000011111111010100100101010110 step 190 11000001111111010100100101010110 step 191 11000001111111010101100101010101 step 192 11000001111111010100100101010101 step 193 10000001111111010100100101010101 step 194 10000001111111010101010101010101 step 195 10000001111111010100010101010101 step 196 10000000111111010100010101010101 step 197 10000000111111110100010101010101 step 198 10000000000001110100010101010101 step 199 10000000000001110101010101010110 step 200 10000000000001110100010101010110 step 201 10000000000011110100010101010110 step 202 10000000000011110101010101011010 step 203 10000000000011110100010101011010 step 204 10000000000010110100010101011010 step 205 10000000000010110101010101011001 step 206 10000000000010110100010101011001 step 207 10000000000110110100010101011001 step 208 10000000000110110101010101101001 step 209 10000000000110110100010101101001 step 210 10000000000111110100010101101001 step 211 10000000000111110101010101101010 step 212 10000000000111110100010101101010 step 213 10000000000101110100010101101010 step 214 10000000000101110101010101100110 step 215 10000000000101110100010101100110 step 216 10000000000100110100010101100110 step 217 10000000000100110101010101100101 step 218 10000000000100110100010101100101 step 219 10000000001100110100010101100101 step 220 10000000001100110101010110100101 step 221 10000000001100110100010110100101 step 222 10000000001101110100010110100101 step 223 10000000001101110101010110100110 step 224 10000000001101110100010110100110 step 225 10000000001111110100010110100110 step 226 10000000001111110101010110101010 step 227 10000000001111110100010110101010 step 228 10000000001110110100010110101010 step 229 10000000001110110101010110101001 step 230 10000000001110110100010110101001 step 231 10000000001010110100010110101001 step 232 10000000001010110101010110011001 step 233 10000000001010110100010110011001 step 234 10000000001011110100010110011001 step 235 10000000001011110101010110011010 step 236 10000000001011110100010110011010 step 237 10000000001001110100010110011010 step 238 10000000001001110101010110010110 step 239 10000000001001110100010110010110 step 240 10000000001000110100010110010110 step 241 10000000001000110101010110010101 step 242 10000000001000110100010110010101 step 243 10000000011000110100010110010101 step 244 10000000011000110101011010010101 step 245 10000000011000110100011010010101 step 246 10000000011001110100011010010101 step 247 10000000011001110101011010010110 step 248 10000000011001110100011010010110 step 249 10000000011011110100011010010110 step 250 10000000011011110101011010011010 step 251 10000000011011110100011010011010 step 252 10000000011010110100011010011010 step 253 10000000011010110101011010011001 step 254 10000000011010110100011010011001 step 255 10000000011110110100011010011001 step 256 10000000011110110101011010101001 step 257 10000000011110110100011010101001 step 258 10000000011111110100011010101001 step 259 10000000011111110101011010101010 step 260 10000000011111110100011010101010 step 261 10000000011101110100011010101010 step 262 10000000011101110101011010100110 step 263 10000000011101110100011010100110 step 264 10000000011100110100011010100110 step 265 10000000011100110101011010100101 step 266 10000000011100110100011010100101 step 267 10000000010100110100011010100101 step 268 10000000010100110101011001100101 step 269 10000000010100110100011001100101 step 270 10000000010101110100011001100101 step 271 10000000010101110101011001100110 step 272 10000000010101110100011001100110 step 273 10000000010111110100011001100110 step 274 10000000010111110101011001101010 step 275 10000000010111110100011001101010 step 276 10000000010110110100011001101010 step 277 10000000010110110101011001101001 step 278 10000000010110110100011001101001 step 279 10000000010010110100011001101001 step 280 10000000010010110101011001011001 step 281 10000000010010110100011001011001 step 282 10000000010011110100011001011001 step 283 10000000010011110101011001011010 step 284 10000000010011110100011001011010 step 285 10000000010001110100011001011010 step 286 10000000010001110101011001010110 step 287 10000000010001110100011001010110 step 288 10000000010000110100011001010110 step 289 10000000010000110101011001010101 step 290 10000000010000110100011001010101 step 291 10000000110000110100011001010101 step 292 10000000110000110101101001010101 step 293 10000000110000110100101001010101 step 294 10000000110001110100101001010101 step 295 10000000110001110101101001010110 step 296 10000000110001110100101001010110 step 297 10000000110011110100101001010110 step 298 10000000110011110101101001011010 step 299 10000000110011110100101001011010 step 300 10000000110010110100101001011010 step 301 10000000110010110101101001011001 step 302 10000000110010110100101001011001 step 303 10000000110110110100101001011001 step 304 10000000110110110101101001101001 step 305 10000000110110110100101001101001 step 306 10000000110111110100101001101001 step 307 10000000110111110101101001101010 step 308 10000000110111110100101001101010 step 309 10000000110101110100101001101010 step 310 10000000110101110101101001100110 step 311 10000000110101110100101001100110 step 312 10000000110100110100101001100110 step 313 10000000110100110101101001100101 step 314 10000000110100110100101001100101 step 315 10000000111100110100101001100101 step 316 10000000111100110101101010100101 step 317 10000000111100110100101010100101 step 318 10000000111101110100101010100101 step 319 10000000111101110101101010100110 step 320 10000000111101110100101010100110 step 321 10000000111111110100101010100110 step 322 10000000111111110101101010101010 step 323 10000000111111110100101010101010 step 324 10000000111110110100101010101010 step 325 10000000111110110101101010101001 step 326 10000000111110110100101010101001 step 327 10000000111010110100101010101001 step 328 10000000111010110101101010011001 step 329 10000000111010110100101010011001 step 330 10000000111011110100101010011001 step 331 10000000111011110101101010011010 step 332 10000000111011110100101010011010 step 333 10000000111001110100101010011010 step 334 10000000111001110101101010010110 step 335 10000000111001110100101010010110 step 336 10000000111000110100101010010110 step 337 10000000111000110101101010010101 step 338 10000000111000110100101010010101 step 339 10000000101000110100101010010101 step 340 10000000101000110101100110010101 step 341 10000000101000110100100110010101 step 342 10000000101001110100100110010101 step 343 10000000101001110101100110010110 step 344 10000000101001110100100110010110 step 345 10000000101011110100100110010110 step 346 10000000101011110101100110011010 step 347 10000000101011110100100110011010 step 348 10000000101010110100100110011010 step 349 10000000101010110101100110011001 step 350 10000000101010110100100110011001 step 351 10000000101110110100100110011001 step 352 10000000101110110101100110101001 step 353 10000000101110110100100110101001 step 354 10000000101111110100100110101001 step 355 10000000101111110101100110101010 step 356 10000000101111110100100110101010 step 357 10000000101101110100100110101010 step 358 10000000101101110101100110100110 step 359 10000000101101110100100110100110 step 360 10000000101100110100100110100110 step 361 10000000101100110101100110100101 step 362 10000000101100110100100110100101 step 363 10000000100100110100100110100101 step 364 10000000100100110101100101100101 step 365 10000000100100110100100101100101 step 366 10000000100101110100100101100101 step 367 10000000100101110101100101100110 step 368 10000000100101110100100101100110 step 369 10000000100111110100100101100110 step 370 10000000100111110101100101101010 step 371 10000000100111110100100101101010 step 372 10000000100110110100100101101010 step 373 10000000100110110101100101101001 step 374 10000000100110110100100101101001 step 375 10000000100010110100100101101001 step 376 10000000100010110101100101011001 step 377 10000000100010110100100101011001 step 378 10000000100011110100100101011001 step 379 10000000100011110101100101011010 step 380 10000000100011110100100101011010 step 381 10000000100001110100100101011010 step 382 10000000100001110101100101010110 step 383 10000000100001110100100101010110 step 384 10000000100000110100100101010110 step 385 10000000100000110101100101010101 step 386 10000000100000110100100101010101 step 387 10000000000000110100100101010101 step 388 10000000000000110101010101010101 step 389 10000000000000110100010101010101 step 390 10000000000000010100010101010101 step 391 10000000000000000100010101010101 step 392 10000011000000000100010101010101 step 393 10000011000000000101010101010110 step 394 10000010000000001100010101010110 step 395 10000010000000001101010101010101 step 396 10000010000000000100010101010101 step 397 10000111000000000100010101010101 step 398 10000111000000000101010101011010 step 399 10000110000000001100010101011010 step 400 10000110000000001101010101010110 step 401 10000110000000000100010101010110 step 402 10000101000000000100010101010110 step 403 10000101000000000101010101011001 step 404 10000100000000001100010101011001 step 405 10000100000000001101010101010110 step 406 10000100000000000100010101010110 step 407 10001101000000000100010101010110 step 408 10001101000000000101010101101001 step 409 10001100000000001100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 410 10001100000000001101010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 411 10001100000000000100010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 412 10001111000000000100010101101010 fail ^^ step 413 10001111000000000101010101101010 step 414 10001110000000001100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 415 10001110000000001101010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 416 10001110000000000100010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 417 10001011000000000100010101101010 fail ^^ step 418 10001011000000000101010101100110 step 419 10001010000000001100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 420 10001010000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 421 10001010000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 422 10001001000000000100010101101001 fail ^^ step 423 10001001000000000101010101100101 step 424 10001000000000001100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 425 10001000000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 426 10001000000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 427 10011001000000000100010101101001 fail ^^ step 428 10011001000000000101010110100101 step 429 10011000000000001100010110100101 step 430 10011000000000001101010101101001 step 431 10011000000000000100010101101001 step 432 10011011000000000100010101101001 step 433 10011011000000000101010110100110 step 434 10011010000000001100010110100110 step 435 10011010000000001101010101101001 step 436 10011010000000000100010101101001 step 437 10011111000000000100010101101001 step 438 10011111000000000101010110101010 step 439 10011110000000001100010110101010 step 440 10011110000000001101010101101010 step 441 10011110000000000100010101101010 step 442 10011101000000000100010101101010 step 443 10011101000000000101010110101001 step 444 10011100000000001100010110101001 step 445 10011100000000001101010101101010 step 446 10011100000000000100010101101010 step 447 10010101000000000100010101101010 step 448 10010101000000000101010110011001 step 449 10010100000000001100010110011001 step 450 10010100000000001101010101100110 step 451 10010100000000000100010101100110 step 452 10010111000000000100010101100110 step 453 10010111000000000101010110011010 step 454 10010110000000001100010110011010 step 455 10010110000000001101010101100110 step 456 10010110000000000100010101100110 step 457 10010011000000000100010101100110 step 458 10010011000000000101010110010110 step 459 10010010000000001100010110010110 step 460 10010010000000001101010101100101 step 461 10010010000000000100010101100101 step 462 10010001000000000100010101100101 step 463 10010001000000000101010110010101 step 464 10010000000000001100010110010101 step 465 10010000000000001101010101100101 step 466 10010000000000000100010101100101 step 467 10110001000000000100010101100101 step 468 10110001000000000101011010010101 step 469 10110000000000001100011010010101 step 470 10110000000000001101010110100101 step 471 10110000000000000100010110100101 step 472 10110011000000000100010110100101 step 473 10110011000000000101011010010110 step 474 10110010000000001100011010010110 step 475 10110010000000001101010110100101 step 476 10110010000000000100010110100101 step 477 10110111000000000100010110100101 step 478 10110111000000000101011010011010 step 479 10110110000000001100011010011010 step 480 10110110000000001101010110100110 step 481 10110110000000000100010110100110 step 482 10110101000000000100010110100110 step 483 10110101000000000101011010011001 step 484 10110100000000001100011010011001 step 485 10110100000000001101010110100110 step 486 10110100000000000100010110100110 step 487 10111101000000000100010110100110 step 488 10111101000000000101011010101001 step 489 10111100000000001100011010101001 step 490 10111100000000001101010110101010 step 491 10111100000000000100010110101010 step 492 10111111000000000100010110101010 step 493 10111111000000000101011010101010 step 494 10111110000000001100011010101010 step 495 10111110000000001101010110101010 step 496 10111110000000000100010110101010 step 497 10111011000000000100010110101010 step 498 10111011000000000101011010100110 step 499 10111010000000001100011010100110 step 500 10111010000000001101010110101001 step 501 10111010000000000100010110101001 step 502 10111001000000000100010110101001 step 503 10111001000000000101011010100101 step 504 10111000000000001100011010100101 step 505 10111000000000001101010110101001 step 506 10111000000000000100010110101001 step 507 10101001000000000100010110101001 step 508 10101001000000000101011001100101 step 509 10101000000000001100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 510 10101000000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 511 10101000000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 512 10101011000000000100010110101001 fail ^^ step 513 10101011000000000101011001100110 step 514 10101010000000001100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 1001 step 515 10101010000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 516 10101010000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 517 10101111000000000100010110101001 fail ^^ step 518 10101111000000000101011001101010 step 519 10101110000000001100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 520 10101110000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 521 10101110000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 522 10101101000000000100010110101010 fail ^^ step 523 10101101000000000101011001101001 step 524 10101100000000001100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 525 10101100000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 526 10101100000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 527 10100101000000000100010110101010 fail ^^ step 528 10100101000000000101011001011001 step 529 10100100000000001100011001011001 step 530 10100100000000001101010110010110 step 531 10100100000000000100010110010110 step 532 10100111000000000100010110010110 step 533 10100111000000000101011001011010 step 534 10100110000000001100011001011010 step 535 10100110000000001101010110010110 step 536 10100110000000000100010110010110 step 537 10100011000000000100010110010110 step 538 10100011000000000101011001010110 step 539 10100010000000001100011001010110 step 540 10100010000000001101010110010101 step 541 10100010000000000100010110010101 step 542 10100001000000000100010110010101 step 543 10100001000000000101011001010101 step 544 10100000000000001100011001010101 step 545 10100000000000001101010110010101 step 546 10100000000000000100010110010101 step 547 11100001000000000100010110010101 step 548 11100001000000000101101001010101 step 549 11100000000000001100101001010101 step 550 11100000000000001101011010010101 step 551 11100000000000000100011010010101 step 552 11100011000000000100011010010101 step 553 11100011000000000101101001010110 step 554 11100010000000001100101001010110 step 555 11100010000000001101011010010101 step 556 11100010000000000100011010010101 step 557 11100111000000000100011010010101 step 558 11100111000000000101101001011010 step 559 11100110000000001100101001011010 step 560 11100110000000001101011010010110 step 561 11100110000000000100011010010110 step 562 11100101000000000100011010010110 step 563 11100101000000000101101001011001 step 564 11100100000000001100101001011001 step 565 11100100000000001101011010010110 step 566 11100100000000000100011010010110 step 567 11101101000000000100011010010110 step 568 11101101000000000101101001101001 step 569 11101100000000001100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 570 11101100000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 571 11101100000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 572 11101111000000000100011010101010 fail ^^ step 573 11101111000000000101101001101010 step 574 11101110000000001100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 575 11101110000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 576 11101110000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 577 11101011000000000100011010101010 fail ^^ step 578 11101011000000000101101001100110 step 579 11101010000000001100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 1001 step 580 11101010000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 581 11101010000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 582 11101001000000000100011010101001 fail ^^ step 583 11101001000000000101101001100101 step 584 11101000000000001100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 585 11101000000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 586 11101000000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 587 11111001000000000100011010101001 fail ^^ step 588 11111001000000000101101010100101 step 589 11111000000000001100101010100101 step 590 11111000000000001101011010101001 step 591 11111000000000000100011010101001 step 592 11111011000000000100011010101001 step 593 11111011000000000101101010100110 step 594 11111010000000001100101010100110 step 595 11111010000000001101011010101001 step 596 11111010000000000100011010101001 step 597 11111111000000000100011010101001 step 598 11111111000000000101101010101010 step 599 11111110000000001100101010101010 step 600 11111110000000001101011010101010 step 601 11111110000000000100011010101010 step 602 11111101000000000100011010101010 step 603 11111101000000000101101010101001 step 604 11111100000000001100101010101001 step 605 11111100000000001101011010101010 step 606 11111100000000000100011010101010 step 607 11110101000000000100011010101010 step 608 11110101000000000101101010011001 step 609 11110100000000001100101010011001 step 610 11110100000000001101011010100110 step 611 11110100000000000100011010100110 step 612 11110111000000000100011010100110 step 613 11110111000000000101101010011010 step 614 11110110000000001100101010011010 step 615 11110110000000001101011010100110 step 616 11110110000000000100011010100110 step 617 11110011000000000100011010100110 step 618 11110011000000000101101010010110 step 619 11110010000000001100101010010110 step 620 11110010000000001101011010100101 step 621 11110010000000000100011010100101 step 622 11110001000000000100011010100101 step 623 11110001000000000101101010010101 step 624 11110000000000001100101010010101 step 625 11110000000000001101011010100101 step 626 11110000000000000100011010100101 step 627 11010001000000000100011010100101 step 628 11010001000000000101100110010101 step 629 11010000000000001100100110010101 step 630 11010000000000001101011001100101 step 631 11010000000000000100011001100101 step 632 11010011000000000100011001100101 step 633 11010011000000000101100110010110 step 634 11010010000000001100100110010110 step 635 11010010000000001101011001100101 step 636 11010010000000000100011001100101 step 637 11010111000000000100011001100101 step 638 11010111000000000101100110011010 step 639 11010110000000001100100110011010 step 640 11010110000000001101011001100110 step 641 11010110000000000100011001100110 step 642 11010101000000000100011001100110 step 643 11010101000000000101100110011001 step 644 11010100000000001100100110011001 step 645 11010100000000001101011001100110 step 646 11010100000000000100011001100110 step 647 11011101000000000100011001100110 step 648 11011101000000000101100110101001 step 649 11011100000000001100100110101001 step 650 11011100000000001101011001101010 step 651 11011100000000000100011001101010 step 652 11011111000000000100011001101010 step 653 11011111000000000101100110101010 step 654 11011110000000001100100110101010 step 655 11011110000000001101011001101010 step 656 11011110000000000100011001101010 step 657 11011011000000000100011001101010 step 658 11011011000000000101100110100110 step 659 11011010000000001100100110100110 step 660 11011010000000001101011001101001 step 661 11011010000000000100011001101001 step 662 11011001000000000100011001101001 step 663 11011001000000000101100110100101 step 664 11011000000000001100100110100101 step 665 11011000000000001101011001101001 step 666 11011000000000000100011001101001 step 667 11001001000000000100011001101001 step 668 11001001000000000101100101100101 step 669 11001000000000001100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 670 11001000000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 671 11001000000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 672 11001011000000000100011001101001 fail ^^ step 673 11001011000000000101100101100110 step 674 11001010000000001100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 675 11001010000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 676 11001010000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 677 11001111000000000100011001101001 fail ^^ step 678 11001111000000000101100101101010 step 679 11001110000000001100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 680 11001110000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 681 11001110000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 682 11001101000000000100011001101010 fail ^^ step 683 11001101000000000101100101101001 step 684 11001100000000001100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 685 11001100000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 686 11001100000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 687 11000101000000000100011001101010 fail ^^ step 688 11000101000000000101100101011001 step 689 11000100000000001100100101011001 step 690 11000100000000001101011001010110 step 691 11000100000000000100011001010110 step 692 11000111000000000100011001010110 step 693 11000111000000000101100101011010 step 694 11000110000000001100100101011010 step 695 11000110000000001101011001010110 step 696 11000110000000000100011001010110 step 697 11000011000000000100011001010110 step 698 11000011000000000101100101010110 step 699 11000010000000001100100101010110 step 700 11000010000000001101011001010101 step 701 11000010000000000100011001010101 step 702 11000001000000000100011001010101 step 703 11000001000000000101100101010101 step 704 11000000000000001100100101010101 step 705 11000000000000001101011001010101 step 706 11000000000000000100011001010101 step 707 10000001000000000100011001010101 step 708 10000001000000000101010101010101 step 709 10000000000000001100010101010101 step 710 10000000000000001101010101010101 step 711 10000000000000000100010101010101 step 712 10000000000000010100010101010101 step 713 10000011000000010100010101010101 step 714 10000011000000010101010101010110 step 715 10000010000000011100010101010110 step 716 10000010000000011101100101010101 step 717 10000010000000010100100101010101 step 718 10000111000000010100100101010101 step 719 10000111000000010101010101011010 step 720 10000110000000011100010101011010 step 721 10000110000000011101100101010110 step 722 10000110000000010100100101010110 step 723 10000101000000010100100101010110 step 724 10000101000000010101010101011001 step 725 10000100000000011100010101011001 step 726 10000100000000011101100101010110 step 727 10000100000000010100100101010110 step 728 10001101000000010100100101010110 step 729 10001101000000010101010101101001 step 730 10001100000000011100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 731 10001100000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 732 10001100000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 733 10001111000000010100100101101010 fail ^^ step 734 10001111000000010101010101101010 step 735 10001110000000011100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 736 10001110000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 737 10001110000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 738 10001011000000010100100101101010 fail ^^ step 739 10001011000000010101010101100110 step 740 10001010000000011100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 741 10001010000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 742 10001010000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 743 10001001000000010100100101101001 fail ^^ step 744 10001001000000010101010101100101 step 745 10001000000000011100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 746 10001000000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 747 10001000000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 748 10011001000000010100100101101001 fail ^^ step 749 10011001000000010101010110100101 step 750 10011000000000011100010110100101 step 751 10011000000000011101100101101001 step 752 10011000000000010100100101101001 step 753 10011011000000010100100101101001 step 754 10011011000000010101010110100110 step 755 10011010000000011100010110100110 step 756 10011010000000011101100101101001 step 757 10011010000000010100100101101001 step 758 10011111000000010100100101101001 step 759 10011111000000010101010110101010 step 760 10011110000000011100010110101010 step 761 10011110000000011101100101101010 step 762 10011110000000010100100101101010 step 763 10011101000000010100100101101010 step 764 10011101000000010101010110101001 step 765 10011100000000011100010110101001 step 766 10011100000000011101100101101010 step 767 10011100000000010100100101101010 step 768 10010101000000010100100101101010 step 769 10010101000000010101010110011001 step 770 10010100000000011100010110011001 step 771 10010100000000011101100101100110 step 772 10010100000000010100100101100110 step 773 10010111000000010100100101100110 step 774 10010111000000010101010110011010 step 775 10010110000000011100010110011010 step 776 10010110000000011101100101100110 step 777 10010110000000010100100101100110 step 778 10010011000000010100100101100110 step 779 10010011000000010101010110010110 step 780 10010010000000011100010110010110 step 781 10010010000000011101100101100101 step 782 10010010000000010100100101100101 step 783 10010001000000010100100101100101 step 784 10010001000000010101010110010101 step 785 10010000000000011100010110010101 step 786 10010000000000011101100101100101 step 787 10010000000000010100100101100101 step 788 10110001000000010100100101100101 step 789 10110001000000010101011010010101 step 790 10110000000000011100011010010101 step 791 10110000000000011101100110100101 step 792 10110000000000010100100110100101 step 793 10110011000000010100100110100101 step 794 10110011000000010101011010010110 step 795 10110010000000011100011010010110 step 796 10110010000000011101100110100101 step 797 10110010000000010100100110100101 step 798 10110111000000010100100110100101 step 799 10110111000000010101011010011010 step 800 10110110000000011100011010011010 step 801 10110110000000011101100110100110 step 802 10110110000000010100100110100110 step 803 10110101000000010100100110100110 step 804 10110101000000010101011010011001 step 805 10110100000000011100011010011001 step 806 10110100000000011101100110100110 step 807 10110100000000010100100110100110 step 808 10111101000000010100100110100110 step 809 10111101000000010101011010101001 step 810 10111100000000011100011010101001 step 811 10111100000000011101100110101010 step 812 10111100000000010100100110101010 step 813 10111111000000010100100110101010 step 814 10111111000000010101011010101010 step 815 10111110000000011100011010101010 step 816 10111110000000011101100110101010 step 817 10111110000000010100100110101010 step 818 10111011000000010100100110101010 step 819 10111011000000010101011010100110 step 820 10111010000000011100011010100110 step 821 10111010000000011101100110101001 step 822 10111010000000010100100110101001 step 823 10111001000000010100100110101001 step 824 10111001000000010101011010100101 step 825 10111000000000011100011010100101 step 826 10111000000000011101100110101001 step 827 10111000000000010100100110101001 step 828 10101001000000010100100110101001 step 829 10101001000000010101011001100101 step 830 10101000000000011100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 831 10101000000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 832 10101000000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 833 10101011000000010100100110101001 fail ^^ step 834 10101011000000010101011001100110 step 835 10101010000000011100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 836 10101010000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 837 10101010000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 838 10101111000000010100100110101001 fail ^^ step 839 10101111000000010101011001101010 step 840 10101110000000011100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 841 10101110000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 842 10101110000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 843 10101101000000010100100110101010 fail ^^ step 844 10101101000000010101011001101001 step 845 10101100000000011100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 846 10101100000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 847 10101100000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 848 10100101000000010100100110101010 fail ^^ step 849 10100101000000010101011001011001 step 850 10100100000000011100011001011001 step 851 10100100000000011101100110010110 step 852 10100100000000010100100110010110 step 853 10100111000000010100100110010110 step 854 10100111000000010101011001011010 step 855 10100110000000011100011001011010 step 856 10100110000000011101100110010110 step 857 10100110000000010100100110010110 step 858 10100011000000010100100110010110 step 859 10100011000000010101011001010110 step 860 10100010000000011100011001010110 step 861 10100010000000011101100110010101 step 862 10100010000000010100100110010101 step 863 10100001000000010100100110010101 step 864 10100001000000010101011001010101 step 865 10100000000000011100011001010101 step 866 10100000000000011101100110010101 step 867 10100000000000010100100110010101 step 868 11100001000000010100100110010101 step 869 11100001000000010101101001010101 step 870 11100000000000011100101001010101 step 871 11100000000000011101101010010101 step 872 11100000000000010100101010010101 step 873 11100011000000010100101010010101 step 874 11100011000000010101101001010110 step 875 11100010000000011100101001010110 step 876 11100010000000011101101010010101 step 877 11100010000000010100101010010101 step 878 11100111000000010100101010010101 step 879 11100111000000010101101001011010 step 880 11100110000000011100101001011010 step 881 11100110000000011101101010010110 step 882 11100110000000010100101010010110 step 883 11100101000000010100101010010110 step 884 11100101000000010101101001011001 step 885 11100100000000011100101001011001 step 886 11100100000000011101101010010110 step 887 11100100000000010100101010010110 step 888 11101101000000010100101010010110 step 889 11101101000000010101101001101001 step 890 11101100000000011100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 891 11101100000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 892 11101100000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 893 11101111000000010100101010101010 fail ^^ step 894 11101111000000010101101001101010 step 895 11101110000000011100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 896 11101110000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 897 11101110000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 898 11101011000000010100101010101010 fail ^^ step 899 11101011000000010101101001100110 step 900 11101010000000011100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 901 11101010000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 902 11101010000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 903 11101001000000010100101010101001 fail ^^ step 904 11101001000000010101101001100101 step 905 11101000000000011100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 906 11101000000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 907 11101000000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 908 11111001000000010100101010101001 fail ^^ step 909 11111001000000010101101010100101 step 910 11111000000000011100101010100101 step 911 11111000000000011101101010101001 step 912 11111000000000010100101010101001 step 913 11111011000000010100101010101001 step 914 11111011000000010101101010100110 step 915 11111010000000011100101010100110 step 916 11111010000000011101101010101001 step 917 11111010000000010100101010101001 step 918 11111111000000010100101010101001 step 919 11111111000000010101101010101010 step 920 11111110000000011100101010101010 step 921 11111110000000011101101010101010 step 922 11111110000000010100101010101010 step 923 11111101000000010100101010101010 step 924 11111101000000010101101010101001 step 925 11111100000000011100101010101001 step 926 11111100000000011101101010101010 step 927 11111100000000010100101010101010 step 928 11110101000000010100101010101010 step 929 11110101000000010101101010011001 step 930 11110100000000011100101010011001 step 931 11110100000000011101101010100110 step 932 11110100000000010100101010100110 step 933 11110111000000010100101010100110 step 934 11110111000000010101101010011010 step 935 11110110000000011100101010011010 step 936 11110110000000011101101010100110 step 937 11110110000000010100101010100110 step 938 11110011000000010100101010100110 step 939 11110011000000010101101010010110 step 940 11110010000000011100101010010110 step 941 11110010000000011101101010100101 step 942 11110010000000010100101010100101 step 943 11110001000000010100101010100101 step 944 11110001000000010101101010010101 step 945 11110000000000011100101010010101 step 946 11110000000000011101101010100101 step 947 11110000000000010100101010100101 step 948 11010001000000010100101010100101 step 949 11010001000000010101100110010101 step 950 11010000000000011100100110010101 step 951 11010000000000011101101001100101 step 952 11010000000000010100101001100101 step 953 11010011000000010100101001100101 step 954 11010011000000010101100110010110 step 955 11010010000000011100100110010110 step 956 11010010000000011101101001100101 step 957 11010010000000010100101001100101 step 958 11010111000000010100101001100101 step 959 11010111000000010101100110011010 step 960 11010110000000011100100110011010 step 961 11010110000000011101101001100110 step 962 11010110000000010100101001100110 step 963 11010101000000010100101001100110 step 964 11010101000000010101100110011001 step 965 11010100000000011100100110011001 step 966 11010100000000011101101001100110 step 967 11010100000000010100101001100110 step 968 11011101000000010100101001100110 step 969 11011101000000010101100110101001 step 970 11011100000000011100100110101001 step 971 11011100000000011101101001101010 step 972 11011100000000010100101001101010 step 973 11011111000000010100101001101010 step 974 11011111000000010101100110101010 step 975 11011110000000011100100110101010 step 976 11011110000000011101101001101010 step 977 11011110000000010100101001101010 step 978 11011011000000010100101001101010 step 979 11011011000000010101100110100110 step 980 11011010000000011100100110100110 step 981 11011010000000011101101001101001 step 982 11011010000000010100101001101001 step 983 11011001000000010100101001101001 step 984 11011001000000010101100110100101 step 985 11011000000000011100100110100101 step 986 11011000000000011101101001101001 step 987 11011000000000010100101001101001 step 988 11001001000000010100101001101001 step 989 11001001000000010101100101100101 step 990 11001000000000011100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 991 11001000000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 992 11001000000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 993 11001011000000010100101001101001 fail ^^ step 994 11001011000000010101100101100110 step 995 11001010000000011100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 996 11001010000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 997 11001010000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 998 11001111000000010100101001101001 fail ^^ step 999 11001111000000010101100101101010 step 1000 11001110000000011100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1001 11001110000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1002 11001110000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1003 11001101000000010100101001101010 fail ^^ step 1004 11001101000000010101100101101001 step 1005 11001100000000011100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1006 11001100000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1007 11001100000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1008 11000101000000010100101001101010 fail ^^ step 1009 11000101000000010101100101011001 step 1010 11000100000000011100100101011001 step 1011 11000100000000011101101001010110 step 1012 11000100000000010100101001010110 step 1013 11000111000000010100101001010110 step 1014 11000111000000010101100101011010 step 1015 11000110000000011100100101011010 step 1016 11000110000000011101101001010110 step 1017 11000110000000010100101001010110 step 1018 11000011000000010100101001010110 step 1019 11000011000000010101100101010110 step 1020 11000010000000011100100101010110 step 1021 11000010000000011101101001010101 step 1022 11000010000000010100101001010101 step 1023 11000001000000010100101001010101 step 1024 11000001000000010101100101010101 step 1025 11000000000000011100100101010101 step 1026 11000000000000011101101001010101 step 1027 11000000000000010100101001010101 step 1028 10000001000000010100101001010101 step 1029 10000001000000010101010101010101 step 1030 10000000000000011100010101010101 step 1031 10000000000000011101100101010101 step 1032 10000000000000010100100101010101 step 1033 10000000000000010000100101010101 step 1034 10000011000000010000100101010101 step 1035 10000011000000010001010101010110 step 1036 10000010000000010010010101010110 step 1037 10000010000000010011010101011001 step 1038 10000010000000010000010101011001 step 1039 10000111000000010000010101011001 step 1040 10000111000000010001010101011010 step 1041 10000110000000010010010101011010 step 1042 10000110000000010011010101101001 step 1043 10000110000000010000010101101001 step 1044 10000101000000010000010101101001 step 1045 10000101000000010001010101011001 step 1046 10000100000000010010010101011001 step 1047 10000100000000010011010101100101 step 1048 10000100000000010000010101100101 step 1049 10001101000000010000010101100101 step 1050 10001101000000010001010101101001 step 1051 10001100000000010010010101101001 step 1052 10001100000000010011010110100101 step 1053 10001100000000010000010110100101 step 1054 10001111000000010000010110100101 step 1055 10001111000000010001010101101010 step 1056 10001110000000010010010101101010 step 1057 10001110000000010011010110101001 step 1058 10001110000000010000010110101001 step 1059 10001011000000010000010110101001 step 1060 10001011000000010001010101100110 step 1061 10001010000000010010010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1062 10001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1063 10001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1064 10001001000000010000010110101001 fail ^^ step 1065 10001001000000010001010101100101 step 1066 10001000000000010010010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1067 10001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1068 10001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1069 10011001000000010000010110100101 fail ^^ step 1070 10011001000000010001010110100101 step 1071 10011000000000010010010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1072 10011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1073 10011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1074 10011011000000010000011010100101 fail ^^ step 1075 10011011000000010001010110100110 step 1076 10011010000000010010010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1077 10011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1078 10011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1079 10011111000000010000011010101001 fail ^^ step 1080 10011111000000010001010110101010 step 1081 10011110000000010010010110101010 step 1082 10011110000000010011011010101001 step 1083 10011110000000010000011010101001 step 1084 10011101000000010000011010101001 step 1085 10011101000000010001010110101001 step 1086 10011100000000010010010110101001 step 1087 10011100000000010011011010100101 step 1088 10011100000000010000011010100101 step 1089 10010101000000010000011010100101 step 1090 10010101000000010001010110011001 step 1091 10010100000000010010010110011001 step 1092 10010100000000010011011001100101 step 1093 10010100000000010000011001100101 step 1094 10010111000000010000011001100101 step 1095 10010111000000010001010110011010 step 1096 10010110000000010010010110011010 step 1097 10010110000000010011011001101001 step 1098 10010110000000010000011001101001 step 1099 10010011000000010000011001101001 step 1100 10010011000000010001010110010110 step 1101 10010010000000010010010110010110 step 1102 10010010000000010011011001011001 step 1103 10010010000000010000011001011001 step 1104 10010001000000010000011001011001 step 1105 10010001000000010001010110010101 step 1106 10010000000000010010010110010101 step 1107 10010000000000010011011001010101 step 1108 10010000000000010000011001010101 step 1109 10110001000000010000011001010101 step 1110 10110001000000010001011010010101 step 1111 10110000000000010010011010010101 step 1112 10110000000000010011101001010101 step 1113 10110000000000010000101001010101 step 1114 10110011000000010000101001010101 step 1115 10110011000000010001011010010110 step 1116 10110010000000010010011010010110 step 1117 10110010000000010011101001011001 step 1118 10110010000000010000101001011001 step 1119 10110111000000010000101001011001 step 1120 10110111000000010001011010011010 step 1121 10110110000000010010011010011010 step 1122 10110110000000010011101001101001 step 1123 10110110000000010000101001101001 step 1124 10110101000000010000101001101001 step 1125 10110101000000010001011010011001 step 1126 10110100000000010010011010011001 step 1127 10110100000000010011101001100101 step 1128 10110100000000010000101001100101 step 1129 10111101000000010000101001100101 step 1130 10111101000000010001011010101001 step 1131 10111100000000010010011010101001 step 1132 10111100000000010011101010100101 step 1133 10111100000000010000101010100101 step 1134 10111111000000010000101010100101 step 1135 10111111000000010001011010101010 step 1136 10111110000000010010011010101010 step 1137 10111110000000010011101010101001 step 1138 10111110000000010000101010101001 step 1139 10111011000000010000101010101001 step 1140 10111011000000010001011010100110 step 1141 10111010000000010010011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 1142 10111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1143 10111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1144 10111001000000010000101010101001 fail ^^ step 1145 10111001000000010001011010100101 step 1146 10111000000000010010011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1147 10111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1148 10111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1149 10101001000000010000101010100101 fail ^^ step 1150 10101001000000010001011001100101 step 1151 10101000000000010010011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 1152 10101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1153 10101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1154 10101011000000010000100110100101 fail ^^ step 1155 10101011000000010001011001100110 step 1156 10101010000000010010011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 1157 10101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1158 10101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1159 10101111000000010000100110101001 fail ^^ step 1160 10101111000000010001011001101010 step 1161 10101110000000010010011001101010 step 1162 10101110000000010011100110101001 step 1163 10101110000000010000100110101001 step 1164 10101101000000010000100110101001 step 1165 10101101000000010001011001101001 step 1166 10101100000000010010011001101001 step 1167 10101100000000010011100110100101 step 1168 10101100000000010000100110100101 step 1169 10100101000000010000100110100101 step 1170 10100101000000010001011001011001 step 1171 10100100000000010010011001011001 step 1172 10100100000000010011100101100101 step 1173 10100100000000010000100101100101 step 1174 10100111000000010000100101100101 step 1175 10100111000000010001011001011010 step 1176 10100110000000010010011001011010 step 1177 10100110000000010011100101101001 step 1178 10100110000000010000100101101001 step 1179 10100011000000010000100101101001 step 1180 10100011000000010001011001010110 step 1181 10100010000000010010011001010110 step 1182 10100010000000010011100101011001 step 1183 10100010000000010000100101011001 step 1184 10100001000000010000100101011001 step 1185 10100001000000010001011001010101 step 1186 10100000000000010010011001010101 step 1187 10100000000000010011100101010101 step 1188 10100000000000010000100101010101 step 1189 11100001000000010000100101010101 step 1190 11100001000000010001101001010101 step 1191 11100000000000010010101001010101 step 1192 11100000000000010011100101010101 step 1193 11100000000000010000100101010101 step 1194 11100011000000010000100101010101 step 1195 11100011000000010001101001010110 step 1196 11100010000000010010101001010110 step 1197 11100010000000010011100101011001 step 1198 11100010000000010000100101011001 step 1199 11100111000000010000100101011001 step 1200 11100111000000010001101001011010 step 1201 11100110000000010010101001011010 step 1202 11100110000000010011100101101001 step 1203 11100110000000010000100101101001 step 1204 11100101000000010000100101101001 step 1205 11100101000000010001101001011001 step 1206 11100100000000010010101001011001 step 1207 11100100000000010011100101100101 step 1208 11100100000000010000100101100101 step 1209 11101101000000010000100101100101 step 1210 11101101000000010001101001101001 step 1211 11101100000000010010101001101001 step 1212 11101100000000010011100110100101 step 1213 11101100000000010000100110100101 step 1214 11101111000000010000100110100101 step 1215 11101111000000010001101001101010 step 1216 11101110000000010010101001101010 step 1217 11101110000000010011100110101001 step 1218 11101110000000010000100110101001 step 1219 11101011000000010000100110101001 step 1220 11101011000000010001101001100110 step 1221 11101010000000010010101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 1001 step 1222 11101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1223 11101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1224 11101001000000010000100110101001 fail ^^ step 1225 11101001000000010001101001100101 step 1226 11101000000000010010101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1227 11101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1228 11101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1229 11111001000000010000100110100101 fail ^^ step 1230 11111001000000010001101010100101 step 1231 11111000000000010010101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1232 11111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1233 11111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1234 11111011000000010000101010100101 fail ^^ step 1235 11111011000000010001101010100110 step 1236 11111010000000010010101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 1237 11111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1238 11111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1239 11111111000000010000101010101001 fail ^^ step 1240 11111111000000010001101010101010 step 1241 11111110000000010010101010101010 step 1242 11111110000000010011101010101001 step 1243 11111110000000010000101010101001 step 1244 11111101000000010000101010101001 step 1245 11111101000000010001101010101001 step 1246 11111100000000010010101010101001 step 1247 11111100000000010011101010100101 step 1248 11111100000000010000101010100101 step 1249 11110101000000010000101010100101 step 1250 11110101000000010001101010011001 step 1251 11110100000000010010101010011001 step 1252 11110100000000010011101001100101 step 1253 11110100000000010000101001100101 step 1254 11110111000000010000101001100101 step 1255 11110111000000010001101010011010 step 1256 11110110000000010010101010011010 step 1257 11110110000000010011101001101001 step 1258 11110110000000010000101001101001 step 1259 11110011000000010000101001101001 step 1260 11110011000000010001101010010110 step 1261 11110010000000010010101010010110 step 1262 11110010000000010011101001011001 step 1263 11110010000000010000101001011001 step 1264 11110001000000010000101001011001 step 1265 11110001000000010001101010010101 step 1266 11110000000000010010101010010101 step 1267 11110000000000010011101001010101 step 1268 11110000000000010000101001010101 step 1269 11010001000000010000101001010101 step 1270 11010001000000010001100110010101 step 1271 11010000000000010010100110010101 step 1272 11010000000000010011011001010101 step 1273 11010000000000010000011001010101 step 1274 11010011000000010000011001010101 step 1275 11010011000000010001100110010110 step 1276 11010010000000010010100110010110 step 1277 11010010000000010011011001011001 step 1278 11010010000000010000011001011001 step 1279 11010111000000010000011001011001 step 1280 11010111000000010001100110011010 step 1281 11010110000000010010100110011010 step 1282 11010110000000010011011001101001 step 1283 11010110000000010000011001101001 step 1284 11010101000000010000011001101001 step 1285 11010101000000010001100110011001 step 1286 11010100000000010010100110011001 step 1287 11010100000000010011011001100101 step 1288 11010100000000010000011001100101 step 1289 11011101000000010000011001100101 step 1290 11011101000000010001100110101001 step 1291 11011100000000010010100110101001 step 1292 11011100000000010011011010100101 step 1293 11011100000000010000011010100101 step 1294 11011111000000010000011010100101 step 1295 11011111000000010001100110101010 step 1296 11011110000000010010100110101010 step 1297 11011110000000010011011010101001 step 1298 11011110000000010000011010101001 step 1299 11011011000000010000011010101001 step 1300 11011011000000010001100110100110 step 1301 11011010000000010010100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 1302 11011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1303 11011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1304 11011001000000010000011010101001 fail ^^ step 1305 11011001000000010001100110100101 step 1306 11011000000000010010100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 1307 11011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1308 11011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1309 11001001000000010000011010100101 fail ^^ step 1310 11001001000000010001100101100101 step 1311 11001000000000010010100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 1312 11001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1313 11001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1314 11001011000000010000010110100101 fail ^^ step 1315 11001011000000010001100101100110 step 1316 11001010000000010010100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 1001 step 1317 11001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1318 11001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1319 11001111000000010000010110101001 fail ^^ step 1320 11001111000000010001100101101010 step 1321 11001110000000010010100101101010 step 1322 11001110000000010011010110101001 step 1323 11001110000000010000010110101001 step 1324 11001101000000010000010110101001 step 1325 11001101000000010001100101101001 step 1326 11001100000000010010100101101001 step 1327 11001100000000010011010110100101 step 1328 11001100000000010000010110100101 step 1329 11000101000000010000010110100101 step 1330 11000101000000010001100101011001 step 1331 11000100000000010010100101011001 step 1332 11000100000000010011010101100101 step 1333 11000100000000010000010101100101 step 1334 11000111000000010000010101100101 step 1335 11000111000000010001100101011010 step 1336 11000110000000010010100101011010 step 1337 11000110000000010011010101101001 step 1338 11000110000000010000010101101001 step 1339 11000011000000010000010101101001 step 1340 11000011000000010001100101010110 step 1341 11000010000000010010100101010110 step 1342 11000010000000010011010101011001 step 1343 11000010000000010000010101011001 step 1344 11000001000000010000010101011001 step 1345 11000001000000010001100101010101 step 1346 11000000000000010010100101010101 step 1347 11000000000000010011010101010101 step 1348 11000000000000010000010101010101 step 1349 10000001000000010000010101010101 step 1350 10000001000000010001010101010101 step 1351 10000000000000010010010101010101 step 1352 10000000000000010011010101010101 step 1353 10000000000000010000010101010101 step 1354 10000000000000010100010101010101 step 1355 10000011000000010100010101010101 step 1356 10000011000000010101010101010110 step 1357 10000010000000010110010101010110 step 1358 10000010000000010111010101011010 step 1359 10000010000000010100010101011010 step 1360 10000111000000010100010101011010 step 1361 10000111000000010101010101011010 step 1362 10000110000000010110010101011010 step 1363 10000110000000010111010101101010 step 1364 10000110000000010100010101101010 step 1365 10000101000000010100010101101010 step 1366 10000101000000010101010101011001 step 1367 10000100000000010110010101011001 step 1368 10000100000000010111010101100110 step 1369 10000100000000010100010101100110 step 1370 10001101000000010100010101100110 step 1371 10001101000000010101010101101001 step 1372 10001100000000010110010101101001 step 1373 10001100000000010111010110100110 step 1374 10001100000000010100010110100110 step 1375 10001111000000010100010110100110 step 1376 10001111000000010101010101101010 step 1377 10001110000000010110010101101010 step 1378 10001110000000010111010110101010 step 1379 10001110000000010100010110101010 step 1380 10001011000000010100010110101010 step 1381 10001011000000010101010101100110 step 1382 10001010000000010110010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1383 10001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1384 10001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1385 10001001000000010100010110101010 fail ^^ step 1386 10001001000000010101010101100101 step 1387 10001000000000010110010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1388 10001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1389 10001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1390 10011001000000010100010110100110 fail ^^ step 1391 10011001000000010101010110100101 step 1392 10011000000000010110010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1393 10011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1394 10011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1395 10011011000000010100011010100110 fail ^^ step 1396 10011011000000010101010110100110 step 1397 10011010000000010110010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1398 10011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1399 10011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1400 10011111000000010100011010101010 fail ^^ step 1401 10011111000000010101010110101010 step 1402 10011110000000010110010110101010 step 1403 10011110000000010111011010101010 step 1404 10011110000000010100011010101010 step 1405 10011101000000010100011010101010 step 1406 10011101000000010101010110101001 step 1407 10011100000000010110010110101001 step 1408 10011100000000010111011010100110 step 1409 10011100000000010100011010100110 step 1410 10010101000000010100011010100110 step 1411 10010101000000010101010110011001 step 1412 10010100000000010110010110011001 step 1413 10010100000000010111011001100110 step 1414 10010100000000010100011001100110 step 1415 10010111000000010100011001100110 step 1416 10010111000000010101010110011010 step 1417 10010110000000010110010110011010 step 1418 10010110000000010111011001101010 step 1419 10010110000000010100011001101010 step 1420 10010011000000010100011001101010 step 1421 10010011000000010101010110010110 step 1422 10010010000000010110010110010110 step 1423 10010010000000010111011001011010 step 1424 10010010000000010100011001011010 step 1425 10010001000000010100011001011010 step 1426 10010001000000010101010110010101 step 1427 10010000000000010110010110010101 step 1428 10010000000000010111011001010110 step 1429 10010000000000010100011001010110 step 1430 10110001000000010100011001010110 step 1431 10110001000000010101011010010101 step 1432 10110000000000010110011010010101 step 1433 10110000000000010111101001010110 step 1434 10110000000000010100101001010110 step 1435 10110011000000010100101001010110 step 1436 10110011000000010101011010010110 step 1437 10110010000000010110011010010110 step 1438 10110010000000010111101001011010 step 1439 10110010000000010100101001011010 step 1440 10110111000000010100101001011010 step 1441 10110111000000010101011010011010 step 1442 10110110000000010110011010011010 step 1443 10110110000000010111101001101010 step 1444 10110110000000010100101001101010 step 1445 10110101000000010100101001101010 step 1446 10110101000000010101011010011001 step 1447 10110100000000010110011010011001 step 1448 10110100000000010111101001100110 step 1449 10110100000000010100101001100110 step 1450 10111101000000010100101001100110 step 1451 10111101000000010101011010101001 step 1452 10111100000000010110011010101001 step 1453 10111100000000010111101010100110 step 1454 10111100000000010100101010100110 step 1455 10111111000000010100101010100110 step 1456 10111111000000010101011010101010 step 1457 10111110000000010110011010101010 step 1458 10111110000000010111101010101010 step 1459 10111110000000010100101010101010 step 1460 10111011000000010100101010101010 step 1461 10111011000000010101011010100110 step 1462 10111010000000010110011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1463 10111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1464 10111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1465 10111001000000010100101010101010 fail ^^ step 1466 10111001000000010101011010100101 step 1467 10111000000000010110011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1468 10111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1469 10111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1470 10101001000000010100101010100110 fail ^^ step 1471 10101001000000010101011001100101 step 1472 10101000000000010110011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1473 10101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1474 10101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1475 10101011000000010100100110100110 fail ^^ step 1476 10101011000000010101011001100110 step 1477 10101010000000010110011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1478 10101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1479 10101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1480 10101111000000010100100110101010 fail ^^ step 1481 10101111000000010101011001101010 step 1482 10101110000000010110011001101010 step 1483 10101110000000010111100110101010 step 1484 10101110000000010100100110101010 step 1485 10101101000000010100100110101010 step 1486 10101101000000010101011001101001 step 1487 10101100000000010110011001101001 step 1488 10101100000000010111100110100110 step 1489 10101100000000010100100110100110 step 1490 10100101000000010100100110100110 step 1491 10100101000000010101011001011001 step 1492 10100100000000010110011001011001 step 1493 10100100000000010111100101100110 step 1494 10100100000000010100100101100110 step 1495 10100111000000010100100101100110 step 1496 10100111000000010101011001011010 step 1497 10100110000000010110011001011010 step 1498 10100110000000010111100101101010 step 1499 10100110000000010100100101101010 step 1500 10100011000000010100100101101010 step 1501 10100011000000010101011001010110 step 1502 10100010000000010110011001010110 step 1503 10100010000000010111100101011010 step 1504 10100010000000010100100101011010 step 1505 10100001000000010100100101011010 step 1506 10100001000000010101011001010101 step 1507 10100000000000010110011001010101 step 1508 10100000000000010111100101010110 step 1509 10100000000000010100100101010110 step 1510 11100001000000010100100101010110 step 1511 11100001000000010101101001010101 step 1512 11100000000000010110101001010101 step 1513 11100000000000010111100101010110 step 1514 11100000000000010100100101010110 step 1515 11100011000000010100100101010110 step 1516 11100011000000010101101001010110 step 1517 11100010000000010110101001010110 step 1518 11100010000000010111100101011010 step 1519 11100010000000010100100101011010 step 1520 11100111000000010100100101011010 step 1521 11100111000000010101101001011010 step 1522 11100110000000010110101001011010 step 1523 11100110000000010111100101101010 step 1524 11100110000000010100100101101010 step 1525 11100101000000010100100101101010 step 1526 11100101000000010101101001011001 step 1527 11100100000000010110101001011001 step 1528 11100100000000010111100101100110 step 1529 11100100000000010100100101100110 step 1530 11101101000000010100100101100110 step 1531 11101101000000010101101001101001 step 1532 11101100000000010110101001101001 step 1533 11101100000000010111100110100110 step 1534 11101100000000010100100110100110 step 1535 11101111000000010100100110100110 step 1536 11101111000000010101101001101010 step 1537 11101110000000010110101001101010 step 1538 11101110000000010111100110101010 step 1539 11101110000000010100100110101010 step 1540 11101011000000010100100110101010 step 1541 11101011000000010101101001100110 step 1542 11101010000000010110101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1543 11101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1544 11101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1545 11101001000000010100100110101010 fail ^^ step 1546 11101001000000010101101001100101 step 1547 11101000000000010110101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1548 11101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1549 11101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1550 11111001000000010100100110100110 fail ^^ step 1551 11111001000000010101101010100101 step 1552 11111000000000010110101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1553 11111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1554 11111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1555 11111011000000010100101010100110 fail ^^ step 1556 11111011000000010101101010100110 step 1557 11111010000000010110101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1558 11111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1559 11111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1560 11111111000000010100101010101010 fail ^^ step 1561 11111111000000010101101010101010 step 1562 11111110000000010110101010101010 step 1563 11111110000000010111101010101010 step 1564 11111110000000010100101010101010 step 1565 11111101000000010100101010101010 step 1566 11111101000000010101101010101001 step 1567 11111100000000010110101010101001 step 1568 11111100000000010111101010100110 step 1569 11111100000000010100101010100110 step 1570 11110101000000010100101010100110 step 1571 11110101000000010101101010011001 step 1572 11110100000000010110101010011001 step 1573 11110100000000010111101001100110 step 1574 11110100000000010100101001100110 step 1575 11110111000000010100101001100110 step 1576 11110111000000010101101010011010 step 1577 11110110000000010110101010011010 step 1578 11110110000000010111101001101010 step 1579 11110110000000010100101001101010 step 1580 11110011000000010100101001101010 step 1581 11110011000000010101101010010110 step 1582 11110010000000010110101010010110 step 1583 11110010000000010111101001011010 step 1584 11110010000000010100101001011010 step 1585 11110001000000010100101001011010 step 1586 11110001000000010101101010010101 step 1587 11110000000000010110101010010101 step 1588 11110000000000010111101001010110 step 1589 11110000000000010100101001010110 step 1590 11010001000000010100101001010110 step 1591 11010001000000010101100110010101 step 1592 11010000000000010110100110010101 step 1593 11010000000000010111011001010110 step 1594 11010000000000010100011001010110 step 1595 11010011000000010100011001010110 step 1596 11010011000000010101100110010110 step 1597 11010010000000010110100110010110 step 1598 11010010000000010111011001011010 step 1599 11010010000000010100011001011010 step 1600 11010111000000010100011001011010 step 1601 11010111000000010101100110011010 step 1602 11010110000000010110100110011010 step 1603 11010110000000010111011001101010 step 1604 11010110000000010100011001101010 step 1605 11010101000000010100011001101010 step 1606 11010101000000010101100110011001 step 1607 11010100000000010110100110011001 step 1608 11010100000000010111011001100110 step 1609 11010100000000010100011001100110 step 1610 11011101000000010100011001100110 step 1611 11011101000000010101100110101001 step 1612 11011100000000010110100110101001 step 1613 11011100000000010111011010100110 step 1614 11011100000000010100011010100110 step 1615 11011111000000010100011010100110 step 1616 11011111000000010101100110101010 step 1617 11011110000000010110100110101010 step 1618 11011110000000010111011010101010 step 1619 11011110000000010100011010101010 step 1620 11011011000000010100011010101010 step 1621 11011011000000010101100110100110 step 1622 11011010000000010110100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1623 11011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1624 11011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1625 11011001000000010100011010101010 fail ^^ step 1626 11011001000000010101100110100101 step 1627 11011000000000010110100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1628 11011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1629 11011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1630 11001001000000010100011010100110 fail ^^ step 1631 11001001000000010101100101100101 step 1632 11001000000000010110100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1633 11001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1634 11001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1635 11001011000000010100010110100110 fail ^^ step 1636 11001011000000010101100101100110 step 1637 11001010000000010110100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1638 11001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1639 11001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1640 11001111000000010100010110101010 fail ^^ step 1641 11001111000000010101100101101010 step 1642 11001110000000010110100101101010 step 1643 11001110000000010111010110101010 step 1644 11001110000000010100010110101010 step 1645 11001101000000010100010110101010 step 1646 11001101000000010101100101101001 step 1647 11001100000000010110100101101001 step 1648 11001100000000010111010110100110 step 1649 11001100000000010100010110100110 step 1650 11000101000000010100010110100110 step 1651 11000101000000010101100101011001 step 1652 11000100000000010110100101011001 step 1653 11000100000000010111010101100110 step 1654 11000100000000010100010101100110 step 1655 11000111000000010100010101100110 step 1656 11000111000000010101100101011010 step 1657 11000110000000010110100101011010 step 1658 11000110000000010111010101101010 step 1659 11000110000000010100010101101010 step 1660 11000011000000010100010101101010 step 1661 11000011000000010101100101010110 step 1662 11000010000000010110100101010110 step 1663 11000010000000010111010101011010 step 1664 11000010000000010100010101011010 step 1665 11000001000000010100010101011010 step 1666 11000001000000010101100101010101 step 1667 11000000000000010110100101010101 step 1668 11000000000000010111010101010110 step 1669 11000000000000010100010101010110 step 1670 10000001000000010100010101010110 step 1671 10000001000000010101010101010101 step 1672 10000000000000010110010101010101 step 1673 10000000000000010111010101010110 step 1674 10000000000000010100010101010110 step 1675 00000000000000010100010101010101 step 1676 10000000000000010100010101010101 step 1677 11111110111111010100010101010101 test 7: *** FAIL *************************** 192 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 7, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 7, total passes 0 Main menu Fri Jun 30 16:19:26 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:23:11 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:23:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 23 Main menu Fri Jun 30 16:23:15 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:23:30 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:23:31 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 35 Main menu Fri Jun 30 16:23:34 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Fri Jun 30 16:23:55 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:24:00 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:24:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 22 Main menu Fri Jun 30 16:24:02 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:24:21 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:24:22 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 35 Main menu Fri Jun 30 16:24:24 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst could not open test file. valid test files are: reverting back to test file: tests\m113.tst Main menu Fri Jun 30 16:24:47 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:24:49 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O O O O O O O IO OI O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111 total fails 35, total passes 0 Main menu Fri Jun 30 16:24:53 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst could not open test file. valid test files are: reverting back to test file: tests\m113.tst Main menu Fri Jun 30 16:25:04 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 16:25:18 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:25:26 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:25:28 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 77 Main menu Fri Jun 30 16:25:32 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m700.tst reading test file: tests\m700.tst comment: M700 REV E PCB REV E MANUAL TIMING GENERATOR comment: comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AL2 POWER CLEAR-N pins: 2 I AS2 FILTER INPUT pins: 3 I AR2 RESTART-N pins: 4 I AP2 RUN-N pins: 5 O AN2 MFTS 0-N (PULSED, XXUS DELAY FROM AS2 FILTER IN, ???MS WIDE) pins: 6 O AM2 MFTS 0 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 7 O AT2 MFTP 0 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 8 O AJ2 MFTS 1 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 9 O AK2 MFTS 1-N (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 10 O AE2 MFTP 1 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 11 O BD2 MFTP 2 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 12 O AF2 MFTS 2 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 13 O AH2 MFTS 2 -N (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: direction: IIIIOOOOOOOOO test 1: 0010100010001 comment: ; remove POWER CLEAR-N test 2: 1 comment: ; toggle FILTER INPUT (no action, RUN-N is LO) test 3: 1 test 4: 0 comment: ; enable with RUN-N HI test 5: 1 comment: ; set FILTER INPUT (pulses...) test 6: 1 XXXXXXXXX test 7: 0 comment: test 8: needs work error: unexpect character: 0x6E n error: expected '0', '1', or 'X' for test step comment: end: END bad test file Main menu Fri Jun 30 16:26:08 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: Main menu Fri Jun 30 16:26:23 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m700.tst reading test file: tests\m700.tst comment: M700 REV E PCB REV E MANUAL TIMING GENERATOR comment: comment: USE OSCILLOSCOPE TO SEE PULSES. comment: comment: AE1 IS THE INPUT FOR THE AF1 OUTPUT. comment: AH1 IS THE INPUT FOR THE AJ1 OUTPUT. comment: CONNECT AE1 TO EACH TAP: comment: pins: PINS pins: 1 I AL2 POWER CLEAR-N pins: 2 I AS2 FILTER INPUT pins: 3 I AR2 RESTART-N pins: 4 I AP2 RUN-N pins: 5 O AN2 MFTS 0-N (PULSED, XXUS DELAY FROM AS2 FILTER IN, ???MS WIDE) pins: 6 O AM2 MFTS 0 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 7 O AT2 MFTP 0 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 8 O AJ2 MFTS 1 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 9 O AK2 MFTS 1-N (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 10 O AE2 MFTP 1 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 11 O BD2 MFTP 2 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 12 O AF2 MFTS 2 (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: 13 O AH2 MFTS 2 -N (PULSED, XXUS DELAY FROM ?????????????, ???MS WIDE) pins: direction: IIIIOOOOOOOOO test 1: 0010100010001 comment: ; remove POWER CLEAR-N test 2: 1 comment: ; toggle FILTER INPUT (no action, RUN-N is LO) test 3: 1 test 4: 0 comment: ; enable with RUN-N HI test 5: 1 comment: ; set FILTER INPUT (pulses...) test 6: 1 XXXXXXXXX test 7: 0 comment: test 8: needs work error: unexpect character: 0x6E n error: expected '0', '1', or 'X' for test step comment: end: END bad test file Main menu Fri Jun 30 16:26:38 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:27:16 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:27:18 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 60 Main menu Fri Jun 30 16:27:21 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 16:27:50 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:27:51 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 16:27:52 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:27:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 33 Main menu Fri Jun 30 16:27:55 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:28:09 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:28:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 34 Main menu Fri Jun 30 16:28:13 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:28:27 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:28:28 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:28:30 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 54 Main menu Fri Jun 30 16:28:33 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:28:48 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:28:48 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 33 Main menu Fri Jun 30 16:28:51 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m141.tst reading test file: tests\m141.tst comment: ; M141 PCB REV C SCHEMATIC REV B AND/NOR GATES comment: ; comment: ; E1 = 7420 DUAL 4-INPUT NAND comment: ; E2,E3,EE4 = 7401 QUAD 2-INPUT NAND WITH OPEN COLLECTOR OUTPUTS comment: ; EQUATION: OUT = (IN_1A NAND IN_1B) WIRE OR (IN_2A NAND IN_2B) WIRE OR ... comment: ; comment: ; HEADER: OUTPUTS: A B C D E F comment: ; AND/NOR TERMS: 2-2-2-2 2-2-2-2 1 1 2-2-2 2 comment: pins: PINS pins: 1 I AC1 E2-12 IN_A_1A 1-X-X-X pins: 2 I AD1 E2-11 IN_A_1B 1-X-X-X pins: 3 I AE1 E2-9 IN_A_2A X-1-X-X pins: 4 I AF1 E2-8 IN_A_2B X-1-X-X pins: 5 I AH1 E2-3 IN_A_3A X-X-1-X pins: 6 I AJ1 E2-2 IN_A_3B X-X-1-X pins: 7 I AJ2 E2-6 IN_A_4A X-X-X-1 pins: 8 I AK2 E2-5 IN_A_4B X-X-X-1 pins: 9 O AB1 E2-13,10,1,4 OUT_A pins: 10 I AN2 E3-9 IN_B_1A 1-X-X-X pins: 11 I AP2 E3-8 IN_B_1B 1-X-X-X pins: 12 I AN1 E3-12 IN_B_2A X-1-X-X pins: 13 I AP1 E3-11 IN_B_2B X-1-X-X pins: 14 I AR2 E3-6 IN_B_3A X-X-1-X pins: 15 I AS2 E3-5 IN_B_3B X-X-1-X pins: 16 I AR1 E3-3 IN_B_4A X-X-X-1 pins: 17 I AS1 E3-1 IN_B_4B X-X-X-1 pins: 18 O AA1 E3-10,13,4,1 OUT_B pins: 19 I AD2 E1-13 1 pins: 20 O AF2 E1-8 OUT_C pins: 21 I AE2 E1-5 1 pins: 22 O AH2 E1-6 OUT_D pins: 23 I AL1 E4-9 IN_E_1A 1-X-X pins: 24 I AM1 E4-8 IN_E_1B 1-X-X pins: 25 I AL2 E4-12 IN_E_2A X-1-X pins: 26 I AM2 E4-11 IN_E_2B X-1-X pins: 27 I AU1 E4-3 IN_E_3A X-X-1 pins: 28 I AV1 E4-2 IN_E_3B X-X-1 pins: 29 O AK1 E4-10,13,1 OUT_E pins: 30 I AU2 E4-6 IN_F_1A 1 pins: 31 I AV2 E4-5 IN_F_1B 1 pins: 32 O AT2 E4-4 OUT_F pins: direction: IIIIIIIIOIIIIIIIIOIOIOIIIIIIOIIO test 1: 00000000100000000101010000001001 comment: comment: ; TEST EACH NAND GATE WITH ALL OTHER INPUTS OFF comment: test 2: 01 1 test 3: 11 0 test 4: 10 1 test 5: 00 1 test 6: 01 1 test 7: 11 0 test 8: 10 1 test 9: 00 1 test 10: 01 1 test 11: 11 0 test 12: 10 1 test 13: 00 1 test 14: 011 test 15: 110 test 16: 101 test 17: 001 test 18: 01 1 test 19: 11 0 test 20: 10 1 test 21: 00 1 test 22: 01 1 test 23: 11 0 test 24: 10 1 test 25: 00 1 test 26: 01 1 test 27: 11 0 test 28: 10 1 test 29: 00 1 test 30: 011 test 31: 110 test 32: 101 test 33: 001 test 34: 10 test 35: 01 test 36: 10 test 37: 01 test 38: 01 1 test 39: 11 0 test 40: 10 1 test 41: 00 1 test 42: 01 1 test 43: 11 0 test 44: 10 1 test 45: 00 1 test 46: 011 test 47: 110 test 48: 101 test 49: 001 test 50: 011 test 51: 110 test 52: 101 test 53: 001 comment: comment: comment: ; TURN ON ALL INPUTS comment: test 54: 10 1 test 55: 11 0 test 56: 10 0 test 57: 11 0 test 58: 10 0 test 59: 11 0 test 60: 100 test 61: 110 test 62: 10 1 test 63: 11 0 test 64: 10 0 test 65: 11 0 test 66: 10 0 test 67: 11 0 test 68: 100 test 69: 110 test 70: 10 test 71: 10 test 72: 10 1 test 73: 11 0 test 74: 10 0 test 75: 11 0 test 76: 100 test 77: 110 test 78: 101 test 79: 110 comment: ; NO CHANGE test 80: 11111111011111111010101111110110 comment: comment: ; TEST EACH NAND GATE WITH ALL OTHER INPUTS ON test 81: 10 0 test 82: 00 0 test 83: 01 0 test 84: 11 0 test 85: 10 0 test 86: 00 0 test 87: 01 0 test 88: 11 0 test 89: 10 0 test 90: 00 0 test 91: 01 0 test 92: 11 0 test 93: 100 test 94: 000 test 95: 010 test 96: 110 test 97: 10 0 test 98: 00 0 test 99: 01 0 test 100: 11 0 test 101: 10 0 test 102: 00 0 test 103: 01 0 test 104: 11 0 test 105: 10 0 test 106: 00 0 test 107: 01 0 test 108: 11 0 test 109: 100 test 110: 000 test 111: 010 test 112: 110 test 113: 01 test 114: 10 test 115: 01 test 116: 10 test 117: 10 0 test 118: 00 0 test 119: 01 0 test 120: 11 0 test 121: 10 0 test 122: 00 0 test 123: 01 0 test 124: 11 0 test 125: 100 test 126: 000 test 127: 010 test 128: 110 test 129: 101 test 130: 001 test 131: 011 test 132: 110 comment: comment: ; NO CHANGE test 133: 11111111011111111010101111110110 comment: comment: ; TURN OFF ALL INPUTS test 134: 01 0 test 135: 00 0 test 136: 01 0 test 137: 00 0 test 138: 01 0 test 139: 00 0 test 140: 011 test 141: 001 test 142: 01 0 test 143: 00 0 test 144: 01 0 test 145: 00 0 test 146: 01 0 test 147: 00 0 test 148: 011 test 149: 001 test 150: 01 test 151: 01 test 152: 01 0 test 153: 00 0 test 154: 01 0 test 155: 00 0 test 156: 011 test 157: 001 test 158: 011 test 159: 001 comment: comment: ; NO CHANGE test 160: 00000000100000000101010000001001 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x1000 column 3: offset 0, mask 0x0800 column 4: offset 0, mask 0x0400 column 5: offset 0, mask 0x0200 column 6: offset 0, mask 0x0100 column 7: offset 0, mask 0x0001 column 8: offset 1, mask 0x0001 column 9: offset 0, mask 0x4000 column 10: offset 1, mask 0x0008 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 1, mask 0x0400 column 17: offset 1, mask 0x0200 column 18: offset 0, mask 0x8000 column 19: offset 0, mask 0x0010 column 20: offset 0, mask 0x0004 column 21: offset 0, mask 0x0008 column 22: offset 0, mask 0x0002 column 23: offset 1, mask 0x4000 column 24: offset 1, mask 0x2000 column 25: offset 1, mask 0x0002 column 26: offset 1, mask 0x0004 column 27: offset 2, mask 0x8000 column 28: offset 2, mask 0x4000 column 29: offset 1, mask 0x8000 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 1, mask 0x0080 direction bits (1=input) 0xC0E6 0x8180 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0xC006 0x8080 0x0000 0x0000 0x0000 2: 0xD006 0x8080 0x0000 0x0000 0x0000 3: 0xB006 0x8080 0x0000 0x0000 0x0000 4: 0xE006 0x8080 0x0000 0x0000 0x0000 5: 0xC006 0x8080 0x0000 0x0000 0x0000 6: 0xC406 0x8080 0x0000 0x0000 0x0000 7: 0x8C06 0x8080 0x0000 0x0000 0x0000 8: 0xC806 0x8080 0x0000 0x0000 0x0000 9: 0xC006 0x8080 0x0000 0x0000 0x0000 10: 0xC106 0x8080 0x0000 0x0000 0x0000 11: 0x8306 0x8080 0x0000 0x0000 0x0000 12: 0xC206 0x8080 0x0000 0x0000 0x0000 13: 0xC006 0x8080 0x0000 0x0000 0x0000 14: 0xC006 0x8081 0x0000 0x0000 0x0000 15: 0x8007 0x8081 0x0000 0x0000 0x0000 16: 0xC007 0x8080 0x0000 0x0000 0x0000 17: 0xC006 0x8080 0x0000 0x0000 0x0000 18: 0xC006 0x8090 0x0000 0x0000 0x0000 19: 0x4006 0x8098 0x0000 0x0000 0x0000 20: 0xC006 0x8088 0x0000 0x0000 0x0000 21: 0xC006 0x8080 0x0000 0x0000 0x0000 22: 0xC006 0x8880 0x0000 0x0000 0x0000 23: 0x4006 0x9880 0x0000 0x0000 0x0000 24: 0xC006 0x9080 0x0000 0x0000 0x0000 25: 0xC006 0x8080 0x0000 0x0000 0x0000 26: 0xC006 0x80C0 0x0000 0x0000 0x0000 27: 0x4006 0x80E0 0x0000 0x0000 0x0000 28: 0xC006 0x80A0 0x0000 0x0000 0x0000 29: 0xC006 0x8080 0x0000 0x0000 0x0000 30: 0xC006 0x8280 0x0000 0x0000 0x0000 31: 0x4006 0x8680 0x0000 0x0000 0x0000 32: 0xC006 0x8480 0x0000 0x0000 0x0000 33: 0xC006 0x8080 0x0000 0x0000 0x0000 34: 0xC012 0x8080 0x0000 0x0000 0x0000 35: 0xC006 0x8080 0x0000 0x0000 0x0000 36: 0xC00C 0x8080 0x0000 0x0000 0x0000 37: 0xC006 0x8080 0x0000 0x0000 0x0000 38: 0xC006 0xA080 0x0000 0x0000 0x0000 39: 0xC006 0x6080 0x0000 0x0000 0x0000 40: 0xC006 0xC080 0x0000 0x0000 0x0000 41: 0xC006 0x8080 0x0000 0x0000 0x0000 42: 0xC006 0x8084 0x0000 0x0000 0x0000 43: 0xC006 0x0086 0x0000 0x0000 0x0000 44: 0xC006 0x8082 0x0000 0x0000 0x0000 45: 0xC006 0x8080 0x0000 0x0000 0x0000 46: 0xC006 0x8080 0x4000 0x0000 0x0000 47: 0xC006 0x0080 0xC000 0x0000 0x0000 48: 0xC006 0x8080 0x8000 0x0000 0x0000 49: 0xC006 0x8080 0x0000 0x0000 0x0000 50: 0xC006 0x8080 0x0002 0x0000 0x0000 51: 0xC006 0x8000 0x0003 0x0000 0x0000 52: 0xC006 0x8080 0x0001 0x0000 0x0000 53: 0xC006 0x8080 0x0000 0x0000 0x0000 54: 0xE006 0x8080 0x0000 0x0000 0x0000 55: 0xB006 0x8080 0x0000 0x0000 0x0000 56: 0xB806 0x8080 0x0000 0x0000 0x0000 57: 0xBC06 0x8080 0x0000 0x0000 0x0000 58: 0xBE06 0x8080 0x0000 0x0000 0x0000 59: 0xBF06 0x8080 0x0000 0x0000 0x0000 60: 0xBF07 0x8080 0x0000 0x0000 0x0000 61: 0xBF07 0x8081 0x0000 0x0000 0x0000 62: 0xBF07 0x8089 0x0000 0x0000 0x0000 63: 0x3F07 0x8099 0x0000 0x0000 0x0000 64: 0x3F07 0x9099 0x0000 0x0000 0x0000 65: 0x3F07 0x9899 0x0000 0x0000 0x0000 66: 0x3F07 0x98B9 0x0000 0x0000 0x0000 67: 0x3F07 0x98F9 0x0000 0x0000 0x0000 68: 0x3F07 0x9CF9 0x0000 0x0000 0x0000 69: 0x3F07 0x9EF9 0x0000 0x0000 0x0000 70: 0x3F13 0x9EF9 0x0000 0x0000 0x0000 71: 0x3F19 0x9EF9 0x0000 0x0000 0x0000 72: 0x3F19 0xDEF9 0x0000 0x0000 0x0000 73: 0x3F19 0x7EF9 0x0000 0x0000 0x0000 74: 0x3F19 0x7EFB 0x0000 0x0000 0x0000 75: 0x3F19 0x7EFF 0x0000 0x0000 0x0000 76: 0x3F19 0x7EFF 0x8000 0x0000 0x0000 77: 0x3F19 0x7EFF 0xC000 0x0000 0x0000 78: 0x3F19 0x7EFF 0xC001 0x0000 0x0000 79: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 80: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 81: 0x2F19 0x7E7F 0xC003 0x0000 0x0000 82: 0x0F19 0x7E7F 0xC003 0x0000 0x0000 83: 0x1F19 0x7E7F 0xC003 0x0000 0x0000 84: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 85: 0x3B19 0x7E7F 0xC003 0x0000 0x0000 86: 0x3319 0x7E7F 0xC003 0x0000 0x0000 87: 0x3719 0x7E7F 0xC003 0x0000 0x0000 88: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 89: 0x3E19 0x7E7F 0xC003 0x0000 0x0000 90: 0x3C19 0x7E7F 0xC003 0x0000 0x0000 91: 0x3D19 0x7E7F 0xC003 0x0000 0x0000 92: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 93: 0x3F19 0x7E7E 0xC003 0x0000 0x0000 94: 0x3F18 0x7E7E 0xC003 0x0000 0x0000 95: 0x3F18 0x7E7F 0xC003 0x0000 0x0000 96: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 97: 0x3F19 0x7E6F 0xC003 0x0000 0x0000 98: 0x3F19 0x7E67 0xC003 0x0000 0x0000 99: 0x3F19 0x7E77 0xC003 0x0000 0x0000 100: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 101: 0x3F19 0x767F 0xC003 0x0000 0x0000 102: 0x3F19 0x667F 0xC003 0x0000 0x0000 103: 0x3F19 0x6E7F 0xC003 0x0000 0x0000 104: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 105: 0x3F19 0x7E3F 0xC003 0x0000 0x0000 106: 0x3F19 0x7E1F 0xC003 0x0000 0x0000 107: 0x3F19 0x7E5F 0xC003 0x0000 0x0000 108: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 109: 0x3F19 0x7C7F 0xC003 0x0000 0x0000 110: 0x3F19 0x787F 0xC003 0x0000 0x0000 111: 0x3F19 0x7A7F 0xC003 0x0000 0x0000 112: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 113: 0x3F0D 0x7E7F 0xC003 0x0000 0x0000 114: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 115: 0x3F13 0x7E7F 0xC003 0x0000 0x0000 116: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 117: 0x3F19 0x5E7F 0xC003 0x0000 0x0000 118: 0x3F19 0x1E7F 0xC003 0x0000 0x0000 119: 0x3F19 0x3E7F 0xC003 0x0000 0x0000 120: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 121: 0x3F19 0x7E7B 0xC003 0x0000 0x0000 122: 0x3F19 0x7E79 0xC003 0x0000 0x0000 123: 0x3F19 0x7E7D 0xC003 0x0000 0x0000 124: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 125: 0x3F19 0x7E7F 0x8003 0x0000 0x0000 126: 0x3F19 0x7E7F 0x0003 0x0000 0x0000 127: 0x3F19 0x7E7F 0x4003 0x0000 0x0000 128: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 129: 0x3F19 0x7EFF 0xC001 0x0000 0x0000 130: 0x3F19 0x7EFF 0xC000 0x0000 0x0000 131: 0x3F19 0x7EFF 0xC002 0x0000 0x0000 132: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 133: 0x3F19 0x7E7F 0xC003 0x0000 0x0000 134: 0x1F19 0x7E7F 0xC003 0x0000 0x0000 135: 0x0F19 0x7E7F 0xC003 0x0000 0x0000 136: 0x0719 0x7E7F 0xC003 0x0000 0x0000 137: 0x0319 0x7E7F 0xC003 0x0000 0x0000 138: 0x0119 0x7E7F 0xC003 0x0000 0x0000 139: 0x0019 0x7E7F 0xC003 0x0000 0x0000 140: 0x4018 0x7E7F 0xC003 0x0000 0x0000 141: 0x4018 0x7E7E 0xC003 0x0000 0x0000 142: 0x4018 0x7E76 0xC003 0x0000 0x0000 143: 0x4018 0x7E66 0xC003 0x0000 0x0000 144: 0x4018 0x6E66 0xC003 0x0000 0x0000 145: 0x4018 0x6666 0xC003 0x0000 0x0000 146: 0x4018 0x6646 0xC003 0x0000 0x0000 147: 0x4018 0x6606 0xC003 0x0000 0x0000 148: 0xC018 0x6206 0xC003 0x0000 0x0000 149: 0xC018 0x6006 0xC003 0x0000 0x0000 150: 0xC00C 0x6006 0xC003 0x0000 0x0000 151: 0xC006 0x6006 0xC003 0x0000 0x0000 152: 0xC006 0x2006 0xC003 0x0000 0x0000 153: 0xC006 0x0006 0xC003 0x0000 0x0000 154: 0xC006 0x0004 0xC003 0x0000 0x0000 155: 0xC006 0x0000 0xC003 0x0000 0x0000 156: 0xC006 0x8000 0x4003 0x0000 0x0000 157: 0xC006 0x8000 0x0003 0x0000 0x0000 158: 0xC006 0x8080 0x0002 0x0000 0x0000 159: 0xC006 0x8080 0x0000 0x0000 0x0000 160: 0xC006 0x8080 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OOIIIIIIOIIIIIIGIIP GIIOOIIIIIIIIOII G P G UUT inputs: 26 UUT outputs: 6 pins used: 32 not used: 34 160 'test steps' 221 lines ; M141 PCB REV C SCHEMATIC REV B AND/NOR GATES ; ; E1 = 7420 DUAL 4-INPUT NAND ; E2,E3,EE4 = 7401 QUAD 2-INPUT NAND WITH OPEN COLLECTOR OUTPUTS ; EQUATION: OUT = (IN_1A NAND IN_1B) WIRE OR (IN_2A NAND IN_2B) WIRE OR ... ; ; HEADER: OUTPUTS: A B C D E F ; AND/NOR TERMS: 2-2-2-2 2-2-2-2 1 1 2-2-2 2 PINS Main menu Fri Jun 30 16:29:10 2017 test file is: tests\m141.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:29:12 2017 test file is: tests\m141.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 16:29:12 2017 test file is: tests\m141.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:29:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDEFHJJKBNPNPRSRSADFEHLMLMUVKUVT SIDE 11111122122112211122221122111222 DIRECTION IIIIIIIIOIIIIIIIIOIOIOIIIIIIOIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 36 Main menu Fri Jun 30 16:29:19 2017 test file is: tests\m141.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:29:33 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDEFHJJKBNPNPRSRSADFEHLMLMUVKUVT SIDE 11111122122112211122221122111222 DIRECTION IIIIIIIIOIIIIIIIIOIOIOIIIIIIOIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 18 Main menu Fri Jun 30 16:29:35 2017 test file is: tests\m141.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:29:48 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDEFHJJKBNPNPRSRSADFEHLMLMUVKUVT SIDE 11111122122112211122221122111222 DIRECTION IIIIIIIIOIIIIIIIIOIOIOIIIIIIOIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 43 Main menu Fri Jun 30 16:29:52 2017 test file is: tests\m141.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m119.tst reading test file: tests\m119.tst comment: M119 REV B 3 8-input NAND comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 I AC1 E1-5 pins: 4 I AD1 E1-6 pins: 5 I AD2 E1-4 pins: 6 I AE2 E1-3 pins: 7 I AF2 E1-2 pins: 8 I AH2 E1-1 pins: 9 O AJ2 E1-8 pins: 10 I AF1 E2-12 pins: 11 I AH1 E2-11 pins: 12 I AJ1 E2-5 pins: 13 I AK1 E2-6 pins: 14 I AK2 E2-4 pins: 15 I AL2 E2-3 pins: 16 I AM2 E2-2 pins: 17 I AN2 E2-1 pins: 18 O AP2 E2-8 pins: 19 I AM1 E3-12 pins: 20 I AN1 E3-11 pins: 21 I AP1 E3-5 pins: 22 I AR1 E3-6 pins: 23 I AR2 E3-4 pins: 24 I AS2 E3-3 pins: 25 I AT2 E3-2 pins: 26 I AU2 E3-1 pins: 27 O AV2 E3-8 pins: direction: IIIIIIIIOIIIIIIIIOIIIIIIIIO test 1: 000000001000000001000000001 test 2: 000000001 test 3: 000000011 test 4: 000000101 test 5: 000000111 test 6: 000001001 test 7: 000001011 test 8: 000001101 test 9: 000001111 test 10: 000010001 test 11: 000010011 test 12: 000010101 test 13: 000010111 test 14: 000011001 test 15: 000011011 test 16: 000011101 test 17: 000011111 test 18: 000100001 test 19: 000100011 test 20: 000100101 test 21: 000100111 test 22: 000101001 test 23: 000101011 test 24: 000101101 test 25: 000101111 test 26: 000110001 test 27: 000110011 test 28: 000110101 test 29: 000110111 test 30: 000111001 test 31: 000111011 test 32: 000111101 test 33: 000111111 test 34: 001000001 test 35: 001000011 test 36: 001000101 test 37: 001000111 test 38: 001001001 test 39: 001001011 test 40: 001001101 test 41: 001001111 test 42: 001010001 test 43: 001010011 test 44: 001010101 test 45: 001010111 test 46: 001011001 test 47: 001011011 test 48: 001011101 test 49: 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test 1095: 010000001 test 1096: 010000011 test 1097: 010000101 test 1098: 010000111 test 1099: 010001001 test 1100: 010001011 test 1101: 010001101 test 1102: 010001111 test 1103: 010010001 test 1104: 010010011 test 1105: 010010101 test 1106: 010010111 test 1107: 010011001 test 1108: 010011011 test 1109: 010011101 test 1110: 010011111 test 1111: 010100001 test 1112: 010100011 test 1113: 010100101 test 1114: 010100111 test 1115: 010101001 test 1116: 010101011 test 1117: 010101101 test 1118: 010101111 test 1119: 010110001 test 1120: 010110011 test 1121: 010110101 test 1122: 010110111 test 1123: 010111001 test 1124: 010111011 test 1125: 010111101 test 1126: 010111111 test 1127: 011000001 test 1128: 011000011 test 1129: 011000101 test 1130: 011000111 test 1131: 011001001 test 1132: 011001011 test 1133: 011001101 test 1134: 011001111 test 1135: 011010001 test 1136: 011010011 test 1137: 011010101 test 1138: 011010111 test 1139: 011011001 test 1140: 011011011 test 1141: 011011101 test 1142: 011011111 test 1143: 011100001 test 1144: 011100011 test 1145: 011100101 test 1146: 011100111 test 1147: 011101001 test 1148: 011101011 test 1149: 011101101 test 1150: 011101111 test 1151: 011110001 test 1152: 011110011 test 1153: 011110101 test 1154: 011110111 test 1155: 011111001 test 1156: 011111011 test 1157: 011111101 test 1158: 011111111 test 1159: 100000001 test 1160: 100000011 test 1161: 100000101 test 1162: 100000111 test 1163: 100001001 test 1164: 100001011 test 1165: 100001101 test 1166: 100001111 test 1167: 100010001 test 1168: 100010011 test 1169: 100010101 test 1170: 100010111 test 1171: 100011001 test 1172: 100011011 test 1173: 100011101 test 1174: 100011111 test 1175: 100100001 test 1176: 100100011 test 1177: 100100101 test 1178: 100100111 test 1179: 100101001 test 1180: 100101011 test 1181: 100101101 test 1182: 100101111 test 1183: 100110001 test 1184: 100110011 test 1185: 100110101 test 1186: 100110111 test 1187: 100111001 test 1188: 100111011 test 1189: 100111101 test 1190: 100111111 test 1191: 101000001 test 1192: 101000011 test 1193: 101000101 test 1194: 101000111 test 1195: 101001001 test 1196: 101001011 test 1197: 101001101 test 1198: 101001111 test 1199: 101010001 test 1200: 101010011 test 1201: 101010101 test 1202: 101010111 test 1203: 101011001 test 1204: 101011011 test 1205: 101011101 test 1206: 101011111 test 1207: 101100001 test 1208: 101100011 test 1209: 101100101 test 1210: 101100111 test 1211: 101101001 test 1212: 101101011 test 1213: 101101101 test 1214: 101101111 test 1215: 101110001 test 1216: 101110011 test 1217: 101110101 test 1218: 101110111 test 1219: 101111001 test 1220: 101111011 test 1221: 101111101 test 1222: 101111111 test 1223: 110000001 test 1224: 110000011 test 1225: 110000101 test 1226: 110000111 test 1227: 110001001 test 1228: 110001011 test 1229: 110001101 test 1230: 110001111 test 1231: 110010001 test 1232: 110010011 test 1233: 110010101 test 1234: 110010111 test 1235: 110011001 test 1236: 110011011 test 1237: 110011101 test 1238: 110011111 test 1239: 110100001 test 1240: 110100011 test 1241: 110100101 test 1242: 110100111 test 1243: 110101001 test 1244: 110101011 test 1245: 110101101 test 1246: 110101111 test 1247: 110110001 test 1248: 110110011 test 1249: 110110101 test 1250: 110110111 test 1251: 110111001 test 1252: 110111011 test 1253: 110111101 test 1254: 110111111 test 1255: 111000001 test 1256: 111000011 test 1257: 111000101 test 1258: 111000111 test 1259: 111001001 test 1260: 111001011 test 1261: 111001101 test 1262: 111001111 test 1263: 111010001 test 1264: 111010011 test 1265: 111010101 test 1266: 111010111 test 1267: 111011001 test 1268: 111011011 test 1269: 111011101 test 1270: 111011111 test 1271: 111100001 test 1272: 111100011 test 1273: 111100101 test 1274: 111100111 test 1275: 111101001 test 1276: 111101011 test 1277: 111101101 test 1278: 111101111 test 1279: 111110001 test 1280: 111110011 test 1281: 111110101 test 1282: 111110111 test 1283: 111111001 test 1284: 111111011 test 1285: 111111101 test 1286: 111111110 test 1287: 000000001 test 1288: 000000011 test 1289: 000000101 test 1290: 000000111 test 1291: 000001001 test 1292: 000001011 test 1293: 000001101 test 1294: 000001111 test 1295: 000010001 test 1296: 000010011 test 1297: 000010101 test 1298: 000010111 test 1299: 000011001 test 1300: 000011011 test 1301: 000011101 test 1302: 000011111 test 1303: 000100001 test 1304: 000100011 test 1305: 000100101 test 1306: 000100111 test 1307: 000101001 test 1308: 000101011 test 1309: 000101101 test 1310: 000101111 test 1311: 000110001 test 1312: 000110011 test 1313: 000110101 test 1314: 000110111 test 1315: 000111001 test 1316: 000111011 test 1317: 000111101 test 1318: 000111111 test 1319: 001000001 test 1320: 001000011 test 1321: 001000101 test 1322: 001000111 test 1323: 001001001 test 1324: 001001011 test 1325: 001001101 test 1326: 001001111 test 1327: 001010001 test 1328: 001010011 test 1329: 001010101 test 1330: 001010111 test 1331: 001011001 test 1332: 001011011 test 1333: 001011101 test 1334: 001011111 test 1335: 001100001 test 1336: 001100011 test 1337: 001100101 test 1338: 001100111 test 1339: 001101001 test 1340: 001101011 test 1341: 001101101 test 1342: 001101111 test 1343: 001110001 test 1344: 001110011 test 1345: 001110101 test 1346: 001110111 test 1347: 001111001 test 1348: 001111011 test 1349: 001111101 test 1350: 001111111 test 1351: 010000001 test 1352: 010000011 test 1353: 010000101 test 1354: 010000111 test 1355: 010001001 test 1356: 010001011 test 1357: 010001101 test 1358: 010001111 test 1359: 010010001 test 1360: 010010011 test 1361: 010010101 test 1362: 010010111 test 1363: 010011001 test 1364: 010011011 test 1365: 010011101 test 1366: 010011111 test 1367: 010100001 test 1368: 010100011 test 1369: 010100101 test 1370: 010100111 test 1371: 010101001 test 1372: 010101011 test 1373: 010101101 test 1374: 010101111 test 1375: 010110001 test 1376: 010110011 test 1377: 010110101 test 1378: 010110111 test 1379: 010111001 test 1380: 010111011 test 1381: 010111101 test 1382: 010111111 test 1383: 011000001 test 1384: 011000011 test 1385: 011000101 test 1386: 011000111 test 1387: 011001001 test 1388: 011001011 test 1389: 011001101 test 1390: 011001111 test 1391: 011010001 test 1392: 011010011 test 1393: 011010101 test 1394: 011010111 test 1395: 011011001 test 1396: 011011011 test 1397: 011011101 test 1398: 011011111 test 1399: 011100001 test 1400: 011100011 test 1401: 011100101 test 1402: 011100111 test 1403: 011101001 test 1404: 011101011 test 1405: 011101101 test 1406: 011101111 test 1407: 011110001 test 1408: 011110011 test 1409: 011110101 test 1410: 011110111 test 1411: 011111001 test 1412: 011111011 test 1413: 011111101 test 1414: 011111111 test 1415: 100000001 test 1416: 100000011 test 1417: 100000101 test 1418: 100000111 test 1419: 100001001 test 1420: 100001011 test 1421: 100001101 test 1422: 100001111 test 1423: 100010001 test 1424: 100010011 test 1425: 100010101 test 1426: 100010111 test 1427: 100011001 test 1428: 100011011 test 1429: 100011101 test 1430: 100011111 test 1431: 100100001 test 1432: 100100011 test 1433: 100100101 test 1434: 100100111 test 1435: 100101001 test 1436: 100101011 test 1437: 100101101 test 1438: 100101111 test 1439: 100110001 test 1440: 100110011 test 1441: 100110101 test 1442: 100110111 test 1443: 100111001 test 1444: 100111011 test 1445: 100111101 test 1446: 100111111 test 1447: 101000001 test 1448: 101000011 test 1449: 101000101 test 1450: 101000111 test 1451: 101001001 test 1452: 101001011 test 1453: 101001101 test 1454: 101001111 test 1455: 101010001 test 1456: 101010011 test 1457: 101010101 test 1458: 101010111 test 1459: 101011001 test 1460: 101011011 test 1461: 101011101 test 1462: 101011111 test 1463: 101100001 test 1464: 101100011 test 1465: 101100101 test 1466: 101100111 test 1467: 101101001 test 1468: 101101011 test 1469: 101101101 test 1470: 101101111 test 1471: 101110001 test 1472: 101110011 test 1473: 101110101 test 1474: 101110111 test 1475: 101111001 test 1476: 101111011 test 1477: 101111101 test 1478: 101111111 test 1479: 110000001 test 1480: 110000011 test 1481: 110000101 test 1482: 110000111 test 1483: 110001001 test 1484: 110001011 test 1485: 110001101 test 1486: 110001111 test 1487: 110010001 test 1488: 110010011 test 1489: 110010101 test 1490: 110010111 test 1491: 110011001 test 1492: 110011011 test 1493: 110011101 test 1494: 110011111 test 1495: 110100001 test 1496: 110100011 test 1497: 110100101 test 1498: 110100111 test 1499: 110101001 test 1500: 110101011 test 1501: 110101101 test 1502: 110101111 test 1503: 110110001 test 1504: 110110011 test 1505: 110110101 test 1506: 110110111 test 1507: 110111001 test 1508: 110111011 test 1509: 110111101 test 1510: 110111111 test 1511: 111000001 test 1512: 111000011 test 1513: 111000101 test 1514: 111000111 test 1515: 111001001 test 1516: 111001011 test 1517: 111001101 test 1518: 111001111 test 1519: 111010001 test 1520: 111010011 test 1521: 111010101 test 1522: 111010111 test 1523: 111011001 test 1524: 111011011 test 1525: 111011101 test 1526: 111011111 test 1527: 111100001 test 1528: 111100011 test 1529: 111100101 test 1530: 111100111 test 1531: 111101001 test 1532: 111101011 test 1533: 111101101 test 1534: 111101111 test 1535: 111110001 test 1536: 111110011 test 1537: 111110101 test 1538: 111110111 test 1539: 111111001 test 1540: 111111011 test 1541: 111111101 test 1542: 111111110 test 1543: 111111110111111110111111110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0001 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 1, mask 0x8000 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x0008 column 18: offset 1, mask 0x0010 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0800 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0080 column 26: offset 2, mask 0x0001 column 27: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0001 0x0010 0x0002 0x0000 0x0000 2: 0x0001 0x0010 0x0002 0x0000 0x0000 3: 0x0003 0x0010 0x0002 0x0000 0x0000 4: 0x0005 0x0010 0x0002 0x0000 0x0000 5: 0x0007 0x0010 0x0002 0x0000 0x0000 6: 0x0009 0x0010 0x0002 0x0000 0x0000 7: 0x000B 0x0010 0x0002 0x0000 0x0000 8: 0x000D 0x0010 0x0002 0x0000 0x0000 9: 0x000F 0x0010 0x0002 0x0000 0x0000 10: 0x0011 0x0010 0x0002 0x0000 0x0000 11: 0x0013 0x0010 0x0002 0x0000 0x0000 12: 0x0015 0x0010 0x0002 0x0000 0x0000 13: 0x0017 0x0010 0x0002 0x0000 0x0000 14: 0x0019 0x0010 0x0002 0x0000 0x0000 15: 0x001B 0x0010 0x0002 0x0000 0x0000 16: 0x001D 0x0010 0x0002 0x0000 0x0000 17: 0x001F 0x0010 0x0002 0x0000 0x0000 18: 0x1001 0x0010 0x0002 0x0000 0x0000 19: 0x1003 0x0010 0x0002 0x0000 0x0000 20: 0x1005 0x0010 0x0002 0x0000 0x0000 21: 0x1007 0x0010 0x0002 0x0000 0x0000 22: 0x1009 0x0010 0x0002 0x0000 0x0000 23: 0x100B 0x0010 0x0002 0x0000 0x0000 24: 0x100D 0x0010 0x0002 0x0000 0x0000 25: 0x100F 0x0010 0x0002 0x0000 0x0000 26: 0x1011 0x0010 0x0002 0x0000 0x0000 27: 0x1013 0x0010 0x0002 0x0000 0x0000 28: 0x1015 0x0010 0x0002 0x0000 0x0000 29: 0x1017 0x0010 0x0002 0x0000 0x0000 30: 0x1019 0x0010 0x0002 0x0000 0x0000 31: 0x101B 0x0010 0x0002 0x0000 0x0000 32: 0x101D 0x0010 0x0002 0x0000 0x0000 33: 0x101F 0x0010 0x0002 0x0000 0x0000 34: 0x2001 0x0010 0x0002 0x0000 0x0000 35: 0x2003 0x0010 0x0002 0x0000 0x0000 36: 0x2005 0x0010 0x0002 0x0000 0x0000 37: 0x2007 0x0010 0x0002 0x0000 0x0000 38: 0x2009 0x0010 0x0002 0x0000 0x0000 39: 0x200B 0x0010 0x0002 0x0000 0x0000 40: 0x200D 0x0010 0x0002 0x0000 0x0000 41: 0x200F 0x0010 0x0002 0x0000 0x0000 42: 0x2011 0x0010 0x0002 0x0000 0x0000 43: 0x2013 0x0010 0x0002 0x0000 0x0000 44: 0x2015 0x0010 0x0002 0x0000 0x0000 45: 0x2017 0x0010 0x0002 0x0000 0x0000 46: 0x2019 0x0010 0x0002 0x0000 0x0000 47: 0x201B 0x0010 0x0002 0x0000 0x0000 48: 0x201D 0x0010 0x0002 0x0000 0x0000 49: 0x201F 0x0010 0x0002 0x0000 0x0000 50: 0x3001 0x0010 0x0002 0x0000 0x0000 51: 0x3003 0x0010 0x0002 0x0000 0x0000 52: 0x3005 0x0010 0x0002 0x0000 0x0000 53: 0x3007 0x0010 0x0002 0x0000 0x0000 54: 0x3009 0x0010 0x0002 0x0000 0x0000 55: 0x300B 0x0010 0x0002 0x0000 0x0000 56: 0x300D 0x0010 0x0002 0x0000 0x0000 57: 0x300F 0x0010 0x0002 0x0000 0x0000 58: 0x3011 0x0010 0x0002 0x0000 0x0000 59: 0x3013 0x0010 0x0002 0x0000 0x0000 60: 0x3015 0x0010 0x0002 0x0000 0x0000 61: 0x3017 0x0010 0x0002 0x0000 0x0000 62: 0x3019 0x0010 0x0002 0x0000 0x0000 63: 0x301B 0x0010 0x0002 0x0000 0x0000 64: 0x301D 0x0010 0x0002 0x0000 0x0000 65: 0x301F 0x0010 0x0002 0x0000 0x0000 66: 0x4001 0x0010 0x0002 0x0000 0x0000 67: 0x4003 0x0010 0x0002 0x0000 0x0000 68: 0x4005 0x0010 0x0002 0x0000 0x0000 69: 0x4007 0x0010 0x0002 0x0000 0x0000 70: 0x4009 0x0010 0x0002 0x0000 0x0000 71: 0x400B 0x0010 0x0002 0x0000 0x0000 72: 0x400D 0x0010 0x0002 0x0000 0x0000 73: 0x400F 0x0010 0x0002 0x0000 0x0000 74: 0x4011 0x0010 0x0002 0x0000 0x0000 75: 0x4013 0x0010 0x0002 0x0000 0x0000 76: 0x4015 0x0010 0x0002 0x0000 0x0000 77: 0x4017 0x0010 0x0002 0x0000 0x0000 78: 0x4019 0x0010 0x0002 0x0000 0x0000 79: 0x401B 0x0010 0x0002 0x0000 0x0000 80: 0x401D 0x0010 0x0002 0x0000 0x0000 81: 0x401F 0x0010 0x0002 0x0000 0x0000 82: 0x5001 0x0010 0x0002 0x0000 0x0000 83: 0x5003 0x0010 0x0002 0x0000 0x0000 84: 0x5005 0x0010 0x0002 0x0000 0x0000 85: 0x5007 0x0010 0x0002 0x0000 0x0000 86: 0x5009 0x0010 0x0002 0x0000 0x0000 87: 0x500B 0x0010 0x0002 0x0000 0x0000 88: 0x500D 0x0010 0x0002 0x0000 0x0000 89: 0x500F 0x0010 0x0002 0x0000 0x0000 90: 0x5011 0x0010 0x0002 0x0000 0x0000 91: 0x5013 0x0010 0x0002 0x0000 0x0000 92: 0x5015 0x0010 0x0002 0x0000 0x0000 93: 0x5017 0x0010 0x0002 0x0000 0x0000 94: 0x5019 0x0010 0x0002 0x0000 0x0000 95: 0x501B 0x0010 0x0002 0x0000 0x0000 96: 0x501D 0x0010 0x0002 0x0000 0x0000 97: 0x501F 0x0010 0x0002 0x0000 0x0000 98: 0x6001 0x0010 0x0002 0x0000 0x0000 99: 0x6003 0x0010 0x0002 0x0000 0x0000 100: 0x6005 0x0010 0x0002 0x0000 0x0000 101: 0x6007 0x0010 0x0002 0x0000 0x0000 102: 0x6009 0x0010 0x0002 0x0000 0x0000 103: 0x600B 0x0010 0x0002 0x0000 0x0000 104: 0x600D 0x0010 0x0002 0x0000 0x0000 105: 0x600F 0x0010 0x0002 0x0000 0x0000 106: 0x6011 0x0010 0x0002 0x0000 0x0000 107: 0x6013 0x0010 0x0002 0x0000 0x0000 108: 0x6015 0x0010 0x0002 0x0000 0x0000 109: 0x6017 0x0010 0x0002 0x0000 0x0000 110: 0x6019 0x0010 0x0002 0x0000 0x0000 111: 0x601B 0x0010 0x0002 0x0000 0x0000 112: 0x601D 0x0010 0x0002 0x0000 0x0000 113: 0x601F 0x0010 0x0002 0x0000 0x0000 114: 0x7001 0x0010 0x0002 0x0000 0x0000 115: 0x7003 0x0010 0x0002 0x0000 0x0000 116: 0x7005 0x0010 0x0002 0x0000 0x0000 117: 0x7007 0x0010 0x0002 0x0000 0x0000 118: 0x7009 0x0010 0x0002 0x0000 0x0000 119: 0x700B 0x0010 0x0002 0x0000 0x0000 120: 0x700D 0x0010 0x0002 0x0000 0x0000 121: 0x700F 0x0010 0x0002 0x0000 0x0000 122: 0x7011 0x0010 0x0002 0x0000 0x0000 123: 0x7013 0x0010 0x0002 0x0000 0x0000 124: 0x7015 0x0010 0x0002 0x0000 0x0000 125: 0x7017 0x0010 0x0002 0x0000 0x0000 126: 0x7019 0x0010 0x0002 0x0000 0x0000 127: 0x701B 0x0010 0x0002 0x0000 0x0000 128: 0x701D 0x0010 0x0002 0x0000 0x0000 129: 0x701F 0x0010 0x0002 0x0000 0x0000 130: 0x8001 0x0010 0x0002 0x0000 0x0000 131: 0x8003 0x0010 0x0002 0x0000 0x0000 132: 0x8005 0x0010 0x0002 0x0000 0x0000 133: 0x8007 0x0010 0x0002 0x0000 0x0000 134: 0x8009 0x0010 0x0002 0x0000 0x0000 135: 0x800B 0x0010 0x0002 0x0000 0x0000 136: 0x800D 0x0010 0x0002 0x0000 0x0000 137: 0x800F 0x0010 0x0002 0x0000 0x0000 138: 0x8011 0x0010 0x0002 0x0000 0x0000 139: 0x8013 0x0010 0x0002 0x0000 0x0000 140: 0x8015 0x0010 0x0002 0x0000 0x0000 141: 0x8017 0x0010 0x0002 0x0000 0x0000 142: 0x8019 0x0010 0x0002 0x0000 0x0000 143: 0x801B 0x0010 0x0002 0x0000 0x0000 144: 0x801D 0x0010 0x0002 0x0000 0x0000 145: 0x801F 0x0010 0x0002 0x0000 0x0000 146: 0x9001 0x0010 0x0002 0x0000 0x0000 147: 0x9003 0x0010 0x0002 0x0000 0x0000 148: 0x9005 0x0010 0x0002 0x0000 0x0000 149: 0x9007 0x0010 0x0002 0x0000 0x0000 150: 0x9009 0x0010 0x0002 0x0000 0x0000 151: 0x900B 0x0010 0x0002 0x0000 0x0000 152: 0x900D 0x0010 0x0002 0x0000 0x0000 153: 0x900F 0x0010 0x0002 0x0000 0x0000 154: 0x9011 0x0010 0x0002 0x0000 0x0000 155: 0x9013 0x0010 0x0002 0x0000 0x0000 156: 0x9015 0x0010 0x0002 0x0000 0x0000 157: 0x9017 0x0010 0x0002 0x0000 0x0000 158: 0x9019 0x0010 0x0002 0x0000 0x0000 159: 0x901B 0x0010 0x0002 0x0000 0x0000 160: 0x901D 0x0010 0x0002 0x0000 0x0000 161: 0x901F 0x0010 0x0002 0x0000 0x0000 162: 0xA001 0x0010 0x0002 0x0000 0x0000 163: 0xA003 0x0010 0x0002 0x0000 0x0000 164: 0xA005 0x0010 0x0002 0x0000 0x0000 165: 0xA007 0x0010 0x0002 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0x0000 1283: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 1284: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 1285: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 1286: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1287: 0xF71E 0x800F 0x0002 0x0000 0x0000 1288: 0xF71E 0x800F 0x0003 0x0000 0x0000 1289: 0xF71E 0x808F 0x0002 0x0000 0x0000 1290: 0xF71E 0x808F 0x0003 0x0000 0x0000 1291: 0xF71E 0x804F 0x0002 0x0000 0x0000 1292: 0xF71E 0x804F 0x0003 0x0000 0x0000 1293: 0xF71E 0x80CF 0x0002 0x0000 0x0000 1294: 0xF71E 0x80CF 0x0003 0x0000 0x0000 1295: 0xF71E 0x802F 0x0002 0x0000 0x0000 1296: 0xF71E 0x802F 0x0003 0x0000 0x0000 1297: 0xF71E 0x80AF 0x0002 0x0000 0x0000 1298: 0xF71E 0x80AF 0x0003 0x0000 0x0000 1299: 0xF71E 0x806F 0x0002 0x0000 0x0000 1300: 0xF71E 0x806F 0x0003 0x0000 0x0000 1301: 0xF71E 0x80EF 0x0002 0x0000 0x0000 1302: 0xF71E 0x80EF 0x0003 0x0000 0x0000 1303: 0xF71E 0x840F 0x0002 0x0000 0x0000 1304: 0xF71E 0x840F 0x0003 0x0000 0x0000 1305: 0xF71E 0x848F 0x0002 0x0000 0x0000 1306: 0xF71E 0x848F 0x0003 0x0000 0x0000 1307: 0xF71E 0x844F 0x0002 0x0000 0x0000 1308: 0xF71E 0x844F 0x0003 0x0000 0x0000 1309: 0xF71E 0x84CF 0x0002 0x0000 0x0000 1310: 0xF71E 0x84CF 0x0003 0x0000 0x0000 1311: 0xF71E 0x842F 0x0002 0x0000 0x0000 1312: 0xF71E 0x842F 0x0003 0x0000 0x0000 1313: 0xF71E 0x84AF 0x0002 0x0000 0x0000 1314: 0xF71E 0x84AF 0x0003 0x0000 0x0000 1315: 0xF71E 0x846F 0x0002 0x0000 0x0000 1316: 0xF71E 0x846F 0x0003 0x0000 0x0000 1317: 0xF71E 0x84EF 0x0002 0x0000 0x0000 1318: 0xF71E 0x84EF 0x0003 0x0000 0x0000 1319: 0xF71E 0x880F 0x0002 0x0000 0x0000 1320: 0xF71E 0x880F 0x0003 0x0000 0x0000 1321: 0xF71E 0x888F 0x0002 0x0000 0x0000 1322: 0xF71E 0x888F 0x0003 0x0000 0x0000 1323: 0xF71E 0x884F 0x0002 0x0000 0x0000 1324: 0xF71E 0x884F 0x0003 0x0000 0x0000 1325: 0xF71E 0x88CF 0x0002 0x0000 0x0000 1326: 0xF71E 0x88CF 0x0003 0x0000 0x0000 1327: 0xF71E 0x882F 0x0002 0x0000 0x0000 1328: 0xF71E 0x882F 0x0003 0x0000 0x0000 1329: 0xF71E 0x88AF 0x0002 0x0000 0x0000 1330: 0xF71E 0x88AF 0x0003 0x0000 0x0000 1331: 0xF71E 0x886F 0x0002 0x0000 0x0000 1332: 0xF71E 0x886F 0x0003 0x0000 0x0000 1333: 0xF71E 0x88EF 0x0002 0x0000 0x0000 1334: 0xF71E 0x88EF 0x0003 0x0000 0x0000 1335: 0xF71E 0x8C0F 0x0002 0x0000 0x0000 1336: 0xF71E 0x8C0F 0x0003 0x0000 0x0000 1337: 0xF71E 0x8C8F 0x0002 0x0000 0x0000 1338: 0xF71E 0x8C8F 0x0003 0x0000 0x0000 1339: 0xF71E 0x8C4F 0x0002 0x0000 0x0000 1340: 0xF71E 0x8C4F 0x0003 0x0000 0x0000 1341: 0xF71E 0x8CCF 0x0002 0x0000 0x0000 1342: 0xF71E 0x8CCF 0x0003 0x0000 0x0000 1343: 0xF71E 0x8C2F 0x0002 0x0000 0x0000 1344: 0xF71E 0x8C2F 0x0003 0x0000 0x0000 1345: 0xF71E 0x8CAF 0x0002 0x0000 0x0000 1346: 0xF71E 0x8CAF 0x0003 0x0000 0x0000 1347: 0xF71E 0x8C6F 0x0002 0x0000 0x0000 1348: 0xF71E 0x8C6F 0x0003 0x0000 0x0000 1349: 0xF71E 0x8CEF 0x0002 0x0000 0x0000 1350: 0xF71E 0x8CEF 0x0003 0x0000 0x0000 1351: 0xF71E 0x900F 0x0002 0x0000 0x0000 1352: 0xF71E 0x900F 0x0003 0x0000 0x0000 1353: 0xF71E 0x908F 0x0002 0x0000 0x0000 1354: 0xF71E 0x908F 0x0003 0x0000 0x0000 1355: 0xF71E 0x904F 0x0002 0x0000 0x0000 1356: 0xF71E 0x904F 0x0003 0x0000 0x0000 1357: 0xF71E 0x90CF 0x0002 0x0000 0x0000 1358: 0xF71E 0x90CF 0x0003 0x0000 0x0000 1359: 0xF71E 0x902F 0x0002 0x0000 0x0000 1360: 0xF71E 0x902F 0x0003 0x0000 0x0000 1361: 0xF71E 0x90AF 0x0002 0x0000 0x0000 1362: 0xF71E 0x90AF 0x0003 0x0000 0x0000 1363: 0xF71E 0x906F 0x0002 0x0000 0x0000 1364: 0xF71E 0x906F 0x0003 0x0000 0x0000 1365: 0xF71E 0x90EF 0x0002 0x0000 0x0000 1366: 0xF71E 0x90EF 0x0003 0x0000 0x0000 1367: 0xF71E 0x940F 0x0002 0x0000 0x0000 1368: 0xF71E 0x940F 0x0003 0x0000 0x0000 1369: 0xF71E 0x948F 0x0002 0x0000 0x0000 1370: 0xF71E 0x948F 0x0003 0x0000 0x0000 1371: 0xF71E 0x944F 0x0002 0x0000 0x0000 1372: 0xF71E 0x944F 0x0003 0x0000 0x0000 1373: 0xF71E 0x94CF 0x0002 0x0000 0x0000 1374: 0xF71E 0x94CF 0x0003 0x0000 0x0000 1375: 0xF71E 0x942F 0x0002 0x0000 0x0000 1376: 0xF71E 0x942F 0x0003 0x0000 0x0000 1377: 0xF71E 0x94AF 0x0002 0x0000 0x0000 1378: 0xF71E 0x94AF 0x0003 0x0000 0x0000 1379: 0xF71E 0x946F 0x0002 0x0000 0x0000 1380: 0xF71E 0x946F 0x0003 0x0000 0x0000 1381: 0xF71E 0x94EF 0x0002 0x0000 0x0000 1382: 0xF71E 0x94EF 0x0003 0x0000 0x0000 1383: 0xF71E 0x980F 0x0002 0x0000 0x0000 1384: 0xF71E 0x980F 0x0003 0x0000 0x0000 1385: 0xF71E 0x988F 0x0002 0x0000 0x0000 1386: 0xF71E 0x988F 0x0003 0x0000 0x0000 1387: 0xF71E 0x984F 0x0002 0x0000 0x0000 1388: 0xF71E 0x984F 0x0003 0x0000 0x0000 1389: 0xF71E 0x98CF 0x0002 0x0000 0x0000 1390: 0xF71E 0x98CF 0x0003 0x0000 0x0000 1391: 0xF71E 0x982F 0x0002 0x0000 0x0000 1392: 0xF71E 0x982F 0x0003 0x0000 0x0000 1393: 0xF71E 0x98AF 0x0002 0x0000 0x0000 1394: 0xF71E 0x98AF 0x0003 0x0000 0x0000 1395: 0xF71E 0x986F 0x0002 0x0000 0x0000 1396: 0xF71E 0x986F 0x0003 0x0000 0x0000 1397: 0xF71E 0x98EF 0x0002 0x0000 0x0000 1398: 0xF71E 0x98EF 0x0003 0x0000 0x0000 1399: 0xF71E 0x9C0F 0x0002 0x0000 0x0000 1400: 0xF71E 0x9C0F 0x0003 0x0000 0x0000 1401: 0xF71E 0x9C8F 0x0002 0x0000 0x0000 1402: 0xF71E 0x9C8F 0x0003 0x0000 0x0000 1403: 0xF71E 0x9C4F 0x0002 0x0000 0x0000 1404: 0xF71E 0x9C4F 0x0003 0x0000 0x0000 1405: 0xF71E 0x9CCF 0x0002 0x0000 0x0000 1406: 0xF71E 0x9CCF 0x0003 0x0000 0x0000 1407: 0xF71E 0x9C2F 0x0002 0x0000 0x0000 1408: 0xF71E 0x9C2F 0x0003 0x0000 0x0000 1409: 0xF71E 0x9CAF 0x0002 0x0000 0x0000 1410: 0xF71E 0x9CAF 0x0003 0x0000 0x0000 1411: 0xF71E 0x9C6F 0x0002 0x0000 0x0000 1412: 0xF71E 0x9C6F 0x0003 0x0000 0x0000 1413: 0xF71E 0x9CEF 0x0002 0x0000 0x0000 1414: 0xF71E 0x9CEF 0x0003 0x0000 0x0000 1415: 0xF71E 0xA00F 0x0002 0x0000 0x0000 1416: 0xF71E 0xA00F 0x0003 0x0000 0x0000 1417: 0xF71E 0xA08F 0x0002 0x0000 0x0000 1418: 0xF71E 0xA08F 0x0003 0x0000 0x0000 1419: 0xF71E 0xA04F 0x0002 0x0000 0x0000 1420: 0xF71E 0xA04F 0x0003 0x0000 0x0000 1421: 0xF71E 0xA0CF 0x0002 0x0000 0x0000 1422: 0xF71E 0xA0CF 0x0003 0x0000 0x0000 1423: 0xF71E 0xA02F 0x0002 0x0000 0x0000 1424: 0xF71E 0xA02F 0x0003 0x0000 0x0000 1425: 0xF71E 0xA0AF 0x0002 0x0000 0x0000 1426: 0xF71E 0xA0AF 0x0003 0x0000 0x0000 1427: 0xF71E 0xA06F 0x0002 0x0000 0x0000 1428: 0xF71E 0xA06F 0x0003 0x0000 0x0000 1429: 0xF71E 0xA0EF 0x0002 0x0000 0x0000 1430: 0xF71E 0xA0EF 0x0003 0x0000 0x0000 1431: 0xF71E 0xA40F 0x0002 0x0000 0x0000 1432: 0xF71E 0xA40F 0x0003 0x0000 0x0000 1433: 0xF71E 0xA48F 0x0002 0x0000 0x0000 1434: 0xF71E 0xA48F 0x0003 0x0000 0x0000 1435: 0xF71E 0xA44F 0x0002 0x0000 0x0000 1436: 0xF71E 0xA44F 0x0003 0x0000 0x0000 1437: 0xF71E 0xA4CF 0x0002 0x0000 0x0000 1438: 0xF71E 0xA4CF 0x0003 0x0000 0x0000 1439: 0xF71E 0xA42F 0x0002 0x0000 0x0000 1440: 0xF71E 0xA42F 0x0003 0x0000 0x0000 1441: 0xF71E 0xA4AF 0x0002 0x0000 0x0000 1442: 0xF71E 0xA4AF 0x0003 0x0000 0x0000 1443: 0xF71E 0xA46F 0x0002 0x0000 0x0000 1444: 0xF71E 0xA46F 0x0003 0x0000 0x0000 1445: 0xF71E 0xA4EF 0x0002 0x0000 0x0000 1446: 0xF71E 0xA4EF 0x0003 0x0000 0x0000 1447: 0xF71E 0xA80F 0x0002 0x0000 0x0000 1448: 0xF71E 0xA80F 0x0003 0x0000 0x0000 1449: 0xF71E 0xA88F 0x0002 0x0000 0x0000 1450: 0xF71E 0xA88F 0x0003 0x0000 0x0000 1451: 0xF71E 0xA84F 0x0002 0x0000 0x0000 1452: 0xF71E 0xA84F 0x0003 0x0000 0x0000 1453: 0xF71E 0xA8CF 0x0002 0x0000 0x0000 1454: 0xF71E 0xA8CF 0x0003 0x0000 0x0000 1455: 0xF71E 0xA82F 0x0002 0x0000 0x0000 1456: 0xF71E 0xA82F 0x0003 0x0000 0x0000 1457: 0xF71E 0xA8AF 0x0002 0x0000 0x0000 1458: 0xF71E 0xA8AF 0x0003 0x0000 0x0000 1459: 0xF71E 0xA86F 0x0002 0x0000 0x0000 1460: 0xF71E 0xA86F 0x0003 0x0000 0x0000 1461: 0xF71E 0xA8EF 0x0002 0x0000 0x0000 1462: 0xF71E 0xA8EF 0x0003 0x0000 0x0000 1463: 0xF71E 0xAC0F 0x0002 0x0000 0x0000 1464: 0xF71E 0xAC0F 0x0003 0x0000 0x0000 1465: 0xF71E 0xAC8F 0x0002 0x0000 0x0000 1466: 0xF71E 0xAC8F 0x0003 0x0000 0x0000 1467: 0xF71E 0xAC4F 0x0002 0x0000 0x0000 1468: 0xF71E 0xAC4F 0x0003 0x0000 0x0000 1469: 0xF71E 0xACCF 0x0002 0x0000 0x0000 1470: 0xF71E 0xACCF 0x0003 0x0000 0x0000 1471: 0xF71E 0xAC2F 0x0002 0x0000 0x0000 1472: 0xF71E 0xAC2F 0x0003 0x0000 0x0000 1473: 0xF71E 0xACAF 0x0002 0x0000 0x0000 1474: 0xF71E 0xACAF 0x0003 0x0000 0x0000 1475: 0xF71E 0xAC6F 0x0002 0x0000 0x0000 1476: 0xF71E 0xAC6F 0x0003 0x0000 0x0000 1477: 0xF71E 0xACEF 0x0002 0x0000 0x0000 1478: 0xF71E 0xACEF 0x0003 0x0000 0x0000 1479: 0xF71E 0xB00F 0x0002 0x0000 0x0000 1480: 0xF71E 0xB00F 0x0003 0x0000 0x0000 1481: 0xF71E 0xB08F 0x0002 0x0000 0x0000 1482: 0xF71E 0xB08F 0x0003 0x0000 0x0000 1483: 0xF71E 0xB04F 0x0002 0x0000 0x0000 1484: 0xF71E 0xB04F 0x0003 0x0000 0x0000 1485: 0xF71E 0xB0CF 0x0002 0x0000 0x0000 1486: 0xF71E 0xB0CF 0x0003 0x0000 0x0000 1487: 0xF71E 0xB02F 0x0002 0x0000 0x0000 1488: 0xF71E 0xB02F 0x0003 0x0000 0x0000 1489: 0xF71E 0xB0AF 0x0002 0x0000 0x0000 1490: 0xF71E 0xB0AF 0x0003 0x0000 0x0000 1491: 0xF71E 0xB06F 0x0002 0x0000 0x0000 1492: 0xF71E 0xB06F 0x0003 0x0000 0x0000 1493: 0xF71E 0xB0EF 0x0002 0x0000 0x0000 1494: 0xF71E 0xB0EF 0x0003 0x0000 0x0000 1495: 0xF71E 0xB40F 0x0002 0x0000 0x0000 1496: 0xF71E 0xB40F 0x0003 0x0000 0x0000 1497: 0xF71E 0xB48F 0x0002 0x0000 0x0000 1498: 0xF71E 0xB48F 0x0003 0x0000 0x0000 1499: 0xF71E 0xB44F 0x0002 0x0000 0x0000 1500: 0xF71E 0xB44F 0x0003 0x0000 0x0000 1501: 0xF71E 0xB4CF 0x0002 0x0000 0x0000 1502: 0xF71E 0xB4CF 0x0003 0x0000 0x0000 1503: 0xF71E 0xB42F 0x0002 0x0000 0x0000 1504: 0xF71E 0xB42F 0x0003 0x0000 0x0000 1505: 0xF71E 0xB4AF 0x0002 0x0000 0x0000 1506: 0xF71E 0xB4AF 0x0003 0x0000 0x0000 1507: 0xF71E 0xB46F 0x0002 0x0000 0x0000 1508: 0xF71E 0xB46F 0x0003 0x0000 0x0000 1509: 0xF71E 0xB4EF 0x0002 0x0000 0x0000 1510: 0xF71E 0xB4EF 0x0003 0x0000 0x0000 1511: 0xF71E 0xB80F 0x0002 0x0000 0x0000 1512: 0xF71E 0xB80F 0x0003 0x0000 0x0000 1513: 0xF71E 0xB88F 0x0002 0x0000 0x0000 1514: 0xF71E 0xB88F 0x0003 0x0000 0x0000 1515: 0xF71E 0xB84F 0x0002 0x0000 0x0000 1516: 0xF71E 0xB84F 0x0003 0x0000 0x0000 1517: 0xF71E 0xB8CF 0x0002 0x0000 0x0000 1518: 0xF71E 0xB8CF 0x0003 0x0000 0x0000 1519: 0xF71E 0xB82F 0x0002 0x0000 0x0000 1520: 0xF71E 0xB82F 0x0003 0x0000 0x0000 1521: 0xF71E 0xB8AF 0x0002 0x0000 0x0000 1522: 0xF71E 0xB8AF 0x0003 0x0000 0x0000 1523: 0xF71E 0xB86F 0x0002 0x0000 0x0000 1524: 0xF71E 0xB86F 0x0003 0x0000 0x0000 1525: 0xF71E 0xB8EF 0x0002 0x0000 0x0000 1526: 0xF71E 0xB8EF 0x0003 0x0000 0x0000 1527: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 1528: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 1529: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 1530: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 1531: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 1532: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 1533: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 1534: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 1535: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 1536: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 1537: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 1538: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 1539: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 1540: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 1541: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 1542: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 1543: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIII IIII IIII G P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 3 pins used: 27 not used: 39 1543 'test steps' 1576 lines M119 REV B 3 8-input NAND PINS Main menu Fri Jun 30 16:30:13 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:30:14 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHJFHJKKLMNPMNPRRSTUV SIDE 111122222111122222111122222 DIRECTION IIIIIIIIOIIIIIIIIOIIIIIIIIO all fails was lo 000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111 total fails 0, total passes 7 Main menu Fri Jun 30 16:30:20 2017 test file is: tests\m119.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 16:30:36 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:30:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 60 Main menu Fri Jun 30 16:30:40 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 16:30:59 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:31:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 20 Main menu Fri Jun 30 16:31:02 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:31:15 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:31:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 38 Main menu Fri Jun 30 16:31:18 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 16:31:34 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:31:34 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 53 Main menu Fri Jun 30 16:31:37 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 16:31:52 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:31:53 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Fri Jun 30 16:31:56 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 16:32:02 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 16:32:09 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:32:15 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:32:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 43 Main menu Fri Jun 30 16:32:20 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:32:34 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:32:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 40 Main menu Fri Jun 30 16:32:37 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m112.tst reading test file: tests\m112.tst comment: M112 PCB REV D SCHEMATIC REV D 10 2-input NOR comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 O AC1 E1-13 pins: 4 I AD1 E1-5 pins: 5 I AE1 E1-6 pins: 6 O AF1 E1-4 pins: 7 I AD2 E1-9 pins: 8 I AE2 E1-8 pins: 9 O AF2 E1-10 pins: 10 I AH1 E1-3 pins: 11 I AJ1 E1-2 pins: 12 O AK1 E1-1 pins: 13 I AH2 E2-3 pins: 14 I AJ2 E2-2 pins: 15 O AK2 E2-1 pins: 16 I AL1 E2-6 pins: 17 I AM1 E2-5 pins: 18 O AN1 E2-4 pins: 19 I AL2 E3-9 pins: 20 I AM2 E3-8 pins: 21 O AN2 E3-10 pins: 22 I AP1 E3-12 pins: 23 I AR1 E3-11 pins: 24 O AS1 E3-13 pins: 25 I AP2 E3-6 pins: 26 I AR2 E3-5 pins: 27 O AS2 E3-4 pins: 28 I AT2 E3-3 pins: 29 I AU2 E3-2 pins: 30 O AV2 E3-1 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 010 test 3: 110 test 4: 100 test 5: 001 test 6: 010 test 7: 110 test 8: 100 test 9: 001 test 10: 010 test 11: 110 test 12: 100 test 13: 001 test 14: 010 test 15: 110 test 16: 100 test 17: 001 test 18: 010 test 19: 110 test 20: 100 test 21: 001 test 22: 010 test 23: 110 test 24: 100 test 25: 001 test 26: 010 test 27: 110 test 28: 100 test 29: 001 test 30: 010 test 31: 110 test 32: 100 test 33: 001 test 34: 010 test 35: 110 test 36: 100 test 37: 001 test 38: 010 test 39: 110 test 40: 100 test 41: 001 test 42: 001001001001001001001001001001 test 43: 110110110110110110110110110110 test 44: 010 test 45: 001 test 46: 100 test 47: 110 test 48: 010 test 49: 001 test 50: 100 test 51: 110 test 52: 010 test 53: 001 test 54: 100 test 55: 110 test 56: 010 test 57: 001 test 58: 100 test 59: 110 test 60: 010 test 61: 001 test 62: 100 test 63: 110 test 64: 010 test 65: 001 test 66: 100 test 67: 110 test 68: 010 test 69: 001 test 70: 100 test 71: 110 test 72: 010 test 73: 001 test 74: 100 test 75: 110 test 76: 010 test 77: 001 test 78: 100 test 79: 110 test 80: 010 test 81: 001 test 82: 100 test 83: 110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0x4404 0x9249 0x0002 0x0000 0x0000 3: 0xC404 0x9249 0x0002 0x0000 0x0000 4: 0x8404 0x9249 0x0002 0x0000 0x0000 5: 0x2404 0x9249 0x0002 0x0000 0x0000 6: 0x2804 0x9249 0x0002 0x0000 0x0000 7: 0x3804 0x9249 0x0002 0x0000 0x0000 8: 0x3004 0x9249 0x0002 0x0000 0x0000 9: 0x2404 0x9249 0x0002 0x0000 0x0000 10: 0x2408 0x9249 0x0002 0x0000 0x0000 11: 0x2418 0x9249 0x0002 0x0000 0x0000 12: 0x2410 0x9249 0x0002 0x0000 0x0000 13: 0x2404 0x9249 0x0002 0x0000 0x0000 14: 0x2504 0x1249 0x0002 0x0000 0x0000 15: 0x2704 0x1249 0x0002 0x0000 0x0000 16: 0x2604 0x1249 0x0002 0x0000 0x0000 17: 0x2404 0x9249 0x0002 0x0000 0x0000 18: 0x2405 0x9248 0x0002 0x0000 0x0000 19: 0x2407 0x9248 0x0002 0x0000 0x0000 20: 0x2406 0x9248 0x0002 0x0000 0x0000 21: 0x2404 0x9249 0x0002 0x0000 0x0000 22: 0x2404 0xA249 0x0002 0x0000 0x0000 23: 0x2404 0xE249 0x0002 0x0000 0x0000 24: 0x2404 0xC249 0x0002 0x0000 0x0000 25: 0x2404 0x9249 0x0002 0x0000 0x0000 26: 0x2404 0x9245 0x0002 0x0000 0x0000 27: 0x2404 0x9247 0x0002 0x0000 0x0000 28: 0x2404 0x9243 0x0002 0x0000 0x0000 29: 0x2404 0x9249 0x0002 0x0000 0x0000 30: 0x2404 0x9449 0x0002 0x0000 0x0000 31: 0x2404 0x9C49 0x0002 0x0000 0x0000 32: 0x2404 0x9849 0x0002 0x0000 0x0000 33: 0x2404 0x9249 0x0002 0x0000 0x0000 34: 0x2404 0x9229 0x0002 0x0000 0x0000 35: 0x2404 0x9239 0x0002 0x0000 0x0000 36: 0x2404 0x9219 0x0002 0x0000 0x0000 37: 0x2404 0x9249 0x0002 0x0000 0x0000 38: 0x2404 0x9249 0x0001 0x0000 0x0000 39: 0x2404 0x92C9 0x0001 0x0000 0x0000 40: 0x2404 0x92C9 0x0000 0x0000 0x0000 41: 0x2404 0x9249 0x0002 0x0000 0x0000 42: 0x2404 0x9249 0x0002 0x0000 0x0000 43: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 44: 0x5B1B 0x6CB6 0x0001 0x0000 0x0000 45: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 46: 0x9B1B 0x6CB6 0x0001 0x0000 0x0000 47: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 48: 0xCB1B 0x6CB6 0x0001 0x0000 0x0000 49: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 50: 0xD31B 0x6CB6 0x0001 0x0000 0x0000 51: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 52: 0xDB0B 0x6CB6 0x0001 0x0000 0x0000 53: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 54: 0xDB13 0x6CB6 0x0001 0x0000 0x0000 55: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 56: 0xD91B 0x6CB6 0x0001 0x0000 0x0000 57: 0xD81B 0xECB6 0x0001 0x0000 0x0000 58: 0xDA1B 0x6CB6 0x0001 0x0000 0x0000 59: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 60: 0xDB19 0x6CB6 0x0001 0x0000 0x0000 61: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 62: 0xDB1A 0x6CB6 0x0001 0x0000 0x0000 63: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 64: 0xDB1B 0x2CB6 0x0001 0x0000 0x0000 65: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 66: 0xDB1B 0x4CB6 0x0001 0x0000 0x0000 67: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 68: 0xDB1B 0x6CB4 0x0001 0x0000 0x0000 69: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 70: 0xDB1B 0x6CB2 0x0001 0x0000 0x0000 71: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 72: 0xDB1B 0x64B6 0x0001 0x0000 0x0000 73: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 74: 0xDB1B 0x68B6 0x0001 0x0000 0x0000 75: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 76: 0xDB1B 0x6CA6 0x0001 0x0000 0x0000 77: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 78: 0xDB1B 0x6C96 0x0001 0x0000 0x0000 79: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 80: 0xDB1B 0x6C36 0x0001 0x0000 0x0000 81: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 82: 0xDB1B 0x6CB6 0x0000 0x0000 0x0000 83: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M112 PCB REV D SCHEMATIC REV D 10 2-input NOR PINS Main menu Fri Jun 30 16:33:03 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:33:05 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 61 Main menu Fri Jun 30 16:33:13 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:33:32 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:33:33 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 34, total passes 0 Main menu Fri Jun 30 16:33:38 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:34:09 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:34:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 29: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 30: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 30, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 30, total passes 0 Main menu Fri Jun 30 16:35:07 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:35:15 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:35:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 37 Main menu Fri Jun 30 16:35:19 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 16:35:35 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:35:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 27 Main menu Fri Jun 30 16:35:39 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 16:35:56 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:35:57 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 40 Main menu Fri Jun 30 16:36:00 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:36:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 53 Main menu Fri Jun 30 16:36:16 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m111.tst Main menu Fri Jun 30 16:36:34 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:37:02 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:37:04 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 37, total passes 0 Main menu Fri Jun 30 16:37:08 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:37:35 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:37:36 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 82 001001001001001001001001001100 fail ^ step 83 001001001001001001001001001001 test 27: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 27, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 41 110110110110110110110110110100 fail ^ step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 82 001001001001001001001001001100 fail ^ step 83 001001001001001001001001001001 test 28: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 28, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 41 110110110110110110110110110100 fail ^ step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 82 001001001001001001001001001100 fail ^ step 83 001001001001001001001001001001 test 29: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 29, total passes 0 Main menu Fri Jun 30 16:38:32 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 16:38:37 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:38:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 26 Main menu Fri Jun 30 16:38:42 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 16:39:23 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:39:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 16 Main menu Fri Jun 30 16:39:26 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 16:39:40 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:39:42 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 20 Main menu Fri Jun 30 16:39:45 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 16:39:59 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:40:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 20 Main menu Fri Jun 30 16:40:04 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst could not open test file. valid test files are: reverting back to test file: tests\m121.tst Main menu Fri Jun 30 16:40:20 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:40:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails I O I OI IOI IO I O I O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 22, total passes 0 Main menu Fri Jun 30 16:40:30 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst could not open test file. valid test files are: reverting back to test file: tests\m121.tst Main menu Fri Jun 30 16:40:36 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:40:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails I O I OI IOI IO I O I O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 19, total passes 0 Main menu Fri Jun 30 16:40:42 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst could not open test file. valid test files are: reverting back to test file: tests\m121.tst Main menu Fri Jun 30 16:40:50 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 16:41:06 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Fri Jun 30 16:41:12 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:41:17 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:41:18 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 16:41:18 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:41:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 48 Main menu Fri Jun 30 16:41:23 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 16:41:37 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:41:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 43 Main menu Fri Jun 30 16:41:40 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x000D Main menu Fri Jun 30 16:41:41 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:41:55 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 66 Main menu Fri Jun 30 16:41:58 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:42:13 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:42:14 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 27 Main menu Fri Jun 30 16:42:17 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 16:42:33 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:42:34 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 28 Main menu Fri Jun 30 16:42:38 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 16:42:52 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:42:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 23 Main menu Fri Jun 30 16:42:57 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 16:43:15 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:43:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 36 Main menu Fri Jun 30 16:43:18 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m115.tst reading test file: tests\m115.tst comment: M115 REV C 8 3-input NAND comment: pins: PINS pins: 1 I AA1 E1-11 pins: 2 I AB1 E1-10 pins: 3 I AC1 E1-9 pins: 4 O AD1 E1-8 pins: 5 I AD2 E1-2 pins: 6 I AE2 E1-1 pins: 7 I AF2 E1-13 pins: 8 O AH2 E1-12 pins: 9 I AE1 E1-3 pins: 10 I AF1 E1-4 pins: 11 I AH1 E1-5 pins: 12 O AJ1 E1-6 pins: 13 I AJ2 E3-11 pins: 14 I AK2 E3-10 pins: 15 I AL2 E3-9 pins: 16 O AM2 E3-8 pins: 17 I AK1 E2-1 pins: 18 I AL1 E2-2 pins: 19 I AM1 E2-13 pins: 20 O AN1 E2-12 pins: 21 I AN2 E2-11 pins: 22 I AP2 E2-10 pins: 23 I AR2 E2-9 pins: 24 O AS2 E2-8 pins: 25 I AP1 E2-3 pins: 26 I AR1 E2-4 pins: 27 I AS1 E2-5 pins: 28 O AU1 E2-6 pins: 29 I AT2 E3-5 pins: 30 I AU2 E3-4 pins: 31 I AV2 E3-3 pins: 32 O AV1 E3-6 pins: direction: IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO test 1: 00010001000100010001000100010001 test 2: 0001 test 3: 0011 test 4: 0101 test 5: 0111 test 6: 1001 test 7: 1011 test 8: 1101 test 9: 1110 test 10: 0001 test 11: 0001 test 12: 0011 test 13: 0101 test 14: 0111 test 15: 1001 test 16: 1011 test 17: 1101 test 18: 1110 test 19: 0001 test 20: 0001 test 21: 0011 test 22: 0101 test 23: 0111 test 24: 1001 test 25: 1011 test 26: 1101 test 27: 1110 test 28: 0001 test 29: 0001 test 30: 0011 test 31: 0101 test 32: 0111 test 33: 1001 test 34: 1011 test 35: 1101 test 36: 1110 test 37: 0001 test 38: 0001 test 39: 0011 test 40: 0101 test 41: 0111 test 42: 1001 test 43: 1011 test 44: 1101 test 45: 1110 test 46: 0001 test 47: 0001 test 48: 0011 test 49: 0101 test 50: 0111 test 51: 1001 test 52: 1011 test 53: 1101 test 54: 1110 test 55: 0001 test 56: 0001 test 57: 0011 test 58: 0101 test 59: 0111 test 60: 1001 test 61: 1011 test 62: 1101 test 63: 1110 test 64: 0001 test 65: 0001 test 66: 0011 test 67: 0101 test 68: 0111 test 69: 1001 test 70: 1011 test 71: 1101 test 72: 1110 test 73: 0001 test 74: 00010001000100010001000100010001 test 75: 11101110111011101110111011101110 test 76: 0001 test 77: 0011 test 78: 0101 test 79: 0111 test 80: 1001 test 81: 1011 test 82: 1101 test 83: 1110 test 84: 0001 test 85: 0011 test 86: 0101 test 87: 0111 test 88: 1001 test 89: 1011 test 90: 1101 test 91: 1110 test 92: 0001 test 93: 0011 test 94: 0101 test 95: 0111 test 96: 1001 test 97: 1011 test 98: 1101 test 99: 1110 test 100: 0001 test 101: 0011 test 102: 0101 test 103: 0111 test 104: 1001 test 105: 1011 test 106: 1101 test 107: 1110 test 108: 0001 test 109: 0011 test 110: 0101 test 111: 0111 test 112: 1001 test 113: 1011 test 114: 1101 test 115: 1110 test 116: 0001 test 117: 0011 test 118: 0101 test 119: 0111 test 120: 1001 test 121: 1011 test 122: 1101 test 123: 1110 test 124: 0001 test 125: 0011 test 126: 0101 test 127: 0111 test 128: 1001 test 129: 1011 test 130: 1101 test 131: 1110 test 132: 0001 test 133: 0011 test 134: 0101 test 135: 0111 test 136: 1001 test 137: 1011 test 138: 1101 test 139: 1110 test 140: 11101110111011101110111011101110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0010 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0002 column 9: offset 0, mask 0x0800 column 10: offset 0, mask 0x0400 column 11: offset 0, mask 0x0200 column 12: offset 0, mask 0x0100 column 13: offset 0, mask 0x0001 column 14: offset 1, mask 0x0001 column 15: offset 1, mask 0x0002 column 16: offset 1, mask 0x0004 column 17: offset 1, mask 0x8000 column 18: offset 1, mask 0x4000 column 19: offset 1, mask 0x2000 column 20: offset 1, mask 0x1000 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0010 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0040 column 25: offset 1, mask 0x0800 column 26: offset 1, mask 0x0400 column 27: offset 1, mask 0x0200 column 28: offset 2, mask 0x8000 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x11E2 0x1144 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1102 0x1044 0xC000 0x0000 0x0000 2: 0x1102 0x1044 0xC000 0x0000 0x0000 3: 0x3102 0x1044 0xC000 0x0000 0x0000 4: 0x5102 0x1044 0xC000 0x0000 0x0000 5: 0x7102 0x1044 0xC000 0x0000 0x0000 6: 0x9102 0x1044 0xC000 0x0000 0x0000 7: 0xB102 0x1044 0xC000 0x0000 0x0000 8: 0xD102 0x1044 0xC000 0x0000 0x0000 9: 0xE102 0x1044 0xC000 0x0000 0x0000 10: 0x1102 0x1044 0xC000 0x0000 0x0000 11: 0x1102 0x1044 0xC000 0x0000 0x0000 12: 0x1106 0x1044 0xC000 0x0000 0x0000 13: 0x110A 0x1044 0xC000 0x0000 0x0000 14: 0x110E 0x1044 0xC000 0x0000 0x0000 15: 0x1112 0x1044 0xC000 0x0000 0x0000 16: 0x1116 0x1044 0xC000 0x0000 0x0000 17: 0x111A 0x1044 0xC000 0x0000 0x0000 18: 0x111C 0x1044 0xC000 0x0000 0x0000 19: 0x1102 0x1044 0xC000 0x0000 0x0000 20: 0x1102 0x1044 0xC000 0x0000 0x0000 21: 0x1302 0x1044 0xC000 0x0000 0x0000 22: 0x1502 0x1044 0xC000 0x0000 0x0000 23: 0x1702 0x1044 0xC000 0x0000 0x0000 24: 0x1902 0x1044 0xC000 0x0000 0x0000 25: 0x1B02 0x1044 0xC000 0x0000 0x0000 26: 0x1D02 0x1044 0xC000 0x0000 0x0000 27: 0x1E02 0x1044 0xC000 0x0000 0x0000 28: 0x1102 0x1044 0xC000 0x0000 0x0000 29: 0x1102 0x1044 0xC000 0x0000 0x0000 30: 0x1102 0x1046 0xC000 0x0000 0x0000 31: 0x1102 0x1045 0xC000 0x0000 0x0000 32: 0x1102 0x1047 0xC000 0x0000 0x0000 33: 0x1103 0x1044 0xC000 0x0000 0x0000 34: 0x1103 0x1046 0xC000 0x0000 0x0000 35: 0x1103 0x1045 0xC000 0x0000 0x0000 36: 0x1103 0x1043 0xC000 0x0000 0x0000 37: 0x1102 0x1044 0xC000 0x0000 0x0000 38: 0x1102 0x1044 0xC000 0x0000 0x0000 39: 0x1102 0x3044 0xC000 0x0000 0x0000 40: 0x1102 0x5044 0xC000 0x0000 0x0000 41: 0x1102 0x7044 0xC000 0x0000 0x0000 42: 0x1102 0x9044 0xC000 0x0000 0x0000 43: 0x1102 0xB044 0xC000 0x0000 0x0000 44: 0x1102 0xD044 0xC000 0x0000 0x0000 45: 0x1102 0xE044 0xC000 0x0000 0x0000 46: 0x1102 0x1044 0xC000 0x0000 0x0000 47: 0x1102 0x1044 0xC000 0x0000 0x0000 48: 0x1102 0x1064 0xC000 0x0000 0x0000 49: 0x1102 0x1054 0xC000 0x0000 0x0000 50: 0x1102 0x1074 0xC000 0x0000 0x0000 51: 0x1102 0x104C 0xC000 0x0000 0x0000 52: 0x1102 0x106C 0xC000 0x0000 0x0000 53: 0x1102 0x105C 0xC000 0x0000 0x0000 54: 0x1102 0x103C 0xC000 0x0000 0x0000 55: 0x1102 0x1044 0xC000 0x0000 0x0000 56: 0x1102 0x1044 0xC000 0x0000 0x0000 57: 0x1102 0x1244 0xC000 0x0000 0x0000 58: 0x1102 0x1444 0xC000 0x0000 0x0000 59: 0x1102 0x1644 0xC000 0x0000 0x0000 60: 0x1102 0x1844 0xC000 0x0000 0x0000 61: 0x1102 0x1A44 0xC000 0x0000 0x0000 62: 0x1102 0x1C44 0xC000 0x0000 0x0000 63: 0x1102 0x1E44 0x4000 0x0000 0x0000 64: 0x1102 0x1044 0xC000 0x0000 0x0000 65: 0x1102 0x1044 0xC000 0x0000 0x0000 66: 0x1102 0x1044 0xC002 0x0000 0x0000 67: 0x1102 0x1044 0xC001 0x0000 0x0000 68: 0x1102 0x1044 0xC003 0x0000 0x0000 69: 0x1102 0x10C4 0xC000 0x0000 0x0000 70: 0x1102 0x10C4 0xC002 0x0000 0x0000 71: 0x1102 0x10C4 0xC001 0x0000 0x0000 72: 0x1102 0x10C4 0x8003 0x0000 0x0000 73: 0x1102 0x1044 0xC000 0x0000 0x0000 74: 0x1102 0x1044 0xC000 0x0000 0x0000 75: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 76: 0x1E1D 0xEEBB 0x0003 0x0000 0x0000 77: 0x3E1D 0xEEBB 0x0003 0x0000 0x0000 78: 0x5E1D 0xEEBB 0x0003 0x0000 0x0000 79: 0x7E1D 0xEEBB 0x0003 0x0000 0x0000 80: 0x9E1D 0xEEBB 0x0003 0x0000 0x0000 81: 0xBE1D 0xEEBB 0x0003 0x0000 0x0000 82: 0xDE1D 0xEEBB 0x0003 0x0000 0x0000 83: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 84: 0xEE03 0xEEBB 0x0003 0x0000 0x0000 85: 0xEE07 0xEEBB 0x0003 0x0000 0x0000 86: 0xEE0B 0xEEBB 0x0003 0x0000 0x0000 87: 0xEE0F 0xEEBB 0x0003 0x0000 0x0000 88: 0xEE13 0xEEBB 0x0003 0x0000 0x0000 89: 0xEE17 0xEEBB 0x0003 0x0000 0x0000 90: 0xEE1B 0xEEBB 0x0003 0x0000 0x0000 91: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 92: 0xE11D 0xEEBB 0x0003 0x0000 0x0000 93: 0xE31D 0xEEBB 0x0003 0x0000 0x0000 94: 0xE51D 0xEEBB 0x0003 0x0000 0x0000 95: 0xE71D 0xEEBB 0x0003 0x0000 0x0000 96: 0xE91D 0xEEBB 0x0003 0x0000 0x0000 97: 0xEB1D 0xEEBB 0x0003 0x0000 0x0000 98: 0xED1D 0xEEBB 0x0003 0x0000 0x0000 99: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 100: 0xEE1C 0xEEBC 0x0003 0x0000 0x0000 101: 0xEE1C 0xEEBE 0x0003 0x0000 0x0000 102: 0xEE1C 0xEEBD 0x0003 0x0000 0x0000 103: 0xEE1C 0xEEBF 0x0003 0x0000 0x0000 104: 0xEE1D 0xEEBC 0x0003 0x0000 0x0000 105: 0xEE1D 0xEEBE 0x0003 0x0000 0x0000 106: 0xEE1D 0xEEBD 0x0003 0x0000 0x0000 107: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 108: 0xEE1D 0x1EBB 0x0003 0x0000 0x0000 109: 0xEE1D 0x3EBB 0x0003 0x0000 0x0000 110: 0xEE1D 0x5EBB 0x0003 0x0000 0x0000 111: 0xEE1D 0x7EBB 0x0003 0x0000 0x0000 112: 0xEE1D 0x9EBB 0x0003 0x0000 0x0000 113: 0xEE1D 0xBEBB 0x0003 0x0000 0x0000 114: 0xEE1D 0xDEBB 0x0003 0x0000 0x0000 115: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 116: 0xEE1D 0xEEC3 0x0003 0x0000 0x0000 117: 0xEE1D 0xEEE3 0x0003 0x0000 0x0000 118: 0xEE1D 0xEED3 0x0003 0x0000 0x0000 119: 0xEE1D 0xEEF3 0x0003 0x0000 0x0000 120: 0xEE1D 0xEECB 0x0003 0x0000 0x0000 121: 0xEE1D 0xEEEB 0x0003 0x0000 0x0000 122: 0xEE1D 0xEEDB 0x0003 0x0000 0x0000 123: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 124: 0xEE1D 0xE0BB 0x8003 0x0000 0x0000 125: 0xEE1D 0xE2BB 0x8003 0x0000 0x0000 126: 0xEE1D 0xE4BB 0x8003 0x0000 0x0000 127: 0xEE1D 0xE6BB 0x8003 0x0000 0x0000 128: 0xEE1D 0xE8BB 0x8003 0x0000 0x0000 129: 0xEE1D 0xEABB 0x8003 0x0000 0x0000 130: 0xEE1D 0xECBB 0x8003 0x0000 0x0000 131: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 132: 0xEE1D 0xEE3B 0x4000 0x0000 0x0000 133: 0xEE1D 0xEE3B 0x4002 0x0000 0x0000 134: 0xEE1D 0xEE3B 0x4001 0x0000 0x0000 135: 0xEE1D 0xEE3B 0x4003 0x0000 0x0000 136: 0xEE1D 0xEEBB 0x4000 0x0000 0x0000 137: 0xEE1D 0xEEBB 0x4002 0x0000 0x0000 138: 0xEE1D 0xEEBB 0x4001 0x0000 0x0000 139: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 140: 0xEE1D 0xEEBB 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOIIIOIIIOIIIGOOP GIIIOIIIOIIIOIII G P G UUT inputs: 24 UUT outputs: 8 pins used: 32 not used: 34 140 'test steps' 178 lines M115 REV C 8 3-input NAND PINS Main menu Fri Jun 30 16:43:37 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:43:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDDEFHEFHJJKLMKLMNNPRSPRSUTUVV SIDE 11112222111122221111222211112221 DIRECTION IIIOIIIOIIIOIIIOIIIOIIIOIIIOIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 26 Main menu Fri Jun 30 16:43:40 2017 test file is: tests\m115.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:43:53 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:43:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 55 Main menu Fri Jun 30 16:43:58 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:44:20 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:44:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 94 Main menu Fri Jun 30 16:44:28 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 16:44:44 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:44:46 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 67 Main menu Fri Jun 30 16:44:49 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m112.tst reading test file: tests\m112.tst comment: M112 PCB REV D SCHEMATIC REV D 10 2-input NOR comment: pins: PINS pins: 1 I AA1 E1-12 pins: 2 I AB1 E1-11 pins: 3 O AC1 E1-13 pins: 4 I AD1 E1-5 pins: 5 I AE1 E1-6 pins: 6 O AF1 E1-4 pins: 7 I AD2 E1-9 pins: 8 I AE2 E1-8 pins: 9 O AF2 E1-10 pins: 10 I AH1 E1-3 pins: 11 I AJ1 E1-2 pins: 12 O AK1 E1-1 pins: 13 I AH2 E2-3 pins: 14 I AJ2 E2-2 pins: 15 O AK2 E2-1 pins: 16 I AL1 E2-6 pins: 17 I AM1 E2-5 pins: 18 O AN1 E2-4 pins: 19 I AL2 E3-9 pins: 20 I AM2 E3-8 pins: 21 O AN2 E3-10 pins: 22 I AP1 E3-12 pins: 23 I AR1 E3-11 pins: 24 O AS1 E3-13 pins: 25 I AP2 E3-6 pins: 26 I AR2 E3-5 pins: 27 O AS2 E3-4 pins: 28 I AT2 E3-3 pins: 29 I AU2 E3-2 pins: 30 O AV2 E3-1 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 010 test 3: 110 test 4: 100 test 5: 001 test 6: 010 test 7: 110 test 8: 100 test 9: 001 test 10: 010 test 11: 110 test 12: 100 test 13: 001 test 14: 010 test 15: 110 test 16: 100 test 17: 001 test 18: 010 test 19: 110 test 20: 100 test 21: 001 test 22: 010 test 23: 110 test 24: 100 test 25: 001 test 26: 010 test 27: 110 test 28: 100 test 29: 001 test 30: 010 test 31: 110 test 32: 100 test 33: 001 test 34: 010 test 35: 110 test 36: 100 test 37: 001 test 38: 010 test 39: 110 test 40: 100 test 41: 001 test 42: 001001001001001001001001001001 test 43: 110110110110110110110110110110 test 44: 010 test 45: 001 test 46: 100 test 47: 110 test 48: 010 test 49: 001 test 50: 100 test 51: 110 test 52: 010 test 53: 001 test 54: 100 test 55: 110 test 56: 010 test 57: 001 test 58: 100 test 59: 110 test 60: 010 test 61: 001 test 62: 100 test 63: 110 test 64: 010 test 65: 001 test 66: 100 test 67: 110 test 68: 010 test 69: 001 test 70: 100 test 71: 110 test 72: 010 test 73: 001 test 74: 100 test 75: 110 test 76: 010 test 77: 001 test 78: 100 test 79: 110 test 80: 010 test 81: 001 test 82: 100 test 83: 110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0x4404 0x9249 0x0002 0x0000 0x0000 3: 0xC404 0x9249 0x0002 0x0000 0x0000 4: 0x8404 0x9249 0x0002 0x0000 0x0000 5: 0x2404 0x9249 0x0002 0x0000 0x0000 6: 0x2804 0x9249 0x0002 0x0000 0x0000 7: 0x3804 0x9249 0x0002 0x0000 0x0000 8: 0x3004 0x9249 0x0002 0x0000 0x0000 9: 0x2404 0x9249 0x0002 0x0000 0x0000 10: 0x2408 0x9249 0x0002 0x0000 0x0000 11: 0x2418 0x9249 0x0002 0x0000 0x0000 12: 0x2410 0x9249 0x0002 0x0000 0x0000 13: 0x2404 0x9249 0x0002 0x0000 0x0000 14: 0x2504 0x1249 0x0002 0x0000 0x0000 15: 0x2704 0x1249 0x0002 0x0000 0x0000 16: 0x2604 0x1249 0x0002 0x0000 0x0000 17: 0x2404 0x9249 0x0002 0x0000 0x0000 18: 0x2405 0x9248 0x0002 0x0000 0x0000 19: 0x2407 0x9248 0x0002 0x0000 0x0000 20: 0x2406 0x9248 0x0002 0x0000 0x0000 21: 0x2404 0x9249 0x0002 0x0000 0x0000 22: 0x2404 0xA249 0x0002 0x0000 0x0000 23: 0x2404 0xE249 0x0002 0x0000 0x0000 24: 0x2404 0xC249 0x0002 0x0000 0x0000 25: 0x2404 0x9249 0x0002 0x0000 0x0000 26: 0x2404 0x9245 0x0002 0x0000 0x0000 27: 0x2404 0x9247 0x0002 0x0000 0x0000 28: 0x2404 0x9243 0x0002 0x0000 0x0000 29: 0x2404 0x9249 0x0002 0x0000 0x0000 30: 0x2404 0x9449 0x0002 0x0000 0x0000 31: 0x2404 0x9C49 0x0002 0x0000 0x0000 32: 0x2404 0x9849 0x0002 0x0000 0x0000 33: 0x2404 0x9249 0x0002 0x0000 0x0000 34: 0x2404 0x9229 0x0002 0x0000 0x0000 35: 0x2404 0x9239 0x0002 0x0000 0x0000 36: 0x2404 0x9219 0x0002 0x0000 0x0000 37: 0x2404 0x9249 0x0002 0x0000 0x0000 38: 0x2404 0x9249 0x0001 0x0000 0x0000 39: 0x2404 0x92C9 0x0001 0x0000 0x0000 40: 0x2404 0x92C9 0x0000 0x0000 0x0000 41: 0x2404 0x9249 0x0002 0x0000 0x0000 42: 0x2404 0x9249 0x0002 0x0000 0x0000 43: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 44: 0x5B1B 0x6CB6 0x0001 0x0000 0x0000 45: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 46: 0x9B1B 0x6CB6 0x0001 0x0000 0x0000 47: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 48: 0xCB1B 0x6CB6 0x0001 0x0000 0x0000 49: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 50: 0xD31B 0x6CB6 0x0001 0x0000 0x0000 51: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 52: 0xDB0B 0x6CB6 0x0001 0x0000 0x0000 53: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 54: 0xDB13 0x6CB6 0x0001 0x0000 0x0000 55: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 56: 0xD91B 0x6CB6 0x0001 0x0000 0x0000 57: 0xD81B 0xECB6 0x0001 0x0000 0x0000 58: 0xDA1B 0x6CB6 0x0001 0x0000 0x0000 59: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 60: 0xDB19 0x6CB6 0x0001 0x0000 0x0000 61: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 62: 0xDB1A 0x6CB6 0x0001 0x0000 0x0000 63: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 64: 0xDB1B 0x2CB6 0x0001 0x0000 0x0000 65: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 66: 0xDB1B 0x4CB6 0x0001 0x0000 0x0000 67: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 68: 0xDB1B 0x6CB4 0x0001 0x0000 0x0000 69: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 70: 0xDB1B 0x6CB2 0x0001 0x0000 0x0000 71: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 72: 0xDB1B 0x64B6 0x0001 0x0000 0x0000 73: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 74: 0xDB1B 0x68B6 0x0001 0x0000 0x0000 75: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 76: 0xDB1B 0x6CA6 0x0001 0x0000 0x0000 77: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 78: 0xDB1B 0x6C96 0x0001 0x0000 0x0000 79: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 80: 0xDB1B 0x6C36 0x0001 0x0000 0x0000 81: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 82: 0xDB1B 0x6CB6 0x0000 0x0000 0x0000 83: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M112 PCB REV D SCHEMATIC REV D 10 2-input NOR PINS Main menu Fri Jun 30 16:45:10 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:45:11 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 94 Main menu Fri Jun 30 16:45:17 2017 test file is: tests\m112.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 16:45:33 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:45:33 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 18 Main menu Fri Jun 30 16:45:36 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:45:50 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:45:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 51 Main menu Fri Jun 30 16:45:57 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:46:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Fri Jun 30 16:46:17 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 16:46:39 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:46:47 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 49 Main menu Fri Jun 30 16:46:50 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m660.tst could not open test file. valid test files are: reverting back to test file: tests\m113.tst Main menu Fri Jun 30 16:47:07 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0078 Main menu Fri Jun 30 16:47:08 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m113.tst Main menu Fri Jun 30 16:47:13 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 16:47:25 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: Main menu Fri Jun 30 16:47:28 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m660.tst reading test file: tests\m660.tst comment: M660 PCB Rev B Schematic Rev A Three 2-input NAND Positive Level Driver comment: comment: pins: PINS pins: 1 I AH2 E1-6 pins: 2 I AJ2 E1-5 pins: 3 O AD2 Q1,Q2 pins: 4 I AN2 E1-3 pins: 5 I AP2 E1-2 pins: 6 O AK2 Q3,Q4 pins: 7 I AU2 E2-3 pins: 8 I AV2 E2-2 pins: 9 O AS2 Q5,Q6 pins: direction: IIOIIOIIO test 1: 001001001 test 2: 001 test 3: 011 test 4: 101 test 5: 110 test 6: 001 test 7: 001 test 8: 011 test 9: 101 test 10: 110 test 11: 001 test 12: 001 test 13: 011 test 14: 101 test 15: 110 test 16: 001 test 17: 001001001 test 18: 110110110 test 19: 001 test 20: 011 test 21: 101 test 22: 110 test 23: 001 test 24: 011 test 25: 101 test 26: 110 test 27: 001 test 28: 011 test 29: 101 test 30: 110 test 31: 110110110 end: END summary column 1: offset 0, mask 0x0002 column 2: offset 0, mask 0x0001 column 3: offset 0, mask 0x0010 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0001 column 7: offset 2, mask 0x0001 column 8: offset 2, mask 0x0002 column 9: offset 1, mask 0x0040 direction bits (1=input) 0xFFFC 0xFFE7 0xFFF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0010 0x0041 0x0000 0x0000 0x0000 2: 0x0010 0x0041 0x0000 0x0000 0x0000 3: 0x0011 0x0041 0x0000 0x0000 0x0000 4: 0x0012 0x0041 0x0000 0x0000 0x0000 5: 0x0003 0x0041 0x0000 0x0000 0x0000 6: 0x0010 0x0041 0x0000 0x0000 0x0000 7: 0x0010 0x0041 0x0000 0x0000 0x0000 8: 0x0010 0x0051 0x0000 0x0000 0x0000 9: 0x0010 0x0049 0x0000 0x0000 0x0000 10: 0x0010 0x0058 0x0000 0x0000 0x0000 11: 0x0010 0x0041 0x0000 0x0000 0x0000 12: 0x0010 0x0041 0x0000 0x0000 0x0000 13: 0x0010 0x0041 0x0002 0x0000 0x0000 14: 0x0010 0x0041 0x0001 0x0000 0x0000 15: 0x0010 0x0001 0x0003 0x0000 0x0000 16: 0x0010 0x0041 0x0000 0x0000 0x0000 17: 0x0010 0x0041 0x0000 0x0000 0x0000 18: 0x0003 0x0018 0x0003 0x0000 0x0000 19: 0x0010 0x0018 0x0003 0x0000 0x0000 20: 0x0011 0x0018 0x0003 0x0000 0x0000 21: 0x0012 0x0018 0x0003 0x0000 0x0000 22: 0x0003 0x0018 0x0003 0x0000 0x0000 23: 0x0003 0x0001 0x0003 0x0000 0x0000 24: 0x0003 0x0011 0x0003 0x0000 0x0000 25: 0x0003 0x0009 0x0003 0x0000 0x0000 26: 0x0003 0x0018 0x0003 0x0000 0x0000 27: 0x0003 0x0058 0x0000 0x0000 0x0000 28: 0x0003 0x0058 0x0002 0x0000 0x0000 29: 0x0003 0x0058 0x0001 0x0000 0x0000 30: 0x0003 0x0018 0x0003 0x0000 0x0000 31: 0x0003 0x0018 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P GO IIO II O II G P G UUT inputs: 6 UUT outputs: 3 pins used: 9 not used: 57 31 'test steps' 47 lines M660 PCB Rev B Schematic Rev A Three 2-input NAND Positive Level Driver PINS Main menu Fri Jun 30 16:47:38 2017 test file is: tests\m660.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:47:50 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAA LETTER HJDNPKUVS SIDE 222222222 DIRECTION IIOIIOIIO all fails was lo 000000000 falling vvvvvvvvv rising ^^^^^^^^^ was hi 111111111 total fails 0, total passes 240 Main menu Fri Jun 30 16:47:55 2017 test file is: tests\m660.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:48:13 2017 test file is: tests\m660.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 16:48:13 2017 test file is: tests\m660.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:48:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAA LETTER HJDNPKUVS SIDE 222222222 DIRECTION IIOIIOIIO all fails was lo 000000000 falling vvvvvvvvv rising ^^^^^^^^^ was hi 111111111 total fails 0, total passes 122 Main menu Fri Jun 30 16:48:18 2017 test file is: tests\m660.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:48:30 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAA LETTER HJDNPKUVS SIDE 222222222 DIRECTION IIOIIOIIO all fails was lo 000000000 falling vvvvvvvvv rising ^^^^^^^^^ was hi 111111111 total fails 0, total passes 252 Main menu Fri Jun 30 16:48:36 2017 test file is: tests\m660.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.tst could not open test file. valid test files are: reverting back to test file: tests\m660.tst Main menu Fri Jun 30 16:49:15 2017 test file is: tests\m660.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.new reading test file: tests\m623.new comment: M623 12 2-input OR bus buffer (open collector transistor outputs) comment: comment: WORKS, BUT NEEDS ALL INPUTS HI TESTS. comment: pins: PINS pins: 1 I AC1 E1-11,8 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 2 I AA1 E1-12 INPUT A pins: 3 I AB1 E1-9 INPUT B pins: 4 P AD1 E1-13,Q2 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 5 P AE1 E1-10,Q4 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: 6 I AJ1 E2-11,8 ENABLE C,D-N LOW TO ENABLE OUTPUT C AND D. pins: 7 I AF1 E2-12 INPUT C pins: 8 I AH1 E2-9 INPUT D pins: 9 P AK1 E2-13,Q6 OUTPUT C = INPUT C OR ENABLE C,D-N. pins: 10 P AL1 E2-10,Q8 OUTPUT D = INPUT D OR ENABLE C,D-N. pins: 11 I AP1 E3-11,8 ENABLE E,F-N LOW TO ENABLE OUTPUT E AND F. pins: 12 I AM1 E3-12 INPUT E pins: 13 I AN1 E3-9 INPUT F pins: 14 P AR1 E3-13,Q10 OUTPUT E = INPUT E OR ENABLE E,F-N. pins: 15 P AS1 E3-10,Q12 OUTPUT F = INPUT F OR ENABLE E,F-N. pins: 16 I AF2 E1-5,2 ENABLE H,J-N LOW TO ENABLE OUTPUT H AND J. pins: 17 I AD2 E1-6 INPUT H pins: 18 I AE2 E1-3 INPUT J pins: 19 P AH2 E1-4,Q1 OUTPUT H = INPUT H OR ENABLE H,J-N. pins: 20 P AJ2 E1-1,Q3 OUTPUT J = INPUT J OR ENABLE H,J-N. pins: 21 I AM2 E2-5,2 ENABLE K,L-N LOW TO ENABLE OUTPUT K AND L. pins: 22 I AK2 E2-6 INPUT K pins: 23 I AL2 E2-3 INPUT L pins: 24 P AN2 E2-4,Q5 OUTPUT K = INPUT K OR ENABLE K,L-N. pins: 25 P AP2 E2-1,Q7 OUTPUT L = INPUT L OR ENABLE K,L-N. pins: 26 I AT2 E3-5,2 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 27 I AR2 E3-6 INPUT A pins: 28 I AS2 E3-3 INPUT B pins: 29 P AU2 E3-4,Q9 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 30 P AV2 E3-1,Q11 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: direction: IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP test 1: 100111001110011100111001110011 test 2: 10111 test 3: 11111 test 4: 11011 test 5: 01010 test 6: 01111 test 7: 00101 test 8: 00000 test 9: 10011 test 10: 10111 test 11: 11111 test 12: 11011 test 13: 01010 test 14: 01111 test 15: 00101 test 16: 00000 test 17: 10011 test 18: 10111 test 19: 11111 test 20: 11011 test 21: 01010 test 22: 01111 test 23: 00101 test 24: 00000 test 25: 10011 test 26: 10111 test 27: 11111 test 28: 11011 test 29: 01010 test 30: 01111 test 31: 00101 test 32: 00000 test 33: 10011 test 34: 10111 test 35: 11111 test 36: 11011 test 37: 01010 test 38: 01111 test 39: 00101 test 40: 00000 test 41: 10011 test 42: 10111 test 43: 11111 test 44: 11011 test 45: 01010 test 46: 01111 test 47: 00101 test 48: 00000 test 49: 10011 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x8000 column 3: offset 0, mask 0x4000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0100 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0200 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x0800 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x1000 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0004 column 17: offset 0, mask 0x0010 column 18: offset 0, mask 0x0008 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0004 column 22: offset 1, mask 0x0001 column 23: offset 1, mask 0x0002 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0080 column 27: offset 1, mask 0x0020 column 28: offset 1, mask 0x0040 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x18E3 0xC718 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x1803 0xC618 0x0003 0x0000 0x0000 test step out_data dont care 1: 0x3907 0xCE9C 0x0003 0x0000 0x0000 2: 0x7907 0xCE9C 0x0003 0x0000 0x0000 3: 0xF907 0xCE9C 0x0003 0x0000 0x0000 4: 0xB907 0xCE9C 0x0003 0x0000 0x0000 5: 0x9107 0xCE9C 0x0003 0x0000 0x0000 6: 0xD907 0xCE9C 0x0003 0x0000 0x0000 7: 0x4907 0xCE9C 0x0003 0x0000 0x0000 8: 0x0107 0xCE9C 0x0003 0x0000 0x0000 9: 0x3907 0xCE9C 0x0003 0x0000 0x0000 10: 0x3B07 0xCE9C 0x0003 0x0000 0x0000 11: 0x3F07 0xCE9C 0x0003 0x0000 0x0000 12: 0x3D07 0xCE9C 0x0003 0x0000 0x0000 13: 0x3C07 0x8E9C 0x0003 0x0000 0x0000 14: 0x3E07 0xCE9C 0x0003 0x0000 0x0000 15: 0x3A07 0x4E9C 0x0003 0x0000 0x0000 16: 0x3807 0x0E9C 0x0003 0x0000 0x0000 17: 0x3907 0xCE9C 0x0003 0x0000 0x0000 18: 0x3907 0xDE9C 0x0003 0x0000 0x0000 19: 0x3907 0xFE9C 0x0003 0x0000 0x0000 20: 0x3907 0xEE9C 0x0003 0x0000 0x0000 21: 0x3907 0xE49C 0x0003 0x0000 0x0000 22: 0x3907 0xF69C 0x0003 0x0000 0x0000 23: 0x3907 0xD29C 0x0003 0x0000 0x0000 24: 0x3907 0xC09C 0x0003 0x0000 0x0000 25: 0x3907 0xCE9C 0x0003 0x0000 0x0000 26: 0x390F 0xCE9C 0x0003 0x0000 0x0000 27: 0x391F 0xCE9C 0x0003 0x0000 0x0000 28: 0x3917 0xCE9C 0x0003 0x0000 0x0000 29: 0x3912 0xCE9C 0x0003 0x0000 0x0000 30: 0x391B 0xCE9C 0x0003 0x0000 0x0000 31: 0x3909 0xCE9C 0x0003 0x0000 0x0000 32: 0x3900 0xCE9C 0x0003 0x0000 0x0000 33: 0x3907 0xCE9C 0x0003 0x0000 0x0000 34: 0x3907 0xCE9E 0x0003 0x0000 0x0000 35: 0x3907 0xCE9F 0x0003 0x0000 0x0000 36: 0x3907 0xCE9D 0x0003 0x0000 0x0000 37: 0x3907 0xCE89 0x0003 0x0000 0x0000 38: 0x3907 0xCE9B 0x0003 0x0000 0x0000 39: 0x3907 0xCE92 0x0003 0x0000 0x0000 40: 0x3907 0xCE80 0x0003 0x0000 0x0000 41: 0x3907 0xCE9C 0x0003 0x0000 0x0000 42: 0x3907 0xCEDC 0x0003 0x0000 0x0000 43: 0x3907 0xCEFC 0x0003 0x0000 0x0000 44: 0x3907 0xCEBC 0x0003 0x0000 0x0000 45: 0x3907 0xCE3C 0x0001 0x0000 0x0000 46: 0x3907 0xCE7C 0x0003 0x0000 0x0000 47: 0x3907 0xCE5C 0x0002 0x0000 0x0000 48: 0x3907 0xCE1C 0x0000 0x0000 0x0000 49: 0x3907 0xCE9C 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIPPIIIPPIIIPPG P GIIIPPIIIPPIIIPP G P G UUT inputs: 18 UUT outputs: 12 pins used: 30 not used: 36 49 'test steps' 87 lines M623 12 2-input OR bus buffer (open collector transistor outputs) WORKS, BUT NEEDS ALL INPUTS HI TESTS. PINS Main menu Fri Jun 30 16:49:24 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 16:49:25 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:49:28 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 189 Main menu Fri Jun 30 16:49:41 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:49:55 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 61 Main menu Fri Jun 30 16:49:57 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:50:11 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails PP PP P PP PP was lo 00000000 000 00000000 00000 falling vvvvvvvv vvv vvvvvvvv vvvvv rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ was hi 111111111111111111111111111111 total fails 58, total passes 0 Main menu Fri Jun 30 16:50:19 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.new reading test file: tests\m623.new comment: M623 12 2-input OR bus buffer (open collector transistor outputs) comment: comment: WORKS, BUT NEEDS ALL INPUTS HI TESTS. comment: pins: PINS pins: 1 I AC1 E1-11,8 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 2 I AA1 E1-12 INPUT A pins: 3 I AB1 E1-9 INPUT B pins: 4 P AD1 E1-13,Q2 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 5 P AE1 E1-10,Q4 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: 6 I AJ1 E2-11,8 ENABLE C,D-N LOW TO ENABLE OUTPUT C AND D. pins: 7 I AF1 E2-12 INPUT C pins: 8 I AH1 E2-9 INPUT D pins: 9 P AK1 E2-13,Q6 OUTPUT C = INPUT C OR ENABLE C,D-N. pins: 10 P AL1 E2-10,Q8 OUTPUT D = INPUT D OR ENABLE C,D-N. pins: 11 I AP1 E3-11,8 ENABLE E,F-N LOW TO ENABLE OUTPUT E AND F. pins: 12 I AM1 E3-12 INPUT E pins: 13 I AN1 E3-9 INPUT F pins: 14 P AR1 E3-13,Q10 OUTPUT E = INPUT E OR ENABLE E,F-N. pins: 15 P AS1 E3-10,Q12 OUTPUT F = INPUT F OR ENABLE E,F-N. pins: 16 I AF2 E1-5,2 ENABLE H,J-N LOW TO ENABLE OUTPUT H AND J. pins: 17 I AD2 E1-6 INPUT H pins: 18 I AE2 E1-3 INPUT J pins: 19 P AH2 E1-4,Q1 OUTPUT H = INPUT H OR ENABLE H,J-N. pins: 20 P AJ2 E1-1,Q3 OUTPUT J = INPUT J OR ENABLE H,J-N. pins: 21 I AM2 E2-5,2 ENABLE K,L-N LOW TO ENABLE OUTPUT K AND L. pins: 22 I AK2 E2-6 INPUT K pins: 23 I AL2 E2-3 INPUT L pins: 24 P AN2 E2-4,Q5 OUTPUT K = INPUT K OR ENABLE K,L-N. pins: 25 P AP2 E2-1,Q7 OUTPUT L = INPUT L OR ENABLE K,L-N. pins: 26 I AT2 E3-5,2 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 27 I AR2 E3-6 INPUT A pins: 28 I AS2 E3-3 INPUT B pins: 29 P AU2 E3-4,Q9 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 30 P AV2 E3-1,Q11 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: direction: IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP test 1: 100111001110011100111001110011 test 2: 10111 test 3: 11111 test 4: 11011 test 5: 01010 test 6: 01111 test 7: 00101 test 8: 00000 test 9: 10011 test 10: 10111 test 11: 11111 test 12: 11011 test 13: 01010 test 14: 01111 test 15: 00101 test 16: 00000 test 17: 10011 test 18: 10111 test 19: 11111 test 20: 11011 test 21: 01010 test 22: 01111 test 23: 00101 test 24: 00000 test 25: 10011 test 26: 10111 test 27: 11111 test 28: 11011 test 29: 01010 test 30: 01111 test 31: 00101 test 32: 00000 test 33: 10011 test 34: 10111 test 35: 11111 test 36: 11011 test 37: 01010 test 38: 01111 test 39: 00101 test 40: 00000 test 41: 10011 test 42: 10111 test 43: 11111 test 44: 11011 test 45: 01010 test 46: 01111 test 47: 00101 test 48: 00000 test 49: 10011 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x8000 column 3: offset 0, mask 0x4000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0100 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0200 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x0800 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x1000 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0004 column 17: offset 0, mask 0x0010 column 18: offset 0, mask 0x0008 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0004 column 22: offset 1, mask 0x0001 column 23: offset 1, mask 0x0002 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0080 column 27: offset 1, mask 0x0020 column 28: offset 1, mask 0x0040 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x18E3 0xC718 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x1803 0xC618 0x0003 0x0000 0x0000 test step out_data dont care 1: 0x3907 0xCE9C 0x0003 0x0000 0x0000 2: 0x7907 0xCE9C 0x0003 0x0000 0x0000 3: 0xF907 0xCE9C 0x0003 0x0000 0x0000 4: 0xB907 0xCE9C 0x0003 0x0000 0x0000 5: 0x9107 0xCE9C 0x0003 0x0000 0x0000 6: 0xD907 0xCE9C 0x0003 0x0000 0x0000 7: 0x4907 0xCE9C 0x0003 0x0000 0x0000 8: 0x0107 0xCE9C 0x0003 0x0000 0x0000 9: 0x3907 0xCE9C 0x0003 0x0000 0x0000 10: 0x3B07 0xCE9C 0x0003 0x0000 0x0000 11: 0x3F07 0xCE9C 0x0003 0x0000 0x0000 12: 0x3D07 0xCE9C 0x0003 0x0000 0x0000 13: 0x3C07 0x8E9C 0x0003 0x0000 0x0000 14: 0x3E07 0xCE9C 0x0003 0x0000 0x0000 15: 0x3A07 0x4E9C 0x0003 0x0000 0x0000 16: 0x3807 0x0E9C 0x0003 0x0000 0x0000 17: 0x3907 0xCE9C 0x0003 0x0000 0x0000 18: 0x3907 0xDE9C 0x0003 0x0000 0x0000 19: 0x3907 0xFE9C 0x0003 0x0000 0x0000 20: 0x3907 0xEE9C 0x0003 0x0000 0x0000 21: 0x3907 0xE49C 0x0003 0x0000 0x0000 22: 0x3907 0xF69C 0x0003 0x0000 0x0000 23: 0x3907 0xD29C 0x0003 0x0000 0x0000 24: 0x3907 0xC09C 0x0003 0x0000 0x0000 25: 0x3907 0xCE9C 0x0003 0x0000 0x0000 26: 0x390F 0xCE9C 0x0003 0x0000 0x0000 27: 0x391F 0xCE9C 0x0003 0x0000 0x0000 28: 0x3917 0xCE9C 0x0003 0x0000 0x0000 29: 0x3912 0xCE9C 0x0003 0x0000 0x0000 30: 0x391B 0xCE9C 0x0003 0x0000 0x0000 31: 0x3909 0xCE9C 0x0003 0x0000 0x0000 32: 0x3900 0xCE9C 0x0003 0x0000 0x0000 33: 0x3907 0xCE9C 0x0003 0x0000 0x0000 34: 0x3907 0xCE9E 0x0003 0x0000 0x0000 35: 0x3907 0xCE9F 0x0003 0x0000 0x0000 36: 0x3907 0xCE9D 0x0003 0x0000 0x0000 37: 0x3907 0xCE89 0x0003 0x0000 0x0000 38: 0x3907 0xCE9B 0x0003 0x0000 0x0000 39: 0x3907 0xCE92 0x0003 0x0000 0x0000 40: 0x3907 0xCE80 0x0003 0x0000 0x0000 41: 0x3907 0xCE9C 0x0003 0x0000 0x0000 42: 0x3907 0xCEDC 0x0003 0x0000 0x0000 43: 0x3907 0xCEFC 0x0003 0x0000 0x0000 44: 0x3907 0xCEBC 0x0003 0x0000 0x0000 45: 0x3907 0xCE3C 0x0001 0x0000 0x0000 46: 0x3907 0xCE7C 0x0003 0x0000 0x0000 47: 0x3907 0xCE5C 0x0002 0x0000 0x0000 48: 0x3907 0xCE1C 0x0000 0x0000 0x0000 49: 0x3907 0xCE9C 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIPPIIIPPIIIPPG P GIIIPPIIIPPIIIPP G P G UUT inputs: 18 UUT outputs: 12 pins used: 30 not used: 36 49 'test steps' 87 lines M623 12 2-input OR bus buffer (open collector transistor outputs) WORKS, BUT NEEDS ALL INPUTS HI TESTS. PINS Main menu Fri Jun 30 16:50:38 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:50:40 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 32 100111001110011000001001110011 step 33 100111001110011100111001110011 step 34 100111001110011100111011110011 step 35 100111001110011100111111110011 step 36 100111001110011100111101110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 37 100111001110011100110101110011 fail ^ step 38 100111001110011100110111110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 39 100111001110011100110011110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 0 step 40 100111001110011100110001010011 fail ^ step 41 100111001110011100111001110011 step 42 100111001110011100111001110111 step 43 100111001110011100111001111111 step 44 100111001110011100111001111011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 45 100111001110011100111001101011 fail ^ step 46 100111001110011100111001101111 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 47 100111001110011100111001100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 00 step 48 100111001110011100111001100001 fail ^ step 49 100111001110011100111001110011 test 47: *** FAIL *************************** 13 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail PP PP P PP PP all fails PP PP P PP PP was hi 111111111111111111111111111111 rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ falling vvvvvvvv vvv vvvvvvvv vvvvv was lo 00000000 000 00000000 00000 total fails 47, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100111001110011100111001110011 step 2 101111001110011100111001110011 step 3 111111001110011100111001110011 step 4 110111001110011100111001110011 step 5 010101001110011100111001110011 step 6 011111001110011100111001110011 step 7 001011001110011100111001110011 step 8 000001001110011100111001110011 step 9 100111001110011100111001110011 step 10 100111011110011100111001110011 step 11 100111111110011100111001110011 step 12 100111101110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 13 100110101110011100111001110011 fail ^ step 14 100110111110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 15 100110011110011100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 16 100110001110011100111001110011 fail ^^ step 17 100111001110011100111001110011 step 18 100111001110111100111001110011 step 19 100111001111111100111001110011 step 20 100111001111011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 21 100111001101011100111001110011 fail ^ step 22 100111001101111100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 23 100111001100111100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 24 100111001100011100111001110011 fail ^^ step 25 100111001110011100111001110011 step 26 100111001110011101111001110011 step 27 100111001110011111111001110011 step 28 100111001110011110111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 29 100111001110011010111001110011 fail ^ step 30 100111001110011011111001110011 step 31 100111001110011001011001110011 step 32 100111001110011000001001110011 step 33 100111001110011100111001110011 step 34 100111001110011100111011110011 step 35 100111001110011100111111110011 step 36 100111001110011100111101110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 37 100111001110011100110101110011 fail ^ step 38 100111001110011100110111110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 39 100111001110011100110011110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 0 step 40 100111001110011100110001010011 fail ^ step 41 100111001110011100111001110011 step 42 100111001110011100111001110111 step 43 100111001110011100111001111111 step 44 100111001110011100111001111011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 45 100111001110011100111001101011 fail ^ step 46 100111001110011100111001101111 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 47 100111001110011100111001100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 00 step 48 100111001110011100111001100001 fail ^ step 49 100111001110011100111001110011 test 48: *** FAIL *************************** 13 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail PP PP P PP PP all fails PP PP P PP PP was hi 111111111111111111111111111111 rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ falling vvvvvvvv vvv vvvvvvvv vvvvv was lo 00000000 000 00000000 00000 total fails 48, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100111001110011100111001110011 step 2 101111001110011100111001110011 step 3 111111001110011100111001110011 step 4 110111001110011100111001110011 step 5 010101001110011100111001110011 step 6 011111001110011100111001110011 step 7 001011001110011100111001110011 step 8 000001001110011100111001110011 step 9 100111001110011100111001110011 step 10 100111011110011100111001110011 step 11 100111111110011100111001110011 step 12 100111101110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 13 100110101110011100111001110011 fail ^ step 14 100110111110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 15 100110011110011100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 16 100110001110011100111001110011 fail ^^ step 17 100111001110011100111001110011 step 18 100111001110111100111001110011 step 19 100111001111111100111001110011 step 20 100111001111011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 21 100111001101011100111001110011 fail ^ step 22 100111001101111100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 23 100111001100111100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 24 100111001100011100111001110011 fail ^^ step 25 100111001110011100111001110011 step 26 100111001110011101111001110011 step 27 100111001110011111111001110011 step 28 100111001110011110111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 29 100111001110011010111001110011 fail ^ step 30 100111001110011011111001110011 step 31 100111001110011001011001110011 step 32 100111001110011000001001110011 step 33 100111001110011100111001110011 step 34 100111001110011100111011110011 step 35 100111001110011100111111110011 step 36 100111001110011100111101110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 37 100111001110011100110101110011 fail ^ step 38 100111001110011100110111110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 39 100111001110011100110011110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 0 step 40 100111001110011100110001010011 fail ^ step 41 100111001110011100111001110011 step 42 100111001110011100111001110111 step 43 100111001110011100111001111111 step 44 100111001110011100111001111011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 45 100111001110011100111001101011 fail ^ step 46 100111001110011100111001101111 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 47 100111001110011100111001100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 00 step 48 100111001110011100111001100001 fail ^ step 49 100111001110011100111001110011 test 49: *** FAIL *************************** 13 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail PP PP P PP PP all fails PP PP P PP PP was hi 111111111111111111111111111111 rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ falling vvvvvvvv vvv vvvvvvvv vvvvv was lo 00000000 000 00000000 00000 total fails 49, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100111001110011100111001110011 step 2 101111001110011100111001110011 step 3 111111001110011100111001110011 step 4 110111001110011100111001110011 step 5 010101001110011100111001110011 step 6 011111001110011100111001110011 step 7 001011001110011100111001110011 step 8 000001001110011100111001110011 step 9 100111001110011100111001110011 step 10 100111011110011100111001110011 step 11 100111111110011100111001110011 step 12 100111101110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 13 100110101110011100111001110011 fail ^ step 14 100110111110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 15 100110011110011100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 16 100110001110011100111001110011 fail ^^ step 17 100111001110011100111001110011 step 18 100111001110111100111001110011 step 19 100111001111111100111001110011 step 20 100111001111011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 21 100111001101011100111001110011 fail ^ step 22 100111001101111100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 23 100111001100111100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 24 100111001100011100111001110011 fail ^^ step 25 100111001110011100111001110011 step 26 100111001110011101111001110011 step 27 100111001110011111111001110011 step 28 100111001110011110111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 29 100111001110011010111001110011 fail ^ step 30 100111001110011011111001110011 step 31 100111001110011001011001110011 step 32 100111001110011000001001110011 step 33 100111001110011100111001110011 step 34 100111001110011100111011110011 step 35 100111001110011100111111110011 step 36 100111001110011100111101110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 37 100111001110011100110101110011 fail ^ step 38 100111001110011100110111110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 39 100111001110011100110011110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 0 step 40 100111001110011100110001010011 fail ^ step 41 100111001110011100111001110011 step 42 100111001110011100111001110111 step 43 100111001110011100111001111111 step 44 100111001110011100111001111011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 45 100111001110011100111001101011 fail ^ step 46 100111001110011100111001101111 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 47 100111001110011100111001100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 00 step 48 100111001110011100111001100001 fail ^ step 49 100111001110011100111001110011 test 50: *** FAIL *************************** 13 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail PP PP P PP PP all fails PP PP P PP PP was hi 111111111111111111111111111111 rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ falling vvvvvvvv vvv vvvvvvvv vvvvv was lo 00000000 000 00000000 00000 total fails 50, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100111001110011100111001110011 step 2 101111001110011100111001110011 step 3 111111001110011100111001110011 step 4 110111001110011100111001110011 step 5 010101001110011100111001110011 step 6 011111001110011100111001110011 step 7 001011001110011100111001110011 step 8 000001001110011100111001110011 step 9 100111001110011100111001110011 step 10 100111011110011100111001110011 step 11 100111111110011100111001110011 step 12 100111101110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 13 100110101110011100111001110011 fail ^ step 14 100110111110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 15 100110011110011100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 16 100110001110011100111001110011 fail ^^ step 17 100111001110011100111001110011 step 18 100111001110111100111001110011 step 19 100111001111111100111001110011 step 20 100111001111011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 21 100111001101011100111001110011 fail ^ step 22 100111001101111100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 23 100111001100111100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 24 100111001100011100111001110011 fail ^^ step 25 100111001110011100111001110011 step 26 100111001110011101111001110011 step 27 100111001110011111111001110011 step 28 100111001110011110111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 29 100111001110011010111001110011 fail ^ step 30 100111001110011011111001110011 step 31 100111001110011001011001110011 step 32 100111001110011000001001110011 step 33 100111001110011100111001110011 step 34 100111001110011100111011110011 step 35 100111001110011100111111110011 step 36 100111001110011100111101110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 37 100111001110011100110101110011 fail ^ step 38 100111001110011100110111110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 39 100111001110011100110011110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 0 step 40 100111001110011100110001010011 fail ^ step 41 100111001110011100111001110011 step 42 100111001110011100111001110111 step 43 100111001110011100111001111111 step 44 100111001110011100111001111011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 45 100111001110011100111001101011 fail ^ step 46 100111001110011100111001101111 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 47 100111001110011100111001100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 00 step 48 100111001110011100111001100001 fail ^ step 49 100111001110011100111001110011 test 51: *** FAIL *************************** 13 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail PP PP P PP PP all fails PP PP P PP PP was hi 111111111111111111111111111111 rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ falling vvvvvvvv vvv vvvvvvvv vvvvv was lo 00000000 000 00000000 00000 total fails 51, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails PP PP P PP PP was lo 00000000 000 00000000 00000 falling vvvvvvvv vvv vvvvvvvv vvvvv rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ was hi 111111111111111111111111111111 total fails 51, total passes 0 Main menu Fri Jun 30 16:50:54 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.tst could not open test file. valid test files are: reverting back to test file: tests\m623.new Main menu Fri Jun 30 16:50:59 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.new reading test file: tests\m623.new comment: M623 12 2-input OR bus buffer (open collector transistor outputs) comment: comment: WORKS, BUT NEEDS ALL INPUTS HI TESTS. comment: pins: PINS pins: 1 I AC1 E1-11,8 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 2 I AA1 E1-12 INPUT A pins: 3 I AB1 E1-9 INPUT B pins: 4 P AD1 E1-13,Q2 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 5 P AE1 E1-10,Q4 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: 6 I AJ1 E2-11,8 ENABLE C,D-N LOW TO ENABLE OUTPUT C AND D. pins: 7 I AF1 E2-12 INPUT C pins: 8 I AH1 E2-9 INPUT D pins: 9 P AK1 E2-13,Q6 OUTPUT C = INPUT C OR ENABLE C,D-N. pins: 10 P AL1 E2-10,Q8 OUTPUT D = INPUT D OR ENABLE C,D-N. pins: 11 I AP1 E3-11,8 ENABLE E,F-N LOW TO ENABLE OUTPUT E AND F. pins: 12 I AM1 E3-12 INPUT E pins: 13 I AN1 E3-9 INPUT F pins: 14 P AR1 E3-13,Q10 OUTPUT E = INPUT E OR ENABLE E,F-N. pins: 15 P AS1 E3-10,Q12 OUTPUT F = INPUT F OR ENABLE E,F-N. pins: 16 I AF2 E1-5,2 ENABLE H,J-N LOW TO ENABLE OUTPUT H AND J. pins: 17 I AD2 E1-6 INPUT H pins: 18 I AE2 E1-3 INPUT J pins: 19 P AH2 E1-4,Q1 OUTPUT H = INPUT H OR ENABLE H,J-N. pins: 20 P AJ2 E1-1,Q3 OUTPUT J = INPUT J OR ENABLE H,J-N. pins: 21 I AM2 E2-5,2 ENABLE K,L-N LOW TO ENABLE OUTPUT K AND L. pins: 22 I AK2 E2-6 INPUT K pins: 23 I AL2 E2-3 INPUT L pins: 24 P AN2 E2-4,Q5 OUTPUT K = INPUT K OR ENABLE K,L-N. pins: 25 P AP2 E2-1,Q7 OUTPUT L = INPUT L OR ENABLE K,L-N. pins: 26 I AT2 E3-5,2 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 27 I AR2 E3-6 INPUT A pins: 28 I AS2 E3-3 INPUT B pins: 29 P AU2 E3-4,Q9 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 30 P AV2 E3-1,Q11 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: direction: IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP test 1: 100111001110011100111001110011 test 2: 10111 test 3: 11111 test 4: 11011 test 5: 01010 test 6: 01111 test 7: 00101 test 8: 00000 test 9: 10011 test 10: 10111 test 11: 11111 test 12: 11011 test 13: 01010 test 14: 01111 test 15: 00101 test 16: 00000 test 17: 10011 test 18: 10111 test 19: 11111 test 20: 11011 test 21: 01010 test 22: 01111 test 23: 00101 test 24: 00000 test 25: 10011 test 26: 10111 test 27: 11111 test 28: 11011 test 29: 01010 test 30: 01111 test 31: 00101 test 32: 00000 test 33: 10011 test 34: 10111 test 35: 11111 test 36: 11011 test 37: 01010 test 38: 01111 test 39: 00101 test 40: 00000 test 41: 10011 test 42: 10111 test 43: 11111 test 44: 11011 test 45: 01010 test 46: 01111 test 47: 00101 test 48: 00000 test 49: 10011 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x8000 column 3: offset 0, mask 0x4000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0100 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0200 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x0800 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x1000 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0004 column 17: offset 0, mask 0x0010 column 18: offset 0, mask 0x0008 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0004 column 22: offset 1, mask 0x0001 column 23: offset 1, mask 0x0002 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0080 column 27: offset 1, mask 0x0020 column 28: offset 1, mask 0x0040 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x18E3 0xC718 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x1803 0xC618 0x0003 0x0000 0x0000 test step out_data dont care 1: 0x3907 0xCE9C 0x0003 0x0000 0x0000 2: 0x7907 0xCE9C 0x0003 0x0000 0x0000 3: 0xF907 0xCE9C 0x0003 0x0000 0x0000 4: 0xB907 0xCE9C 0x0003 0x0000 0x0000 5: 0x9107 0xCE9C 0x0003 0x0000 0x0000 6: 0xD907 0xCE9C 0x0003 0x0000 0x0000 7: 0x4907 0xCE9C 0x0003 0x0000 0x0000 8: 0x0107 0xCE9C 0x0003 0x0000 0x0000 9: 0x3907 0xCE9C 0x0003 0x0000 0x0000 10: 0x3B07 0xCE9C 0x0003 0x0000 0x0000 11: 0x3F07 0xCE9C 0x0003 0x0000 0x0000 12: 0x3D07 0xCE9C 0x0003 0x0000 0x0000 13: 0x3C07 0x8E9C 0x0003 0x0000 0x0000 14: 0x3E07 0xCE9C 0x0003 0x0000 0x0000 15: 0x3A07 0x4E9C 0x0003 0x0000 0x0000 16: 0x3807 0x0E9C 0x0003 0x0000 0x0000 17: 0x3907 0xCE9C 0x0003 0x0000 0x0000 18: 0x3907 0xDE9C 0x0003 0x0000 0x0000 19: 0x3907 0xFE9C 0x0003 0x0000 0x0000 20: 0x3907 0xEE9C 0x0003 0x0000 0x0000 21: 0x3907 0xE49C 0x0003 0x0000 0x0000 22: 0x3907 0xF69C 0x0003 0x0000 0x0000 23: 0x3907 0xD29C 0x0003 0x0000 0x0000 24: 0x3907 0xC09C 0x0003 0x0000 0x0000 25: 0x3907 0xCE9C 0x0003 0x0000 0x0000 26: 0x390F 0xCE9C 0x0003 0x0000 0x0000 27: 0x391F 0xCE9C 0x0003 0x0000 0x0000 28: 0x3917 0xCE9C 0x0003 0x0000 0x0000 29: 0x3912 0xCE9C 0x0003 0x0000 0x0000 30: 0x391B 0xCE9C 0x0003 0x0000 0x0000 31: 0x3909 0xCE9C 0x0003 0x0000 0x0000 32: 0x3900 0xCE9C 0x0003 0x0000 0x0000 33: 0x3907 0xCE9C 0x0003 0x0000 0x0000 34: 0x3907 0xCE9E 0x0003 0x0000 0x0000 35: 0x3907 0xCE9F 0x0003 0x0000 0x0000 36: 0x3907 0xCE9D 0x0003 0x0000 0x0000 37: 0x3907 0xCE89 0x0003 0x0000 0x0000 38: 0x3907 0xCE9B 0x0003 0x0000 0x0000 39: 0x3907 0xCE92 0x0003 0x0000 0x0000 40: 0x3907 0xCE80 0x0003 0x0000 0x0000 41: 0x3907 0xCE9C 0x0003 0x0000 0x0000 42: 0x3907 0xCEDC 0x0003 0x0000 0x0000 43: 0x3907 0xCEFC 0x0003 0x0000 0x0000 44: 0x3907 0xCEBC 0x0003 0x0000 0x0000 45: 0x3907 0xCE3C 0x0001 0x0000 0x0000 46: 0x3907 0xCE7C 0x0003 0x0000 0x0000 47: 0x3907 0xCE5C 0x0002 0x0000 0x0000 48: 0x3907 0xCE1C 0x0000 0x0000 0x0000 49: 0x3907 0xCE9C 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIPPIIIPPIIIPPG P GIIIPPIIIPPIIIPP G P G UUT inputs: 18 UUT outputs: 12 pins used: 30 not used: 36 49 'test steps' 87 lines M623 12 2-input OR bus buffer (open collector transistor outputs) WORKS, BUT NEEDS ALL INPUTS HI TESTS. PINS Main menu Fri Jun 30 16:51:08 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:51:29 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 9 100111001110011100111001110011 step 10 100111011110011100111001110011 step 11 100111111110011100111001110011 step 12 100111101110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 13 100110101110011100111001110011 fail ^ step 14 100110111110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 15 100110011110011100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 16 100110001110011100111001110011 fail ^^ step 17 100111001110011100111001110011 step 18 100111001110111100111001110011 step 19 100111001111111100111001110011 step 20 100111001111011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 21 100111001101011100111001110011 fail ^ step 22 100111001101111100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 23 100111001100111100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 24 100111001100011100111001110011 fail ^^ step 25 100111001110011100111001110011 step 26 100111001110011101111001110011 step 27 100111001110011111111001110011 step 28 100111001110011110111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 29 100111001110011010111001110011 fail ^ step 30 100111001110011011111001110011 step 31 100111001110011001011001110011 step 32 100111001110011000001001110011 step 33 100111001110011100111001110011 step 34 100111001110011100111011110011 step 35 100111001110011100111111110011 step 36 100111001110011100111101110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 37 100111001110011100110101110011 fail ^ step 38 100111001110011100110111110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 39 100111001110011100110011110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 0 step 40 100111001110011100110001010011 fail ^ step 41 100111001110011100111001110011 step 42 100111001110011100111001110111 step 43 100111001110011100111001111111 step 44 100111001110011100111001111011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 45 100111001110011100111001101011 fail ^ step 46 100111001110011100111001101111 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 47 100111001110011100111001100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 00 step 48 100111001110011100111001100001 fail ^ step 49 100111001110011100111001110011 test 47: *** FAIL *************************** 13 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail PP PP P PP PP all fails PP PP P PP PP was hi 111111111111111111111111111111 rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ falling vvvvvvvv vvv vvvvvvvv vvvvv was lo 00000000 000 00000000 00000 total fails 47, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100111001110011100111001110011 step 2 101111001110011100111001110011 step 3 111111001110011100111001110011 step 4 110111001110011100111001110011 step 5 010101001110011100111001110011 step 6 011111001110011100111001110011 step 7 001011001110011100111001110011 step 8 000001001110011100111001110011 step 9 100111001110011100111001110011 step 10 100111011110011100111001110011 step 11 100111111110011100111001110011 step 12 100111101110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 13 100110101110011100111001110011 fail ^ step 14 100110111110011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 15 100110011110011100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 16 100110001110011100111001110011 fail ^^ step 17 100111001110011100111001110011 step 18 100111001110111100111001110011 step 19 100111001111111100111001110011 step 20 100111001111011100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 21 100111001101011100111001110011 fail ^ step 22 100111001101111100111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 23 100111001100111100111001110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 24 100111001100011100111001110011 fail ^^ step 25 100111001110011100111001110011 step 26 100111001110011101111001110011 step 27 100111001110011111111001110011 step 28 100111001110011110111001110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 29 100111001110011010111001110011 fail ^ step 30 100111001110011011111001110011 step 31 100111001110011001011001110011 step 32 100111001110011000001001110011 step 33 100111001110011100111001110011 step 34 100111001110011100111011110011 step 35 100111001110011100111111110011 step 36 100111001110011100111101110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 37 100111001110011100110101110011 fail ^ step 38 100111001110011100110111110011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 39 100111001110011100110011110011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 0 step 40 100111001110011100110001010011 fail ^ step 41 100111001110011100111001110011 step 42 100111001110011100111001110111 step 43 100111001110011100111001111111 step 44 100111001110011100111001111011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 45 100111001110011100111001101011 fail ^ step 46 100111001110011100111001101111 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 0 step 47 100111001110011100111001100111 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP changed: 00 step 48 100111001110011100111001100001 fail ^ step 49 100111001110011100111001110011 test 48: *** FAIL *************************** 13 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail PP PP P PP PP all fails PP PP P PP PP was hi 111111111111111111111111111111 rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ falling vvvvvvvv vvv vvvvvvvv vvvvv was lo 00000000 000 00000000 00000 total fails 48, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails PP PP P PP PP was lo 00000000 000 00000000 00000 falling vvvvvvvv vvv vvvvvvvv vvvvv rising ^^^^^^^^ ^^^ ^^^^^^^^ ^^^^^ was hi 111111111111111111111111111111 total fails 48, total passes 0 Main menu Fri Jun 30 16:57:56 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m516.tst could not open test file. valid test files are: reverting back to test file: tests\m623.new Main menu Fri Jun 30 16:58:01 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.tst could not open test file. valid test files are: reverting back to test file: tests\m623.new Main menu Fri Jun 30 16:58:53 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.new reading test file: tests\m623.new comment: M623 12 2-input OR bus buffer (open collector transistor outputs) comment: comment: WORKS, BUT NEEDS ALL INPUTS HI TESTS. comment: pins: PINS pins: 1 I AC1 E1-11,8 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 2 I AA1 E1-12 INPUT A pins: 3 I AB1 E1-9 INPUT B pins: 4 P AD1 E1-13,Q2 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 5 P AE1 E1-10,Q4 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: 6 I AJ1 E2-11,8 ENABLE C,D-N LOW TO ENABLE OUTPUT C AND D. pins: 7 I AF1 E2-12 INPUT C pins: 8 I AH1 E2-9 INPUT D pins: 9 P AK1 E2-13,Q6 OUTPUT C = INPUT C OR ENABLE C,D-N. pins: 10 P AL1 E2-10,Q8 OUTPUT D = INPUT D OR ENABLE C,D-N. pins: 11 I AP1 E3-11,8 ENABLE E,F-N LOW TO ENABLE OUTPUT E AND F. pins: 12 I AM1 E3-12 INPUT E pins: 13 I AN1 E3-9 INPUT F pins: 14 P AR1 E3-13,Q10 OUTPUT E = INPUT E OR ENABLE E,F-N. pins: 15 P AS1 E3-10,Q12 OUTPUT F = INPUT F OR ENABLE E,F-N. pins: 16 I AF2 E1-5,2 ENABLE H,J-N LOW TO ENABLE OUTPUT H AND J. pins: 17 I AD2 E1-6 INPUT H pins: 18 I AE2 E1-3 INPUT J pins: 19 P AH2 E1-4,Q1 OUTPUT H = INPUT H OR ENABLE H,J-N. pins: 20 P AJ2 E1-1,Q3 OUTPUT J = INPUT J OR ENABLE H,J-N. pins: 21 I AM2 E2-5,2 ENABLE K,L-N LOW TO ENABLE OUTPUT K AND L. pins: 22 I AK2 E2-6 INPUT K pins: 23 I AL2 E2-3 INPUT L pins: 24 P AN2 E2-4,Q5 OUTPUT K = INPUT K OR ENABLE K,L-N. pins: 25 P AP2 E2-1,Q7 OUTPUT L = INPUT L OR ENABLE K,L-N. pins: 26 I AT2 E3-5,2 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 27 I AR2 E3-6 INPUT A pins: 28 I AS2 E3-3 INPUT B pins: 29 P AU2 E3-4,Q9 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 30 P AV2 E3-1,Q11 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: direction: IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP test 1: 100111001110011100111001110011 test 2: 10111 test 3: 11111 test 4: 11011 test 5: 01010 test 6: 01111 test 7: 00101 test 8: 00000 test 9: 10011 test 10: 10111 test 11: 11111 test 12: 11011 test 13: 01010 test 14: 01111 test 15: 00101 test 16: 00000 test 17: 10011 test 18: 10111 test 19: 11111 test 20: 11011 test 21: 01010 test 22: 01111 test 23: 00101 test 24: 00000 test 25: 10011 test 26: 10111 test 27: 11111 test 28: 11011 test 29: 01010 test 30: 01111 test 31: 00101 test 32: 00000 test 33: 10011 test 34: 10111 test 35: 11111 test 36: 11011 test 37: 01010 test 38: 01111 test 39: 00101 test 40: 00000 test 41: 10011 test 42: 10111 test 43: 11111 test 44: 11011 test 45: 01010 test 46: 01111 test 47: 00101 test 48: 00000 test 49: 10011 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x8000 column 3: offset 0, mask 0x4000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0100 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0200 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x0800 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x1000 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0004 column 17: offset 0, mask 0x0010 column 18: offset 0, mask 0x0008 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0004 column 22: offset 1, mask 0x0001 column 23: offset 1, mask 0x0002 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0080 column 27: offset 1, mask 0x0020 column 28: offset 1, mask 0x0040 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x18E3 0xC718 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x1803 0xC618 0x0003 0x0000 0x0000 test step out_data dont care 1: 0x3907 0xCE9C 0x0003 0x0000 0x0000 2: 0x7907 0xCE9C 0x0003 0x0000 0x0000 3: 0xF907 0xCE9C 0x0003 0x0000 0x0000 4: 0xB907 0xCE9C 0x0003 0x0000 0x0000 5: 0x9107 0xCE9C 0x0003 0x0000 0x0000 6: 0xD907 0xCE9C 0x0003 0x0000 0x0000 7: 0x4907 0xCE9C 0x0003 0x0000 0x0000 8: 0x0107 0xCE9C 0x0003 0x0000 0x0000 9: 0x3907 0xCE9C 0x0003 0x0000 0x0000 10: 0x3B07 0xCE9C 0x0003 0x0000 0x0000 11: 0x3F07 0xCE9C 0x0003 0x0000 0x0000 12: 0x3D07 0xCE9C 0x0003 0x0000 0x0000 13: 0x3C07 0x8E9C 0x0003 0x0000 0x0000 14: 0x3E07 0xCE9C 0x0003 0x0000 0x0000 15: 0x3A07 0x4E9C 0x0003 0x0000 0x0000 16: 0x3807 0x0E9C 0x0003 0x0000 0x0000 17: 0x3907 0xCE9C 0x0003 0x0000 0x0000 18: 0x3907 0xDE9C 0x0003 0x0000 0x0000 19: 0x3907 0xFE9C 0x0003 0x0000 0x0000 20: 0x3907 0xEE9C 0x0003 0x0000 0x0000 21: 0x3907 0xE49C 0x0003 0x0000 0x0000 22: 0x3907 0xF69C 0x0003 0x0000 0x0000 23: 0x3907 0xD29C 0x0003 0x0000 0x0000 24: 0x3907 0xC09C 0x0003 0x0000 0x0000 25: 0x3907 0xCE9C 0x0003 0x0000 0x0000 26: 0x390F 0xCE9C 0x0003 0x0000 0x0000 27: 0x391F 0xCE9C 0x0003 0x0000 0x0000 28: 0x3917 0xCE9C 0x0003 0x0000 0x0000 29: 0x3912 0xCE9C 0x0003 0x0000 0x0000 30: 0x391B 0xCE9C 0x0003 0x0000 0x0000 31: 0x3909 0xCE9C 0x0003 0x0000 0x0000 32: 0x3900 0xCE9C 0x0003 0x0000 0x0000 33: 0x3907 0xCE9C 0x0003 0x0000 0x0000 34: 0x3907 0xCE9E 0x0003 0x0000 0x0000 35: 0x3907 0xCE9F 0x0003 0x0000 0x0000 36: 0x3907 0xCE9D 0x0003 0x0000 0x0000 37: 0x3907 0xCE89 0x0003 0x0000 0x0000 38: 0x3907 0xCE9B 0x0003 0x0000 0x0000 39: 0x3907 0xCE92 0x0003 0x0000 0x0000 40: 0x3907 0xCE80 0x0003 0x0000 0x0000 41: 0x3907 0xCE9C 0x0003 0x0000 0x0000 42: 0x3907 0xCEDC 0x0003 0x0000 0x0000 43: 0x3907 0xCEFC 0x0003 0x0000 0x0000 44: 0x3907 0xCEBC 0x0003 0x0000 0x0000 45: 0x3907 0xCE3C 0x0001 0x0000 0x0000 46: 0x3907 0xCE7C 0x0003 0x0000 0x0000 47: 0x3907 0xCE5C 0x0002 0x0000 0x0000 48: 0x3907 0xCE1C 0x0000 0x0000 0x0000 49: 0x3907 0xCE9C 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIPPIIIPPIIIPPG P GIIIPPIIIPPIIIPP G P G UUT inputs: 18 UUT outputs: 12 pins used: 30 not used: 36 49 'test steps' 87 lines M623 12 2-input OR bus buffer (open collector transistor outputs) WORKS, BUT NEEDS ALL INPUTS HI TESTS. PINS Main menu Fri Jun 30 16:58:59 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:59:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 49 Main menu Fri Jun 30 16:59:03 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.new reading test file: tests\m623.new comment: M623 12 2-input OR bus buffer (open collector transistor outputs) comment: comment: WORKS, BUT NEEDS ALL INPUTS HI TESTS. comment: pins: PINS pins: 1 I AC1 E1-11,8 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 2 I AA1 E1-12 INPUT A pins: 3 I AB1 E1-9 INPUT B pins: 4 P AD1 E1-13,Q2 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 5 P AE1 E1-10,Q4 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: 6 I AJ1 E2-11,8 ENABLE C,D-N LOW TO ENABLE OUTPUT C AND D. pins: 7 I AF1 E2-12 INPUT C pins: 8 I AH1 E2-9 INPUT D pins: 9 P AK1 E2-13,Q6 OUTPUT C = INPUT C OR ENABLE C,D-N. pins: 10 P AL1 E2-10,Q8 OUTPUT D = INPUT D OR ENABLE C,D-N. pins: 11 I AP1 E3-11,8 ENABLE E,F-N LOW TO ENABLE OUTPUT E AND F. pins: 12 I AM1 E3-12 INPUT E pins: 13 I AN1 E3-9 INPUT F pins: 14 P AR1 E3-13,Q10 OUTPUT E = INPUT E OR ENABLE E,F-N. pins: 15 P AS1 E3-10,Q12 OUTPUT F = INPUT F OR ENABLE E,F-N. pins: 16 I AF2 E1-5,2 ENABLE H,J-N LOW TO ENABLE OUTPUT H AND J. pins: 17 I AD2 E1-6 INPUT H pins: 18 I AE2 E1-3 INPUT J pins: 19 P AH2 E1-4,Q1 OUTPUT H = INPUT H OR ENABLE H,J-N. pins: 20 P AJ2 E1-1,Q3 OUTPUT J = INPUT J OR ENABLE H,J-N. pins: 21 I AM2 E2-5,2 ENABLE K,L-N LOW TO ENABLE OUTPUT K AND L. pins: 22 I AK2 E2-6 INPUT K pins: 23 I AL2 E2-3 INPUT L pins: 24 P AN2 E2-4,Q5 OUTPUT K = INPUT K OR ENABLE K,L-N. pins: 25 P AP2 E2-1,Q7 OUTPUT L = INPUT L OR ENABLE K,L-N. pins: 26 I AT2 E3-5,2 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 27 I AR2 E3-6 INPUT A pins: 28 I AS2 E3-3 INPUT B pins: 29 P AU2 E3-4,Q9 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 30 P AV2 E3-1,Q11 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: direction: IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP test 1: 100111001110011100111001110011 test 2: 10111 test 3: 11111 test 4: 11011 test 5: 01010 test 6: 01111 test 7: 00101 test 8: 00000 test 9: 10011 test 10: 10111 test 11: 11111 test 12: 11011 test 13: 01010 test 14: 01111 test 15: 00101 test 16: 00000 test 17: 10011 test 18: 10111 test 19: 11111 test 20: 11011 test 21: 01010 test 22: 01111 test 23: 00101 test 24: 00000 test 25: 10011 test 26: 10111 test 27: 11111 test 28: 11011 test 29: 01010 test 30: 01111 test 31: 00101 test 32: 00000 test 33: 10011 test 34: 10111 test 35: 11111 test 36: 11011 test 37: 01010 test 38: 01111 test 39: 00101 test 40: 00000 test 41: 10011 test 42: 10111 test 43: 11111 test 44: 11011 test 45: 01010 test 46: 01111 test 47: 00101 test 48: 00000 test 49: 10011 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x8000 column 3: offset 0, mask 0x4000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0100 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0200 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x0800 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x1000 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0004 column 17: offset 0, mask 0x0010 column 18: offset 0, mask 0x0008 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0004 column 22: offset 1, mask 0x0001 column 23: offset 1, mask 0x0002 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0080 column 27: offset 1, mask 0x0020 column 28: offset 1, mask 0x0040 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x18E3 0xC718 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x1803 0xC618 0x0003 0x0000 0x0000 test step out_data dont care 1: 0x3907 0xCE9C 0x0003 0x0000 0x0000 2: 0x7907 0xCE9C 0x0003 0x0000 0x0000 3: 0xF907 0xCE9C 0x0003 0x0000 0x0000 4: 0xB907 0xCE9C 0x0003 0x0000 0x0000 5: 0x9107 0xCE9C 0x0003 0x0000 0x0000 6: 0xD907 0xCE9C 0x0003 0x0000 0x0000 7: 0x4907 0xCE9C 0x0003 0x0000 0x0000 8: 0x0107 0xCE9C 0x0003 0x0000 0x0000 9: 0x3907 0xCE9C 0x0003 0x0000 0x0000 10: 0x3B07 0xCE9C 0x0003 0x0000 0x0000 11: 0x3F07 0xCE9C 0x0003 0x0000 0x0000 12: 0x3D07 0xCE9C 0x0003 0x0000 0x0000 13: 0x3C07 0x8E9C 0x0003 0x0000 0x0000 14: 0x3E07 0xCE9C 0x0003 0x0000 0x0000 15: 0x3A07 0x4E9C 0x0003 0x0000 0x0000 16: 0x3807 0x0E9C 0x0003 0x0000 0x0000 17: 0x3907 0xCE9C 0x0003 0x0000 0x0000 18: 0x3907 0xDE9C 0x0003 0x0000 0x0000 19: 0x3907 0xFE9C 0x0003 0x0000 0x0000 20: 0x3907 0xEE9C 0x0003 0x0000 0x0000 21: 0x3907 0xE49C 0x0003 0x0000 0x0000 22: 0x3907 0xF69C 0x0003 0x0000 0x0000 23: 0x3907 0xD29C 0x0003 0x0000 0x0000 24: 0x3907 0xC09C 0x0003 0x0000 0x0000 25: 0x3907 0xCE9C 0x0003 0x0000 0x0000 26: 0x390F 0xCE9C 0x0003 0x0000 0x0000 27: 0x391F 0xCE9C 0x0003 0x0000 0x0000 28: 0x3917 0xCE9C 0x0003 0x0000 0x0000 29: 0x3912 0xCE9C 0x0003 0x0000 0x0000 30: 0x391B 0xCE9C 0x0003 0x0000 0x0000 31: 0x3909 0xCE9C 0x0003 0x0000 0x0000 32: 0x3900 0xCE9C 0x0003 0x0000 0x0000 33: 0x3907 0xCE9C 0x0003 0x0000 0x0000 34: 0x3907 0xCE9E 0x0003 0x0000 0x0000 35: 0x3907 0xCE9F 0x0003 0x0000 0x0000 36: 0x3907 0xCE9D 0x0003 0x0000 0x0000 37: 0x3907 0xCE89 0x0003 0x0000 0x0000 38: 0x3907 0xCE9B 0x0003 0x0000 0x0000 39: 0x3907 0xCE92 0x0003 0x0000 0x0000 40: 0x3907 0xCE80 0x0003 0x0000 0x0000 41: 0x3907 0xCE9C 0x0003 0x0000 0x0000 42: 0x3907 0xCEDC 0x0003 0x0000 0x0000 43: 0x3907 0xCEFC 0x0003 0x0000 0x0000 44: 0x3907 0xCEBC 0x0003 0x0000 0x0000 45: 0x3907 0xCE3C 0x0001 0x0000 0x0000 46: 0x3907 0xCE7C 0x0003 0x0000 0x0000 47: 0x3907 0xCE5C 0x0002 0x0000 0x0000 48: 0x3907 0xCE1C 0x0000 0x0000 0x0000 49: 0x3907 0xCE9C 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIPPIIIPPIIIPPG P GIIIPPIIIPPIIIPP G P G UUT inputs: 18 UUT outputs: 12 pins used: 30 not used: 36 49 'test steps' 87 lines M623 12 2-input OR bus buffer (open collector transistor outputs) WORKS, BUT NEEDS ALL INPUTS HI TESTS. PINS Main menu Fri Jun 30 16:59:20 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:59:25 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 97 Main menu Fri Jun 30 16:59:29 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 16:59:54 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 16:59:55 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 17 Main menu Fri Jun 30 16:59:57 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:00:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 21 Main menu Fri Jun 30 17:00:16 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 17:00:31 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:00:33 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 30 Main menu Fri Jun 30 17:00:37 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 17:00:53 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:00:53 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 13, total passes 0 Main menu Fri Jun 30 17:01:19 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Fri Jun 30 17:01:20 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 17:01:25 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:01:25 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 step 109 001111111011110111101111011110 step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 step 113 011111111011110111101111011110 step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 step 117 101111111011110111101111011110 step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 12: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 12, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 step 5 001110000100001000010000100001 step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 step 9 011110000100001000010000100001 step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 step 13 101110000100001000010000100001 step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 step 109 001111111011110111101111011110 step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 step 113 011111111011110111101111011110 step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 step 117 101111111011110111101111011110 step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 13: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 13, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000010000100001000010000100001 step 2 000010000100001000010000100001 step 3 000110000100001000010000100001 step 4 001010000100001000010000100001 step 5 001110000100001000010000100001 step 6 010010000100001000010000100001 step 7 010110000100001000010000100001 step 8 011010000100001000010000100001 step 9 011110000100001000010000100001 step 10 100010000100001000010000100001 step 11 100110000100001000010000100001 step 12 101010000100001000010000100001 step 13 101110000100001000010000100001 step 14 110010000100001000010000100001 step 15 110110000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 16 111000000100001000010000100001 fail ^ step 17 111100000100001000010000100001 step 18 000010000100001000010000100001 step 19 000010000100001000010000100001 step 20 000010001100001000010000100001 step 21 000010010100001000010000100001 step 22 000010011100001000010000100001 step 23 000010100100001000010000100001 step 24 000010101100001000010000100001 step 25 000010110100001000010000100001 step 26 000010111100001000010000100001 step 27 000011000100001000010000100001 step 28 000011001100001000010000100001 step 29 000011010100001000010000100001 step 30 000011011100001000010000100001 step 31 000011100100001000010000100001 step 32 000011101100001000010000100001 step 33 000011110100001000010000100001 step 34 000011111000001000010000100001 step 35 000010000100001000010000100001 step 36 000010000100001000010000100001 step 37 000010000100011000010000100001 step 38 000010000100101000010000100001 step 39 000010000100111000010000100001 step 40 000010000101001000010000100001 step 41 000010000101011000010000100001 step 42 000010000101101000010000100001 step 43 000010000101111000010000100001 step 44 000010000110001000010000100001 step 45 000010000110011000010000100001 step 46 000010000110101000010000100001 step 47 000010000110111000010000100001 step 48 000010000111001000010000100001 step 49 000010000111011000010000100001 step 50 000010000111101000010000100001 step 51 000010000111110000010000100001 step 52 000010000100001000010000100001 step 53 000010000100001000010000100001 step 54 000010000100001000110000100001 step 55 000010000100001001010000100001 step 56 000010000100001001110000100001 step 57 000010000100001010010000100001 step 58 000010000100001010110000100001 step 59 000010000100001011010000100001 step 60 000010000100001011110000100001 step 61 000010000100001100010000100001 step 62 000010000100001100110000100001 step 63 000010000100001101010000100001 step 64 000010000100001101110000100001 step 65 000010000100001110010000100001 step 66 000010000100001110110000100001 step 67 000010000100001111010000100001 step 68 000010000100001111100000100001 step 69 000010000100001000010000100001 step 70 000010000100001000010000100001 step 71 000010000100001000010001100001 step 72 000010000100001000010010100001 step 73 000010000100001000010011100001 step 74 000010000100001000010100100001 step 75 000010000100001000010101100001 step 76 000010000100001000010110100001 step 77 000010000100001000010111100001 step 78 000010000100001000011000100001 step 79 000010000100001000011001100001 step 80 000010000100001000011010100001 step 81 000010000100001000011011100001 step 82 000010000100001000011100100001 step 83 000010000100001000011101100001 step 84 000010000100001000011110100001 step 85 000010000100001000011111000001 step 86 000010000100001000010000100001 step 87 000010000100001000010000100001 step 88 000010000100001000010000100011 step 89 000010000100001000010000100101 step 90 000010000100001000010000100111 step 91 000010000100001000010000101001 step 92 000010000100001000010000101011 step 93 000010000100001000010000101101 step 94 000010000100001000010000101111 step 95 000010000100001000010000110001 step 96 000010000100001000010000110011 step 97 000010000100001000010000110101 step 98 000010000100001000010000110111 step 99 000010000100001000010000111001 step 100 000010000100001000010000111011 step 101 000010000100001000010000111101 step 102 000010000100001000010000111110 step 103 000010000100001000010000100001 step 104 000010000100001000010000100001 step 105 111101111011110111101111011110 step 106 000011111011110111101111011110 step 107 000111111011110111101111011110 step 108 001011111011110111101111011110 step 109 001111111011110111101111011110 step 110 010011111011110111101111011110 step 111 010111111011110111101111011110 step 112 011011111011110111101111011110 step 113 011111111011110111101111011110 step 114 100011111011110111101111011110 step 115 100111111011110111101111011110 step 116 101011111011110111101111011110 step 117 101111111011110111101111011110 step 118 110011111011110111101111011110 step 119 110111111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO changed: 100 step 120 111001111011110111101111011110 fail ^ step 121 111101111011110111101111011110 step 122 111100000111110111101111011110 step 123 111100001111110111101111011110 step 124 111100010111110111101111011110 step 125 111100011111110111101111011110 step 126 111100100111110111101111011110 step 127 111100101111110111101111011110 step 128 111100110111110111101111011110 step 129 111100111111110111101111011110 step 130 111101000111110111101111011110 step 131 111101001111110111101111011110 step 132 111101010111110111101111011110 step 133 111101011111110111101111011110 step 134 111101100111110111101111011110 step 135 111101101111110111101111011110 step 136 111101110111110111101111011110 step 137 111101111011110111101111011110 step 138 111101111000001111101111011110 step 139 111101111000011111101111011110 step 140 111101111000101111101111011110 step 141 111101111000111111101111011110 step 142 111101111001001111101111011110 step 143 111101111001011111101111011110 step 144 111101111001101111101111011110 step 145 111101111001111111101111011110 step 146 111101111010001111101111011110 step 147 111101111010011111101111011110 step 148 111101111010101111101111011110 step 149 111101111010111111101111011110 step 150 111101111011001111101111011110 step 151 111101111011011111101111011110 step 152 111101111011101111101111011110 step 153 111101111011110111101111011110 step 154 111101111011110000011111011110 step 155 111101111011110000111111011110 step 156 111101111011110001011111011110 step 157 111101111011110001111111011110 step 158 111101111011110010011111011110 step 159 111101111011110010111111011110 step 160 111101111011110011011111011110 step 161 111101111011110011111111011110 step 162 111101111011110100011111011110 step 163 111101111011110100111111011110 step 164 111101111011110101011111011110 step 165 111101111011110101111111011110 step 166 111101111011110110011111011110 step 167 111101111011110110111111011110 step 168 111101111011110111011111011110 step 169 111101111011110111101111011110 step 170 111101111011110111100000111110 step 171 111101111011110111100001111110 step 172 111101111011110111100010111110 step 173 111101111011110111100011111110 step 174 111101111011110111100100111110 step 175 111101111011110111100101111110 step 176 111101111011110111100110111110 step 177 111101111011110111100111111110 step 178 111101111011110111101000111110 step 179 111101111011110111101001111110 step 180 111101111011110111101010111110 step 181 111101111011110111101011111110 step 182 111101111011110111101100111110 step 183 111101111011110111101101111110 step 184 111101111011110111101110111110 step 185 111101111011110111101111011110 step 186 111101111011110111101111000001 step 187 111101111011110111101111000011 step 188 111101111011110111101111000101 step 189 111101111011110111101111000111 step 190 111101111011110111101111001001 step 191 111101111011110111101111001011 step 192 111101111011110111101111001101 step 193 111101111011110111101111001111 step 194 111101111011110111101111010001 step 195 111101111011110111101111010011 step 196 111101111011110111101111010101 step 197 111101111011110111101111010111 step 198 111101111011110111101111011001 step 199 111101111011110111101111011011 step 200 111101111011110111101111011101 step 201 111101111011110111101111011110 step 202 111101111011110111101111011110 test 14: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 14, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit pin 1: offset is 0; mask is 0x8000 pin 2: offset is 0; mask is 0x4000 pin 3: offset is 0; mask is 0x2000 pin 4: offset is 0; mask is 0x1000 pin 5: offset is 0; mask is 0x0800 pin 6: offset is 0; mask is 0x0400 pin 7: offset is 0; mask is 0x0200 pin 8: offset is 0; mask is 0x0100 pin 9: offset is 1; mask is 0x8000 pin 10: offset is 1; mask is 0x4000 pin 11: offset is 1; mask is 0x2000 pin 12: offset is 1; mask is 0x1000 pin 13: offset is 1; mask is 0x0800 pin 14: offset is 1; mask is 0x0400 pin 15: offset is 1; mask is 0x0200 pin 16: offset is 0; mask is 0x0010 pin 17: offset is 0; mask is 0x0008 pin 18: offset is 0; mask is 0x0004 pin 19: offset is 0; mask is 0x0002 pin 20: offset is 0; mask is 0x0001 pin 21: offset is 1; mask is 0x0001 pin 22: offset is 1; mask is 0x0002 pin 23: offset is 1; mask is 0x0004 pin 24: offset is 1; mask is 0x0008 pin 25: offset is 1; mask is 0x0010 pin 26: offset is 1; mask is 0x0020 pin 27: offset is 1; mask is 0x0040 pin 28: offset is 1; mask is 0x0080 pin 29: offset is 2; mask is 0x0001 pin 30: offset is 2; mask is 0x0002 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 14, total passes 0 Main menu Fri Jun 30 17:02:13 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Fri Jun 30 17:02:17 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:02:18 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 32 Main menu Fri Jun 30 17:02:22 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 17:02:55 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:02:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 72 Main menu Fri Jun 30 17:03:00 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m121.tst reading test file: tests\m121.tst comment: ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s comment: ; comment: ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) comment: pins: PINS pins: 1 I AA1 E1-1 A1A 1-X pins: 2 I AB1 E1-13 A1B 1-X pins: 3 I AC1 E1-10 A2A X-1 pins: 4 I AD1 E1-9 A2B X-1 pins: 5 O AE1 E1-8 OUTPUT A pins: 6 I AD2 E1-5 B1A 1-X pins: 7 I AE2 E1-4 B1B 1-X pins: 8 I AF2 E1-3 B2A X-1 pins: 9 I AH2 E1-2 B2B X-1 pins: 10 O AJ2 E1-6 OUTPUT B pins: 11 I AF1 E2-1 C1A 1-X pins: 12 I AH1 E2-13 C1B 1-X pins: 13 I AJ1 E2-10 C2A X-1 pins: 14 I AK1 E2-9 C2B X-1 pins: 15 O AL1 E2-8 OUTPUT C pins: 16 I AK2 E2-5 D1A 1-X pins: 17 I AL2 E2-4 D1B 1-X pins: 18 I AM2 E2-3 D2A X-1 pins: 19 I AN2 E2-2 D2B X-1 pins: 20 O AP2 E2-6 OUTPUT D pins: 21 I AM1 E3-1 E1A 1-X pins: 22 I AN1 E3-13 E1B 1-X pins: 23 I AP1 E3-10 E2A X-1 pins: 24 I AR1 E3-9 E2B X-1 pins: 25 O AS1 E3-8 OUTPUT E pins: 26 I AR2 E3-5 F1A 1-X pins: 27 I AS2 E3-4 F1B 1-X pins: 28 I AT2 E3-3 F2A X-1 pins: 29 I AU2 E3-2 F2B X-1 pins: 30 O AV2 E3-6 OUTPUT F pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00011 test 3: 00110 test 4: 00101 test 5: 01101 test 6: 01110 test 7: 01011 test 8: 01001 test 9: 11000 test 10: 11010 test 11: 11110 test 12: 11100 test 13: 10101 test 14: 10110 test 15: 10011 test 16: 10001 test 17: 00001 test 18: 00011 test 19: 00110 test 20: 00101 test 21: 01101 test 22: 01110 test 23: 01011 test 24: 01001 test 25: 11000 test 26: 11010 test 27: 11110 test 28: 11100 test 29: 10101 test 30: 10110 test 31: 10011 test 32: 10001 test 33: 00001 test 34: 00011 test 35: 00110 test 36: 00101 test 37: 01101 test 38: 01110 test 39: 01011 test 40: 01001 test 41: 11000 test 42: 11010 test 43: 11110 test 44: 11100 test 45: 10101 test 46: 10110 test 47: 10011 test 48: 10001 test 49: 00001 test 50: 00011 test 51: 00110 test 52: 00101 test 53: 01101 test 54: 01110 test 55: 01011 test 56: 01001 test 57: 11000 test 58: 11010 test 59: 11110 test 60: 11100 test 61: 10101 test 62: 10110 test 63: 10011 test 64: 10001 test 65: 00001 test 66: 00011 test 67: 00110 test 68: 00101 test 69: 01101 test 70: 01110 test 71: 01011 test 72: 01001 test 73: 11000 test 74: 11010 test 75: 11110 test 76: 11100 test 77: 10101 test 78: 10110 test 79: 10011 test 80: 10001 test 81: 00001 test 82: 00011 test 83: 00110 test 84: 00101 test 85: 01101 test 86: 01110 test 87: 01011 test 88: 01001 test 89: 11000 test 90: 11010 test 91: 11110 test 92: 11100 test 93: 10101 test 94: 10110 test 95: 10011 test 96: 10001 test 97: 00001 test 98: 000010000100001000010000100001 test 99: 111101111011110111101111011110 test 100: 11100 test 101: 10101 test 102: 10110 test 103: 10011 test 104: 10001 test 105: 00001 test 106: 00011 test 107: 00110 test 108: 00101 test 109: 01101 test 110: 01110 test 111: 01011 test 112: 01001 test 113: 11000 test 114: 11010 test 115: 11110 test 116: 11100 test 117: 10101 test 118: 10110 test 119: 10011 test 120: 10001 test 121: 00001 test 122: 00011 test 123: 00110 test 124: 00101 test 125: 01101 test 126: 01110 test 127: 01011 test 128: 01001 test 129: 11000 test 130: 11010 test 131: 11110 test 132: 11100 test 133: 10101 test 134: 10110 test 135: 10011 test 136: 10001 test 137: 00001 test 138: 00011 test 139: 00110 test 140: 00101 test 141: 01101 test 142: 01110 test 143: 01011 test 144: 01001 test 145: 11000 test 146: 11010 test 147: 11110 test 148: 11100 test 149: 10101 test 150: 10110 test 151: 10011 test 152: 10001 test 153: 00001 test 154: 00011 test 155: 00110 test 156: 00101 test 157: 01101 test 158: 01110 test 159: 01011 test 160: 01001 test 161: 11000 test 162: 11010 test 163: 11110 test 164: 11100 test 165: 10101 test 166: 10110 test 167: 10011 test 168: 10001 test 169: 00001 test 170: 00011 test 171: 00110 test 172: 00101 test 173: 01101 test 174: 01110 test 175: 01011 test 176: 01001 test 177: 11000 test 178: 11010 test 179: 11110 test 180: 11100 test 181: 10101 test 182: 10110 test 183: 10011 test 184: 10001 test 185: 00001 test 186: 00011 test 187: 00110 test 188: 00101 test 189: 01101 test 190: 01110 test 191: 01011 test 192: 01001 test 193: 11000 test 194: 11010 test 195: 11110 test 196: 111101111011110111101111011110 test 197: 000010000100001000010000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0010 column 7: offset 0, mask 0x0008 column 8: offset 0, mask 0x0004 column 9: offset 0, mask 0x0002 column 10: offset 0, mask 0x0001 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x0001 column 17: offset 1, mask 0x0002 column 18: offset 1, mask 0x0004 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0010 column 21: offset 1, mask 0x2000 column 22: offset 1, mask 0x1000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0400 column 25: offset 1, mask 0x0200 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x1801 0x4210 0x0002 0x0000 0x0000 3: 0x3001 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x6801 0x4210 0x0002 0x0000 0x0000 6: 0x7001 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x4801 0x4210 0x0002 0x0000 0x0000 9: 0xC001 0x4210 0x0002 0x0000 0x0000 10: 0xD001 0x4210 0x0002 0x0000 0x0000 11: 0xF001 0x4210 0x0002 0x0000 0x0000 12: 0xE001 0x4210 0x0002 0x0000 0x0000 13: 0xA801 0x4210 0x0002 0x0000 0x0000 14: 0xB001 0x4210 0x0002 0x0000 0x0000 15: 0x9801 0x4210 0x0002 0x0000 0x0000 16: 0x8801 0x4210 0x0002 0x0000 0x0000 17: 0x0801 0x4210 0x0002 0x0000 0x0000 18: 0x0803 0x4210 0x0002 0x0000 0x0000 19: 0x0806 0x4210 0x0002 0x0000 0x0000 20: 0x0805 0x4210 0x0002 0x0000 0x0000 21: 0x080D 0x4210 0x0002 0x0000 0x0000 22: 0x080E 0x4210 0x0002 0x0000 0x0000 23: 0x080B 0x4210 0x0002 0x0000 0x0000 24: 0x0809 0x4210 0x0002 0x0000 0x0000 25: 0x0818 0x4210 0x0002 0x0000 0x0000 26: 0x081A 0x4210 0x0002 0x0000 0x0000 27: 0x081E 0x4210 0x0002 0x0000 0x0000 28: 0x081C 0x4210 0x0002 0x0000 0x0000 29: 0x0815 0x4210 0x0002 0x0000 0x0000 30: 0x0816 0x4210 0x0002 0x0000 0x0000 31: 0x0813 0x4210 0x0002 0x0000 0x0000 32: 0x0811 0x4210 0x0002 0x0000 0x0000 33: 0x0801 0x4210 0x0002 0x0000 0x0000 34: 0x0801 0xC210 0x0002 0x0000 0x0000 35: 0x0901 0x8210 0x0002 0x0000 0x0000 36: 0x0901 0x4210 0x0002 0x0000 0x0000 37: 0x0B01 0x4210 0x0002 0x0000 0x0000 38: 0x0B01 0x8210 0x0002 0x0000 0x0000 39: 0x0A01 0xC210 0x0002 0x0000 0x0000 40: 0x0A01 0x4210 0x0002 0x0000 0x0000 41: 0x0E01 0x0210 0x0002 0x0000 0x0000 42: 0x0E01 0x8210 0x0002 0x0000 0x0000 43: 0x0F01 0x8210 0x0002 0x0000 0x0000 44: 0x0F01 0x0210 0x0002 0x0000 0x0000 45: 0x0D01 0x4210 0x0002 0x0000 0x0000 46: 0x0D01 0x8210 0x0002 0x0000 0x0000 47: 0x0C01 0xC210 0x0002 0x0000 0x0000 48: 0x0C01 0x4210 0x0002 0x0000 0x0000 49: 0x0801 0x4210 0x0002 0x0000 0x0000 50: 0x0801 0x4218 0x0002 0x0000 0x0000 51: 0x0801 0x420C 0x0002 0x0000 0x0000 52: 0x0801 0x4214 0x0002 0x0000 0x0000 53: 0x0801 0x4216 0x0002 0x0000 0x0000 54: 0x0801 0x420E 0x0002 0x0000 0x0000 55: 0x0801 0x421A 0x0002 0x0000 0x0000 56: 0x0801 0x4212 0x0002 0x0000 0x0000 57: 0x0801 0x4203 0x0002 0x0000 0x0000 58: 0x0801 0x420B 0x0002 0x0000 0x0000 59: 0x0801 0x420F 0x0002 0x0000 0x0000 60: 0x0801 0x4207 0x0002 0x0000 0x0000 61: 0x0801 0x4215 0x0002 0x0000 0x0000 62: 0x0801 0x420D 0x0002 0x0000 0x0000 63: 0x0801 0x4219 0x0002 0x0000 0x0000 64: 0x0801 0x4211 0x0002 0x0000 0x0000 65: 0x0801 0x4210 0x0002 0x0000 0x0000 66: 0x0801 0x4610 0x0002 0x0000 0x0000 67: 0x0801 0x4C10 0x0002 0x0000 0x0000 68: 0x0801 0x4A10 0x0002 0x0000 0x0000 69: 0x0801 0x5A10 0x0002 0x0000 0x0000 70: 0x0801 0x5C10 0x0002 0x0000 0x0000 71: 0x0801 0x5610 0x0002 0x0000 0x0000 72: 0x0801 0x5210 0x0002 0x0000 0x0000 73: 0x0801 0x7010 0x0002 0x0000 0x0000 74: 0x0801 0x7410 0x0002 0x0000 0x0000 75: 0x0801 0x7C10 0x0002 0x0000 0x0000 76: 0x0801 0x7810 0x0002 0x0000 0x0000 77: 0x0801 0x6A10 0x0002 0x0000 0x0000 78: 0x0801 0x6C10 0x0002 0x0000 0x0000 79: 0x0801 0x6610 0x0002 0x0000 0x0000 80: 0x0801 0x6210 0x0002 0x0000 0x0000 81: 0x0801 0x4210 0x0002 0x0000 0x0000 82: 0x0801 0x4210 0x0003 0x0000 0x0000 83: 0x0801 0x4290 0x0001 0x0000 0x0000 84: 0x0801 0x4290 0x0002 0x0000 0x0000 85: 0x0801 0x42D0 0x0002 0x0000 0x0000 86: 0x0801 0x42D0 0x0001 0x0000 0x0000 87: 0x0801 0x4250 0x0003 0x0000 0x0000 88: 0x0801 0x4250 0x0002 0x0000 0x0000 89: 0x0801 0x4270 0x0000 0x0000 0x0000 90: 0x0801 0x4270 0x0001 0x0000 0x0000 91: 0x0801 0x42F0 0x0001 0x0000 0x0000 92: 0x0801 0x42F0 0x0000 0x0000 0x0000 93: 0x0801 0x42B0 0x0002 0x0000 0x0000 94: 0x0801 0x42B0 0x0001 0x0000 0x0000 95: 0x0801 0x4230 0x0003 0x0000 0x0000 96: 0x0801 0x4230 0x0002 0x0000 0x0000 97: 0x0801 0x4210 0x0002 0x0000 0x0000 98: 0x0801 0x4210 0x0002 0x0000 0x0000 99: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 100: 0xE71E 0xBCEF 0x0001 0x0000 0x0000 101: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 102: 0xB71E 0xBCEF 0x0001 0x0000 0x0000 103: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 104: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 105: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 106: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x371E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x771E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0xC71E 0xBCEF 0x0001 0x0000 0x0000 114: 0xD71E 0xBCEF 0x0001 0x0000 0x0000 115: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 116: 0xF71C 0xBCEF 0x0001 0x0000 0x0000 117: 0xF715 0xBCEF 0x0001 0x0000 0x0000 118: 0xF716 0xBCEF 0x0001 0x0000 0x0000 119: 0xF713 0xBCEF 0x0001 0x0000 0x0000 120: 0xF711 0xBCEF 0x0001 0x0000 0x0000 121: 0xF701 0xBCEF 0x0001 0x0000 0x0000 122: 0xF703 0xBCEF 0x0001 0x0000 0x0000 123: 0xF706 0xBCEF 0x0001 0x0000 0x0000 124: 0xF705 0xBCEF 0x0001 0x0000 0x0000 125: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 126: 0xF70E 0xBCEF 0x0001 0x0000 0x0000 127: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 128: 0xF709 0xBCEF 0x0001 0x0000 0x0000 129: 0xF718 0xBCEF 0x0001 0x0000 0x0000 130: 0xF71A 0xBCEF 0x0001 0x0000 0x0000 131: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 132: 0xF71E 0x3CEF 0x0001 0x0000 0x0000 133: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 134: 0xF51E 0xBCEF 0x0001 0x0000 0x0000 135: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 138: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 139: 0xF11E 0xBCEF 0x0001 0x0000 0x0000 140: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 141: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 142: 0xF31E 0xBCEF 0x0001 0x0000 0x0000 143: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 144: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 145: 0xF61E 0x3CEF 0x0001 0x0000 0x0000 146: 0xF61E 0xBCEF 0x0001 0x0000 0x0000 147: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 148: 0xF71E 0xBCE7 0x0001 0x0000 0x0000 149: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 150: 0xF71E 0xBCED 0x0001 0x0000 0x0000 151: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 152: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 153: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 154: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 155: 0xF71E 0xBCEC 0x0001 0x0000 0x0000 156: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 157: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 158: 0xF71E 0xBCEE 0x0001 0x0000 0x0000 159: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 160: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 161: 0xF71E 0xBCE3 0x0001 0x0000 0x0000 162: 0xF71E 0xBCEB 0x0001 0x0000 0x0000 163: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 164: 0xF71E 0xB8EF 0x0001 0x0000 0x0000 165: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 166: 0xF71E 0xACEF 0x0001 0x0000 0x0000 167: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 168: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 169: 0xF71E 0x82EF 0x0001 0x0000 0x0000 170: 0xF71E 0x86EF 0x0001 0x0000 0x0000 171: 0xF71E 0x8CEF 0x0001 0x0000 0x0000 172: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 173: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 174: 0xF71E 0x9CEF 0x0001 0x0000 0x0000 175: 0xF71E 0x96EF 0x0001 0x0000 0x0000 176: 0xF71E 0x92EF 0x0001 0x0000 0x0000 177: 0xF71E 0xB0EF 0x0001 0x0000 0x0000 178: 0xF71E 0xB4EF 0x0001 0x0000 0x0000 179: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 180: 0xF71E 0xBCEF 0x0000 0x0000 0x0000 181: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 182: 0xF71E 0xBCAF 0x0001 0x0000 0x0000 183: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 184: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 185: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 187: 0xF71E 0xBC8F 0x0001 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 190: 0xF71E 0xBCCF 0x0001 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 193: 0xF71E 0xBC6F 0x0000 0x0000 0x0000 194: 0xF71E 0xBC6F 0x0001 0x0000 0x0000 195: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 196: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 197: 0x0801 0x4210 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 197 'test steps' 235 lines ; M121 PCB REV D SCHEMATIC REV C 6 2-2 AND-NOR USING 3 7450s ; ; EXAMPLE EQUATION: A = (A1A AND A1B) NOR (A2A AND A2B) PINS Main menu Fri Jun 30 17:03:19 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:03:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEDEFHJFHJKLKLMNPMNPRSRSTUV SIDE 111112222211111222221111122222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 17 Main menu Fri Jun 30 17:03:22 2017 test file is: tests\m121.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 17:03:34 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:03:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 59 Main menu Fri Jun 30 17:03:38 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:03:51 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 59 Main menu Fri Jun 30 17:03:57 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 17:04:14 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:04:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 46 Main menu Fri Jun 30 17:04:20 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m169.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 17:04:34 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:04:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails I OO OO IOO OO OO OO was lo 000000000000000 00000000000000 0 falling vvvvv vvv vvv vvvvvvvvvv vvv rising ^^^^^ ^^^ ^^^ ^^^^^^^^^^ ^^^ was hi 11111 111 111 11111111111 1111 total fails 48, total passes 0 Main menu Fri Jun 30 17:05:02 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m169.tst could not open test file. valid test files are: reverting back to test file: tests\m216.tst Main menu Fri Jun 30 17:05:07 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 17:05:21 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m169.tst reading test file: tests\m169.tst comment: ; M169 PCB REV B SCHEMATIC REV A comment: ; 4 AND-OR TREES (2-2-2-2) WITH 2 SETS OF ENABLES; EXTRA OR ON OUTPUT. comment: comment: ; PINS HEADER comment: ; PIN HEADER A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2D3D4 comment: ; EX EQUATION: A = A5-N OR (EN_A1B1 AND A1) comment: ; OR (EN_A2B2 AND A2) comment: ; OR (EN_A3B3 AND A3) comment: ; OR (EN_A4B4 AND A4) comment: pins: PINS pins: 1 I AC1 E1-13,E2-13 EN_A1B1 1-X-X-X 1-X-X-X pins: 2 I AD1 E1-1 A1 1-X-X-X pins: 3 I AD2 E1-10,E2-10 EN_A2B2 X-1-X-X X-1-X-X pins: 4 I AE1 E1-9 A2 X-1-X-X pins: 5 I AE2 E1-4,E2-4 EN_A3B3 X-X-1-X X-X-1-X pins: 6 I AF1 E1-5 A3 X-X-1-X pins: 7 I AF2 E1-2,E2-2 EN_A4B4 X-X-X-1 X-X-X-1 pins: 8 I AH1 E1-3 A4 X-X-X-1 pins: 9 I AB1 E3-12 A5-N pins: 10 O AA1 E3-11 OUTPUT A pins: 11 I AH2 E2-1 B1 1-X-X-X pins: 12 I AJ2 E2-9 B2 X-1-X-X pins: 13 I AK2 E2-5 B3 X-X-1-X pins: 14 I AL2 E2-3 B4 X-X-X-1 pins: 15 I AJ1 E3-9 B5-N pins: 16 O AK1 E3-8 OUTPUT B pins: 17 I AM2 E5-13,E4-13 EN_C1D1 1-X-X-X 1-X-X-X pins: 18 I AN1 E5-1 C1 1-X-X-X pins: 19 I AN2 E5-10,E4-10 EN_C2D2 X-1-X-X X-1-X-X pins: 20 I AP1 E5-9 C2 X-1-X-X pins: 21 I AP2 E5-4,E4-4 EN_C3D3 X-X-1-X X-X-1-X pins: 22 I AR1 E5-5 C3 X-X-1-X pins: 23 I AR2 E5-2,E4-2 EN_C4D4 X-X-X-1 X-X-X-1 pins: 24 I AS1 E1-3 C4 X-X-X-1 pins: 25 I AL1 E3-5 C5-N pins: 26 O AM1 E3-6 OUTPUT C pins: 27 I AS2 E4-1 D1 1-X-X-X pins: 28 I AT2 E4-9 D2 X-1-X-X pins: 29 I AU1 E4-5 D3 X-X-1-X pins: 30 I AV1 E4-3 D4 X-X-X-1 pins: 31 I AU2 E3-1 D5-N pins: 32 O AV2 E3-3 OUTPUT D pins: direction: IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO test 1: 00000000100000100000000010000010 comment: comment: ; TEST OUTPUT A TURNING ON test 2: 01 0 test 3: 11 1 test 4: 10 0 test 5: 00 0 test 6: 01 0 test 7: 11 1 test 8: 10 0 test 9: 00 0 test 10: 01 0 test 11: 11 1 test 12: 10 0 test 13: 00 0 test 14: 01 0 test 15: 11 1 test 16: 10 0 test 17: 00 0 test 18: 01 test 19: 11 1 test 20: 00 1 test 21: 10 test 22: 00000000100000100000000010000010 comment: ; TEST OUTPUT A NOT TURNING ON test 23: 1 0 test 24: 1 0 test 25: 1 0 test 26: 1 0 test 27: 0 0 test 28: 0 0 test 29: 0 0 test 30: 0 0 test 31: 1 0 test 32: 0 0 test 33: 00000000100000100000000010000010 comment: ;TEST OUTPUT B TURNING ON test 34: 0 1 0 test 35: 1 1 1 test 36: 1 0 0 test 37: 0 0 0 test 38: 0 1 0 test 39: 1 1 1 test 40: 1 0 0 test 41: 0 0 0 comment: test 42: 0 1 0 test 43: 1 1 1 test 44: 1 0 0 test 45: 0 0 0 comment: test 46: 0 1 0 test 47: 1 1 1 test 48: 1 0 0 test 49: 0 0 0 test 50: 01 test 51: 1 1 1 test 52: 0 0 1 test 53: 10 test 54: 00000000100000100000000010000010 comment: ; TEST OUTPUT B NOT TURNING ON test 55: 1 0 test 56: 1 0 test 57: 1 0 test 58: 1 0 test 59: 0 0 test 60: 0 0 test 61: 0 0 test 62: 0 0 test 63: 1 0 test 64: 0 0 test 65: 00000000100000100000000010000010 comment: ; TEST EN_A1B1 test 66: 10 00 0 test 67: 11 10 0 test 68: 11 11 1 test 69: 01 01 0 test 70: 11 11 1 test 71: 10 01 1 test 72: 10 00 0 test 73: 00 00 0 test 74: 00000000100000100000000010000010 comment: ; TEST EN_A2B2 test 75: 10 0 0 0 test 76: 11 1 0 0 test 77: 11 1 1 1 test 78: 01 0 1 0 test 79: 11 1 1 1 test 80: 10 0 1 1 test 81: 10 0 0 0 test 82: 00 0 0 0 test 83: 00000000100000100000000010000010 comment: ; TEST EN_A3B3 test 84: 10 0 0 0 test 85: 11 1 0 0 test 86: 11 1 1 1 test 87: 01 0 1 0 test 88: 11 1 1 1 test 89: 10 0 1 1 test 90: 10 0 0 0 test 91: 00 0 0 0 test 92: 00000000100000100000000010000010 comment: ; TEST EN_A4B4 test 93: 10 0 0 0 test 94: 11 1 0 0 test 95: 11 1 1 1 test 96: 01 0 1 0 test 97: 11 1 1 1 test 98: 10 0 1 1 test 99: 10 0 0 0 test 100: 00 0 0 0 test 101: 00000000100000100000000010000010 comment: ; TEST OUTPUT C TURNING ON test 102: 01 0 test 103: 11 1 test 104: 10 0 test 105: 00 0 test 106: 01 0 test 107: 11 1 test 108: 10 0 test 109: 00 0 test 110: 01 0 test 111: 11 1 test 112: 10 0 test 113: 00 0 test 114: 01 0 test 115: 11 1 test 116: 10 0 test 117: 00 0 test 118: 01 test 119: 11 1 test 120: 00 1 test 121: 10 test 122: 00000000100000100000000010000010 comment: ; TEST OUTPUT C NOT TURNING ON test 123: 1 0 test 124: 1 0 test 125: 1 0 test 126: 1 0 test 127: 0 0 test 128: 0 0 test 129: 0 0 test 130: 0 0 test 131: 1 0 test 132: 0 0 test 133: 00000000100000100000000010000010 comment: ; TEST OUTPUT D TURNING ON test 134: 0 1 0 test 135: 1 1 1 test 136: 1 0 0 test 137: 0 0 0 test 138: 0 1 0 test 139: 1 1 1 test 140: 1 0 0 test 141: 0 0 0 test 142: 0 1 0 test 143: 1 1 1 test 144: 1 0 0 test 145: 0 0 0 test 146: 0 1 0 test 147: 1 1 1 test 148: 1 0 0 test 149: 0 0 0 test 150: 01 test 151: 1 1 1 test 152: 0 0 1 test 153: 10 test 154: 00000000100000100000000010000010 comment: ; TEST OUTPUT D NOT TURNING ON test 155: 1 0 test 156: 1 0 test 157: 1 0 test 158: 1 0 test 159: 0 0 test 160: 0 0 test 161: 0 0 test 162: 0 0 test 163: 1 0 test 164: 0 0 test 165: 00000000100000100000000010000010 comment: ; TEST EN_C1D1 test 166: 10 00 0 test 167: 11 10 0 test 168: 11 11 1 test 169: 01 01 0 test 170: 11 11 1 test 171: 10 01 1 test 172: 10 00 0 test 173: 00 00 0 test 174: 00000000100000100000000010000010 comment: ; TEST EN_C2D2 test 175: 10 0 0 0 test 176: 11 1 0 0 test 177: 11 1 1 1 test 178: 01 0 1 0 test 179: 11 1 1 1 test 180: 10 0 1 1 test 181: 10 0 0 0 test 182: 00 0 0 0 test 183: 00000000100000100000000010000010 comment: ; TEST EN_C3D3 test 184: 10 0 0 0 test 185: 11 1 0 0 test 186: 11 1 1 1 test 187: 01 0 1 0 test 188: 11 1 1 1 test 189: 10 0 1 1 test 190: 10 0 0 0 test 191: 00 0 0 0 test 192: 00000000100000100000000010000010 comment: ; TEST EN_C4D4 test 193: 10 0 0 0 test 194: 11 1 0 0 test 195: 11 1 1 1 test 196: 01 0 1 0 test 197: 11 1 1 1 test 198: 10 0 1 1 test 199: 10 0 0 0 test 200: 00 0 0 0 test 201: 00000000100000100000000010000010 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x1000 column 3: offset 0, mask 0x0010 column 4: offset 0, mask 0x0800 column 5: offset 0, mask 0x0008 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0004 column 8: offset 0, mask 0x0200 column 9: offset 0, mask 0x4000 column 10: offset 0, mask 0x8000 column 11: offset 0, mask 0x0002 column 12: offset 0, mask 0x0001 column 13: offset 1, mask 0x0001 column 14: offset 1, mask 0x0002 column 15: offset 0, mask 0x0100 column 16: offset 1, mask 0x8000 column 17: offset 1, mask 0x0004 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0008 column 20: offset 1, mask 0x0800 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0400 column 23: offset 1, mask 0x0020 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x4000 column 26: offset 1, mask 0x2000 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x80E0 0xA100 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4100 0x4000 0x0001 0x0000 0x0000 2: 0x5100 0x4000 0x0001 0x0000 0x0000 3: 0xF100 0x4000 0x0001 0x0000 0x0000 4: 0x6100 0x4000 0x0001 0x0000 0x0000 5: 0x4100 0x4000 0x0001 0x0000 0x0000 6: 0x4900 0x4000 0x0001 0x0000 0x0000 7: 0xC910 0x4000 0x0001 0x0000 0x0000 8: 0x4110 0x4000 0x0001 0x0000 0x0000 9: 0x4100 0x4000 0x0001 0x0000 0x0000 10: 0x4500 0x4000 0x0001 0x0000 0x0000 11: 0xC508 0x4000 0x0001 0x0000 0x0000 12: 0x4108 0x4000 0x0001 0x0000 0x0000 13: 0x4100 0x4000 0x0001 0x0000 0x0000 14: 0x4300 0x4000 0x0001 0x0000 0x0000 15: 0xC304 0x4000 0x0001 0x0000 0x0000 16: 0x4104 0x4000 0x0001 0x0000 0x0000 17: 0x4100 0x4000 0x0001 0x0000 0x0000 18: 0x8100 0x4000 0x0001 0x0000 0x0000 19: 0x8304 0x4000 0x0001 0x0000 0x0000 20: 0x8100 0x4000 0x0001 0x0000 0x0000 21: 0x4100 0x4000 0x0001 0x0000 0x0000 22: 0x4100 0x4000 0x0001 0x0000 0x0000 23: 0x5100 0x4000 0x0001 0x0000 0x0000 24: 0x5900 0x4000 0x0001 0x0000 0x0000 25: 0x5D00 0x4000 0x0001 0x0000 0x0000 26: 0x5F00 0x4000 0x0001 0x0000 0x0000 27: 0x5D00 0x4000 0x0001 0x0000 0x0000 28: 0x5900 0x4000 0x0001 0x0000 0x0000 29: 0x5100 0x4000 0x0001 0x0000 0x0000 30: 0x4100 0x4000 0x0001 0x0000 0x0000 31: 0x6100 0x4000 0x0001 0x0000 0x0000 32: 0x4100 0x4000 0x0001 0x0000 0x0000 33: 0x4100 0x4000 0x0001 0x0000 0x0000 34: 0x4102 0x4000 0x0001 0x0000 0x0000 35: 0x6102 0xC000 0x0001 0x0000 0x0000 36: 0x6100 0x4000 0x0001 0x0000 0x0000 37: 0x4100 0x4000 0x0001 0x0000 0x0000 38: 0x4101 0x4000 0x0001 0x0000 0x0000 39: 0x4111 0xC000 0x0001 0x0000 0x0000 40: 0x4110 0x4000 0x0001 0x0000 0x0000 41: 0x4100 0x4000 0x0001 0x0000 0x0000 42: 0x4100 0x4001 0x0001 0x0000 0x0000 43: 0x4108 0xC001 0x0001 0x0000 0x0000 44: 0x4108 0x4000 0x0001 0x0000 0x0000 45: 0x4100 0x4000 0x0001 0x0000 0x0000 46: 0x4100 0x4002 0x0001 0x0000 0x0000 47: 0x4104 0xC002 0x0001 0x0000 0x0000 48: 0x4104 0x4000 0x0001 0x0000 0x0000 49: 0x4100 0x4000 0x0001 0x0000 0x0000 50: 0x4000 0xC000 0x0001 0x0000 0x0000 51: 0x4004 0xC002 0x0001 0x0000 0x0000 52: 0x4000 0xC000 0x0001 0x0000 0x0000 53: 0x4100 0x4000 0x0001 0x0000 0x0000 54: 0x4100 0x4000 0x0001 0x0000 0x0000 55: 0x4102 0x4000 0x0001 0x0000 0x0000 56: 0x4103 0x4000 0x0001 0x0000 0x0000 57: 0x4103 0x4001 0x0001 0x0000 0x0000 58: 0x4103 0x4003 0x0001 0x0000 0x0000 59: 0x4103 0x4001 0x0001 0x0000 0x0000 60: 0x4103 0x4000 0x0001 0x0000 0x0000 61: 0x4102 0x4000 0x0001 0x0000 0x0000 62: 0x4100 0x4000 0x0001 0x0000 0x0000 63: 0x6100 0x4000 0x0001 0x0000 0x0000 64: 0x4100 0x4000 0x0001 0x0000 0x0000 65: 0x4100 0x4000 0x0001 0x0000 0x0000 66: 0x6100 0x4000 0x0001 0x0000 0x0000 67: 0xF100 0x4000 0x0001 0x0000 0x0000 68: 0xF102 0xC000 0x0001 0x0000 0x0000 69: 0x5102 0x4000 0x0001 0x0000 0x0000 70: 0xF102 0xC000 0x0001 0x0000 0x0000 71: 0x6102 0xC000 0x0001 0x0000 0x0000 72: 0x6100 0x4000 0x0001 0x0000 0x0000 73: 0x4100 0x4000 0x0001 0x0000 0x0000 74: 0x4100 0x4000 0x0001 0x0000 0x0000 75: 0x4110 0x4000 0x0001 0x0000 0x0000 76: 0xC910 0x4000 0x0001 0x0000 0x0000 77: 0xC911 0xC000 0x0001 0x0000 0x0000 78: 0x4901 0x4000 0x0001 0x0000 0x0000 79: 0xC911 0xC000 0x0001 0x0000 0x0000 80: 0x4111 0xC000 0x0001 0x0000 0x0000 81: 0x4110 0x4000 0x0001 0x0000 0x0000 82: 0x4100 0x4000 0x0001 0x0000 0x0000 83: 0x4100 0x4000 0x0001 0x0000 0x0000 84: 0x4108 0x4000 0x0001 0x0000 0x0000 85: 0xC508 0x4000 0x0001 0x0000 0x0000 86: 0xC508 0xC001 0x0001 0x0000 0x0000 87: 0x4500 0x4001 0x0001 0x0000 0x0000 88: 0xC508 0xC001 0x0001 0x0000 0x0000 89: 0x4108 0xC001 0x0001 0x0000 0x0000 90: 0x4108 0x4000 0x0001 0x0000 0x0000 91: 0x4100 0x4000 0x0001 0x0000 0x0000 92: 0x4100 0x4000 0x0001 0x0000 0x0000 93: 0x4104 0x4000 0x0001 0x0000 0x0000 94: 0xC304 0x4000 0x0001 0x0000 0x0000 95: 0xC304 0xC002 0x0001 0x0000 0x0000 96: 0x4300 0x4002 0x0001 0x0000 0x0000 97: 0xC304 0xC002 0x0001 0x0000 0x0000 98: 0x4104 0xC002 0x0001 0x0000 0x0000 99: 0x4104 0x4000 0x0001 0x0000 0x0000 100: 0x4100 0x4000 0x0001 0x0000 0x0000 101: 0x4100 0x4000 0x0001 0x0000 0x0000 102: 0x4100 0x5000 0x0001 0x0000 0x0000 103: 0x4100 0x7004 0x0001 0x0000 0x0000 104: 0x4100 0x4004 0x0001 0x0000 0x0000 105: 0x4100 0x4000 0x0001 0x0000 0x0000 106: 0x4100 0x4800 0x0001 0x0000 0x0000 107: 0x4100 0x6808 0x0001 0x0000 0x0000 108: 0x4100 0x4008 0x0001 0x0000 0x0000 109: 0x4100 0x4000 0x0001 0x0000 0x0000 110: 0x4100 0x4400 0x0001 0x0000 0x0000 111: 0x4100 0x6410 0x0001 0x0000 0x0000 112: 0x4100 0x4010 0x0001 0x0000 0x0000 113: 0x4100 0x4000 0x0001 0x0000 0x0000 114: 0x4100 0x4200 0x0001 0x0000 0x0000 115: 0x4100 0x6220 0x0001 0x0000 0x0000 116: 0x4100 0x4020 0x0001 0x0000 0x0000 117: 0x4100 0x4000 0x0001 0x0000 0x0000 118: 0x4100 0x2000 0x0001 0x0000 0x0000 119: 0x4100 0x2220 0x0001 0x0000 0x0000 120: 0x4100 0x2000 0x0001 0x0000 0x0000 121: 0x4100 0x4000 0x0001 0x0000 0x0000 122: 0x4100 0x4000 0x0001 0x0000 0x0000 123: 0x4100 0x5000 0x0001 0x0000 0x0000 124: 0x4100 0x5800 0x0001 0x0000 0x0000 125: 0x4100 0x5C00 0x0001 0x0000 0x0000 126: 0x4100 0x5E00 0x0001 0x0000 0x0000 127: 0x4100 0x5C00 0x0001 0x0000 0x0000 128: 0x4100 0x5800 0x0001 0x0000 0x0000 129: 0x4100 0x5000 0x0001 0x0000 0x0000 130: 0x4100 0x4000 0x0001 0x0000 0x0000 131: 0x4100 0x4004 0x0001 0x0000 0x0000 132: 0x4100 0x4000 0x0001 0x0000 0x0000 133: 0x4100 0x4000 0x0001 0x0000 0x0000 134: 0x4100 0x4040 0x0001 0x0000 0x0000 135: 0x4100 0x4044 0x0003 0x0000 0x0000 136: 0x4100 0x4004 0x0001 0x0000 0x0000 137: 0x4100 0x4000 0x0001 0x0000 0x0000 138: 0x4100 0x4080 0x0001 0x0000 0x0000 139: 0x4100 0x4088 0x0003 0x0000 0x0000 140: 0x4100 0x4008 0x0001 0x0000 0x0000 141: 0x4100 0x4000 0x0001 0x0000 0x0000 142: 0x4100 0x4000 0x8001 0x0000 0x0000 143: 0x4100 0x4010 0x8003 0x0000 0x0000 144: 0x4100 0x4010 0x0001 0x0000 0x0000 145: 0x4100 0x4000 0x0001 0x0000 0x0000 146: 0x4100 0x4000 0x4001 0x0000 0x0000 147: 0x4100 0x4020 0x4003 0x0000 0x0000 148: 0x4100 0x4020 0x0001 0x0000 0x0000 149: 0x4100 0x4000 0x0001 0x0000 0x0000 150: 0x4100 0x4000 0x0002 0x0000 0x0000 151: 0x4100 0x4020 0x4002 0x0000 0x0000 152: 0x4100 0x4000 0x0002 0x0000 0x0000 153: 0x4100 0x4000 0x0001 0x0000 0x0000 154: 0x4100 0x4000 0x0001 0x0000 0x0000 155: 0x4100 0x4040 0x0001 0x0000 0x0000 156: 0x4100 0x40C0 0x0001 0x0000 0x0000 157: 0x4100 0x40C0 0x8001 0x0000 0x0000 158: 0x4100 0x40C0 0xC001 0x0000 0x0000 159: 0x4100 0x40C0 0x8001 0x0000 0x0000 160: 0x4100 0x40C0 0x0001 0x0000 0x0000 161: 0x4100 0x4040 0x0001 0x0000 0x0000 162: 0x4100 0x4000 0x0001 0x0000 0x0000 163: 0x4100 0x4004 0x0001 0x0000 0x0000 164: 0x4100 0x4000 0x0001 0x0000 0x0000 165: 0x4100 0x4000 0x0001 0x0000 0x0000 166: 0x4100 0x4004 0x0001 0x0000 0x0000 167: 0x4100 0x7004 0x0001 0x0000 0x0000 168: 0x4100 0x7044 0x0003 0x0000 0x0000 169: 0x4100 0x5040 0x0001 0x0000 0x0000 170: 0x4100 0x7044 0x0003 0x0000 0x0000 171: 0x4100 0x4044 0x0003 0x0000 0x0000 172: 0x4100 0x4004 0x0001 0x0000 0x0000 173: 0x4100 0x4000 0x0001 0x0000 0x0000 174: 0x4100 0x4000 0x0001 0x0000 0x0000 175: 0x4100 0x4008 0x0001 0x0000 0x0000 176: 0x4100 0x6808 0x0001 0x0000 0x0000 177: 0x4100 0x6888 0x0003 0x0000 0x0000 178: 0x4100 0x4880 0x0001 0x0000 0x0000 179: 0x4100 0x6888 0x0003 0x0000 0x0000 180: 0x4100 0x4088 0x0003 0x0000 0x0000 181: 0x4100 0x4008 0x0001 0x0000 0x0000 182: 0x4100 0x4000 0x0001 0x0000 0x0000 183: 0x4100 0x4000 0x0001 0x0000 0x0000 184: 0x4100 0x4010 0x0001 0x0000 0x0000 185: 0x4100 0x6410 0x0001 0x0000 0x0000 186: 0x4100 0x6410 0x8003 0x0000 0x0000 187: 0x4100 0x4400 0x8001 0x0000 0x0000 188: 0x4100 0x6410 0x8003 0x0000 0x0000 189: 0x4100 0x4010 0x8003 0x0000 0x0000 190: 0x4100 0x4010 0x0001 0x0000 0x0000 191: 0x4100 0x4000 0x0001 0x0000 0x0000 192: 0x4100 0x4000 0x0001 0x0000 0x0000 193: 0x4100 0x4020 0x0001 0x0000 0x0000 194: 0x4100 0x6220 0x0001 0x0000 0x0000 195: 0x4100 0x6220 0x4003 0x0000 0x0000 196: 0x4100 0x4200 0x4001 0x0000 0x0000 197: 0x4100 0x6220 0x4003 0x0000 0x0000 198: 0x4100 0x4020 0x4003 0x0000 0x0000 199: 0x4100 0x4020 0x0001 0x0000 0x0000 200: 0x4100 0x4000 0x0001 0x0000 0x0000 201: 0x4100 0x4000 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE OIIIIIIIOIOIIIIGIIP GIIIIIIIIIIIIIIO G P G UUT inputs: 28 UUT outputs: 4 pins used: 32 not used: 34 201 'test steps' 266 lines ; M169 PCB REV B SCHEMATIC REV A ; 4 AND-OR TREES (2-2-2-2) WITH 2 SETS OF ENABLES; EXTRA OR ON OUTPUT. ; PINS HEADER ; PIN HEADER A1A2A3A4 B1B2B3B4 C1C2C3C4 D1D2D3D4 ; EX EQUATION: A = A5-N OR (EN_A1B1 AND A1) ; OR (EN_A2B2 AND A2) ; OR (EN_A3B3 AND A3) ; OR (EN_A4B4 AND A4) PINS Main menu Fri Jun 30 17:05:26 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:05:27 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CDDEEFFHBAHJKLJKMNNPPRRSLMSTUVUV SIDE 11212121112222112121212111221122 DIRECTION IIIIIIIIIOIIIIIOIIIIIIIIIOIIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 27 Main menu Fri Jun 30 17:05:31 2017 test file is: tests\m169.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 17:05:47 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:05:48 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 66 Main menu Fri Jun 30 17:05:52 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m117.tst reading test file: tests\m117.tst comment: M117 REV 3 6 4-input NAND comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M117 REV 3 6 4-input NAND PINS Main menu Fri Jun 30 17:06:08 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:06:08 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 17 Main menu Fri Jun 30 17:06:11 2017 test file is: tests\m117.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 17:06:25 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:06:26 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 39 Main menu Fri Jun 30 17:06:29 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:06:42 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 36 Main menu Fri Jun 30 17:06:44 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:06:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo falling rising was hi total fails 0, total passes 0 Main menu Fri Jun 30 17:06:59 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 17:07:02 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:07:03 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 61 Main menu Fri Jun 30 17:07:07 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 17:07:21 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:07:22 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 41 Main menu Fri Jun 30 17:07:24 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 17:07:39 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:07:40 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 73 Main menu Fri Jun 30 17:07:44 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m111.tst reading test file: tests\m111.tst comment: M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s pins: PINS pins: 1 I AV1 E4-9 pins: 2 O AU1 E4-8 pins: 3 I AR1 E4-12 pins: 4 O AS1 E4-11 pins: 5 I AN1 E3-10 pins: 6 O AP1 E3-8 pins: 7 I AL1 E3-12 pins: 8 O AM1 E3-11 pins: 9 I AJ1 E1-9 pins: 10 O AK1 E1-8 pins: 11 I AF1 E1-12 pins: 12 O AH1 E1-11 pins: 13 I AD1 E2-9 pins: 14 O AE1 E2-8 pins: 15 I AC1 E2-5 pins: 16 O AD2 E2-6 pins: 17 I AA1 E2-12 pins: 18 O AB1 E2-11 pins: 19 I AU2 E4-1 pins: 20 O AV2 E4-2 pins: 21 I AS2 E4-5 pins: 22 O AT2 E4-6 pins: 23 I AP2 E3-1 pins: 24 O AR2 E3-2 pins: 25 I AM2 E3-5 pins: 26 O AN2 E3-6 pins: 27 I AK2 E1-1 pins: 28 O AL2 E1-3 pins: 29 I AH2 E1-5 pins: 30 O AJ2 E1-6 pins: 31 I AE2 E2-1 pins: 32 O AF2 E2-3 pins: direction: IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO test 1: 01010101010101010101010101010101 test 2: 01 test 3: 10 test 4: 01 test 5: 01 test 6: 10 test 7: 01 test 8: 01 test 9: 10 test 10: 01 test 11: 01 test 12: 10 test 13: 01 test 14: 01 test 15: 10 test 16: 01 test 17: 01 test 18: 10 test 19: 01 test 20: 01 test 21: 10 test 22: 01 test 23: 01 test 24: 10 test 25: 01 test 26: 01 test 27: 10 test 28: 01 test 29: 01 test 30: 10 test 31: 01 test 32: 01 test 33: 10 test 34: 01 test 35: 01 test 36: 10 test 37: 01 test 38: 01 test 39: 10 test 40: 01 test 41: 01 test 42: 10 test 43: 01 test 44: 01 test 45: 10 test 46: 01 test 47: 01 test 48: 10 test 49: 01 test 50: 01010101010101010101010101010101 test 51: 10101010101010101010101010101010 test 52: 01 test 53: 10 test 54: 01 test 55: 10 test 56: 01 test 57: 10 test 58: 01 test 59: 10 test 60: 01 test 61: 10 test 62: 01 test 63: 10 test 64: 01 test 65: 10 test 66: 01 test 67: 10 test 68: 01 test 69: 10 test 70: 01 test 71: 10 test 72: 01 test 73: 10 test 74: 01 test 75: 10 test 76: 01 test 77: 10 test 78: 01 test 79: 10 test 80: 01 test 81: 10 test 82: 01 test 83: 10 test 84: 10101010101010101010101010101010 end: END summary column 1: offset 2, mask 0x4000 column 2: offset 2, mask 0x8000 column 3: offset 1, mask 0x0400 column 4: offset 1, mask 0x0200 column 5: offset 1, mask 0x1000 column 6: offset 1, mask 0x0800 column 7: offset 1, mask 0x4000 column 8: offset 1, mask 0x2000 column 9: offset 0, mask 0x0100 column 10: offset 1, mask 0x8000 column 11: offset 0, mask 0x0400 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x1000 column 14: offset 0, mask 0x0800 column 15: offset 0, mask 0x2000 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x8000 column 18: offset 0, mask 0x4000 column 19: offset 2, mask 0x0001 column 20: offset 2, mask 0x0002 column 21: offset 1, mask 0x0040 column 22: offset 1, mask 0x0080 column 23: offset 1, mask 0x0010 column 24: offset 1, mask 0x0020 column 25: offset 1, mask 0x0004 column 26: offset 1, mask 0x0008 column 27: offset 1, mask 0x0001 column 28: offset 1, mask 0x0002 column 29: offset 0, mask 0x0002 column 30: offset 0, mask 0x0001 column 31: offset 0, mask 0x0008 column 32: offset 0, mask 0x0004 direction bits (1=input) 0x4AF5 0xABAA 0xBFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 2: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 3: 0x4A15 0xAAAA 0x4002 0x0000 0x0000 4: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 5: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 6: 0x4A15 0xACAA 0x8002 0x0000 0x0000 7: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 8: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 9: 0x4A15 0xB2AA 0x8002 0x0000 0x0000 10: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 11: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 12: 0x4A15 0xCAAA 0x8002 0x0000 0x0000 13: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 14: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 15: 0x4B15 0x2AAA 0x8002 0x0000 0x0000 16: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 17: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 18: 0x4C15 0xAAAA 0x8002 0x0000 0x0000 19: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 20: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 21: 0x5215 0xAAAA 0x8002 0x0000 0x0000 22: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 23: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 24: 0x6A05 0xAAAA 0x8002 0x0000 0x0000 25: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 26: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 27: 0x8A15 0xAAAA 0x8002 0x0000 0x0000 28: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 29: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 30: 0x4A15 0xAAAA 0x8001 0x0000 0x0000 31: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 32: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 33: 0x4A15 0xAA6A 0x8002 0x0000 0x0000 34: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 35: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 36: 0x4A15 0xAA9A 0x8002 0x0000 0x0000 37: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 38: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 39: 0x4A15 0xAAA6 0x8002 0x0000 0x0000 40: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 41: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 42: 0x4A15 0xAAA9 0x8002 0x0000 0x0000 43: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 44: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 45: 0x4A16 0xAAAA 0x8002 0x0000 0x0000 46: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 47: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 48: 0x4A19 0xAAAA 0x8002 0x0000 0x0000 49: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 50: 0x4A15 0xAAAA 0x8002 0x0000 0x0000 51: 0xB50A 0x5455 0x4001 0x0000 0x0000 52: 0xB50A 0x5455 0x8001 0x0000 0x0000 53: 0xB50A 0x5455 0x4001 0x0000 0x0000 54: 0xB50A 0x5255 0x4001 0x0000 0x0000 55: 0xB50A 0x5455 0x4001 0x0000 0x0000 56: 0xB50A 0x4C55 0x4001 0x0000 0x0000 57: 0xB50A 0x5455 0x4001 0x0000 0x0000 58: 0xB50A 0x3455 0x4001 0x0000 0x0000 59: 0xB50A 0x5455 0x4001 0x0000 0x0000 60: 0xB40A 0xD455 0x4001 0x0000 0x0000 61: 0xB50A 0x5455 0x4001 0x0000 0x0000 62: 0xB30A 0x5455 0x4001 0x0000 0x0000 63: 0xB50A 0x5455 0x4001 0x0000 0x0000 64: 0xAD0A 0x5455 0x4001 0x0000 0x0000 65: 0xB50A 0x5455 0x4001 0x0000 0x0000 66: 0x951A 0x5455 0x4001 0x0000 0x0000 67: 0xB50A 0x5455 0x4001 0x0000 0x0000 68: 0x750A 0x5455 0x4001 0x0000 0x0000 69: 0xB50A 0x5455 0x4001 0x0000 0x0000 70: 0xB50A 0x5455 0x4002 0x0000 0x0000 71: 0xB50A 0x5455 0x4001 0x0000 0x0000 72: 0xB50A 0x5495 0x4001 0x0000 0x0000 73: 0xB50A 0x5455 0x4001 0x0000 0x0000 74: 0xB50A 0x5465 0x4001 0x0000 0x0000 75: 0xB50A 0x5455 0x4001 0x0000 0x0000 76: 0xB50A 0x5459 0x4001 0x0000 0x0000 77: 0xB50A 0x5455 0x4001 0x0000 0x0000 78: 0xB50A 0x5456 0x4001 0x0000 0x0000 79: 0xB50A 0x5455 0x4001 0x0000 0x0000 80: 0xB509 0x5455 0x4001 0x0000 0x0000 81: 0xB50A 0x5455 0x4001 0x0000 0x0000 82: 0xB506 0x5455 0x4001 0x0000 0x0000 83: 0xB50A 0x5455 0x4001 0x0000 0x0000 84: 0xB50A 0x5455 0x4001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IOIIOIOIOIOIOIOGOIP GOIOIOIOIOIOIOIO G P G UUT inputs: 16 UUT outputs: 16 pins used: 32 not used: 34 84 'test steps' 121 lines M111 PCB REV C SCHEMATIC REV A 16 INVERTERS USING 7400s PINS Main menu Fri Jun 30 17:07:57 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Fri Jun 30 17:07:59 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 17:07:59 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:08:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER VURSNPLMJKFHDECDABUVSTPRMNKLHJEF SIDE 11111111111111121122222222222222 DIRECTION IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 48 Main menu Fri Jun 30 17:08:04 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m304 could not open test file. valid test files are: reverting back to test file: tests\m111.tst Main menu Fri Jun 30 17:08:17 2017 test file is: tests\m111.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m304.tst reading test file: tests\m304.tst comment: M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. comment: comment: USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. comment: comment: PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AF1 OUT-A, comment: NEGATIVE PULSE ON AH1 OUT-A-N comment: PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AJ1 OUT-B, comment: NEGATIVE PULSE ON AK1 OUT-B-N. comment: PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AL1 OUT-C, comment: NEGATIVE PULSE ON AM1 OUT-C-N. comment: PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AP1 OUT-D, comment: NEGATIVE PULSE ON AN1 OUT-D-N. comment: comment: TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE comment: INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE comment: TRIGGER. comment: pins: PINS pins: 1 I AD1 E2-13 INPUT A1 (LOW TRIGGERS) pins: 2 I AD2 E2-12 INPUT A2 (LOW TRIGGERS) pins: 3 O AF1 E1-08 OUTPUT A POSITIVE PULSE pins: 4 O AH1 E1-06 OUTPUT A-N NEGATIVE PULSE pins: 5 I AE1 E2-10 INPUT B1 (LOW TRIGGERS) pins: 6 I AE2 E2-09 INPUT B2 (LOW TRIGGERS) pins: 7 O AJ1 E3-08 OUTPUT B POSITIVE PULSE pins: 8 O AK1 E3-06 OUTPUT B-N NEGATIVE PULSE pins: 9 I AS1 E7-01 INPUT C1 (LOW TRIGGERS) pins: 10 I AS2 E7-02 INPUT C2 (LOW TRIGGERS) pins: 11 O AL1 E5-08 OUTPUT C POSITIVE PULSE pins: 12 O AM1 E5-06 OUTPUT C-N NEGATIVE PULSE pins: 13 I AR1 E7-04 INPUT D1 (LOW TRIGGERS) pins: 14 I AR2 E7-05 INPUT D2 (LOW TRIGGERS) pins: 15 O AP1 E6-06 OUTPUT D POSITIVE PULSE pins: 16 O AN1 E6-08 OUTPUT D-N NEGATIVE PULSE pins: direction: IIOOIIOOIIOOIIOO test 1: 1101110111011101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 2: 0101 test 3: 1101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 4: 1001 test 5: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 6: 0101 test 7: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 8: 1001 test 9: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 10: 0101 test 11: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 12: 1001 test 13: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 14: 0101 test 15: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 16: 1001 test 17: 1101 test 18: 1101110111011101 end: END summary column 1: offset 0, mask 0x1000 column 2: offset 0, mask 0x0010 column 3: offset 0, mask 0x0400 column 4: offset 0, mask 0x0200 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0100 column 8: offset 1, mask 0x8000 column 9: offset 1, mask 0x0200 column 10: offset 1, mask 0x0040 column 11: offset 1, mask 0x4000 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x0400 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0800 column 16: offset 1, mask 0x1000 direction bits (1=input) 0xE7E7 0xF99F 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1A18 0xB660 0x0000 0x0000 0x0000 2: 0x0A18 0xB660 0x0000 0x0000 0x0000 3: 0x1A18 0xB660 0x0000 0x0000 0x0000 4: 0x1A08 0xB660 0x0000 0x0000 0x0000 5: 0x1A18 0xB660 0x0000 0x0000 0x0000 6: 0x1218 0xB660 0x0000 0x0000 0x0000 7: 0x1A18 0xB660 0x0000 0x0000 0x0000 8: 0x1A10 0xB660 0x0000 0x0000 0x0000 9: 0x1A18 0xB660 0x0000 0x0000 0x0000 10: 0x1A18 0xB460 0x0000 0x0000 0x0000 11: 0x1A18 0xB660 0x0000 0x0000 0x0000 12: 0x1A18 0xB620 0x0000 0x0000 0x0000 13: 0x1A18 0xB660 0x0000 0x0000 0x0000 14: 0x1A18 0xB260 0x0000 0x0000 0x0000 15: 0x1A18 0xB660 0x0000 0x0000 0x0000 16: 0x1A18 0xB640 0x0000 0x0000 0x0000 17: 0x1A18 0xB660 0x0000 0x0000 0x0000 18: 0x1A18 0xB660 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOOOOOOOOIIG P GII II G P G UUT inputs: 8 UUT outputs: 8 pins used: 16 not used: 50 18 'test steps' 67 lines M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) POSITIVE PULSE ON AF1 OUT-A, NEGATIVE PULSE ON AH1 OUT-A-N PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) POSITIVE PULSE ON AJ1 OUT-B, NEGATIVE PULSE ON AK1 OUT-B-N. PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) POSITIVE PULSE ON AL1 OUT-C, NEGATIVE PULSE ON AM1 OUT-C-N. PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) POSITIVE PULSE ON AP1 OUT-D, NEGATIVE PULSE ON AN1 OUT-D-N. TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE TRIGGER. PINS Main menu Fri Jun 30 17:08:28 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:08:32 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO all fails was lo 000 000 000 000 falling vv vv vv vv rising ^^ ^^ ^^ ^^ was hi 11 111 111 111 1 total fails 0, total passes 205 Main menu Fri Jun 30 17:08:36 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m304.tst Main menu Fri Jun 30 17:08:49 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 17:09:14 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 17:09:19 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 17:09:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 48 Main menu Fri Jun 30 17:09:23 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Fri Jun 30 18:36:38 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 18:36:43 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 18:40:14 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 18:40:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 23 110110110110110001110110110110 fail ^ step 24 110110110110110001110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 25 110110110110110001110110110110 fail ^ step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 64 001001001001001001001001001001 fail ^ step 65 001001001001001110001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 66 001001001001001001001001001001 fail ^ step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 27: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail II all fails II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 27, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 23 110110110110110001110110110110 fail ^ step 24 110110110110110001110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 25 110110110110110001110110110110 fail ^ step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 64 001001001001001001001001001001 fail ^ step 65 001001001001001110001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 66 001001001001001001001001001001 fail ^ step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 28: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail II all fails II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 28, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 23 110110110110110001110110110110 fail ^ step 24 110110110110110001110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 25 110110110110110001110110110110 fail ^ step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 64 001001001001001001001001001001 fail ^ step 65 001001001001001110001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 66 001001001001001001001001001001 fail ^ step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 29: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail II all fails II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails II was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 29, total passes 0 Main menu Fri Jun 30 18:42:33 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 18:42:38 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0066 Main menu Fri Jun 30 18:42:40 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 18:42:43 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 23 110110110110110001110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001 changed: step 24 110110110110110001110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: step 25 110110110110110001110110110110 fail ^ source: 110 changed: 110 step 26 110110110110110110110110110110 source: 011 changed: 0 1 step 27 110110110110110110011110110110 source: 001 changed: 0 step 28 110110110110110110001110110110 source: 101 changed: 1 step 29 110110110110110110101110110110 source: 110 changed: 10 step 30 110110110110110110110110110110 source: 011 changed: 0 1 step 31 110110110110110110110011110110 source: 001 changed: 0 step 32 110110110110110110110001110110 source: 101 changed: 1 step 33 110110110110110110110101110110 source: 110 changed: 10 step 34 110110110110110110110110110110 source: 011 changed: 0 1 step 35 110110110110110110110110011110 source: 001 changed: 0 step 36 110110110110110110110110001110 source: 101 changed: 1 step 37 110110110110110110110110101110 source: 110 changed: 10 step 38 110110110110110110110110110110 source: 011 changed: 0 1 step 39 110110110110110110110110110011 source: 001 changed: 0 step 40 110110110110110110110110110001 source: 101 changed: 1 step 41 110110110110110110110110110101 source: 110 changed: 10 step 42 110110110110110110110110110110 source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 source: 011 changed: 1 step 44 011001001001001001001001001001 source: 110 changed: 1 0 step 45 110001001001001001001001001001 source: 101 changed: 01 step 46 101001001001001001001001001001 source: 001 changed: 0 step 47 001001001001001001001001001001 source: 011 changed: 1 step 48 001011001001001001001001001001 source: 110 changed: 1 0 step 49 001110001001001001001001001001 source: 101 changed: 01 step 50 001101001001001001001001001001 source: 001 changed: 0 step 51 001001001001001001001001001001 source: 011 changed: 1 step 52 001001011001001001001001001001 source: 110 changed: 1 0 step 53 001001110001001001001001001001 source: 101 changed: 01 step 54 001001101001001001001001001001 source: 001 changed: 0 step 55 001001001001001001001001001001 source: 011 changed: 1 step 56 001001001011001001001001001001 source: 110 changed: 1 0 step 57 001001001110001001001001001001 source: 101 changed: 01 step 58 001001001101001001001001001001 source: 001 changed: 0 step 59 001001001001001001001001001001 source: 011 changed: 1 step 60 001001001001011001001001001001 source: 110 changed: 1 0 step 61 001001001001110001001001001001 source: 101 changed: 01 step 62 001001001001101001001001001001 source: 001 changed: 0 step 63 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: step 64 001001001001001001001001001001 fail ^ source: 110 changed: 110 step 65 001001001001001110001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 001 step 66 001001001001001001001001001001 fail ^ source: 001 changed: step 67 001001001001001001001001001001 source: 011 changed: 1 step 68 001001001001001001011001001001 source: 110 changed: 1 0 step 69 001001001001001001110001001001 source: 101 changed: 01 step 70 001001001001001001101001001001 source: 001 changed: 0 step 71 001001001001001001001001001001 source: 011 changed: 1 step 72 001001001001001001001011001001 source: 110 changed: 1 0 step 73 001001001001001001001110001001 source: 101 changed: 01 step 74 001001001001001001001101001001 source: 001 changed: 0 step 75 001001001001001001001001001001 source: 011 changed: 1 step 76 001001001001001001001001011001 source: 110 changed: 1 0 step 77 001001001001001001001001110001 source: 101 changed: 01 step 78 001001001001001001001001101001 source: 001 changed: 0 step 79 001001001001001001001001001001 source: 011 changed: 1 step 80 001001001001001001001001001011 source: 110 changed: 1 0 step 81 001001001001001001001001001110 source: 101 changed: 01 step 82 001001001001001001001001001101 source: 001 changed: 0 step 83 001001001001001001001001001001 test 1: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail II all fails II was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001001001001001001001001001001 changed: step 1 001001001001001001001001001001 source: 110110110110110110110110110110 changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 source: 011 changed: 0 1 step 3 011110110110110110110110110110 source: 001 changed: 0 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 001 step 23 110110110110110001110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001 changed: step 24 110110110110110001110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails II was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 1, total passes 0 Main menu Fri Jun 30 18:44:15 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 18:44:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 001 step 23 110110110110110001110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 24 110110110110110001110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: step 25 110110110110110001110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 110 step 26 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 1 step 27 110110110110110110011110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 28 110110110110110110001110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails II was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvv v v v rising ^^^^^^^^^^^^^^^^^^^^^^^ ^^ ^^ was hi 111111111111111111111111111111 total fails 0, total passes 0 Main menu Fri Jun 30 18:46:18 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m304.tst reading test file: tests\m304.tst comment: M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. comment: comment: USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. comment: comment: PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AF1 OUT-A, comment: NEGATIVE PULSE ON AH1 OUT-A-N comment: PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AJ1 OUT-B, comment: NEGATIVE PULSE ON AK1 OUT-B-N. comment: PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AL1 OUT-C, comment: NEGATIVE PULSE ON AM1 OUT-C-N. comment: PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AP1 OUT-D, comment: NEGATIVE PULSE ON AN1 OUT-D-N. comment: comment: TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE comment: INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE comment: TRIGGER. comment: pins: PINS pins: 1 I AD1 E2-13 INPUT A1 (LOW TRIGGERS) pins: 2 I AD2 E2-12 INPUT A2 (LOW TRIGGERS) pins: 3 O AF1 E1-08 OUTPUT A POSITIVE PULSE pins: 4 O AH1 E1-06 OUTPUT A-N NEGATIVE PULSE pins: 5 I AE1 E2-10 INPUT B1 (LOW TRIGGERS) pins: 6 I AE2 E2-09 INPUT B2 (LOW TRIGGERS) pins: 7 O AJ1 E3-08 OUTPUT B POSITIVE PULSE pins: 8 O AK1 E3-06 OUTPUT B-N NEGATIVE PULSE pins: 9 I AS1 E7-01 INPUT C1 (LOW TRIGGERS) pins: 10 I AS2 E7-02 INPUT C2 (LOW TRIGGERS) pins: 11 O AL1 E5-08 OUTPUT C POSITIVE PULSE pins: 12 O AM1 E5-06 OUTPUT C-N NEGATIVE PULSE pins: 13 I AR1 E7-04 INPUT D1 (LOW TRIGGERS) pins: 14 I AR2 E7-05 INPUT D2 (LOW TRIGGERS) pins: 15 O AP1 E6-06 OUTPUT D POSITIVE PULSE pins: 16 O AN1 E6-08 OUTPUT D-N NEGATIVE PULSE pins: direction: IIOOIIOOIIOOIIOO test 1: 1101110111011101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 2: 0101 test 3: 1101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 4: 1001 test 5: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 6: 0101 test 7: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 8: 1001 test 9: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 10: 0101 test 11: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 12: 1001 test 13: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 14: 0101 test 15: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 16: 1001 test 17: 1101 test 18: 1101110111011101 end: END summary column 1: offset 0, mask 0x1000 column 2: offset 0, mask 0x0010 column 3: offset 0, mask 0x0400 column 4: offset 0, mask 0x0200 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0100 column 8: offset 1, mask 0x8000 column 9: offset 1, mask 0x0200 column 10: offset 1, mask 0x0040 column 11: offset 1, mask 0x4000 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x0400 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0800 column 16: offset 1, mask 0x1000 direction bits (1=input) 0xE7E7 0xF99F 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1A18 0xB660 0x0000 0x0000 0x0000 2: 0x0A18 0xB660 0x0000 0x0000 0x0000 3: 0x1A18 0xB660 0x0000 0x0000 0x0000 4: 0x1A08 0xB660 0x0000 0x0000 0x0000 5: 0x1A18 0xB660 0x0000 0x0000 0x0000 6: 0x1218 0xB660 0x0000 0x0000 0x0000 7: 0x1A18 0xB660 0x0000 0x0000 0x0000 8: 0x1A10 0xB660 0x0000 0x0000 0x0000 9: 0x1A18 0xB660 0x0000 0x0000 0x0000 10: 0x1A18 0xB460 0x0000 0x0000 0x0000 11: 0x1A18 0xB660 0x0000 0x0000 0x0000 12: 0x1A18 0xB620 0x0000 0x0000 0x0000 13: 0x1A18 0xB660 0x0000 0x0000 0x0000 14: 0x1A18 0xB260 0x0000 0x0000 0x0000 15: 0x1A18 0xB660 0x0000 0x0000 0x0000 16: 0x1A18 0xB640 0x0000 0x0000 0x0000 17: 0x1A18 0xB660 0x0000 0x0000 0x0000 18: 0x1A18 0xB660 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOOOOOOOOIIG P GII II G P G UUT inputs: 8 UUT outputs: 8 pins used: 16 not used: 50 18 'test steps' 67 lines M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) POSITIVE PULSE ON AF1 OUT-A, NEGATIVE PULSE ON AH1 OUT-A-N PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) POSITIVE PULSE ON AJ1 OUT-B, NEGATIVE PULSE ON AK1 OUT-B-N. PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) POSITIVE PULSE ON AL1 OUT-C, NEGATIVE PULSE ON AM1 OUT-C-N. PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) POSITIVE PULSE ON AP1 OUT-D, NEGATIVE PULSE ON AN1 OUT-D-N. TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE TRIGGER. PINS Main menu Fri Jun 30 18:47:25 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 18:47:28 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 105: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 105, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) source: 0101 changed: 0 step 2 0100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 3 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) source: 1001 changed: 0 step 4 1000110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 5 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) source: 0101 changed: 0 step 6 1100010111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 7 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) source: 1001 changed: 0 step 8 1100100111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 9 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) source: 0101 changed: 0 step 10 1100110101011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 11 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) source: 1001 changed: 0 step 12 1100110110011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 13 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) source: 0101 changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) source: 1001 changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101 changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101110111011101 changed: step 18 1100110111011101 fail ^ test 106: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 106, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO source: 1101110111011101 changed: step 1 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO all fails O was lo 0000000 000 000 falling vv vv vv vv rising ^^ ^^ ^^ ^^ was hi 11 11 111 111 1 total fails 106, total passes 0 Main menu Fri Jun 30 18:57:10 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Fri Jun 30 18:57:11 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Fri Jun 30 18:57:12 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 18:57:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 1: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO all fails O was lo 0000000 000 000 falling vv vv vv vv rising ^^ ^^ ^^ ^^ was hi 11 11 111 111 1 total fails 1, total passes 0 Main menu Fri Jun 30 18:59:20 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0066 Main menu Fri Jun 30 18:59:21 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 18:59:24 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Fri Jun 30 18:59:24 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 18:59:26 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 1: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 2: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 1 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 2 0100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 3 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 4 1000110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 5 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 6 1100010111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 7 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 8 1100100111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 9 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 10 1100110101011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 11 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 12 1100110110011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 13 1100110111011101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 14 1100110111010101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 15 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 0 step 16 1100110111011001 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: 1 step 17 1100110111011101 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO changed: step 18 1100110111011101 fail ^ test 3: *** FAIL *************************** 18 steps failed SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO this fail O all fails O was hi 11 11 111 111 1 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000 000 000 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low 3 O AF1 E1-08 OUTPUT A POSITIVE PULSE 4 O AH1 E1-06 OUTPUT A-N NEGATIVE PULSE 7 O AJ1 E3-08 OUTPUT B POSITIVE PULSE 11 O AL1 E5-08 OUTPUT C POSITIVE PULSE 15 O AP1 E6-06 OUTPUT D POSITIVE PULSE PINS that are always high 8 O AK1 E3-06 OUTPUT B-N NEGATIVE PULSE 12 O AM1 E5-06 OUTPUT C-N NEGATIVE PULSE 16 O AN1 E6-08 OUTPUT D-N NEGATIVE PULSE space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO all fails O was lo 0000000 000 000 falling vv vv vv vv rising ^^ ^^ ^^ ^^ was hi 11 11 111 111 1 total fails 3, total passes 0 Main menu Fri Jun 30 19:01:35 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Fri Jun 30 19:01:44 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 19:01:45 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 59 Main menu Fri Jun 30 19:01:50 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0066 Main menu Fri Jun 30 19:05:24 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 19:05:29 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 19:05:31 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 step 52 00001100011000111000101010100010 step 53 00001100011000111000101110100010 step 54 00001100011000111000100110100010 step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 29: *** FAIL *************************** 24 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail I OO OO OO all fails I OO OO OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 2 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 3 00011000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 4 01011000010000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 step 5 11111000010000100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 6 10111000010000100000110001100011 fail ^^ step 7 11111000010000100000110001100011 step 8 11011000010000100000110001100011 step 9 10011000010000100000110001100011 step 10 00010100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 11 00010100010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 12 00001000010000100000110001100011 fail ^ step 13 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 14 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 15 00001000110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 16 00001010110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 17 00001011110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 18 00001001110000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 19 00001011110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 20 00001010110000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 21 00001000110000100000110001100011 fail ^ step 22 00001100101000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 23 00001000101000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 24 00001000010000100000110001100011 fail ^ step 25 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 26 00001000010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 27 00001000010001100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 01 step 28 00001000010101010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 10 step 29 10001000010111100000110001100011 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 30 10001000010011100000110001100011 fail ^^ step 31 10001000010111100000110001100011 step 32 10001000010101100000110001100011 step 33 10001000010001100000110001100011 step 34 00001100011001010000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 35 00001000010001010000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 36 00001000010000100000110001100011 fail ^ step 37 00001100011000110000110001100011 step 38 00001100011000111000100001000010 step 39 00001100011000111001100001000010 step 40 00001100011000111101010001000010 step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 step 52 00001100011000111000101010100010 step 53 00001100011000111000101110100010 step 54 00001100011000111000100110100010 step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 30: *** FAIL *************************** 24 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail I OO OO OO all fails I OO OO OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 30, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 0 step 2 00001000010000100000110001100011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails I OO OO OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 30, total passes 0 Main menu Fri Jun 30 19:09:24 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 19:09:31 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Fri Jun 30 19:09:34 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 19:09:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 2 00001100010000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 10 step 3 00010100010000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 step 4 01011100010000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 0 step 5 01111000010000100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 6 00111000010000100000110001100011 fail ^ ^^ step 7 11111000010000100000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 1 step 8 11011100010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 9 10010100010000100000110001100011 fail ^^ step 10 00010100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 11 00010100010000100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 01 step 12 00001100010000100000110001100011 fail ^ ^ step 13 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 14 00001100010000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 15 00001100110000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 16 00001110110000100000110001100011 fail ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 17 00001111110000100000110001100011 fail ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 18 00001101110000100000110001100011 fail ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 19 00001111110000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 20 00001110110000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 21 00001100110000100000110001100011 fail ^ ^ step 22 00001100101000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 23 00001100101000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 24 00001100010000100000110001100011 fail ^ ^ step 25 00001100011000110000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 0 step 26 00001100010000100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 27 00001100010001100000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 28 00001100010101100000110001100011 fail ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 1 step 29 10001100010111100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 30 10001100010011100000110001100011 fail ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 1 step 31 10001100010111100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 32 10001100010101100000110001100011 fail ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 33 10001100010001100000110001100011 fail ^ step 34 00001100011001010000110001100011 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 0 step 35 00001100010001010000110001100011 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO changed: 010 step 36 00001100010000100000110001100011 fail ^ ^ step 37 00001100011000110000110001100011 step 38 00001100011000111000100001000010 step 39 00001100011000111001100001000010 step 40 00001100011000111101010001000010 step 41 00001100011000111111010001000010 step 42 00001100011000111011010001000010 step 43 00001100011000111111100001000010 step 44 00001100011000111101100001000010 step 45 00001100011000111001100001000010 step 46 00001100011000110001010001100011 step 47 00001100011000111001010001000010 step 48 00001100011000111000100001000010 step 49 00001100011000110000110001100011 step 50 00001100011000111000100001000010 step 51 00001100011000111000100011000010 step 52 00001100011000111000101010100010 step 53 00001100011000111000101110100010 step 54 00001100011000111000100110100010 step 55 00001100011000111000101111000010 step 56 00001100011000111000101011000010 step 57 00001100011000111000100011000010 step 58 00001100011000110000110010100011 step 59 00001100011000111000100010100010 step 60 00001100011000111000100001000010 step 61 00001100011000110000110001100011 step 62 00001100011000111000100001000010 step 63 00001100011000111000100001000110 step 64 00001100011000111000100001010101 step 65 00001100011000111000100001011101 step 66 00001100011000111000100001001101 step 67 00001100011000111000100001011110 step 68 00001100011000111000100001010110 step 69 00001100011000111000100001000110 step 70 00001100011000110000110001100101 step 71 00001100011000111000100001000101 step 72 00001100011000111000100001000010 step 73 00001100011000110000110001100011 test 1: *** FAIL *************************** 29 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO this fail I OO OO OO all fails I OO OO OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails I OO OO OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 1, total passes 0 Main menu Fri Jun 30 19:11:39 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m212.tst reading test file: tests\m212.tst comment: ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER comment: comment: ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) comment: pins: PINS pins: 1 I AB1 E3-4,10;E6-4,10;E9-4,10 CLEAR-N CLEARS FF0 THRU FF5 pins: 2 I AL2 E1-3 INA0-N pins: 3 I AM2 E2-2 INA1-N pins: 4 I AN2 E4-2 INA2-N pins: 5 I AR2 E5-2 INA3-N pins: 6 I AV1 E7-2 INA4-N pins: 7 I AV2 E8-2 INA5-N pins: 8 I AN1 ENABLE_INPUT_A pins: 9 I AP2 E1-4 INB0-N pins: 10 I AR1 E2-4 INB1-N pins: 11 I AS1 E4-4 INB2-N pins: 12 I AU1 E5-4 INB3-N pins: 13 I AA1 E7-4 INB4-N pins: 14 I AT2 E8-4 INB5-N pins: 15 I AU2 ENABLE_INPUT_B pins: 16 I AM1 E1-1 SHIFT_R_INSERT-N RIGHT SHIFTS INTO FF0 pins: 17 I AL1 ENABLE_R_SHIFT pins: 18 I AS2 E8-9 SHIFT_L_INSERT-N LEFT SHIFTS INTO FF5 pins: 19 I AP1 ENABLE_L_SHIFT pins: 20 I AC1 E3-3,11;E6-3,11;E9-3,11 CLOCK (RISING EDGE) pins: 21 O AD1 E3-6 FF0 pins: 22 O AD2 E3-5 FF0-N pins: 23 O AF1 E3-8 FF1 pins: 24 O AE1 E3-9 FF1-N pins: 25 O AH2 E6-6 FF2 pins: 26 O AE2 E6-5 FF2-N pins: 27 O AH1 E6-8 FF3 pins: 28 O AF2 E6-9 FF3-N pins: 29 O AK2 E9-6 FF4 pins: 30 O AJ2 E9-5 FF4-N pins: 31 O AK1 E9-8 FF5 pins: 32 O AJ1 A9-9 FF5-N pins: direction: IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO comment: ; CLEAR-N, NO ENABLES test 1: 01111110111111010100010101010101 test 2: 1 comment: comment: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM comment: ; see mk_m212_ld_shift.c comment: comment: comment: ; TEST A INPUTS, GRAY CODE PATTERN comment: comment: ; ENABLE A INPUTS test 3: 1 comment: ; LOAD FFs FROM INPUT A comment: test 4: 000001 test 5: 1010101010110 test 6: 0 test 7: 000011 test 8: 1010101011010 test 9: 0 test 10: 000010 test 11: 1010101011001 test 12: 0 test 13: 000110 test 14: 1010101101001 test 15: 0 test 16: 000111 test 17: 1010101101010 test 18: 0 test 19: 000101 test 20: 1010101100110 test 21: 0 test 22: 000100 test 23: 1010101100101 test 24: 0 test 25: 001100 test 26: 1010110100101 test 27: 0 test 28: 001101 test 29: 1010110100110 test 30: 0 test 31: 001111 test 32: 1010110101010 test 33: 0 test 34: 001110 test 35: 1010110101001 test 36: 0 test 37: 001010 test 38: 1010110011001 test 39: 0 test 40: 001011 test 41: 1010110011010 test 42: 0 test 43: 001001 test 44: 1010110010110 test 45: 0 test 46: 001000 test 47: 1010110010101 test 48: 0 test 49: 011000 test 50: 1011010010101 test 51: 0 test 52: 011001 test 53: 1011010010110 test 54: 0 test 55: 011011 test 56: 1011010011010 test 57: 0 test 58: 011010 test 59: 1011010011001 test 60: 0 test 61: 011110 test 62: 1011010101001 test 63: 0 test 64: 011111 test 65: 1011010101010 test 66: 0 test 67: 011101 test 68: 1011010100110 test 69: 0 test 70: 011100 test 71: 1011010100101 test 72: 0 test 73: 010100 test 74: 1011001100101 test 75: 0 test 76: 010101 test 77: 1011001100110 test 78: 0 test 79: 010111 test 80: 1011001101010 test 81: 0 test 82: 010110 test 83: 1011001101001 test 84: 0 test 85: 010010 test 86: 1011001011001 test 87: 0 test 88: 010011 test 89: 1011001011010 test 90: 0 test 91: 010001 test 92: 1011001010110 test 93: 0 test 94: 010000 test 95: 1011001010101 test 96: 0 test 97: 110000 test 98: 1101001010101 test 99: 0 test 100: 110001 test 101: 1101001010110 test 102: 0 test 103: 110011 test 104: 1101001011010 test 105: 0 test 106: 110010 test 107: 1101001011001 test 108: 0 test 109: 110110 test 110: 1101001101001 test 111: 0 test 112: 110111 test 113: 1101001101010 test 114: 0 test 115: 110101 test 116: 1101001100110 test 117: 0 test 118: 110100 test 119: 1101001100101 test 120: 0 test 121: 111100 test 122: 1101010100101 test 123: 0 test 124: 111101 test 125: 1101010100110 test 126: 0 test 127: 111111 test 128: 1101010101010 test 129: 0 test 130: 111110 test 131: 1101010101001 test 132: 0 test 133: 111010 test 134: 1101010011001 test 135: 0 test 136: 111011 test 137: 1101010011010 test 138: 0 test 139: 111001 test 140: 1101010010110 test 141: 0 test 142: 111000 test 143: 1101010010101 test 144: 0 test 145: 101000 test 146: 1100110010101 test 147: 0 test 148: 101001 test 149: 1100110010110 test 150: 0 test 151: 101011 test 152: 1100110011010 test 153: 0 test 154: 101010 test 155: 1100110011001 test 156: 0 test 157: 101110 test 158: 1100110101001 test 159: 0 test 160: 101111 test 161: 1100110101010 test 162: 0 test 163: 101101 test 164: 1100110100110 test 165: 0 test 166: 101100 test 167: 1100110100101 test 168: 0 test 169: 100100 test 170: 1100101100101 test 171: 0 test 172: 100101 test 173: 1100101100110 test 174: 0 test 175: 100111 test 176: 1100101101010 test 177: 0 test 178: 100110 test 179: 1100101101001 test 180: 0 test 181: 100010 test 182: 1100101011001 test 183: 0 test 184: 100011 test 185: 1100101011010 test 186: 0 test 187: 100001 test 188: 1100101010110 test 189: 0 test 190: 100000 test 191: 1100101010101 test 192: 0 test 193: 000000 test 194: 1010101010101 test 195: 0 comment: comment: ; DISABLE A INPUTS test 196: 0 comment: comment: comment: ; TEST B INPUTS comment: comment: ; ENABLE B INPUTS test 197: 1 comment: ; LOAD FFs FROM INPUT B comment: test 198: 000001 test 199: 1010101010110 test 200: 0 test 201: 000011 test 202: 1010101011010 test 203: 0 test 204: 000010 test 205: 1010101011001 test 206: 0 test 207: 000110 test 208: 1010101101001 test 209: 0 test 210: 000111 test 211: 1010101101010 test 212: 0 test 213: 000101 test 214: 1010101100110 test 215: 0 test 216: 000100 test 217: 1010101100101 test 218: 0 test 219: 001100 test 220: 1010110100101 test 221: 0 test 222: 001101 test 223: 1010110100110 test 224: 0 test 225: 001111 test 226: 1010110101010 test 227: 0 test 228: 001110 test 229: 1010110101001 test 230: 0 test 231: 001010 test 232: 1010110011001 test 233: 0 test 234: 001011 test 235: 1010110011010 test 236: 0 test 237: 001001 test 238: 1010110010110 test 239: 0 test 240: 001000 test 241: 1010110010101 test 242: 0 test 243: 011000 test 244: 1011010010101 test 245: 0 test 246: 011001 test 247: 1011010010110 test 248: 0 test 249: 011011 test 250: 1011010011010 test 251: 0 test 252: 011010 test 253: 1011010011001 test 254: 0 test 255: 011110 test 256: 1011010101001 test 257: 0 test 258: 011111 test 259: 1011010101010 test 260: 0 test 261: 011101 test 262: 1011010100110 test 263: 0 test 264: 011100 test 265: 1011010100101 test 266: 0 test 267: 010100 test 268: 1011001100101 test 269: 0 test 270: 010101 test 271: 1011001100110 test 272: 0 test 273: 010111 test 274: 1011001101010 test 275: 0 test 276: 010110 test 277: 1011001101001 test 278: 0 test 279: 010010 test 280: 1011001011001 test 281: 0 test 282: 010011 test 283: 1011001011010 test 284: 0 test 285: 010001 test 286: 1011001010110 test 287: 0 test 288: 010000 test 289: 1011001010101 test 290: 0 test 291: 110000 test 292: 1101001010101 test 293: 0 test 294: 110001 test 295: 1101001010110 test 296: 0 test 297: 110011 test 298: 1101001011010 test 299: 0 test 300: 110010 test 301: 1101001011001 test 302: 0 test 303: 110110 test 304: 1101001101001 test 305: 0 test 306: 110111 test 307: 1101001101010 test 308: 0 test 309: 110101 test 310: 1101001100110 test 311: 0 test 312: 110100 test 313: 1101001100101 test 314: 0 test 315: 111100 test 316: 1101010100101 test 317: 0 test 318: 111101 test 319: 1101010100110 test 320: 0 test 321: 111111 test 322: 1101010101010 test 323: 0 test 324: 111110 test 325: 1101010101001 test 326: 0 test 327: 111010 test 328: 1101010011001 test 329: 0 test 330: 111011 test 331: 1101010011010 test 332: 0 test 333: 111001 test 334: 1101010010110 test 335: 0 test 336: 111000 test 337: 1101010010101 test 338: 0 test 339: 101000 test 340: 1100110010101 test 341: 0 test 342: 101001 test 343: 1100110010110 test 344: 0 test 345: 101011 test 346: 1100110011010 test 347: 0 test 348: 101010 test 349: 1100110011001 test 350: 0 test 351: 101110 test 352: 1100110101001 test 353: 0 test 354: 101111 test 355: 1100110101010 test 356: 0 test 357: 101101 test 358: 1100110100110 test 359: 0 test 360: 101100 test 361: 1100110100101 test 362: 0 test 363: 100100 test 364: 1100101100101 test 365: 0 test 366: 100101 test 367: 1100101100110 test 368: 0 test 369: 100111 test 370: 1100101101010 test 371: 0 test 372: 100110 test 373: 1100101101001 test 374: 0 test 375: 100010 test 376: 1100101011001 test 377: 0 test 378: 100011 test 379: 1100101011010 test 380: 0 test 381: 100001 test 382: 1100101010110 test 383: 0 test 384: 100000 test 385: 1100101010101 test 386: 0 test 387: 000000 test 388: 1010101010101 test 389: 0 comment: comment: ; DISABLE B INPUTS test 390: 0 comment: comment: comment: ; TEST SHIFT R (LOAD VIA A INPUTS) comment: comment: ; SHIFT IN A ZERO test 391: 0 comment: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS comment: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT test 392: 0000011 test 393: 1010101010110 test 394: 0 1 0 test 395: 1010101010101 test 396: 0 0 test 397: 0000111 test 398: 1010101011010 test 399: 0 1 0 test 400: 1010101010110 test 401: 0 0 test 402: 0000101 test 403: 1010101011001 test 404: 0 1 0 test 405: 1010101010110 test 406: 0 0 test 407: 0001101 test 408: 1010101101001 test 409: 0 1 0 test 410: 1010101011010 test 411: 0 0 test 412: 0001111 test 413: 1010101101010 test 414: 0 1 0 test 415: 1010101011010 test 416: 0 0 test 417: 0001011 test 418: 1010101100110 test 419: 0 1 0 test 420: 1010101011001 test 421: 0 0 test 422: 0001001 test 423: 1010101100101 test 424: 0 1 0 test 425: 1010101011001 test 426: 0 0 test 427: 0011001 test 428: 1010110100101 test 429: 0 1 0 test 430: 1010101101001 test 431: 0 0 test 432: 0011011 test 433: 1010110100110 test 434: 0 1 0 test 435: 1010101101001 test 436: 0 0 test 437: 0011111 test 438: 1010110101010 test 439: 0 1 0 test 440: 1010101101010 test 441: 0 0 test 442: 0011101 test 443: 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test 1386: 1010101100101 test 1387: 0 10 test 1388: 1010110010110 test 1389: 00 test 1390: 0011001 test 1391: 1010110100101 test 1392: 0 10 test 1393: 1011010010110 test 1394: 00 test 1395: 0011011 test 1396: 1010110100110 test 1397: 0 10 test 1398: 1011010011010 test 1399: 00 test 1400: 0011111 test 1401: 1010110101010 test 1402: 0 10 test 1403: 1011010101010 test 1404: 00 test 1405: 0011101 test 1406: 1010110101001 test 1407: 0 10 test 1408: 1011010100110 test 1409: 00 test 1410: 0010101 test 1411: 1010110011001 test 1412: 0 10 test 1413: 1011001100110 test 1414: 00 test 1415: 0010111 test 1416: 1010110011010 test 1417: 0 10 test 1418: 1011001101010 test 1419: 00 test 1420: 0010011 test 1421: 1010110010110 test 1422: 0 10 test 1423: 1011001011010 test 1424: 00 test 1425: 0010001 test 1426: 1010110010101 test 1427: 0 10 test 1428: 1011001010110 test 1429: 00 test 1430: 0110001 test 1431: 1011010010101 test 1432: 0 10 test 1433: 1101001010110 test 1434: 00 test 1435: 0110011 test 1436: 1011010010110 test 1437: 0 10 test 1438: 1101001011010 test 1439: 00 test 1440: 0110111 test 1441: 1011010011010 test 1442: 0 10 test 1443: 1101001101010 test 1444: 00 test 1445: 0110101 test 1446: 1011010011001 test 1447: 0 10 test 1448: 1101001100110 test 1449: 00 test 1450: 0111101 test 1451: 1011010101001 test 1452: 0 10 test 1453: 1101010100110 test 1454: 00 test 1455: 0111111 test 1456: 1011010101010 test 1457: 0 10 test 1458: 1101010101010 test 1459: 00 test 1460: 0111011 test 1461: 1011010100110 test 1462: 0 10 test 1463: 1101010011010 test 1464: 00 test 1465: 0111001 test 1466: 1011010100101 test 1467: 0 10 test 1468: 1101010010110 test 1469: 00 test 1470: 0101001 test 1471: 1011001100101 test 1472: 0 10 test 1473: 1100110010110 test 1474: 00 test 1475: 0101011 test 1476: 1011001100110 test 1477: 0 10 test 1478: 1100110011010 test 1479: 00 test 1480: 0101111 test 1481: 1011001101010 test 1482: 0 10 test 1483: 1100110101010 test 1484: 00 test 1485: 0101101 test 1486: 1011001101001 test 1487: 0 10 test 1488: 1100110100110 test 1489: 00 test 1490: 0100101 test 1491: 1011001011001 test 1492: 0 10 test 1493: 1100101100110 test 1494: 00 test 1495: 0100111 test 1496: 1011001011010 test 1497: 0 10 test 1498: 1100101101010 test 1499: 00 test 1500: 0100011 test 1501: 1011001010110 test 1502: 0 10 test 1503: 1100101011010 test 1504: 00 test 1505: 0100001 test 1506: 1011001010101 test 1507: 0 10 test 1508: 1100101010110 test 1509: 00 test 1510: 1100001 test 1511: 1101001010101 test 1512: 0 10 test 1513: 1100101010110 test 1514: 00 test 1515: 1100011 test 1516: 1101001010110 test 1517: 0 10 test 1518: 1100101011010 test 1519: 00 test 1520: 1100111 test 1521: 1101001011010 test 1522: 0 10 test 1523: 1100101101010 test 1524: 00 test 1525: 1100101 test 1526: 1101001011001 test 1527: 0 10 test 1528: 1100101100110 test 1529: 00 test 1530: 1101101 test 1531: 1101001101001 test 1532: 0 10 test 1533: 1100110100110 test 1534: 00 test 1535: 1101111 test 1536: 1101001101010 test 1537: 0 10 test 1538: 1100110101010 test 1539: 00 test 1540: 1101011 test 1541: 1101001100110 test 1542: 0 10 test 1543: 1100110011010 test 1544: 00 test 1545: 1101001 test 1546: 1101001100101 test 1547: 0 10 test 1548: 1100110010110 test 1549: 00 test 1550: 1111001 test 1551: 1101010100101 test 1552: 0 10 test 1553: 1101010010110 test 1554: 00 test 1555: 1111011 test 1556: 1101010100110 test 1557: 0 10 test 1558: 1101010011010 test 1559: 00 test 1560: 1111111 test 1561: 1101010101010 test 1562: 0 10 test 1563: 1101010101010 test 1564: 00 test 1565: 1111101 test 1566: 1101010101001 test 1567: 0 10 test 1568: 1101010100110 test 1569: 00 test 1570: 1110101 test 1571: 1101010011001 test 1572: 0 10 test 1573: 1101001100110 test 1574: 00 test 1575: 1110111 test 1576: 1101010011010 test 1577: 0 10 test 1578: 1101001101010 test 1579: 00 test 1580: 1110011 test 1581: 1101010010110 test 1582: 0 10 test 1583: 1101001011010 test 1584: 00 test 1585: 1110001 test 1586: 1101010010101 test 1587: 0 10 test 1588: 1101001010110 test 1589: 00 test 1590: 1010001 test 1591: 1100110010101 test 1592: 0 10 test 1593: 1011001010110 test 1594: 00 test 1595: 1010011 test 1596: 1100110010110 test 1597: 0 10 test 1598: 1011001011010 test 1599: 00 test 1600: 1010111 test 1601: 1100110011010 test 1602: 0 10 test 1603: 1011001101010 test 1604: 00 test 1605: 1010101 test 1606: 1100110011001 test 1607: 0 10 test 1608: 1011001100110 test 1609: 00 test 1610: 1011101 test 1611: 1100110101001 test 1612: 0 10 test 1613: 1011010100110 test 1614: 00 test 1615: 1011111 test 1616: 1100110101010 test 1617: 0 10 test 1618: 1011010101010 test 1619: 00 test 1620: 1011011 test 1621: 1100110100110 test 1622: 0 10 test 1623: 1011010011010 test 1624: 00 test 1625: 1011001 test 1626: 1100110100101 test 1627: 0 10 test 1628: 1011010010110 test 1629: 00 test 1630: 1001001 test 1631: 1100101100101 test 1632: 0 10 test 1633: 1010110010110 test 1634: 00 test 1635: 1001011 test 1636: 1100101100110 test 1637: 0 10 test 1638: 1010110011010 test 1639: 00 test 1640: 1001111 test 1641: 1100101101010 test 1642: 0 10 test 1643: 1010110101010 test 1644: 00 test 1645: 1001101 test 1646: 1100101101001 test 1647: 0 10 test 1648: 1010110100110 test 1649: 00 test 1650: 1000101 test 1651: 1100101011001 test 1652: 0 10 test 1653: 1010101100110 test 1654: 00 test 1655: 1000111 test 1656: 1100101011010 test 1657: 0 10 test 1658: 1010101101010 test 1659: 00 test 1660: 1000011 test 1661: 1100101010110 test 1662: 0 10 test 1663: 1010101011010 test 1664: 00 test 1665: 1000001 test 1666: 1100101010101 test 1667: 0 10 test 1668: 1010101010110 test 1669: 00 test 1670: 0000001 test 1671: 1010101010101 test 1672: 0 10 test 1673: 1010101010110 test 1674: 00 comment: comment: comment: ; end of SECTION GENERATED BY A PROGRAM comment: comment: comment: ; CLEAR FFs test 1675: 0 010101010101 test 1676: 1 comment: test 1677: 11111110111111010100010101010101 comment: end: END summary column 1: offset 0, mask 0x4000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0020 column 6: offset 2, mask 0x4000 column 7: offset 2, mask 0x0002 column 8: offset 1, mask 0x1000 column 9: offset 1, mask 0x0010 column 10: offset 1, mask 0x0400 column 11: offset 1, mask 0x0200 column 12: offset 2, mask 0x8000 column 13: offset 0, mask 0x8000 column 14: offset 1, mask 0x0080 column 15: offset 2, mask 0x0001 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x4000 column 18: offset 1, mask 0x0040 column 19: offset 1, mask 0x0800 column 20: offset 0, mask 0x2000 column 21: offset 0, mask 0x1000 column 22: offset 0, mask 0x0010 column 23: offset 0, mask 0x0400 column 24: offset 0, mask 0x0800 column 25: offset 0, mask 0x0002 column 26: offset 0, mask 0x0008 column 27: offset 0, mask 0x0200 column 28: offset 0, mask 0x0004 column 29: offset 1, mask 0x0001 column 30: offset 0, mask 0x0001 column 31: offset 1, mask 0x8000 column 32: offset 0, mask 0x0100 direction bits (1=input) 0x1FFF 0x8101 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x891D 0x26FE 0xC002 0x0000 0x0000 2: 0xC91D 0x26FE 0xC002 0x0000 0x0000 3: 0xC91D 0x36FE 0xC002 0x0000 0x0000 4: 0xC91D 0x36D0 0x8002 0x0000 0x0000 5: 0xE81D 0xB6D0 0x8002 0x0000 0x0000 6: 0xC81D 0xB6D0 0x8002 0x0000 0x0000 7: 0xC81D 0xB6D0 0xC002 0x0000 0x0000 8: 0xE81C 0xB6D1 0xC002 0x0000 0x0000 9: 0xC81C 0xB6D1 0xC002 0x0000 0x0000 10: 0xC81C 0xB6D1 0xC000 0x0000 0x0000 11: 0xE91C 0x36D1 0xC000 0x0000 0x0000 12: 0xC91C 0x36D1 0xC000 0x0000 0x0000 13: 0xC91C 0x36F1 0xC000 0x0000 0x0000 14: 0xEB18 0x36F1 0xC000 0x0000 0x0000 15: 0xCB18 0x36F1 0xC000 0x0000 0x0000 16: 0xCB18 0x36F1 0xC002 0x0000 0x0000 17: 0xEA18 0xB6F1 0xC002 0x0000 0x0000 18: 0xCA18 0xB6F1 0xC002 0x0000 0x0000 19: 0xCA18 0xB6F1 0x8002 0x0000 0x0000 20: 0xEA19 0xB6F0 0x8002 0x0000 0x0000 21: 0xCA19 0xB6F0 0x8002 0x0000 0x0000 22: 0xCA19 0xB6F0 0x8000 0x0000 0x0000 23: 0xEB19 0x36F0 0x8000 0x0000 0x0000 24: 0xCB19 0x36F0 0x8000 0x0000 0x0000 25: 0xCB19 0x36F8 0x8000 0x0000 0x0000 26: 0xEB13 0x36F8 0x8000 0x0000 0x0000 27: 0xCB13 0x36F8 0x8000 0x0000 0x0000 28: 0xCB13 0x36F8 0x8002 0x0000 0x0000 29: 0xEA13 0xB6F8 0x8002 0x0000 0x0000 30: 0xCA13 0xB6F8 0x8002 0x0000 0x0000 31: 0xCA13 0xB6F8 0xC002 0x0000 0x0000 32: 0xEA12 0xB6F9 0xC002 0x0000 0x0000 33: 0xCA12 0xB6F9 0xC002 0x0000 0x0000 34: 0xCA12 0xB6F9 0xC000 0x0000 0x0000 35: 0xEB12 0x36F9 0xC000 0x0000 0x0000 36: 0xCB12 0x36F9 0xC000 0x0000 0x0000 37: 0xCB12 0x36D9 0xC000 0x0000 0x0000 38: 0xE916 0x36D9 0xC000 0x0000 0x0000 39: 0xC916 0x36D9 0xC000 0x0000 0x0000 40: 0xC916 0x36D9 0xC002 0x0000 0x0000 41: 0xE816 0xB6D9 0xC002 0x0000 0x0000 42: 0xC816 0xB6D9 0xC002 0x0000 0x0000 43: 0xC816 0xB6D9 0x8002 0x0000 0x0000 44: 0xE817 0xB6D8 0x8002 0x0000 0x0000 45: 0xC817 0xB6D8 0x8002 0x0000 0x0000 46: 0xC817 0xB6D8 0x8000 0x0000 0x0000 47: 0xE917 0x36D8 0x8000 0x0000 0x0000 48: 0xC917 0x36D8 0x8000 0x0000 0x0000 49: 0xC917 0x36DC 0x8000 0x0000 0x0000 50: 0xE517 0x36DC 0x8000 0x0000 0x0000 51: 0xC517 0x36DC 0x8000 0x0000 0x0000 52: 0xC517 0x36DC 0x8002 0x0000 0x0000 53: 0xE417 0xB6DC 0x8002 0x0000 0x0000 54: 0xC417 0xB6DC 0x8002 0x0000 0x0000 55: 0xC417 0xB6DC 0xC002 0x0000 0x0000 56: 0xE416 0xB6DD 0xC002 0x0000 0x0000 57: 0xC416 0xB6DD 0xC002 0x0000 0x0000 58: 0xC416 0xB6DD 0xC000 0x0000 0x0000 59: 0xE516 0x36DD 0xC000 0x0000 0x0000 60: 0xC516 0x36DD 0xC000 0x0000 0x0000 61: 0xC516 0x36FD 0xC000 0x0000 0x0000 62: 0xE712 0x36FD 0xC000 0x0000 0x0000 63: 0xC712 0x36FD 0xC000 0x0000 0x0000 64: 0xC712 0x36FD 0xC002 0x0000 0x0000 65: 0xE612 0xB6FD 0xC002 0x0000 0x0000 66: 0xC612 0xB6FD 0xC002 0x0000 0x0000 67: 0xC612 0xB6FD 0x8002 0x0000 0x0000 68: 0xE613 0xB6FC 0x8002 0x0000 0x0000 69: 0xC613 0xB6FC 0x8002 0x0000 0x0000 70: 0xC613 0xB6FC 0x8000 0x0000 0x0000 71: 0xE713 0x36FC 0x8000 0x0000 0x0000 72: 0xC713 0x36FC 0x8000 0x0000 0x0000 73: 0xC713 0x36F4 0x8000 0x0000 0x0000 74: 0xE719 0x36F4 0x8000 0x0000 0x0000 75: 0xC719 0x36F4 0x8000 0x0000 0x0000 76: 0xC719 0x36F4 0x8002 0x0000 0x0000 77: 0xE619 0xB6F4 0x8002 0x0000 0x0000 78: 0xC619 0xB6F4 0x8002 0x0000 0x0000 79: 0xC619 0xB6F4 0xC002 0x0000 0x0000 80: 0xE618 0xB6F5 0xC002 0x0000 0x0000 81: 0xC618 0xB6F5 0xC002 0x0000 0x0000 82: 0xC618 0xB6F5 0xC000 0x0000 0x0000 83: 0xE718 0x36F5 0xC000 0x0000 0x0000 84: 0xC718 0x36F5 0xC000 0x0000 0x0000 85: 0xC718 0x36D5 0xC000 0x0000 0x0000 86: 0xE51C 0x36D5 0xC000 0x0000 0x0000 87: 0xC51C 0x36D5 0xC000 0x0000 0x0000 88: 0xC51C 0x36D5 0xC002 0x0000 0x0000 89: 0xE41C 0xB6D5 0xC002 0x0000 0x0000 90: 0xC41C 0xB6D5 0xC002 0x0000 0x0000 91: 0xC41C 0xB6D5 0x8002 0x0000 0x0000 92: 0xE41D 0xB6D4 0x8002 0x0000 0x0000 93: 0xC41D 0xB6D4 0x8002 0x0000 0x0000 94: 0xC41D 0xB6D4 0x8000 0x0000 0x0000 95: 0xE51D 0x36D4 0x8000 0x0000 0x0000 96: 0xC51D 0x36D4 0x8000 0x0000 0x0000 97: 0xC51D 0x36D6 0x8000 0x0000 0x0000 98: 0xF50D 0x36D6 0x8000 0x0000 0x0000 99: 0xD50D 0x36D6 0x8000 0x0000 0x0000 100: 0xD50D 0x36D6 0x8002 0x0000 0x0000 101: 0xF40D 0xB6D6 0x8002 0x0000 0x0000 102: 0xD40D 0xB6D6 0x8002 0x0000 0x0000 103: 0xD40D 0xB6D6 0xC002 0x0000 0x0000 104: 0xF40C 0xB6D7 0xC002 0x0000 0x0000 105: 0xD40C 0xB6D7 0xC002 0x0000 0x0000 106: 0xD40C 0xB6D7 0xC000 0x0000 0x0000 107: 0xF50C 0x36D7 0xC000 0x0000 0x0000 108: 0xD50C 0x36D7 0xC000 0x0000 0x0000 109: 0xD50C 0x36F7 0xC000 0x0000 0x0000 110: 0xF708 0x36F7 0xC000 0x0000 0x0000 111: 0xD708 0x36F7 0xC000 0x0000 0x0000 112: 0xD708 0x36F7 0xC002 0x0000 0x0000 113: 0xF608 0xB6F7 0xC002 0x0000 0x0000 114: 0xD608 0xB6F7 0xC002 0x0000 0x0000 115: 0xD608 0xB6F7 0x8002 0x0000 0x0000 116: 0xF609 0xB6F6 0x8002 0x0000 0x0000 117: 0xD609 0xB6F6 0x8002 0x0000 0x0000 118: 0xD609 0xB6F6 0x8000 0x0000 0x0000 119: 0xF709 0x36F6 0x8000 0x0000 0x0000 120: 0xD709 0x36F6 0x8000 0x0000 0x0000 121: 0xD709 0x36FE 0x8000 0x0000 0x0000 122: 0xF703 0x36FE 0x8000 0x0000 0x0000 123: 0xD703 0x36FE 0x8000 0x0000 0x0000 124: 0xD703 0x36FE 0x8002 0x0000 0x0000 125: 0xF603 0xB6FE 0x8002 0x0000 0x0000 126: 0xD603 0xB6FE 0x8002 0x0000 0x0000 127: 0xD603 0xB6FE 0xC002 0x0000 0x0000 128: 0xF602 0xB6FF 0xC002 0x0000 0x0000 129: 0xD602 0xB6FF 0xC002 0x0000 0x0000 130: 0xD602 0xB6FF 0xC000 0x0000 0x0000 131: 0xF702 0x36FF 0xC000 0x0000 0x0000 132: 0xD702 0x36FF 0xC000 0x0000 0x0000 133: 0xD702 0x36DF 0xC000 0x0000 0x0000 134: 0xF506 0x36DF 0xC000 0x0000 0x0000 135: 0xD506 0x36DF 0xC000 0x0000 0x0000 136: 0xD506 0x36DF 0xC002 0x0000 0x0000 137: 0xF406 0xB6DF 0xC002 0x0000 0x0000 138: 0xD406 0xB6DF 0xC002 0x0000 0x0000 139: 0xD406 0xB6DF 0x8002 0x0000 0x0000 140: 0xF407 0xB6DE 0x8002 0x0000 0x0000 141: 0xD407 0xB6DE 0x8002 0x0000 0x0000 142: 0xD407 0xB6DE 0x8000 0x0000 0x0000 143: 0xF507 0x36DE 0x8000 0x0000 0x0000 144: 0xD507 0x36DE 0x8000 0x0000 0x0000 145: 0xD507 0x36DA 0x8000 0x0000 0x0000 146: 0xF907 0x36DA 0x8000 0x0000 0x0000 147: 0xD907 0x36DA 0x8000 0x0000 0x0000 148: 0xD907 0x36DA 0x8002 0x0000 0x0000 149: 0xF807 0xB6DA 0x8002 0x0000 0x0000 150: 0xD807 0xB6DA 0x8002 0x0000 0x0000 151: 0xD807 0xB6DA 0xC002 0x0000 0x0000 152: 0xF806 0xB6DB 0xC002 0x0000 0x0000 153: 0xD806 0xB6DB 0xC002 0x0000 0x0000 154: 0xD806 0xB6DB 0xC000 0x0000 0x0000 155: 0xF906 0x36DB 0xC000 0x0000 0x0000 156: 0xD906 0x36DB 0xC000 0x0000 0x0000 157: 0xD906 0x36FB 0xC000 0x0000 0x0000 158: 0xFB02 0x36FB 0xC000 0x0000 0x0000 159: 0xDB02 0x36FB 0xC000 0x0000 0x0000 160: 0xDB02 0x36FB 0xC002 0x0000 0x0000 161: 0xFA02 0xB6FB 0xC002 0x0000 0x0000 162: 0xDA02 0xB6FB 0xC002 0x0000 0x0000 163: 0xDA02 0xB6FB 0x8002 0x0000 0x0000 164: 0xFA03 0xB6FA 0x8002 0x0000 0x0000 165: 0xDA03 0xB6FA 0x8002 0x0000 0x0000 166: 0xDA03 0xB6FA 0x8000 0x0000 0x0000 167: 0xFB03 0x36FA 0x8000 0x0000 0x0000 168: 0xDB03 0x36FA 0x8000 0x0000 0x0000 169: 0xDB03 0x36F2 0x8000 0x0000 0x0000 170: 0xFB09 0x36F2 0x8000 0x0000 0x0000 171: 0xDB09 0x36F2 0x8000 0x0000 0x0000 172: 0xDB09 0x36F2 0x8002 0x0000 0x0000 173: 0xFA09 0xB6F2 0x8002 0x0000 0x0000 174: 0xDA09 0xB6F2 0x8002 0x0000 0x0000 175: 0xDA09 0xB6F2 0xC002 0x0000 0x0000 176: 0xFA08 0xB6F3 0xC002 0x0000 0x0000 177: 0xDA08 0xB6F3 0xC002 0x0000 0x0000 178: 0xDA08 0xB6F3 0xC000 0x0000 0x0000 179: 0xFB08 0x36F3 0xC000 0x0000 0x0000 180: 0xDB08 0x36F3 0xC000 0x0000 0x0000 181: 0xDB08 0x36D3 0xC000 0x0000 0x0000 182: 0xF90C 0x36D3 0xC000 0x0000 0x0000 183: 0xD90C 0x36D3 0xC000 0x0000 0x0000 184: 0xD90C 0x36D3 0xC002 0x0000 0x0000 185: 0xF80C 0xB6D3 0xC002 0x0000 0x0000 186: 0xD80C 0xB6D3 0xC002 0x0000 0x0000 187: 0xD80C 0xB6D3 0x8002 0x0000 0x0000 188: 0xF80D 0xB6D2 0x8002 0x0000 0x0000 189: 0xD80D 0xB6D2 0x8002 0x0000 0x0000 190: 0xD80D 0xB6D2 0x8000 0x0000 0x0000 191: 0xF90D 0x36D2 0x8000 0x0000 0x0000 192: 0xD90D 0x36D2 0x8000 0x0000 0x0000 193: 0xD90D 0x36D0 0x8000 0x0000 0x0000 194: 0xE91D 0x36D0 0x8000 0x0000 0x0000 195: 0xC91D 0x36D0 0x8000 0x0000 0x0000 196: 0xC91D 0x26D0 0x8000 0x0000 0x0000 197: 0xC91D 0x26D0 0x8001 0x0000 0x0000 198: 0x491D 0x20C0 0x0001 0x0000 0x0000 199: 0x681D 0xA0C0 0x0001 0x0000 0x0000 200: 0x481D 0xA0C0 0x0001 0x0000 0x0000 201: 0xC81D 0xA0C0 0x0001 0x0000 0x0000 202: 0xE81C 0xA0C1 0x0001 0x0000 0x0000 203: 0xC81C 0xA0C1 0x0001 0x0000 0x0000 204: 0xC81C 0xA041 0x0001 0x0000 0x0000 205: 0xE91C 0x2041 0x0001 0x0000 0x0000 206: 0xC91C 0x2041 0x0001 0x0000 0x0000 207: 0xC91C 0x2041 0x8001 0x0000 0x0000 208: 0xEB18 0x2041 0x8001 0x0000 0x0000 209: 0xCB18 0x2041 0x8001 0x0000 0x0000 210: 0xCB18 0x20C1 0x8001 0x0000 0x0000 211: 0xEA18 0xA0C1 0x8001 0x0000 0x0000 212: 0xCA18 0xA0C1 0x8001 0x0000 0x0000 213: 0x4A18 0xA0C1 0x8001 0x0000 0x0000 214: 0x6A19 0xA0C0 0x8001 0x0000 0x0000 215: 0x4A19 0xA0C0 0x8001 0x0000 0x0000 216: 0x4A19 0xA040 0x8001 0x0000 0x0000 217: 0x6B19 0x2040 0x8001 0x0000 0x0000 218: 0x4B19 0x2040 0x8001 0x0000 0x0000 219: 0x4B19 0x2240 0x8001 0x0000 0x0000 220: 0x6B13 0x2240 0x8001 0x0000 0x0000 221: 0x4B13 0x2240 0x8001 0x0000 0x0000 222: 0x4B13 0x22C0 0x8001 0x0000 0x0000 223: 0x6A13 0xA2C0 0x8001 0x0000 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0x0000 1656: 0x780C 0xB043 0x4002 0x0000 0x0000 1657: 0x580C 0xA843 0x4002 0x0000 0x0000 1658: 0x6A18 0xA843 0x4002 0x0000 0x0000 1659: 0x4A18 0xA043 0x4002 0x0000 0x0000 1660: 0x4A18 0xB043 0x0002 0x0000 0x0000 1661: 0x780D 0xB042 0x0002 0x0000 0x0000 1662: 0x580D 0xA842 0x0002 0x0000 0x0000 1663: 0x681C 0xA843 0x0002 0x0000 0x0000 1664: 0x481C 0xA043 0x0002 0x0000 0x0000 1665: 0x481C 0xB043 0x0000 0x0000 0x0000 1666: 0x790D 0x3042 0x0000 0x0000 0x0000 1667: 0x590D 0x2842 0x0000 0x0000 0x0000 1668: 0x681D 0xA842 0x0000 0x0000 0x0000 1669: 0x481D 0xA042 0x0000 0x0000 0x0000 1670: 0x481D 0xB040 0x0000 0x0000 0x0000 1671: 0x691D 0x3040 0x0000 0x0000 0x0000 1672: 0x491D 0x2840 0x0000 0x0000 0x0000 1673: 0x681D 0xA840 0x0000 0x0000 0x0000 1674: 0x481D 0xA040 0x0000 0x0000 0x0000 1675: 0x091D 0x2040 0x0000 0x0000 0x0000 1676: 0x491D 0x2040 0x0000 0x0000 0x0000 1677: 0xC91D 0x26FE 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOOOOOOIIIIIIGIIP GOOOOOOIIIIIIIII G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 1677 'test steps' 1775 lines ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) PINS Main menu Fri Jun 30 19:11:49 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 19:15:44 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 593 11111011000000000101101010100110 step 594 11111010000000001100101010100110 step 595 11111010000000001101011010101001 step 596 11111010000000000100011010101001 step 597 11111111000000000100011010101001 step 598 11111111000000000101101010101010 step 599 11111110000000001100101010101010 step 600 11111110000000001101011010101010 step 601 11111110000000000100011010101010 step 602 11111101000000000100011010101010 step 603 11111101000000000101101010101001 step 604 11111100000000001100101010101001 step 605 11111100000000001101011010101010 step 606 11111100000000000100011010101010 step 607 11110101000000000100011010101010 step 608 11110101000000000101101010011001 step 609 11110100000000001100101010011001 step 610 11110100000000001101011010100110 step 611 11110100000000000100011010100110 step 612 11110111000000000100011010100110 step 613 11110111000000000101101010011010 step 614 11110110000000001100101010011010 step 615 11110110000000001101011010100110 step 616 11110110000000000100011010100110 step 617 11110011000000000100011010100110 step 618 11110011000000000101101010010110 step 619 11110010000000001100101010010110 step 620 11110010000000001101011010100101 step 621 11110010000000000100011010100101 step 622 11110001000000000100011010100101 step 623 11110001000000000101101010010101 step 624 11110000000000001100101010010101 step 625 11110000000000001101011010100101 step 626 11110000000000000100011010100101 step 627 11010001000000000100011010100101 step 628 11010001000000000101100110010101 step 629 11010000000000001100100110010101 step 630 11010000000000001101011001100101 step 631 11010000000000000100011001100101 step 632 11010011000000000100011001100101 step 633 11010011000000000101100110010110 step 634 11010010000000001100100110010110 step 635 11010010000000001101011001100101 step 636 11010010000000000100011001100101 step 637 11010111000000000100011001100101 step 638 11010111000000000101100110011010 step 639 11010110000000001100100110011010 step 640 11010110000000001101011001100110 step 641 11010110000000000100011001100110 step 642 11010101000000000100011001100110 step 643 11010101000000000101100110011001 step 644 11010100000000001100100110011001 step 645 11010100000000001101011001100110 step 646 11010100000000000100011001100110 step 647 11011101000000000100011001100110 step 648 11011101000000000101100110101001 step 649 11011100000000001100100110101001 step 650 11011100000000001101011001101010 step 651 11011100000000000100011001101010 step 652 11011111000000000100011001101010 step 653 11011111000000000101100110101010 step 654 11011110000000001100100110101010 step 655 11011110000000001101011001101010 step 656 11011110000000000100011001101010 step 657 11011011000000000100011001101010 step 658 11011011000000000101100110100110 step 659 11011010000000001100100110100110 step 660 11011010000000001101011001101001 step 661 11011010000000000100011001101001 step 662 11011001000000000100011001101001 step 663 11011001000000000101100110100101 step 664 11011000000000001100100110100101 step 665 11011000000000001101011001101001 step 666 11011000000000000100011001101001 step 667 11001001000000000100011001101001 step 668 11001001000000000101100101100101 step 669 11001000000000001100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 670 11001000000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 671 11001000000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 672 11001011000000000100011001101001 fail ^^ step 673 11001011000000000101100101100110 step 674 11001010000000001100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 675 11001010000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 676 11001010000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 677 11001111000000000100011001101001 fail ^^ step 678 11001111000000000101100101101010 step 679 11001110000000001100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 680 11001110000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 681 11001110000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 682 11001101000000000100011001101010 fail ^^ step 683 11001101000000000101100101101001 step 684 11001100000000001100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 685 11001100000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 686 11001100000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 687 11000101000000000100011001101010 fail ^^ step 688 11000101000000000101100101011001 step 689 11000100000000001100100101011001 step 690 11000100000000001101011001010110 step 691 11000100000000000100011001010110 step 692 11000111000000000100011001010110 step 693 11000111000000000101100101011010 step 694 11000110000000001100100101011010 step 695 11000110000000001101011001010110 step 696 11000110000000000100011001010110 step 697 11000011000000000100011001010110 step 698 11000011000000000101100101010110 step 699 11000010000000001100100101010110 step 700 11000010000000001101011001010101 step 701 11000010000000000100011001010101 step 702 11000001000000000100011001010101 step 703 11000001000000000101100101010101 step 704 11000000000000001100100101010101 step 705 11000000000000001101011001010101 step 706 11000000000000000100011001010101 step 707 10000001000000000100011001010101 step 708 10000001000000000101010101010101 step 709 10000000000000001100010101010101 step 710 10000000000000001101010101010101 step 711 10000000000000000100010101010101 step 712 10000000000000010100010101010101 step 713 10000011000000010100010101010101 step 714 10000011000000010101010101010110 step 715 10000010000000011100010101010110 step 716 10000010000000011101100101010101 step 717 10000010000000010100100101010101 step 718 10000111000000010100100101010101 step 719 10000111000000010101010101011010 step 720 10000110000000011100010101011010 step 721 10000110000000011101100101010110 step 722 10000110000000010100100101010110 step 723 10000101000000010100100101010110 step 724 10000101000000010101010101011001 step 725 10000100000000011100010101011001 step 726 10000100000000011101100101010110 step 727 10000100000000010100100101010110 step 728 10001101000000010100100101010110 step 729 10001101000000010101010101101001 step 730 10001100000000011100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 731 10001100000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 732 10001100000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 733 10001111000000010100100101101010 fail ^^ step 734 10001111000000010101010101101010 step 735 10001110000000011100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 736 10001110000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 737 10001110000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 738 10001011000000010100100101101010 fail ^^ step 739 10001011000000010101010101100110 step 740 10001010000000011100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 741 10001010000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 742 10001010000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 743 10001001000000010100100101101001 fail ^^ step 744 10001001000000010101010101100101 step 745 10001000000000011100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 746 10001000000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 747 10001000000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 748 10011001000000010100100101101001 fail ^^ step 749 10011001000000010101010110100101 step 750 10011000000000011100010110100101 step 751 10011000000000011101100101101001 step 752 10011000000000010100100101101001 step 753 10011011000000010100100101101001 step 754 10011011000000010101010110100110 step 755 10011010000000011100010110100110 step 756 10011010000000011101100101101001 step 757 10011010000000010100100101101001 step 758 10011111000000010100100101101001 step 759 10011111000000010101010110101010 step 760 10011110000000011100010110101010 step 761 10011110000000011101100101101010 step 762 10011110000000010100100101101010 step 763 10011101000000010100100101101010 step 764 10011101000000010101010110101001 step 765 10011100000000011100010110101001 step 766 10011100000000011101100101101010 step 767 10011100000000010100100101101010 step 768 10010101000000010100100101101010 step 769 10010101000000010101010110011001 step 770 10010100000000011100010110011001 step 771 10010100000000011101100101100110 step 772 10010100000000010100100101100110 step 773 10010111000000010100100101100110 step 774 10010111000000010101010110011010 step 775 10010110000000011100010110011010 step 776 10010110000000011101100101100110 step 777 10010110000000010100100101100110 step 778 10010011000000010100100101100110 step 779 10010011000000010101010110010110 step 780 10010010000000011100010110010110 step 781 10010010000000011101100101100101 step 782 10010010000000010100100101100101 step 783 10010001000000010100100101100101 step 784 10010001000000010101010110010101 step 785 10010000000000011100010110010101 step 786 10010000000000011101100101100101 step 787 10010000000000010100100101100101 step 788 10110001000000010100100101100101 step 789 10110001000000010101011010010101 step 790 10110000000000011100011010010101 step 791 10110000000000011101100110100101 step 792 10110000000000010100100110100101 step 793 10110011000000010100100110100101 step 794 10110011000000010101011010010110 step 795 10110010000000011100011010010110 step 796 10110010000000011101100110100101 step 797 10110010000000010100100110100101 step 798 10110111000000010100100110100101 step 799 10110111000000010101011010011010 step 800 10110110000000011100011010011010 step 801 10110110000000011101100110100110 step 802 10110110000000010100100110100110 step 803 10110101000000010100100110100110 step 804 10110101000000010101011010011001 step 805 10110100000000011100011010011001 step 806 10110100000000011101100110100110 step 807 10110100000000010100100110100110 step 808 10111101000000010100100110100110 step 809 10111101000000010101011010101001 step 810 10111100000000011100011010101001 step 811 10111100000000011101100110101010 step 812 10111100000000010100100110101010 step 813 10111111000000010100100110101010 step 814 10111111000000010101011010101010 step 815 10111110000000011100011010101010 step 816 10111110000000011101100110101010 step 817 10111110000000010100100110101010 step 818 10111011000000010100100110101010 step 819 10111011000000010101011010100110 step 820 10111010000000011100011010100110 step 821 10111010000000011101100110101001 step 822 10111010000000010100100110101001 step 823 10111001000000010100100110101001 step 824 10111001000000010101011010100101 step 825 10111000000000011100011010100101 step 826 10111000000000011101100110101001 step 827 10111000000000010100100110101001 step 828 10101001000000010100100110101001 step 829 10101001000000010101011001100101 step 830 10101000000000011100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 831 10101000000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 832 10101000000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 833 10101011000000010100100110101001 fail ^^ step 834 10101011000000010101011001100110 step 835 10101010000000011100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 836 10101010000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 837 10101010000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 838 10101111000000010100100110101001 fail ^^ step 839 10101111000000010101011001101010 step 840 10101110000000011100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 841 10101110000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 842 10101110000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 843 10101101000000010100100110101010 fail ^^ step 844 10101101000000010101011001101001 step 845 10101100000000011100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 846 10101100000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 847 10101100000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 848 10100101000000010100100110101010 fail ^^ step 849 10100101000000010101011001011001 step 850 10100100000000011100011001011001 step 851 10100100000000011101100110010110 step 852 10100100000000010100100110010110 step 853 10100111000000010100100110010110 step 854 10100111000000010101011001011010 step 855 10100110000000011100011001011010 step 856 10100110000000011101100110010110 step 857 10100110000000010100100110010110 step 858 10100011000000010100100110010110 step 859 10100011000000010101011001010110 step 860 10100010000000011100011001010110 step 861 10100010000000011101100110010101 step 862 10100010000000010100100110010101 step 863 10100001000000010100100110010101 step 864 10100001000000010101011001010101 step 865 10100000000000011100011001010101 step 866 10100000000000011101100110010101 step 867 10100000000000010100100110010101 step 868 11100001000000010100100110010101 step 869 11100001000000010101101001010101 step 870 11100000000000011100101001010101 step 871 11100000000000011101101010010101 step 872 11100000000000010100101010010101 step 873 11100011000000010100101010010101 step 874 11100011000000010101101001010110 step 875 11100010000000011100101001010110 step 876 11100010000000011101101010010101 step 877 11100010000000010100101010010101 step 878 11100111000000010100101010010101 step 879 11100111000000010101101001011010 step 880 11100110000000011100101001011010 step 881 11100110000000011101101010010110 step 882 11100110000000010100101010010110 step 883 11100101000000010100101010010110 step 884 11100101000000010101101001011001 step 885 11100100000000011100101001011001 step 886 11100100000000011101101010010110 step 887 11100100000000010100101010010110 step 888 11101101000000010100101010010110 step 889 11101101000000010101101001101001 step 890 11101100000000011100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 891 11101100000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 892 11101100000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 893 11101111000000010100101010101010 fail ^^ step 894 11101111000000010101101001101010 step 895 11101110000000011100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 896 11101110000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 897 11101110000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 898 11101011000000010100101010101010 fail ^^ step 899 11101011000000010101101001100110 step 900 11101010000000011100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 901 11101010000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 902 11101010000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 903 11101001000000010100101010101001 fail ^^ step 904 11101001000000010101101001100101 step 905 11101000000000011100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 906 11101000000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 907 11101000000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 908 11111001000000010100101010101001 fail ^^ step 909 11111001000000010101101010100101 step 910 11111000000000011100101010100101 step 911 11111000000000011101101010101001 step 912 11111000000000010100101010101001 step 913 11111011000000010100101010101001 step 914 11111011000000010101101010100110 step 915 11111010000000011100101010100110 step 916 11111010000000011101101010101001 step 917 11111010000000010100101010101001 step 918 11111111000000010100101010101001 step 919 11111111000000010101101010101010 step 920 11111110000000011100101010101010 step 921 11111110000000011101101010101010 step 922 11111110000000010100101010101010 step 923 11111101000000010100101010101010 step 924 11111101000000010101101010101001 step 925 11111100000000011100101010101001 step 926 11111100000000011101101010101010 step 927 11111100000000010100101010101010 step 928 11110101000000010100101010101010 step 929 11110101000000010101101010011001 step 930 11110100000000011100101010011001 step 931 11110100000000011101101010100110 step 932 11110100000000010100101010100110 step 933 11110111000000010100101010100110 step 934 11110111000000010101101010011010 step 935 11110110000000011100101010011010 step 936 11110110000000011101101010100110 step 937 11110110000000010100101010100110 step 938 11110011000000010100101010100110 step 939 11110011000000010101101010010110 step 940 11110010000000011100101010010110 step 941 11110010000000011101101010100101 step 942 11110010000000010100101010100101 step 943 11110001000000010100101010100101 step 944 11110001000000010101101010010101 step 945 11110000000000011100101010010101 step 946 11110000000000011101101010100101 step 947 11110000000000010100101010100101 step 948 11010001000000010100101010100101 step 949 11010001000000010101100110010101 step 950 11010000000000011100100110010101 step 951 11010000000000011101101001100101 step 952 11010000000000010100101001100101 step 953 11010011000000010100101001100101 step 954 11010011000000010101100110010110 step 955 11010010000000011100100110010110 step 956 11010010000000011101101001100101 step 957 11010010000000010100101001100101 step 958 11010111000000010100101001100101 step 959 11010111000000010101100110011010 step 960 11010110000000011100100110011010 step 961 11010110000000011101101001100110 step 962 11010110000000010100101001100110 step 963 11010101000000010100101001100110 step 964 11010101000000010101100110011001 step 965 11010100000000011100100110011001 step 966 11010100000000011101101001100110 step 967 11010100000000010100101001100110 step 968 11011101000000010100101001100110 step 969 11011101000000010101100110101001 step 970 11011100000000011100100110101001 step 971 11011100000000011101101001101010 step 972 11011100000000010100101001101010 step 973 11011111000000010100101001101010 step 974 11011111000000010101100110101010 step 975 11011110000000011100100110101010 step 976 11011110000000011101101001101010 step 977 11011110000000010100101001101010 step 978 11011011000000010100101001101010 step 979 11011011000000010101100110100110 step 980 11011010000000011100100110100110 step 981 11011010000000011101101001101001 step 982 11011010000000010100101001101001 step 983 11011001000000010100101001101001 step 984 11011001000000010101100110100101 step 985 11011000000000011100100110100101 step 986 11011000000000011101101001101001 step 987 11011000000000010100101001101001 step 988 11001001000000010100101001101001 step 989 11001001000000010101100101100101 step 990 11001000000000011100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 991 11001000000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 992 11001000000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 993 11001011000000010100101001101001 fail ^^ step 994 11001011000000010101100101100110 step 995 11001010000000011100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 996 11001010000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 997 11001010000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 998 11001111000000010100101001101001 fail ^^ step 999 11001111000000010101100101101010 step 1000 11001110000000011100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1001 11001110000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1002 11001110000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1003 11001101000000010100101001101010 fail ^^ step 1004 11001101000000010101100101101001 step 1005 11001100000000011100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1006 11001100000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1007 11001100000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1008 11000101000000010100101001101010 fail ^^ step 1009 11000101000000010101100101011001 step 1010 11000100000000011100100101011001 step 1011 11000100000000011101101001010110 step 1012 11000100000000010100101001010110 step 1013 11000111000000010100101001010110 step 1014 11000111000000010101100101011010 step 1015 11000110000000011100100101011010 step 1016 11000110000000011101101001010110 step 1017 11000110000000010100101001010110 step 1018 11000011000000010100101001010110 step 1019 11000011000000010101100101010110 step 1020 11000010000000011100100101010110 step 1021 11000010000000011101101001010101 step 1022 11000010000000010100101001010101 step 1023 11000001000000010100101001010101 step 1024 11000001000000010101100101010101 step 1025 11000000000000011100100101010101 step 1026 11000000000000011101101001010101 step 1027 11000000000000010100101001010101 step 1028 10000001000000010100101001010101 step 1029 10000001000000010101010101010101 step 1030 10000000000000011100010101010101 step 1031 10000000000000011101100101010101 step 1032 10000000000000010100100101010101 step 1033 10000000000000010000100101010101 step 1034 10000011000000010000100101010101 step 1035 10000011000000010001010101010110 step 1036 10000010000000010010010101010110 step 1037 10000010000000010011010101011001 step 1038 10000010000000010000010101011001 step 1039 10000111000000010000010101011001 step 1040 10000111000000010001010101011010 step 1041 10000110000000010010010101011010 step 1042 10000110000000010011010101101001 step 1043 10000110000000010000010101101001 step 1044 10000101000000010000010101101001 step 1045 10000101000000010001010101011001 step 1046 10000100000000010010010101011001 step 1047 10000100000000010011010101100101 step 1048 10000100000000010000010101100101 step 1049 10001101000000010000010101100101 step 1050 10001101000000010001010101101001 step 1051 10001100000000010010010101101001 step 1052 10001100000000010011010110100101 step 1053 10001100000000010000010110100101 step 1054 10001111000000010000010110100101 step 1055 10001111000000010001010101101010 step 1056 10001110000000010010010101101010 step 1057 10001110000000010011010110101001 step 1058 10001110000000010000010110101001 step 1059 10001011000000010000010110101001 step 1060 10001011000000010001010101100110 step 1061 10001010000000010010010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1062 10001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1063 10001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1064 10001001000000010000010110101001 fail ^^ step 1065 10001001000000010001010101100101 step 1066 10001000000000010010010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1067 10001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1068 10001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1069 10011001000000010000010110100101 fail ^^ step 1070 10011001000000010001010110100101 step 1071 10011000000000010010010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1072 10011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1073 10011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1074 10011011000000010000011010100101 fail ^^ step 1075 10011011000000010001010110100110 step 1076 10011010000000010010010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1077 10011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1078 10011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1079 10011111000000010000011010101001 fail ^^ step 1080 10011111000000010001010110101010 step 1081 10011110000000010010010110101010 step 1082 10011110000000010011011010101001 step 1083 10011110000000010000011010101001 step 1084 10011101000000010000011010101001 step 1085 10011101000000010001010110101001 step 1086 10011100000000010010010110101001 step 1087 10011100000000010011011010100101 step 1088 10011100000000010000011010100101 step 1089 10010101000000010000011010100101 step 1090 10010101000000010001010110011001 step 1091 10010100000000010010010110011001 step 1092 10010100000000010011011001100101 step 1093 10010100000000010000011001100101 step 1094 10010111000000010000011001100101 step 1095 10010111000000010001010110011010 step 1096 10010110000000010010010110011010 step 1097 10010110000000010011011001101001 step 1098 10010110000000010000011001101001 step 1099 10010011000000010000011001101001 step 1100 10010011000000010001010110010110 step 1101 10010010000000010010010110010110 step 1102 10010010000000010011011001011001 step 1103 10010010000000010000011001011001 step 1104 10010001000000010000011001011001 step 1105 10010001000000010001010110010101 step 1106 10010000000000010010010110010101 step 1107 10010000000000010011011001010101 step 1108 10010000000000010000011001010101 step 1109 10110001000000010000011001010101 step 1110 10110001000000010001011010010101 step 1111 10110000000000010010011010010101 step 1112 10110000000000010011101001010101 step 1113 10110000000000010000101001010101 step 1114 10110011000000010000101001010101 step 1115 10110011000000010001011010010110 step 1116 10110010000000010010011010010110 step 1117 10110010000000010011101001011001 step 1118 10110010000000010000101001011001 step 1119 10110111000000010000101001011001 step 1120 10110111000000010001011010011010 step 1121 10110110000000010010011010011010 step 1122 10110110000000010011101001101001 step 1123 10110110000000010000101001101001 step 1124 10110101000000010000101001101001 step 1125 10110101000000010001011010011001 step 1126 10110100000000010010011010011001 step 1127 10110100000000010011101001100101 step 1128 10110100000000010000101001100101 step 1129 10111101000000010000101001100101 step 1130 10111101000000010001011010101001 step 1131 10111100000000010010011010101001 step 1132 10111100000000010011101010100101 step 1133 10111100000000010000101010100101 step 1134 10111111000000010000101010100101 step 1135 10111111000000010001011010101010 step 1136 10111110000000010010011010101010 step 1137 10111110000000010011101010101001 step 1138 10111110000000010000101010101001 step 1139 10111011000000010000101010101001 step 1140 10111011000000010001011010100110 step 1141 10111010000000010010011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 1142 10111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1143 10111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1144 10111001000000010000101010101001 fail ^^ step 1145 10111001000000010001011010100101 step 1146 10111000000000010010011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1147 10111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1148 10111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1149 10101001000000010000101010100101 fail ^^ step 1150 10101001000000010001011001100101 step 1151 10101000000000010010011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 1152 10101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1153 10101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1154 10101011000000010000100110100101 fail ^^ step 1155 10101011000000010001011001100110 step 1156 10101010000000010010011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 1157 10101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1158 10101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1159 10101111000000010000100110101001 fail ^^ step 1160 10101111000000010001011001101010 step 1161 10101110000000010010011001101010 step 1162 10101110000000010011100110101001 step 1163 10101110000000010000100110101001 step 1164 10101101000000010000100110101001 step 1165 10101101000000010001011001101001 step 1166 10101100000000010010011001101001 step 1167 10101100000000010011100110100101 step 1168 10101100000000010000100110100101 step 1169 10100101000000010000100110100101 step 1170 10100101000000010001011001011001 step 1171 10100100000000010010011001011001 step 1172 10100100000000010011100101100101 step 1173 10100100000000010000100101100101 step 1174 10100111000000010000100101100101 step 1175 10100111000000010001011001011010 step 1176 10100110000000010010011001011010 step 1177 10100110000000010011100101101001 step 1178 10100110000000010000100101101001 step 1179 10100011000000010000100101101001 step 1180 10100011000000010001011001010110 step 1181 10100010000000010010011001010110 step 1182 10100010000000010011100101011001 step 1183 10100010000000010000100101011001 step 1184 10100001000000010000100101011001 step 1185 10100001000000010001011001010101 step 1186 10100000000000010010011001010101 step 1187 10100000000000010011100101010101 step 1188 10100000000000010000100101010101 step 1189 11100001000000010000100101010101 step 1190 11100001000000010001101001010101 step 1191 11100000000000010010101001010101 step 1192 11100000000000010011100101010101 step 1193 11100000000000010000100101010101 step 1194 11100011000000010000100101010101 step 1195 11100011000000010001101001010110 step 1196 11100010000000010010101001010110 step 1197 11100010000000010011100101011001 step 1198 11100010000000010000100101011001 step 1199 11100111000000010000100101011001 step 1200 11100111000000010001101001011010 step 1201 11100110000000010010101001011010 step 1202 11100110000000010011100101101001 step 1203 11100110000000010000100101101001 step 1204 11100101000000010000100101101001 step 1205 11100101000000010001101001011001 step 1206 11100100000000010010101001011001 step 1207 11100100000000010011100101100101 step 1208 11100100000000010000100101100101 step 1209 11101101000000010000100101100101 step 1210 11101101000000010001101001101001 step 1211 11101100000000010010101001101001 step 1212 11101100000000010011100110100101 step 1213 11101100000000010000100110100101 step 1214 11101111000000010000100110100101 step 1215 11101111000000010001101001101010 step 1216 11101110000000010010101001101010 step 1217 11101110000000010011100110101001 step 1218 11101110000000010000100110101001 step 1219 11101011000000010000100110101001 step 1220 11101011000000010001101001100110 step 1221 11101010000000010010101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 1001 step 1222 11101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1223 11101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1224 11101001000000010000100110101001 fail ^^ step 1225 11101001000000010001101001100101 step 1226 11101000000000010010101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1227 11101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1228 11101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1229 11111001000000010000100110100101 fail ^^ step 1230 11111001000000010001101010100101 step 1231 11111000000000010010101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1232 11111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1233 11111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1234 11111011000000010000101010100101 fail ^^ step 1235 11111011000000010001101010100110 step 1236 11111010000000010010101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 1237 11111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1238 11111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1239 11111111000000010000101010101001 fail ^^ step 1240 11111111000000010001101010101010 step 1241 11111110000000010010101010101010 step 1242 11111110000000010011101010101001 step 1243 11111110000000010000101010101001 step 1244 11111101000000010000101010101001 step 1245 11111101000000010001101010101001 step 1246 11111100000000010010101010101001 step 1247 11111100000000010011101010100101 step 1248 11111100000000010000101010100101 step 1249 11110101000000010000101010100101 step 1250 11110101000000010001101010011001 step 1251 11110100000000010010101010011001 step 1252 11110100000000010011101001100101 step 1253 11110100000000010000101001100101 step 1254 11110111000000010000101001100101 step 1255 11110111000000010001101010011010 step 1256 11110110000000010010101010011010 step 1257 11110110000000010011101001101001 step 1258 11110110000000010000101001101001 step 1259 11110011000000010000101001101001 step 1260 11110011000000010001101010010110 step 1261 11110010000000010010101010010110 step 1262 11110010000000010011101001011001 step 1263 11110010000000010000101001011001 step 1264 11110001000000010000101001011001 step 1265 11110001000000010001101010010101 step 1266 11110000000000010010101010010101 step 1267 11110000000000010011101001010101 step 1268 11110000000000010000101001010101 step 1269 11010001000000010000101001010101 step 1270 11010001000000010001100110010101 step 1271 11010000000000010010100110010101 step 1272 11010000000000010011011001010101 step 1273 11010000000000010000011001010101 step 1274 11010011000000010000011001010101 step 1275 11010011000000010001100110010110 step 1276 11010010000000010010100110010110 step 1277 11010010000000010011011001011001 step 1278 11010010000000010000011001011001 step 1279 11010111000000010000011001011001 step 1280 11010111000000010001100110011010 step 1281 11010110000000010010100110011010 step 1282 11010110000000010011011001101001 step 1283 11010110000000010000011001101001 step 1284 11010101000000010000011001101001 step 1285 11010101000000010001100110011001 step 1286 11010100000000010010100110011001 step 1287 11010100000000010011011001100101 step 1288 11010100000000010000011001100101 step 1289 11011101000000010000011001100101 step 1290 11011101000000010001100110101001 step 1291 11011100000000010010100110101001 step 1292 11011100000000010011011010100101 step 1293 11011100000000010000011010100101 step 1294 11011111000000010000011010100101 step 1295 11011111000000010001100110101010 step 1296 11011110000000010010100110101010 step 1297 11011110000000010011011010101001 step 1298 11011110000000010000011010101001 step 1299 11011011000000010000011010101001 step 1300 11011011000000010001100110100110 step 1301 11011010000000010010100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 1302 11011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1303 11011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1304 11011001000000010000011010101001 fail ^^ step 1305 11011001000000010001100110100101 step 1306 11011000000000010010100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 1307 11011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1308 11011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1309 11001001000000010000011010100101 fail ^^ step 1310 11001001000000010001100101100101 step 1311 11001000000000010010100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 1312 11001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1313 11001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1314 11001011000000010000010110100101 fail ^^ step 1315 11001011000000010001100101100110 step 1316 11001010000000010010100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 1001 step 1317 11001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1318 11001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1319 11001111000000010000010110101001 fail ^^ step 1320 11001111000000010001100101101010 step 1321 11001110000000010010100101101010 step 1322 11001110000000010011010110101001 step 1323 11001110000000010000010110101001 step 1324 11001101000000010000010110101001 step 1325 11001101000000010001100101101001 step 1326 11001100000000010010100101101001 step 1327 11001100000000010011010110100101 step 1328 11001100000000010000010110100101 step 1329 11000101000000010000010110100101 step 1330 11000101000000010001100101011001 step 1331 11000100000000010010100101011001 step 1332 11000100000000010011010101100101 step 1333 11000100000000010000010101100101 step 1334 11000111000000010000010101100101 step 1335 11000111000000010001100101011010 step 1336 11000110000000010010100101011010 step 1337 11000110000000010011010101101001 step 1338 11000110000000010000010101101001 step 1339 11000011000000010000010101101001 step 1340 11000011000000010001100101010110 step 1341 11000010000000010010100101010110 step 1342 11000010000000010011010101011001 step 1343 11000010000000010000010101011001 step 1344 11000001000000010000010101011001 step 1345 11000001000000010001100101010101 step 1346 11000000000000010010100101010101 step 1347 11000000000000010011010101010101 step 1348 11000000000000010000010101010101 step 1349 10000001000000010000010101010101 step 1350 10000001000000010001010101010101 step 1351 10000000000000010010010101010101 step 1352 10000000000000010011010101010101 step 1353 10000000000000010000010101010101 step 1354 10000000000000010100010101010101 step 1355 10000011000000010100010101010101 step 1356 10000011000000010101010101010110 step 1357 10000010000000010110010101010110 step 1358 10000010000000010111010101011010 step 1359 10000010000000010100010101011010 step 1360 10000111000000010100010101011010 step 1361 10000111000000010101010101011010 step 1362 10000110000000010110010101011010 step 1363 10000110000000010111010101101010 step 1364 10000110000000010100010101101010 step 1365 10000101000000010100010101101010 step 1366 10000101000000010101010101011001 step 1367 10000100000000010110010101011001 step 1368 10000100000000010111010101100110 step 1369 10000100000000010100010101100110 step 1370 10001101000000010100010101100110 step 1371 10001101000000010101010101101001 step 1372 10001100000000010110010101101001 step 1373 10001100000000010111010110100110 step 1374 10001100000000010100010110100110 step 1375 10001111000000010100010110100110 step 1376 10001111000000010101010101101010 step 1377 10001110000000010110010101101010 step 1378 10001110000000010111010110101010 step 1379 10001110000000010100010110101010 step 1380 10001011000000010100010110101010 step 1381 10001011000000010101010101100110 step 1382 10001010000000010110010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1383 10001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1384 10001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1385 10001001000000010100010110101010 fail ^^ step 1386 10001001000000010101010101100101 step 1387 10001000000000010110010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1388 10001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1389 10001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1390 10011001000000010100010110100110 fail ^^ step 1391 10011001000000010101010110100101 step 1392 10011000000000010110010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1393 10011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1394 10011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1395 10011011000000010100011010100110 fail ^^ step 1396 10011011000000010101010110100110 step 1397 10011010000000010110010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1398 10011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1399 10011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1400 10011111000000010100011010101010 fail ^^ step 1401 10011111000000010101010110101010 step 1402 10011110000000010110010110101010 step 1403 10011110000000010111011010101010 step 1404 10011110000000010100011010101010 step 1405 10011101000000010100011010101010 step 1406 10011101000000010101010110101001 step 1407 10011100000000010110010110101001 step 1408 10011100000000010111011010100110 step 1409 10011100000000010100011010100110 step 1410 10010101000000010100011010100110 step 1411 10010101000000010101010110011001 step 1412 10010100000000010110010110011001 step 1413 10010100000000010111011001100110 step 1414 10010100000000010100011001100110 step 1415 10010111000000010100011001100110 step 1416 10010111000000010101010110011010 step 1417 10010110000000010110010110011010 step 1418 10010110000000010111011001101010 step 1419 10010110000000010100011001101010 step 1420 10010011000000010100011001101010 step 1421 10010011000000010101010110010110 step 1422 10010010000000010110010110010110 step 1423 10010010000000010111011001011010 step 1424 10010010000000010100011001011010 step 1425 10010001000000010100011001011010 step 1426 10010001000000010101010110010101 step 1427 10010000000000010110010110010101 step 1428 10010000000000010111011001010110 step 1429 10010000000000010100011001010110 step 1430 10110001000000010100011001010110 step 1431 10110001000000010101011010010101 step 1432 10110000000000010110011010010101 step 1433 10110000000000010111101001010110 step 1434 10110000000000010100101001010110 step 1435 10110011000000010100101001010110 step 1436 10110011000000010101011010010110 step 1437 10110010000000010110011010010110 step 1438 10110010000000010111101001011010 step 1439 10110010000000010100101001011010 step 1440 10110111000000010100101001011010 step 1441 10110111000000010101011010011010 step 1442 10110110000000010110011010011010 step 1443 10110110000000010111101001101010 step 1444 10110110000000010100101001101010 step 1445 10110101000000010100101001101010 step 1446 10110101000000010101011010011001 step 1447 10110100000000010110011010011001 step 1448 10110100000000010111101001100110 step 1449 10110100000000010100101001100110 step 1450 10111101000000010100101001100110 step 1451 10111101000000010101011010101001 step 1452 10111100000000010110011010101001 step 1453 10111100000000010111101010100110 step 1454 10111100000000010100101010100110 step 1455 10111111000000010100101010100110 step 1456 10111111000000010101011010101010 step 1457 10111110000000010110011010101010 step 1458 10111110000000010111101010101010 step 1459 10111110000000010100101010101010 step 1460 10111011000000010100101010101010 step 1461 10111011000000010101011010100110 step 1462 10111010000000010110011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1463 10111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1464 10111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1465 10111001000000010100101010101010 fail ^^ step 1466 10111001000000010101011010100101 step 1467 10111000000000010110011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1468 10111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1469 10111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1470 10101001000000010100101010100110 fail ^^ step 1471 10101001000000010101011001100101 step 1472 10101000000000010110011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1473 10101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1474 10101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1475 10101011000000010100100110100110 fail ^^ step 1476 10101011000000010101011001100110 step 1477 10101010000000010110011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1478 10101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1479 10101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1480 10101111000000010100100110101010 fail ^^ step 1481 10101111000000010101011001101010 step 1482 10101110000000010110011001101010 step 1483 10101110000000010111100110101010 step 1484 10101110000000010100100110101010 step 1485 10101101000000010100100110101010 step 1486 10101101000000010101011001101001 step 1487 10101100000000010110011001101001 step 1488 10101100000000010111100110100110 step 1489 10101100000000010100100110100110 step 1490 10100101000000010100100110100110 step 1491 10100101000000010101011001011001 step 1492 10100100000000010110011001011001 step 1493 10100100000000010111100101100110 step 1494 10100100000000010100100101100110 step 1495 10100111000000010100100101100110 step 1496 10100111000000010101011001011010 step 1497 10100110000000010110011001011010 step 1498 10100110000000010111100101101010 step 1499 10100110000000010100100101101010 step 1500 10100011000000010100100101101010 step 1501 10100011000000010101011001010110 step 1502 10100010000000010110011001010110 step 1503 10100010000000010111100101011010 step 1504 10100010000000010100100101011010 step 1505 10100001000000010100100101011010 step 1506 10100001000000010101011001010101 step 1507 10100000000000010110011001010101 step 1508 10100000000000010111100101010110 step 1509 10100000000000010100100101010110 step 1510 11100001000000010100100101010110 step 1511 11100001000000010101101001010101 step 1512 11100000000000010110101001010101 step 1513 11100000000000010111100101010110 step 1514 11100000000000010100100101010110 step 1515 11100011000000010100100101010110 step 1516 11100011000000010101101001010110 step 1517 11100010000000010110101001010110 step 1518 11100010000000010111100101011010 step 1519 11100010000000010100100101011010 step 1520 11100111000000010100100101011010 step 1521 11100111000000010101101001011010 step 1522 11100110000000010110101001011010 step 1523 11100110000000010111100101101010 step 1524 11100110000000010100100101101010 step 1525 11100101000000010100100101101010 step 1526 11100101000000010101101001011001 step 1527 11100100000000010110101001011001 step 1528 11100100000000010111100101100110 step 1529 11100100000000010100100101100110 step 1530 11101101000000010100100101100110 step 1531 11101101000000010101101001101001 step 1532 11101100000000010110101001101001 step 1533 11101100000000010111100110100110 step 1534 11101100000000010100100110100110 step 1535 11101111000000010100100110100110 step 1536 11101111000000010101101001101010 step 1537 11101110000000010110101001101010 step 1538 11101110000000010111100110101010 step 1539 11101110000000010100100110101010 step 1540 11101011000000010100100110101010 step 1541 11101011000000010101101001100110 step 1542 11101010000000010110101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1543 11101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1544 11101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1545 11101001000000010100100110101010 fail ^^ step 1546 11101001000000010101101001100101 step 1547 11101000000000010110101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1548 11101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1549 11101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1550 11111001000000010100100110100110 fail ^^ step 1551 11111001000000010101101010100101 step 1552 11111000000000010110101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1553 11111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1554 11111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1555 11111011000000010100101010100110 fail ^^ step 1556 11111011000000010101101010100110 step 1557 11111010000000010110101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1558 11111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1559 11111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1560 11111111000000010100101010101010 fail ^^ step 1561 11111111000000010101101010101010 step 1562 11111110000000010110101010101010 step 1563 11111110000000010111101010101010 step 1564 11111110000000010100101010101010 step 1565 11111101000000010100101010101010 step 1566 11111101000000010101101010101001 step 1567 11111100000000010110101010101001 step 1568 11111100000000010111101010100110 step 1569 11111100000000010100101010100110 step 1570 11110101000000010100101010100110 step 1571 11110101000000010101101010011001 step 1572 11110100000000010110101010011001 step 1573 11110100000000010111101001100110 step 1574 11110100000000010100101001100110 step 1575 11110111000000010100101001100110 step 1576 11110111000000010101101010011010 step 1577 11110110000000010110101010011010 step 1578 11110110000000010111101001101010 step 1579 11110110000000010100101001101010 step 1580 11110011000000010100101001101010 step 1581 11110011000000010101101010010110 step 1582 11110010000000010110101010010110 step 1583 11110010000000010111101001011010 step 1584 11110010000000010100101001011010 step 1585 11110001000000010100101001011010 step 1586 11110001000000010101101010010101 step 1587 11110000000000010110101010010101 step 1588 11110000000000010111101001010110 step 1589 11110000000000010100101001010110 step 1590 11010001000000010100101001010110 step 1591 11010001000000010101100110010101 step 1592 11010000000000010110100110010101 step 1593 11010000000000010111011001010110 step 1594 11010000000000010100011001010110 step 1595 11010011000000010100011001010110 step 1596 11010011000000010101100110010110 step 1597 11010010000000010110100110010110 step 1598 11010010000000010111011001011010 step 1599 11010010000000010100011001011010 step 1600 11010111000000010100011001011010 step 1601 11010111000000010101100110011010 step 1602 11010110000000010110100110011010 step 1603 11010110000000010111011001101010 step 1604 11010110000000010100011001101010 step 1605 11010101000000010100011001101010 step 1606 11010101000000010101100110011001 step 1607 11010100000000010110100110011001 step 1608 11010100000000010111011001100110 step 1609 11010100000000010100011001100110 step 1610 11011101000000010100011001100110 step 1611 11011101000000010101100110101001 step 1612 11011100000000010110100110101001 step 1613 11011100000000010111011010100110 step 1614 11011100000000010100011010100110 step 1615 11011111000000010100011010100110 step 1616 11011111000000010101100110101010 step 1617 11011110000000010110100110101010 step 1618 11011110000000010111011010101010 step 1619 11011110000000010100011010101010 step 1620 11011011000000010100011010101010 step 1621 11011011000000010101100110100110 step 1622 11011010000000010110100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1623 11011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1624 11011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1625 11011001000000010100011010101010 fail ^^ step 1626 11011001000000010101100110100101 step 1627 11011000000000010110100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1628 11011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1629 11011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1630 11001001000000010100011010100110 fail ^^ step 1631 11001001000000010101100101100101 step 1632 11001000000000010110100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1633 11001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1634 11001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1635 11001011000000010100010110100110 fail ^^ step 1636 11001011000000010101100101100110 step 1637 11001010000000010110100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1638 11001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1639 11001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1640 11001111000000010100010110101010 fail ^^ step 1641 11001111000000010101100101101010 step 1642 11001110000000010110100101101010 step 1643 11001110000000010111010110101010 step 1644 11001110000000010100010110101010 step 1645 11001101000000010100010110101010 step 1646 11001101000000010101100101101001 step 1647 11001100000000010110100101101001 step 1648 11001100000000010111010110100110 step 1649 11001100000000010100010110100110 step 1650 11000101000000010100010110100110 step 1651 11000101000000010101100101011001 step 1652 11000100000000010110100101011001 step 1653 11000100000000010111010101100110 step 1654 11000100000000010100010101100110 step 1655 11000111000000010100010101100110 step 1656 11000111000000010101100101011010 step 1657 11000110000000010110100101011010 step 1658 11000110000000010111010101101010 step 1659 11000110000000010100010101101010 step 1660 11000011000000010100010101101010 step 1661 11000011000000010101100101010110 step 1662 11000010000000010110100101010110 step 1663 11000010000000010111010101011010 step 1664 11000010000000010100010101011010 step 1665 11000001000000010100010101011010 step 1666 11000001000000010101100101010101 step 1667 11000000000000010110100101010101 step 1668 11000000000000010111010101010110 step 1669 11000000000000010100010101010110 step 1670 10000001000000010100010101010110 step 1671 10000001000000010101010101010101 step 1672 10000000000000010110010101010101 step 1673 10000000000000010111010101010110 step 1674 10000000000000010100010101010110 step 1675 00000000000000010100010101010101 step 1676 10000000000000010100010101010101 step 1677 11111110111111010100010101010101 test 6: *** FAIL *************************** 192 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 6, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 01111110111111010100010101010101 step 2 11111110111111010100010101010101 step 3 11111111111111010100010101010101 step 4 10000011111111010100010101010101 step 5 10000011111111010101010101010110 step 6 10000011111111010100010101010110 step 7 10000111111111010100010101010110 step 8 10000111111111010101010101011010 step 9 10000111111111010100010101011010 step 10 10000101111111010100010101011010 step 11 10000101111111010101010101011001 step 12 10000101111111010100010101011001 step 13 10001101111111010100010101011001 step 14 10001101111111010101010101101001 step 15 10001101111111010100010101101001 step 16 10001111111111010100010101101001 step 17 10001111111111010101010101101010 step 18 10001111111111010100010101101010 step 19 10001011111111010100010101101010 step 20 10001011111111010101010101100110 step 21 10001011111111010100010101100110 step 22 10001001111111010100010101100110 step 23 10001001111111010101010101100101 step 24 10001001111111010100010101100101 step 25 10011001111111010100010101100101 step 26 10011001111111010101010110100101 step 27 10011001111111010100010110100101 step 28 10011011111111010100010110100101 step 29 10011011111111010101010110100110 step 30 10011011111111010100010110100110 step 31 10011111111111010100010110100110 step 32 10011111111111010101010110101010 step 33 10011111111111010100010110101010 step 34 10011101111111010100010110101010 step 35 10011101111111010101010110101001 step 36 10011101111111010100010110101001 step 37 10010101111111010100010110101001 step 38 10010101111111010101010110011001 step 39 10010101111111010100010110011001 step 40 10010111111111010100010110011001 step 41 10010111111111010101010110011010 step 42 10010111111111010100010110011010 step 43 10010011111111010100010110011010 step 44 10010011111111010101010110010110 step 45 10010011111111010100010110010110 step 46 10010001111111010100010110010110 step 47 10010001111111010101010110010101 step 48 10010001111111010100010110010101 step 49 10110001111111010100010110010101 step 50 10110001111111010101011010010101 step 51 10110001111111010100011010010101 step 52 10110011111111010100011010010101 step 53 10110011111111010101011010010110 step 54 10110011111111010100011010010110 step 55 10110111111111010100011010010110 step 56 10110111111111010101011010011010 step 57 10110111111111010100011010011010 step 58 10110101111111010100011010011010 step 59 10110101111111010101011010011001 step 60 10110101111111010100011010011001 step 61 10111101111111010100011010011001 step 62 10111101111111010101011010101001 step 63 10111101111111010100011010101001 step 64 10111111111111010100011010101001 step 65 10111111111111010101011010101010 step 66 10111111111111010100011010101010 step 67 10111011111111010100011010101010 step 68 10111011111111010101011010100110 step 69 10111011111111010100011010100110 step 70 10111001111111010100011010100110 step 71 10111001111111010101011010100101 step 72 10111001111111010100011010100101 step 73 10101001111111010100011010100101 step 74 10101001111111010101011001100101 step 75 10101001111111010100011001100101 step 76 10101011111111010100011001100101 step 77 10101011111111010101011001100110 step 78 10101011111111010100011001100110 step 79 10101111111111010100011001100110 step 80 10101111111111010101011001101010 step 81 10101111111111010100011001101010 step 82 10101101111111010100011001101010 step 83 10101101111111010101011001101001 step 84 10101101111111010100011001101001 step 85 10100101111111010100011001101001 step 86 10100101111111010101011001011001 step 87 10100101111111010100011001011001 step 88 10100111111111010100011001011001 step 89 10100111111111010101011001011010 step 90 10100111111111010100011001011010 step 91 10100011111111010100011001011010 step 92 10100011111111010101011001010110 step 93 10100011111111010100011001010110 step 94 10100001111111010100011001010110 step 95 10100001111111010101011001010101 step 96 10100001111111010100011001010101 step 97 11100001111111010100011001010101 step 98 11100001111111010101101001010101 step 99 11100001111111010100101001010101 step 100 11100011111111010100101001010101 step 101 11100011111111010101101001010110 step 102 11100011111111010100101001010110 step 103 11100111111111010100101001010110 step 104 11100111111111010101101001011010 step 105 11100111111111010100101001011010 step 106 11100101111111010100101001011010 step 107 11100101111111010101101001011001 step 108 11100101111111010100101001011001 step 109 11101101111111010100101001011001 step 110 11101101111111010101101001101001 step 111 11101101111111010100101001101001 step 112 11101111111111010100101001101001 step 113 11101111111111010101101001101010 step 114 11101111111111010100101001101010 step 115 11101011111111010100101001101010 step 116 11101011111111010101101001100110 step 117 11101011111111010100101001100110 step 118 11101001111111010100101001100110 step 119 11101001111111010101101001100101 step 120 11101001111111010100101001100101 step 121 11111001111111010100101001100101 step 122 11111001111111010101101010100101 step 123 11111001111111010100101010100101 step 124 11111011111111010100101010100101 step 125 11111011111111010101101010100110 step 126 11111011111111010100101010100110 step 127 11111111111111010100101010100110 step 128 11111111111111010101101010101010 step 129 11111111111111010100101010101010 step 130 11111101111111010100101010101010 step 131 11111101111111010101101010101001 step 132 11111101111111010100101010101001 step 133 11110101111111010100101010101001 step 134 11110101111111010101101010011001 step 135 11110101111111010100101010011001 step 136 11110111111111010100101010011001 step 137 11110111111111010101101010011010 step 138 11110111111111010100101010011010 step 139 11110011111111010100101010011010 step 140 11110011111111010101101010010110 step 141 11110011111111010100101010010110 step 142 11110001111111010100101010010110 step 143 11110001111111010101101010010101 step 144 11110001111111010100101010010101 step 145 11010001111111010100101010010101 step 146 11010001111111010101100110010101 step 147 11010001111111010100100110010101 step 148 11010011111111010100100110010101 step 149 11010011111111010101100110010110 step 150 11010011111111010100100110010110 step 151 11010111111111010100100110010110 step 152 11010111111111010101100110011010 step 153 11010111111111010100100110011010 step 154 11010101111111010100100110011010 step 155 11010101111111010101100110011001 step 156 11010101111111010100100110011001 step 157 11011101111111010100100110011001 step 158 11011101111111010101100110101001 step 159 11011101111111010100100110101001 step 160 11011111111111010100100110101001 step 161 11011111111111010101100110101010 step 162 11011111111111010100100110101010 step 163 11011011111111010100100110101010 step 164 11011011111111010101100110100110 step 165 11011011111111010100100110100110 step 166 11011001111111010100100110100110 step 167 11011001111111010101100110100101 step 168 11011001111111010100100110100101 step 169 11001001111111010100100110100101 step 170 11001001111111010101100101100101 step 171 11001001111111010100100101100101 step 172 11001011111111010100100101100101 step 173 11001011111111010101100101100110 step 174 11001011111111010100100101100110 step 175 11001111111111010100100101100110 step 176 11001111111111010101100101101010 step 177 11001111111111010100100101101010 step 178 11001101111111010100100101101010 step 179 11001101111111010101100101101001 step 180 11001101111111010100100101101001 step 181 11000101111111010100100101101001 step 182 11000101111111010101100101011001 step 183 11000101111111010100100101011001 step 184 11000111111111010100100101011001 step 185 11000111111111010101100101011010 step 186 11000111111111010100100101011010 step 187 11000011111111010100100101011010 step 188 11000011111111010101100101010110 step 189 11000011111111010100100101010110 step 190 11000001111111010100100101010110 step 191 11000001111111010101100101010101 step 192 11000001111111010100100101010101 step 193 10000001111111010100100101010101 step 194 10000001111111010101010101010101 step 195 10000001111111010100010101010101 step 196 10000000111111010100010101010101 step 197 10000000111111110100010101010101 step 198 10000000000001110100010101010101 step 199 10000000000001110101010101010110 step 200 10000000000001110100010101010110 step 201 10000000000011110100010101010110 step 202 10000000000011110101010101011010 step 203 10000000000011110100010101011010 step 204 10000000000010110100010101011010 step 205 10000000000010110101010101011001 step 206 10000000000010110100010101011001 step 207 10000000000110110100010101011001 step 208 10000000000110110101010101101001 step 209 10000000000110110100010101101001 step 210 10000000000111110100010101101001 step 211 10000000000111110101010101101010 step 212 10000000000111110100010101101010 step 213 10000000000101110100010101101010 step 214 10000000000101110101010101100110 step 215 10000000000101110100010101100110 step 216 10000000000100110100010101100110 step 217 10000000000100110101010101100101 step 218 10000000000100110100010101100101 step 219 10000000001100110100010101100101 step 220 10000000001100110101010110100101 step 221 10000000001100110100010110100101 step 222 10000000001101110100010110100101 step 223 10000000001101110101010110100110 step 224 10000000001101110100010110100110 step 225 10000000001111110100010110100110 step 226 10000000001111110101010110101010 step 227 10000000001111110100010110101010 step 228 10000000001110110100010110101010 step 229 10000000001110110101010110101001 step 230 10000000001110110100010110101001 step 231 10000000001010110100010110101001 step 232 10000000001010110101010110011001 step 233 10000000001010110100010110011001 step 234 10000000001011110100010110011001 step 235 10000000001011110101010110011010 step 236 10000000001011110100010110011010 step 237 10000000001001110100010110011010 step 238 10000000001001110101010110010110 step 239 10000000001001110100010110010110 step 240 10000000001000110100010110010110 step 241 10000000001000110101010110010101 step 242 10000000001000110100010110010101 step 243 10000000011000110100010110010101 step 244 10000000011000110101011010010101 step 245 10000000011000110100011010010101 step 246 10000000011001110100011010010101 step 247 10000000011001110101011010010110 step 248 10000000011001110100011010010110 step 249 10000000011011110100011010010110 step 250 10000000011011110101011010011010 step 251 10000000011011110100011010011010 step 252 10000000011010110100011010011010 step 253 10000000011010110101011010011001 step 254 10000000011010110100011010011001 step 255 10000000011110110100011010011001 step 256 10000000011110110101011010101001 step 257 10000000011110110100011010101001 step 258 10000000011111110100011010101001 step 259 10000000011111110101011010101010 step 260 10000000011111110100011010101010 step 261 10000000011101110100011010101010 step 262 10000000011101110101011010100110 step 263 10000000011101110100011010100110 step 264 10000000011100110100011010100110 step 265 10000000011100110101011010100101 step 266 10000000011100110100011010100101 step 267 10000000010100110100011010100101 step 268 10000000010100110101011001100101 step 269 10000000010100110100011001100101 step 270 10000000010101110100011001100101 step 271 10000000010101110101011001100110 step 272 10000000010101110100011001100110 step 273 10000000010111110100011001100110 step 274 10000000010111110101011001101010 step 275 10000000010111110100011001101010 step 276 10000000010110110100011001101010 step 277 10000000010110110101011001101001 step 278 10000000010110110100011001101001 step 279 10000000010010110100011001101001 step 280 10000000010010110101011001011001 step 281 10000000010010110100011001011001 step 282 10000000010011110100011001011001 step 283 10000000010011110101011001011010 step 284 10000000010011110100011001011010 step 285 10000000010001110100011001011010 step 286 10000000010001110101011001010110 step 287 10000000010001110100011001010110 step 288 10000000010000110100011001010110 step 289 10000000010000110101011001010101 step 290 10000000010000110100011001010101 step 291 10000000110000110100011001010101 step 292 10000000110000110101101001010101 step 293 10000000110000110100101001010101 step 294 10000000110001110100101001010101 step 295 10000000110001110101101001010110 step 296 10000000110001110100101001010110 step 297 10000000110011110100101001010110 step 298 10000000110011110101101001011010 step 299 10000000110011110100101001011010 step 300 10000000110010110100101001011010 step 301 10000000110010110101101001011001 step 302 10000000110010110100101001011001 step 303 10000000110110110100101001011001 step 304 10000000110110110101101001101001 step 305 10000000110110110100101001101001 step 306 10000000110111110100101001101001 step 307 10000000110111110101101001101010 step 308 10000000110111110100101001101010 step 309 10000000110101110100101001101010 step 310 10000000110101110101101001100110 step 311 10000000110101110100101001100110 step 312 10000000110100110100101001100110 step 313 10000000110100110101101001100101 step 314 10000000110100110100101001100101 step 315 10000000111100110100101001100101 step 316 10000000111100110101101010100101 step 317 10000000111100110100101010100101 step 318 10000000111101110100101010100101 step 319 10000000111101110101101010100110 step 320 10000000111101110100101010100110 step 321 10000000111111110100101010100110 step 322 10000000111111110101101010101010 step 323 10000000111111110100101010101010 step 324 10000000111110110100101010101010 step 325 10000000111110110101101010101001 step 326 10000000111110110100101010101001 step 327 10000000111010110100101010101001 step 328 10000000111010110101101010011001 step 329 10000000111010110100101010011001 step 330 10000000111011110100101010011001 step 331 10000000111011110101101010011010 step 332 10000000111011110100101010011010 step 333 10000000111001110100101010011010 step 334 10000000111001110101101010010110 step 335 10000000111001110100101010010110 step 336 10000000111000110100101010010110 step 337 10000000111000110101101010010101 step 338 10000000111000110100101010010101 step 339 10000000101000110100101010010101 step 340 10000000101000110101100110010101 step 341 10000000101000110100100110010101 step 342 10000000101001110100100110010101 step 343 10000000101001110101100110010110 step 344 10000000101001110100100110010110 step 345 10000000101011110100100110010110 step 346 10000000101011110101100110011010 step 347 10000000101011110100100110011010 step 348 10000000101010110100100110011010 step 349 10000000101010110101100110011001 step 350 10000000101010110100100110011001 step 351 10000000101110110100100110011001 step 352 10000000101110110101100110101001 step 353 10000000101110110100100110101001 step 354 10000000101111110100100110101001 step 355 10000000101111110101100110101010 step 356 10000000101111110100100110101010 step 357 10000000101101110100100110101010 step 358 10000000101101110101100110100110 step 359 10000000101101110100100110100110 step 360 10000000101100110100100110100110 step 361 10000000101100110101100110100101 step 362 10000000101100110100100110100101 step 363 10000000100100110100100110100101 step 364 10000000100100110101100101100101 step 365 10000000100100110100100101100101 step 366 10000000100101110100100101100101 step 367 10000000100101110101100101100110 step 368 10000000100101110100100101100110 step 369 10000000100111110100100101100110 step 370 10000000100111110101100101101010 step 371 10000000100111110100100101101010 step 372 10000000100110110100100101101010 step 373 10000000100110110101100101101001 step 374 10000000100110110100100101101001 step 375 10000000100010110100100101101001 step 376 10000000100010110101100101011001 step 377 10000000100010110100100101011001 step 378 10000000100011110100100101011001 step 379 10000000100011110101100101011010 step 380 10000000100011110100100101011010 step 381 10000000100001110100100101011010 step 382 10000000100001110101100101010110 step 383 10000000100001110100100101010110 step 384 10000000100000110100100101010110 step 385 10000000100000110101100101010101 step 386 10000000100000110100100101010101 step 387 10000000000000110100100101010101 step 388 10000000000000110101010101010101 step 389 10000000000000110100010101010101 step 390 10000000000000010100010101010101 step 391 10000000000000000100010101010101 step 392 10000011000000000100010101010101 step 393 10000011000000000101010101010110 step 394 10000010000000001100010101010110 step 395 10000010000000001101010101010101 step 396 10000010000000000100010101010101 step 397 10000111000000000100010101010101 step 398 10000111000000000101010101011010 step 399 10000110000000001100010101011010 step 400 10000110000000001101010101010110 step 401 10000110000000000100010101010110 step 402 10000101000000000100010101010110 step 403 10000101000000000101010101011001 step 404 10000100000000001100010101011001 step 405 10000100000000001101010101010110 step 406 10000100000000000100010101010110 step 407 10001101000000000100010101010110 step 408 10001101000000000101010101101001 step 409 10001100000000001100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 410 10001100000000001101010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 411 10001100000000000100010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 412 10001111000000000100010101101010 fail ^^ step 413 10001111000000000101010101101010 step 414 10001110000000001100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 415 10001110000000001101010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 416 10001110000000000100010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 417 10001011000000000100010101101010 fail ^^ step 418 10001011000000000101010101100110 step 419 10001010000000001100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 420 10001010000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 421 10001010000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 422 10001001000000000100010101101001 fail ^^ step 423 10001001000000000101010101100101 step 424 10001000000000001100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 425 10001000000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 426 10001000000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 427 10011001000000000100010101101001 fail ^^ step 428 10011001000000000101010110100101 step 429 10011000000000001100010110100101 step 430 10011000000000001101010101101001 step 431 10011000000000000100010101101001 step 432 10011011000000000100010101101001 step 433 10011011000000000101010110100110 step 434 10011010000000001100010110100110 step 435 10011010000000001101010101101001 step 436 10011010000000000100010101101001 step 437 10011111000000000100010101101001 step 438 10011111000000000101010110101010 step 439 10011110000000001100010110101010 step 440 10011110000000001101010101101010 step 441 10011110000000000100010101101010 step 442 10011101000000000100010101101010 step 443 10011101000000000101010110101001 step 444 10011100000000001100010110101001 step 445 10011100000000001101010101101010 step 446 10011100000000000100010101101010 step 447 10010101000000000100010101101010 step 448 10010101000000000101010110011001 step 449 10010100000000001100010110011001 step 450 10010100000000001101010101100110 step 451 10010100000000000100010101100110 step 452 10010111000000000100010101100110 step 453 10010111000000000101010110011010 step 454 10010110000000001100010110011010 step 455 10010110000000001101010101100110 step 456 10010110000000000100010101100110 step 457 10010011000000000100010101100110 step 458 10010011000000000101010110010110 step 459 10010010000000001100010110010110 step 460 10010010000000001101010101100101 step 461 10010010000000000100010101100101 step 462 10010001000000000100010101100101 step 463 10010001000000000101010110010101 step 464 10010000000000001100010110010101 step 465 10010000000000001101010101100101 step 466 10010000000000000100010101100101 step 467 10110001000000000100010101100101 step 468 10110001000000000101011010010101 step 469 10110000000000001100011010010101 step 470 10110000000000001101010110100101 step 471 10110000000000000100010110100101 step 472 10110011000000000100010110100101 step 473 10110011000000000101011010010110 step 474 10110010000000001100011010010110 step 475 10110010000000001101010110100101 step 476 10110010000000000100010110100101 step 477 10110111000000000100010110100101 step 478 10110111000000000101011010011010 step 479 10110110000000001100011010011010 step 480 10110110000000001101010110100110 step 481 10110110000000000100010110100110 step 482 10110101000000000100010110100110 step 483 10110101000000000101011010011001 step 484 10110100000000001100011010011001 step 485 10110100000000001101010110100110 step 486 10110100000000000100010110100110 step 487 10111101000000000100010110100110 step 488 10111101000000000101011010101001 step 489 10111100000000001100011010101001 step 490 10111100000000001101010110101010 step 491 10111100000000000100010110101010 step 492 10111111000000000100010110101010 step 493 10111111000000000101011010101010 step 494 10111110000000001100011010101010 step 495 10111110000000001101010110101010 step 496 10111110000000000100010110101010 step 497 10111011000000000100010110101010 step 498 10111011000000000101011010100110 step 499 10111010000000001100011010100110 step 500 10111010000000001101010110101001 step 501 10111010000000000100010110101001 step 502 10111001000000000100010110101001 step 503 10111001000000000101011010100101 step 504 10111000000000001100011010100101 step 505 10111000000000001101010110101001 step 506 10111000000000000100010110101001 step 507 10101001000000000100010110101001 step 508 10101001000000000101011001100101 step 509 10101000000000001100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 510 10101000000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 511 10101000000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 512 10101011000000000100010110101001 fail ^^ step 513 10101011000000000101011001100110 step 514 10101010000000001100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 1001 step 515 10101010000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 516 10101010000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 517 10101111000000000100010110101001 fail ^^ step 518 10101111000000000101011001101010 step 519 10101110000000001100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 520 10101110000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 521 10101110000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 522 10101101000000000100010110101010 fail ^^ step 523 10101101000000000101011001101001 step 524 10101100000000001100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 525 10101100000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 526 10101100000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 527 10100101000000000100010110101010 fail ^^ step 528 10100101000000000101011001011001 step 529 10100100000000001100011001011001 step 530 10100100000000001101010110010110 step 531 10100100000000000100010110010110 step 532 10100111000000000100010110010110 step 533 10100111000000000101011001011010 step 534 10100110000000001100011001011010 step 535 10100110000000001101010110010110 step 536 10100110000000000100010110010110 step 537 10100011000000000100010110010110 step 538 10100011000000000101011001010110 step 539 10100010000000001100011001010110 step 540 10100010000000001101010110010101 step 541 10100010000000000100010110010101 step 542 10100001000000000100010110010101 step 543 10100001000000000101011001010101 step 544 10100000000000001100011001010101 step 545 10100000000000001101010110010101 step 546 10100000000000000100010110010101 step 547 11100001000000000100010110010101 step 548 11100001000000000101101001010101 step 549 11100000000000001100101001010101 step 550 11100000000000001101011010010101 step 551 11100000000000000100011010010101 step 552 11100011000000000100011010010101 step 553 11100011000000000101101001010110 step 554 11100010000000001100101001010110 step 555 11100010000000001101011010010101 step 556 11100010000000000100011010010101 step 557 11100111000000000100011010010101 step 558 11100111000000000101101001011010 step 559 11100110000000001100101001011010 step 560 11100110000000001101011010010110 step 561 11100110000000000100011010010110 step 562 11100101000000000100011010010110 step 563 11100101000000000101101001011001 step 564 11100100000000001100101001011001 step 565 11100100000000001101011010010110 step 566 11100100000000000100011010010110 step 567 11101101000000000100011010010110 step 568 11101101000000000101101001101001 step 569 11101100000000001100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 570 11101100000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 571 11101100000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 572 11101111000000000100011010101010 fail ^^ step 573 11101111000000000101101001101010 step 574 11101110000000001100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 575 11101110000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 576 11101110000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 577 11101011000000000100011010101010 fail ^^ step 578 11101011000000000101101001100110 step 579 11101010000000001100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 1001 step 580 11101010000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 581 11101010000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 582 11101001000000000100011010101001 fail ^^ step 583 11101001000000000101101001100101 step 584 11101000000000001100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 585 11101000000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 586 11101000000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 587 11111001000000000100011010101001 fail ^^ step 588 11111001000000000101101010100101 step 589 11111000000000001100101010100101 step 590 11111000000000001101011010101001 step 591 11111000000000000100011010101001 step 592 11111011000000000100011010101001 step 593 11111011000000000101101010100110 step 594 11111010000000001100101010100110 step 595 11111010000000001101011010101001 step 596 11111010000000000100011010101001 step 597 11111111000000000100011010101001 step 598 11111111000000000101101010101010 step 599 11111110000000001100101010101010 step 600 11111110000000001101011010101010 step 601 11111110000000000100011010101010 step 602 11111101000000000100011010101010 step 603 11111101000000000101101010101001 step 604 11111100000000001100101010101001 step 605 11111100000000001101011010101010 step 606 11111100000000000100011010101010 step 607 11110101000000000100011010101010 step 608 11110101000000000101101010011001 step 609 11110100000000001100101010011001 step 610 11110100000000001101011010100110 step 611 11110100000000000100011010100110 step 612 11110111000000000100011010100110 step 613 11110111000000000101101010011010 step 614 11110110000000001100101010011010 step 615 11110110000000001101011010100110 step 616 11110110000000000100011010100110 step 617 11110011000000000100011010100110 step 618 11110011000000000101101010010110 step 619 11110010000000001100101010010110 step 620 11110010000000001101011010100101 step 621 11110010000000000100011010100101 step 622 11110001000000000100011010100101 step 623 11110001000000000101101010010101 step 624 11110000000000001100101010010101 step 625 11110000000000001101011010100101 step 626 11110000000000000100011010100101 step 627 11010001000000000100011010100101 step 628 11010001000000000101100110010101 step 629 11010000000000001100100110010101 step 630 11010000000000001101011001100101 step 631 11010000000000000100011001100101 step 632 11010011000000000100011001100101 step 633 11010011000000000101100110010110 step 634 11010010000000001100100110010110 step 635 11010010000000001101011001100101 step 636 11010010000000000100011001100101 step 637 11010111000000000100011001100101 step 638 11010111000000000101100110011010 step 639 11010110000000001100100110011010 step 640 11010110000000001101011001100110 step 641 11010110000000000100011001100110 step 642 11010101000000000100011001100110 step 643 11010101000000000101100110011001 step 644 11010100000000001100100110011001 step 645 11010100000000001101011001100110 step 646 11010100000000000100011001100110 step 647 11011101000000000100011001100110 step 648 11011101000000000101100110101001 step 649 11011100000000001100100110101001 step 650 11011100000000001101011001101010 step 651 11011100000000000100011001101010 step 652 11011111000000000100011001101010 step 653 11011111000000000101100110101010 step 654 11011110000000001100100110101010 step 655 11011110000000001101011001101010 step 656 11011110000000000100011001101010 step 657 11011011000000000100011001101010 step 658 11011011000000000101100110100110 step 659 11011010000000001100100110100110 step 660 11011010000000001101011001101001 step 661 11011010000000000100011001101001 step 662 11011001000000000100011001101001 step 663 11011001000000000101100110100101 step 664 11011000000000001100100110100101 step 665 11011000000000001101011001101001 step 666 11011000000000000100011001101001 step 667 11001001000000000100011001101001 step 668 11001001000000000101100101100101 step 669 11001000000000001100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 670 11001000000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 671 11001000000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 672 11001011000000000100011001101001 fail ^^ step 673 11001011000000000101100101100110 step 674 11001010000000001100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 675 11001010000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 676 11001010000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 677 11001111000000000100011001101001 fail ^^ step 678 11001111000000000101100101101010 step 679 11001110000000001100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 680 11001110000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 681 11001110000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 682 11001101000000000100011001101010 fail ^^ step 683 11001101000000000101100101101001 step 684 11001100000000001100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 685 11001100000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 686 11001100000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 687 11000101000000000100011001101010 fail ^^ step 688 11000101000000000101100101011001 step 689 11000100000000001100100101011001 step 690 11000100000000001101011001010110 step 691 11000100000000000100011001010110 step 692 11000111000000000100011001010110 step 693 11000111000000000101100101011010 step 694 11000110000000001100100101011010 step 695 11000110000000001101011001010110 step 696 11000110000000000100011001010110 step 697 11000011000000000100011001010110 step 698 11000011000000000101100101010110 step 699 11000010000000001100100101010110 step 700 11000010000000001101011001010101 step 701 11000010000000000100011001010101 step 702 11000001000000000100011001010101 step 703 11000001000000000101100101010101 step 704 11000000000000001100100101010101 step 705 11000000000000001101011001010101 step 706 11000000000000000100011001010101 step 707 10000001000000000100011001010101 step 708 10000001000000000101010101010101 step 709 10000000000000001100010101010101 step 710 10000000000000001101010101010101 step 711 10000000000000000100010101010101 step 712 10000000000000010100010101010101 step 713 10000011000000010100010101010101 step 714 10000011000000010101010101010110 step 715 10000010000000011100010101010110 step 716 10000010000000011101100101010101 step 717 10000010000000010100100101010101 step 718 10000111000000010100100101010101 step 719 10000111000000010101010101011010 step 720 10000110000000011100010101011010 step 721 10000110000000011101100101010110 step 722 10000110000000010100100101010110 step 723 10000101000000010100100101010110 step 724 10000101000000010101010101011001 step 725 10000100000000011100010101011001 step 726 10000100000000011101100101010110 step 727 10000100000000010100100101010110 step 728 10001101000000010100100101010110 step 729 10001101000000010101010101101001 step 730 10001100000000011100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 731 10001100000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 732 10001100000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 733 10001111000000010100100101101010 fail ^^ step 734 10001111000000010101010101101010 step 735 10001110000000011100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 736 10001110000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 737 10001110000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 738 10001011000000010100100101101010 fail ^^ step 739 10001011000000010101010101100110 step 740 10001010000000011100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 741 10001010000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 742 10001010000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 743 10001001000000010100100101101001 fail ^^ step 744 10001001000000010101010101100101 step 745 10001000000000011100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 746 10001000000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 747 10001000000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 748 10011001000000010100100101101001 fail ^^ step 749 10011001000000010101010110100101 step 750 10011000000000011100010110100101 step 751 10011000000000011101100101101001 step 752 10011000000000010100100101101001 step 753 10011011000000010100100101101001 step 754 10011011000000010101010110100110 step 755 10011010000000011100010110100110 step 756 10011010000000011101100101101001 step 757 10011010000000010100100101101001 step 758 10011111000000010100100101101001 step 759 10011111000000010101010110101010 step 760 10011110000000011100010110101010 step 761 10011110000000011101100101101010 step 762 10011110000000010100100101101010 step 763 10011101000000010100100101101010 step 764 10011101000000010101010110101001 step 765 10011100000000011100010110101001 step 766 10011100000000011101100101101010 step 767 10011100000000010100100101101010 step 768 10010101000000010100100101101010 step 769 10010101000000010101010110011001 step 770 10010100000000011100010110011001 step 771 10010100000000011101100101100110 step 772 10010100000000010100100101100110 step 773 10010111000000010100100101100110 step 774 10010111000000010101010110011010 step 775 10010110000000011100010110011010 step 776 10010110000000011101100101100110 step 777 10010110000000010100100101100110 step 778 10010011000000010100100101100110 step 779 10010011000000010101010110010110 step 780 10010010000000011100010110010110 step 781 10010010000000011101100101100101 step 782 10010010000000010100100101100101 step 783 10010001000000010100100101100101 step 784 10010001000000010101010110010101 step 785 10010000000000011100010110010101 step 786 10010000000000011101100101100101 step 787 10010000000000010100100101100101 step 788 10110001000000010100100101100101 step 789 10110001000000010101011010010101 step 790 10110000000000011100011010010101 step 791 10110000000000011101100110100101 step 792 10110000000000010100100110100101 step 793 10110011000000010100100110100101 step 794 10110011000000010101011010010110 step 795 10110010000000011100011010010110 step 796 10110010000000011101100110100101 step 797 10110010000000010100100110100101 step 798 10110111000000010100100110100101 step 799 10110111000000010101011010011010 step 800 10110110000000011100011010011010 step 801 10110110000000011101100110100110 step 802 10110110000000010100100110100110 step 803 10110101000000010100100110100110 step 804 10110101000000010101011010011001 step 805 10110100000000011100011010011001 step 806 10110100000000011101100110100110 step 807 10110100000000010100100110100110 step 808 10111101000000010100100110100110 step 809 10111101000000010101011010101001 step 810 10111100000000011100011010101001 step 811 10111100000000011101100110101010 step 812 10111100000000010100100110101010 step 813 10111111000000010100100110101010 step 814 10111111000000010101011010101010 step 815 10111110000000011100011010101010 step 816 10111110000000011101100110101010 step 817 10111110000000010100100110101010 step 818 10111011000000010100100110101010 step 819 10111011000000010101011010100110 step 820 10111010000000011100011010100110 step 821 10111010000000011101100110101001 step 822 10111010000000010100100110101001 step 823 10111001000000010100100110101001 step 824 10111001000000010101011010100101 step 825 10111000000000011100011010100101 step 826 10111000000000011101100110101001 step 827 10111000000000010100100110101001 step 828 10101001000000010100100110101001 step 829 10101001000000010101011001100101 step 830 10101000000000011100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 831 10101000000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 832 10101000000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 833 10101011000000010100100110101001 fail ^^ step 834 10101011000000010101011001100110 step 835 10101010000000011100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 836 10101010000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 837 10101010000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 838 10101111000000010100100110101001 fail ^^ step 839 10101111000000010101011001101010 step 840 10101110000000011100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 841 10101110000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 842 10101110000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 843 10101101000000010100100110101010 fail ^^ step 844 10101101000000010101011001101001 step 845 10101100000000011100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 846 10101100000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 847 10101100000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 848 10100101000000010100100110101010 fail ^^ step 849 10100101000000010101011001011001 step 850 10100100000000011100011001011001 step 851 10100100000000011101100110010110 step 852 10100100000000010100100110010110 step 853 10100111000000010100100110010110 step 854 10100111000000010101011001011010 step 855 10100110000000011100011001011010 step 856 10100110000000011101100110010110 step 857 10100110000000010100100110010110 step 858 10100011000000010100100110010110 step 859 10100011000000010101011001010110 step 860 10100010000000011100011001010110 step 861 10100010000000011101100110010101 step 862 10100010000000010100100110010101 step 863 10100001000000010100100110010101 step 864 10100001000000010101011001010101 step 865 10100000000000011100011001010101 step 866 10100000000000011101100110010101 step 867 10100000000000010100100110010101 step 868 11100001000000010100100110010101 step 869 11100001000000010101101001010101 step 870 11100000000000011100101001010101 step 871 11100000000000011101101010010101 step 872 11100000000000010100101010010101 step 873 11100011000000010100101010010101 step 874 11100011000000010101101001010110 step 875 11100010000000011100101001010110 step 876 11100010000000011101101010010101 step 877 11100010000000010100101010010101 step 878 11100111000000010100101010010101 step 879 11100111000000010101101001011010 step 880 11100110000000011100101001011010 step 881 11100110000000011101101010010110 step 882 11100110000000010100101010010110 step 883 11100101000000010100101010010110 step 884 11100101000000010101101001011001 step 885 11100100000000011100101001011001 step 886 11100100000000011101101010010110 step 887 11100100000000010100101010010110 step 888 11101101000000010100101010010110 step 889 11101101000000010101101001101001 step 890 11101100000000011100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 891 11101100000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 892 11101100000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 893 11101111000000010100101010101010 fail ^^ step 894 11101111000000010101101001101010 step 895 11101110000000011100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 896 11101110000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 897 11101110000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 898 11101011000000010100101010101010 fail ^^ step 899 11101011000000010101101001100110 step 900 11101010000000011100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 901 11101010000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 902 11101010000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 903 11101001000000010100101010101001 fail ^^ step 904 11101001000000010101101001100101 step 905 11101000000000011100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 906 11101000000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 907 11101000000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 908 11111001000000010100101010101001 fail ^^ step 909 11111001000000010101101010100101 step 910 11111000000000011100101010100101 step 911 11111000000000011101101010101001 step 912 11111000000000010100101010101001 step 913 11111011000000010100101010101001 step 914 11111011000000010101101010100110 step 915 11111010000000011100101010100110 step 916 11111010000000011101101010101001 step 917 11111010000000010100101010101001 step 918 11111111000000010100101010101001 step 919 11111111000000010101101010101010 step 920 11111110000000011100101010101010 step 921 11111110000000011101101010101010 step 922 11111110000000010100101010101010 step 923 11111101000000010100101010101010 step 924 11111101000000010101101010101001 step 925 11111100000000011100101010101001 step 926 11111100000000011101101010101010 step 927 11111100000000010100101010101010 step 928 11110101000000010100101010101010 step 929 11110101000000010101101010011001 step 930 11110100000000011100101010011001 step 931 11110100000000011101101010100110 step 932 11110100000000010100101010100110 step 933 11110111000000010100101010100110 step 934 11110111000000010101101010011010 step 935 11110110000000011100101010011010 step 936 11110110000000011101101010100110 step 937 11110110000000010100101010100110 step 938 11110011000000010100101010100110 step 939 11110011000000010101101010010110 step 940 11110010000000011100101010010110 step 941 11110010000000011101101010100101 step 942 11110010000000010100101010100101 step 943 11110001000000010100101010100101 step 944 11110001000000010101101010010101 step 945 11110000000000011100101010010101 step 946 11110000000000011101101010100101 step 947 11110000000000010100101010100101 step 948 11010001000000010100101010100101 step 949 11010001000000010101100110010101 step 950 11010000000000011100100110010101 step 951 11010000000000011101101001100101 step 952 11010000000000010100101001100101 step 953 11010011000000010100101001100101 step 954 11010011000000010101100110010110 step 955 11010010000000011100100110010110 step 956 11010010000000011101101001100101 step 957 11010010000000010100101001100101 step 958 11010111000000010100101001100101 step 959 11010111000000010101100110011010 step 960 11010110000000011100100110011010 step 961 11010110000000011101101001100110 step 962 11010110000000010100101001100110 step 963 11010101000000010100101001100110 step 964 11010101000000010101100110011001 step 965 11010100000000011100100110011001 step 966 11010100000000011101101001100110 step 967 11010100000000010100101001100110 step 968 11011101000000010100101001100110 step 969 11011101000000010101100110101001 step 970 11011100000000011100100110101001 step 971 11011100000000011101101001101010 step 972 11011100000000010100101001101010 step 973 11011111000000010100101001101010 step 974 11011111000000010101100110101010 step 975 11011110000000011100100110101010 step 976 11011110000000011101101001101010 step 977 11011110000000010100101001101010 step 978 11011011000000010100101001101010 step 979 11011011000000010101100110100110 step 980 11011010000000011100100110100110 step 981 11011010000000011101101001101001 step 982 11011010000000010100101001101001 step 983 11011001000000010100101001101001 step 984 11011001000000010101100110100101 step 985 11011000000000011100100110100101 step 986 11011000000000011101101001101001 step 987 11011000000000010100101001101001 step 988 11001001000000010100101001101001 step 989 11001001000000010101100101100101 step 990 11001000000000011100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 991 11001000000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 992 11001000000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 993 11001011000000010100101001101001 fail ^^ step 994 11001011000000010101100101100110 step 995 11001010000000011100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 996 11001010000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 997 11001010000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 998 11001111000000010100101001101001 fail ^^ step 999 11001111000000010101100101101010 step 1000 11001110000000011100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1001 11001110000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1002 11001110000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1003 11001101000000010100101001101010 fail ^^ step 1004 11001101000000010101100101101001 step 1005 11001100000000011100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1006 11001100000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 1007 11001100000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1008 11000101000000010100101001101010 fail ^^ step 1009 11000101000000010101100101011001 step 1010 11000100000000011100100101011001 step 1011 11000100000000011101101001010110 step 1012 11000100000000010100101001010110 step 1013 11000111000000010100101001010110 step 1014 11000111000000010101100101011010 step 1015 11000110000000011100100101011010 step 1016 11000110000000011101101001010110 step 1017 11000110000000010100101001010110 step 1018 11000011000000010100101001010110 step 1019 11000011000000010101100101010110 step 1020 11000010000000011100100101010110 step 1021 11000010000000011101101001010101 step 1022 11000010000000010100101001010101 step 1023 11000001000000010100101001010101 step 1024 11000001000000010101100101010101 step 1025 11000000000000011100100101010101 step 1026 11000000000000011101101001010101 step 1027 11000000000000010100101001010101 step 1028 10000001000000010100101001010101 step 1029 10000001000000010101010101010101 step 1030 10000000000000011100010101010101 step 1031 10000000000000011101100101010101 step 1032 10000000000000010100100101010101 step 1033 10000000000000010000100101010101 step 1034 10000011000000010000100101010101 step 1035 10000011000000010001010101010110 step 1036 10000010000000010010010101010110 step 1037 10000010000000010011010101011001 step 1038 10000010000000010000010101011001 step 1039 10000111000000010000010101011001 step 1040 10000111000000010001010101011010 step 1041 10000110000000010010010101011010 step 1042 10000110000000010011010101101001 step 1043 10000110000000010000010101101001 step 1044 10000101000000010000010101101001 step 1045 10000101000000010001010101011001 step 1046 10000100000000010010010101011001 step 1047 10000100000000010011010101100101 step 1048 10000100000000010000010101100101 step 1049 10001101000000010000010101100101 step 1050 10001101000000010001010101101001 step 1051 10001100000000010010010101101001 step 1052 10001100000000010011010110100101 step 1053 10001100000000010000010110100101 step 1054 10001111000000010000010110100101 step 1055 10001111000000010001010101101010 step 1056 10001110000000010010010101101010 step 1057 10001110000000010011010110101001 step 1058 10001110000000010000010110101001 step 1059 10001011000000010000010110101001 step 1060 10001011000000010001010101100110 step 1061 10001010000000010010010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1062 10001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1063 10001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1064 10001001000000010000010110101001 fail ^^ step 1065 10001001000000010001010101100101 step 1066 10001000000000010010010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1067 10001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1068 10001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1069 10011001000000010000010110100101 fail ^^ step 1070 10011001000000010001010110100101 step 1071 10011000000000010010010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1072 10011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1073 10011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1074 10011011000000010000011010100101 fail ^^ step 1075 10011011000000010001010110100110 step 1076 10011010000000010010010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 1001 step 1077 10011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1078 10011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1079 10011111000000010000011010101001 fail ^^ step 1080 10011111000000010001010110101010 step 1081 10011110000000010010010110101010 step 1082 10011110000000010011011010101001 step 1083 10011110000000010000011010101001 step 1084 10011101000000010000011010101001 step 1085 10011101000000010001010110101001 step 1086 10011100000000010010010110101001 step 1087 10011100000000010011011010100101 step 1088 10011100000000010000011010100101 step 1089 10010101000000010000011010100101 step 1090 10010101000000010001010110011001 step 1091 10010100000000010010010110011001 step 1092 10010100000000010011011001100101 step 1093 10010100000000010000011001100101 step 1094 10010111000000010000011001100101 step 1095 10010111000000010001010110011010 step 1096 10010110000000010010010110011010 step 1097 10010110000000010011011001101001 step 1098 10010110000000010000011001101001 step 1099 10010011000000010000011001101001 step 1100 10010011000000010001010110010110 step 1101 10010010000000010010010110010110 step 1102 10010010000000010011011001011001 step 1103 10010010000000010000011001011001 step 1104 10010001000000010000011001011001 step 1105 10010001000000010001010110010101 step 1106 10010000000000010010010110010101 step 1107 10010000000000010011011001010101 step 1108 10010000000000010000011001010101 step 1109 10110001000000010000011001010101 step 1110 10110001000000010001011010010101 step 1111 10110000000000010010011010010101 step 1112 10110000000000010011101001010101 step 1113 10110000000000010000101001010101 step 1114 10110011000000010000101001010101 step 1115 10110011000000010001011010010110 step 1116 10110010000000010010011010010110 step 1117 10110010000000010011101001011001 step 1118 10110010000000010000101001011001 step 1119 10110111000000010000101001011001 step 1120 10110111000000010001011010011010 step 1121 10110110000000010010011010011010 step 1122 10110110000000010011101001101001 step 1123 10110110000000010000101001101001 step 1124 10110101000000010000101001101001 step 1125 10110101000000010001011010011001 step 1126 10110100000000010010011010011001 step 1127 10110100000000010011101001100101 step 1128 10110100000000010000101001100101 step 1129 10111101000000010000101001100101 step 1130 10111101000000010001011010101001 step 1131 10111100000000010010011010101001 step 1132 10111100000000010011101010100101 step 1133 10111100000000010000101010100101 step 1134 10111111000000010000101010100101 step 1135 10111111000000010001011010101010 step 1136 10111110000000010010011010101010 step 1137 10111110000000010011101010101001 step 1138 10111110000000010000101010101001 step 1139 10111011000000010000101010101001 step 1140 10111011000000010001011010100110 step 1141 10111010000000010010011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 1001 step 1142 10111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1143 10111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1144 10111001000000010000101010101001 fail ^^ step 1145 10111001000000010001011010100101 step 1146 10111000000000010010011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 step 1147 10111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1148 10111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1149 10101001000000010000101010100101 fail ^^ step 1150 10101001000000010001011001100101 step 1151 10101000000000010010011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 step 1152 10101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1153 10101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1154 10101011000000010000100110100101 fail ^^ step 1155 10101011000000010001011001100110 step 1156 10101010000000010010011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 1001 step 1157 10101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1158 10101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1159 10101111000000010000100110101001 fail ^^ step 1160 10101111000000010001011001101010 step 1161 10101110000000010010011001101010 step 1162 10101110000000010011100110101001 step 1163 10101110000000010000100110101001 step 1164 10101101000000010000100110101001 step 1165 10101101000000010001011001101001 step 1166 10101100000000010010011001101001 step 1167 10101100000000010011100110100101 step 1168 10101100000000010000100110100101 step 1169 10100101000000010000100110100101 step 1170 10100101000000010001011001011001 step 1171 10100100000000010010011001011001 step 1172 10100100000000010011100101100101 step 1173 10100100000000010000100101100101 step 1174 10100111000000010000100101100101 step 1175 10100111000000010001011001011010 step 1176 10100110000000010010011001011010 step 1177 10100110000000010011100101101001 step 1178 10100110000000010000100101101001 step 1179 10100011000000010000100101101001 step 1180 10100011000000010001011001010110 step 1181 10100010000000010010011001010110 step 1182 10100010000000010011100101011001 step 1183 10100010000000010000100101011001 step 1184 10100001000000010000100101011001 step 1185 10100001000000010001011001010101 step 1186 10100000000000010010011001010101 step 1187 10100000000000010011100101010101 step 1188 10100000000000010000100101010101 step 1189 11100001000000010000100101010101 step 1190 11100001000000010001101001010101 step 1191 11100000000000010010101001010101 step 1192 11100000000000010011100101010101 step 1193 11100000000000010000100101010101 step 1194 11100011000000010000100101010101 step 1195 11100011000000010001101001010110 step 1196 11100010000000010010101001010110 step 1197 11100010000000010011100101011001 step 1198 11100010000000010000100101011001 step 1199 11100111000000010000100101011001 step 1200 11100111000000010001101001011010 step 1201 11100110000000010010101001011010 step 1202 11100110000000010011100101101001 step 1203 11100110000000010000100101101001 step 1204 11100101000000010000100101101001 step 1205 11100101000000010001101001011001 step 1206 11100100000000010010101001011001 step 1207 11100100000000010011100101100101 step 1208 11100100000000010000100101100101 step 1209 11101101000000010000100101100101 step 1210 11101101000000010001101001101001 step 1211 11101100000000010010101001101001 step 1212 11101100000000010011100110100101 step 1213 11101100000000010000100110100101 step 1214 11101111000000010000100110100101 step 1215 11101111000000010001101001101010 step 1216 11101110000000010010101001101010 step 1217 11101110000000010011100110101001 step 1218 11101110000000010000100110101001 step 1219 11101011000000010000100110101001 step 1220 11101011000000010001101001100110 step 1221 11101010000000010010101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 1001 step 1222 11101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1223 11101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1224 11101001000000010000100110101001 fail ^^ step 1225 11101001000000010001101001100101 step 1226 11101000000000010010101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 1227 11101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1228 11101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1229 11111001000000010000100110100101 fail ^^ step 1230 11111001000000010001101010100101 step 1231 11111000000000010010101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 1232 11111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1233 11111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1234 11111011000000010000101010100101 fail ^^ step 1235 11111011000000010001101010100110 step 1236 11111010000000010010101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 1237 11111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1238 11111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1239 11111111000000010000101010101001 fail ^^ step 1240 11111111000000010001101010101010 step 1241 11111110000000010010101010101010 step 1242 11111110000000010011101010101001 step 1243 11111110000000010000101010101001 step 1244 11111101000000010000101010101001 step 1245 11111101000000010001101010101001 step 1246 11111100000000010010101010101001 step 1247 11111100000000010011101010100101 step 1248 11111100000000010000101010100101 step 1249 11110101000000010000101010100101 step 1250 11110101000000010001101010011001 step 1251 11110100000000010010101010011001 step 1252 11110100000000010011101001100101 step 1253 11110100000000010000101001100101 step 1254 11110111000000010000101001100101 step 1255 11110111000000010001101010011010 step 1256 11110110000000010010101010011010 step 1257 11110110000000010011101001101001 step 1258 11110110000000010000101001101001 step 1259 11110011000000010000101001101001 step 1260 11110011000000010001101010010110 step 1261 11110010000000010010101010010110 step 1262 11110010000000010011101001011001 step 1263 11110010000000010000101001011001 step 1264 11110001000000010000101001011001 step 1265 11110001000000010001101010010101 step 1266 11110000000000010010101010010101 step 1267 11110000000000010011101001010101 step 1268 11110000000000010000101001010101 step 1269 11010001000000010000101001010101 step 1270 11010001000000010001100110010101 step 1271 11010000000000010010100110010101 step 1272 11010000000000010011011001010101 step 1273 11010000000000010000011001010101 step 1274 11010011000000010000011001010101 step 1275 11010011000000010001100110010110 step 1276 11010010000000010010100110010110 step 1277 11010010000000010011011001011001 step 1278 11010010000000010000011001011001 step 1279 11010111000000010000011001011001 step 1280 11010111000000010001100110011010 step 1281 11010110000000010010100110011010 step 1282 11010110000000010011011001101001 step 1283 11010110000000010000011001101001 step 1284 11010101000000010000011001101001 step 1285 11010101000000010001100110011001 step 1286 11010100000000010010100110011001 step 1287 11010100000000010011011001100101 step 1288 11010100000000010000011001100101 step 1289 11011101000000010000011001100101 step 1290 11011101000000010001100110101001 step 1291 11011100000000010010100110101001 step 1292 11011100000000010011011010100101 step 1293 11011100000000010000011010100101 step 1294 11011111000000010000011010100101 step 1295 11011111000000010001100110101010 step 1296 11011110000000010010100110101010 step 1297 11011110000000010011011010101001 step 1298 11011110000000010000011010101001 step 1299 11011011000000010000011010101001 step 1300 11011011000000010001100110100110 step 1301 11011010000000010010100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 1001 step 1302 11011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1303 11011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1304 11011001000000010000011010101001 fail ^^ step 1305 11011001000000010001100110100101 step 1306 11011000000000010010100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 step 1307 11011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1308 11011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1309 11001001000000010000011010100101 fail ^^ step 1310 11001001000000010001100101100101 step 1311 11001000000000010010100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 step 1312 11001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1313 11001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1314 11001011000000010000010110100101 fail ^^ step 1315 11001011000000010001100101100110 step 1316 11001010000000010010100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 1001 step 1317 11001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1318 11001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1319 11001111000000010000010110101001 fail ^^ step 1320 11001111000000010001100101101010 step 1321 11001110000000010010100101101010 step 1322 11001110000000010011010110101001 step 1323 11001110000000010000010110101001 step 1324 11001101000000010000010110101001 step 1325 11001101000000010001100101101001 step 1326 11001100000000010010100101101001 step 1327 11001100000000010011010110100101 step 1328 11001100000000010000010110100101 step 1329 11000101000000010000010110100101 step 1330 11000101000000010001100101011001 step 1331 11000100000000010010100101011001 step 1332 11000100000000010011010101100101 step 1333 11000100000000010000010101100101 step 1334 11000111000000010000010101100101 step 1335 11000111000000010001100101011010 step 1336 11000110000000010010100101011010 step 1337 11000110000000010011010101101001 step 1338 11000110000000010000010101101001 step 1339 11000011000000010000010101101001 step 1340 11000011000000010001100101010110 step 1341 11000010000000010010100101010110 step 1342 11000010000000010011010101011001 step 1343 11000010000000010000010101011001 step 1344 11000001000000010000010101011001 step 1345 11000001000000010001100101010101 step 1346 11000000000000010010100101010101 step 1347 11000000000000010011010101010101 step 1348 11000000000000010000010101010101 step 1349 10000001000000010000010101010101 step 1350 10000001000000010001010101010101 step 1351 10000000000000010010010101010101 step 1352 10000000000000010011010101010101 step 1353 10000000000000010000010101010101 step 1354 10000000000000010100010101010101 step 1355 10000011000000010100010101010101 step 1356 10000011000000010101010101010110 step 1357 10000010000000010110010101010110 step 1358 10000010000000010111010101011010 step 1359 10000010000000010100010101011010 step 1360 10000111000000010100010101011010 step 1361 10000111000000010101010101011010 step 1362 10000110000000010110010101011010 step 1363 10000110000000010111010101101010 step 1364 10000110000000010100010101101010 step 1365 10000101000000010100010101101010 step 1366 10000101000000010101010101011001 step 1367 10000100000000010110010101011001 step 1368 10000100000000010111010101100110 step 1369 10000100000000010100010101100110 step 1370 10001101000000010100010101100110 step 1371 10001101000000010101010101101001 step 1372 10001100000000010110010101101001 step 1373 10001100000000010111010110100110 step 1374 10001100000000010100010110100110 step 1375 10001111000000010100010110100110 step 1376 10001111000000010101010101101010 step 1377 10001110000000010110010101101010 step 1378 10001110000000010111010110101010 step 1379 10001110000000010100010110101010 step 1380 10001011000000010100010110101010 step 1381 10001011000000010101010101100110 step 1382 10001010000000010110010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1383 10001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1384 10001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1385 10001001000000010100010110101010 fail ^^ step 1386 10001001000000010101010101100101 step 1387 10001000000000010110010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1388 10001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1389 10001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1390 10011001000000010100010110100110 fail ^^ step 1391 10011001000000010101010110100101 step 1392 10011000000000010110010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1393 10011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1394 10011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1395 10011011000000010100011010100110 fail ^^ step 1396 10011011000000010101010110100110 step 1397 10011010000000010110010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 10 step 1398 10011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1399 10011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1400 10011111000000010100011010101010 fail ^^ step 1401 10011111000000010101010110101010 step 1402 10011110000000010110010110101010 step 1403 10011110000000010111011010101010 step 1404 10011110000000010100011010101010 step 1405 10011101000000010100011010101010 step 1406 10011101000000010101010110101001 step 1407 10011100000000010110010110101001 step 1408 10011100000000010111011010100110 step 1409 10011100000000010100011010100110 step 1410 10010101000000010100011010100110 step 1411 10010101000000010101010110011001 step 1412 10010100000000010110010110011001 step 1413 10010100000000010111011001100110 step 1414 10010100000000010100011001100110 step 1415 10010111000000010100011001100110 step 1416 10010111000000010101010110011010 step 1417 10010110000000010110010110011010 step 1418 10010110000000010111011001101010 step 1419 10010110000000010100011001101010 step 1420 10010011000000010100011001101010 step 1421 10010011000000010101010110010110 step 1422 10010010000000010110010110010110 step 1423 10010010000000010111011001011010 step 1424 10010010000000010100011001011010 step 1425 10010001000000010100011001011010 step 1426 10010001000000010101010110010101 step 1427 10010000000000010110010110010101 step 1428 10010000000000010111011001010110 step 1429 10010000000000010100011001010110 step 1430 10110001000000010100011001010110 step 1431 10110001000000010101011010010101 step 1432 10110000000000010110011010010101 step 1433 10110000000000010111101001010110 step 1434 10110000000000010100101001010110 step 1435 10110011000000010100101001010110 step 1436 10110011000000010101011010010110 step 1437 10110010000000010110011010010110 step 1438 10110010000000010111101001011010 step 1439 10110010000000010100101001011010 step 1440 10110111000000010100101001011010 step 1441 10110111000000010101011010011010 step 1442 10110110000000010110011010011010 step 1443 10110110000000010111101001101010 step 1444 10110110000000010100101001101010 step 1445 10110101000000010100101001101010 step 1446 10110101000000010101011010011001 step 1447 10110100000000010110011010011001 step 1448 10110100000000010111101001100110 step 1449 10110100000000010100101001100110 step 1450 10111101000000010100101001100110 step 1451 10111101000000010101011010101001 step 1452 10111100000000010110011010101001 step 1453 10111100000000010111101010100110 step 1454 10111100000000010100101010100110 step 1455 10111111000000010100101010100110 step 1456 10111111000000010101011010101010 step 1457 10111110000000010110011010101010 step 1458 10111110000000010111101010101010 step 1459 10111110000000010100101010101010 step 1460 10111011000000010100101010101010 step 1461 10111011000000010101011010100110 step 1462 10111010000000010110011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1463 10111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1464 10111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1465 10111001000000010100101010101010 fail ^^ step 1466 10111001000000010101011010100101 step 1467 10111000000000010110011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 110 10 step 1468 10111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1469 10111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1470 10101001000000010100101010100110 fail ^^ step 1471 10101001000000010101011001100101 step 1472 10101000000000010110011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1473 10101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1474 10101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1475 10101011000000010100100110100110 fail ^^ step 1476 10101011000000010101011001100110 step 1477 10101010000000010110011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1100110 10 step 1478 10101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1479 10101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1480 10101111000000010100100110101010 fail ^^ step 1481 10101111000000010101011001101010 step 1482 10101110000000010110011001101010 step 1483 10101110000000010111100110101010 step 1484 10101110000000010100100110101010 step 1485 10101101000000010100100110101010 step 1486 10101101000000010101011001101001 step 1487 10101100000000010110011001101001 step 1488 10101100000000010111100110100110 step 1489 10101100000000010100100110100110 step 1490 10100101000000010100100110100110 step 1491 10100101000000010101011001011001 step 1492 10100100000000010110011001011001 step 1493 10100100000000010111100101100110 step 1494 10100100000000010100100101100110 step 1495 10100111000000010100100101100110 step 1496 10100111000000010101011001011010 step 1497 10100110000000010110011001011010 step 1498 10100110000000010111100101101010 step 1499 10100110000000010100100101101010 step 1500 10100011000000010100100101101010 step 1501 10100011000000010101011001010110 step 1502 10100010000000010110011001010110 step 1503 10100010000000010111100101011010 step 1504 10100010000000010100100101011010 step 1505 10100001000000010100100101011010 step 1506 10100001000000010101011001010101 step 1507 10100000000000010110011001010101 step 1508 10100000000000010111100101010110 step 1509 10100000000000010100100101010110 step 1510 11100001000000010100100101010110 step 1511 11100001000000010101101001010101 step 1512 11100000000000010110101001010101 step 1513 11100000000000010111100101010110 step 1514 11100000000000010100100101010110 step 1515 11100011000000010100100101010110 step 1516 11100011000000010101101001010110 step 1517 11100010000000010110101001010110 step 1518 11100010000000010111100101011010 step 1519 11100010000000010100100101011010 step 1520 11100111000000010100100101011010 step 1521 11100111000000010101101001011010 step 1522 11100110000000010110101001011010 step 1523 11100110000000010111100101101010 step 1524 11100110000000010100100101101010 step 1525 11100101000000010100100101101010 step 1526 11100101000000010101101001011001 step 1527 11100100000000010110101001011001 step 1528 11100100000000010111100101100110 step 1529 11100100000000010100100101100110 step 1530 11101101000000010100100101100110 step 1531 11101101000000010101101001101001 step 1532 11101100000000010110101001101001 step 1533 11101100000000010111100110100110 step 1534 11101100000000010100100110100110 step 1535 11101111000000010100100110100110 step 1536 11101111000000010101101001101010 step 1537 11101110000000010110101001101010 step 1538 11101110000000010111100110101010 step 1539 11101110000000010100100110101010 step 1540 11101011000000010100100110101010 step 1541 11101011000000010101101001100110 step 1542 11101010000000010110101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1543 11101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1544 11101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1545 11101001000000010100100110101010 fail ^^ step 1546 11101001000000010101101001100101 step 1547 11101000000000010110101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 1548 11101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1549 11101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1550 11111001000000010100100110100110 fail ^^ step 1551 11111001000000010101101010100101 step 1552 11111000000000010110101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1553 11111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1554 11111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1555 11111011000000010100101010100110 fail ^^ step 1556 11111011000000010101101010100110 step 1557 11111010000000010110101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 1558 11111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1559 11111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1560 11111111000000010100101010101010 fail ^^ step 1561 11111111000000010101101010101010 step 1562 11111110000000010110101010101010 step 1563 11111110000000010111101010101010 step 1564 11111110000000010100101010101010 step 1565 11111101000000010100101010101010 step 1566 11111101000000010101101010101001 step 1567 11111100000000010110101010101001 step 1568 11111100000000010111101010100110 step 1569 11111100000000010100101010100110 step 1570 11110101000000010100101010100110 step 1571 11110101000000010101101010011001 step 1572 11110100000000010110101010011001 step 1573 11110100000000010111101001100110 step 1574 11110100000000010100101001100110 step 1575 11110111000000010100101001100110 step 1576 11110111000000010101101010011010 step 1577 11110110000000010110101010011010 step 1578 11110110000000010111101001101010 step 1579 11110110000000010100101001101010 step 1580 11110011000000010100101001101010 step 1581 11110011000000010101101010010110 step 1582 11110010000000010110101010010110 step 1583 11110010000000010111101001011010 step 1584 11110010000000010100101001011010 step 1585 11110001000000010100101001011010 step 1586 11110001000000010101101010010101 step 1587 11110000000000010110101010010101 step 1588 11110000000000010111101001010110 step 1589 11110000000000010100101001010110 step 1590 11010001000000010100101001010110 step 1591 11010001000000010101100110010101 step 1592 11010000000000010110100110010101 step 1593 11010000000000010111011001010110 step 1594 11010000000000010100011001010110 step 1595 11010011000000010100011001010110 step 1596 11010011000000010101100110010110 step 1597 11010010000000010110100110010110 step 1598 11010010000000010111011001011010 step 1599 11010010000000010100011001011010 step 1600 11010111000000010100011001011010 step 1601 11010111000000010101100110011010 step 1602 11010110000000010110100110011010 step 1603 11010110000000010111011001101010 step 1604 11010110000000010100011001101010 step 1605 11010101000000010100011001101010 step 1606 11010101000000010101100110011001 step 1607 11010100000000010110100110011001 step 1608 11010100000000010111011001100110 step 1609 11010100000000010100011001100110 step 1610 11011101000000010100011001100110 step 1611 11011101000000010101100110101001 step 1612 11011100000000010110100110101001 step 1613 11011100000000010111011010100110 step 1614 11011100000000010100011010100110 step 1615 11011111000000010100011010100110 step 1616 11011111000000010101100110101010 step 1617 11011110000000010110100110101010 step 1618 11011110000000010111011010101010 step 1619 11011110000000010100011010101010 step 1620 11011011000000010100011010101010 step 1621 11011011000000010101100110100110 step 1622 11011010000000010110100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1623 11011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1624 11011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 1625 11011001000000010100011010101010 fail ^^ step 1626 11011001000000010101100110100101 step 1627 11011000000000010110100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 10110 10 step 1628 11011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1629 11011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 1630 11001001000000010100011010100110 fail ^^ step 1631 11001001000000010101100101100101 step 1632 11001000000000010110100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1633 11001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1634 11001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 1635 11001011000000010100010110100110 fail ^^ step 1636 11001011000000010101100101100110 step 1637 11001010000000010110100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 101 10 10 step 1638 11001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 00 step 1639 11001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 1640 11001111000000010100010110101010 fail ^^ step 1641 11001111000000010101100101101010 step 1642 11001110000000010110100101101010 step 1643 11001110000000010111010110101010 step 1644 11001110000000010100010110101010 step 1645 11001101000000010100010110101010 step 1646 11001101000000010101100101101001 step 1647 11001100000000010110100101101001 step 1648 11001100000000010111010110100110 step 1649 11001100000000010100010110100110 step 1650 11000101000000010100010110100110 step 1651 11000101000000010101100101011001 step 1652 11000100000000010110100101011001 step 1653 11000100000000010111010101100110 step 1654 11000100000000010100010101100110 step 1655 11000111000000010100010101100110 step 1656 11000111000000010101100101011010 step 1657 11000110000000010110100101011010 step 1658 11000110000000010111010101101010 step 1659 11000110000000010100010101101010 step 1660 11000011000000010100010101101010 step 1661 11000011000000010101100101010110 step 1662 11000010000000010110100101010110 step 1663 11000010000000010111010101011010 step 1664 11000010000000010100010101011010 step 1665 11000001000000010100010101011010 step 1666 11000001000000010101100101010101 step 1667 11000000000000010110100101010101 step 1668 11000000000000010111010101010110 step 1669 11000000000000010100010101010110 step 1670 10000001000000010100010101010110 step 1671 10000001000000010101010101010101 step 1672 10000000000000010110010101010101 step 1673 10000000000000010111010101010110 step 1674 10000000000000010100010101010110 step 1675 00000000000000010100010101010101 step 1676 10000000000000010100010101010101 step 1677 11111110111111010100010101010101 test 7: *** FAIL *************************** 192 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 7, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; CLEAR-N, NO ENABLES source: 01111110111111010100010101010101 changed: 0 0 0 0 0 0 0 step 1 01111110111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1 changed: 1 step 2 11111110111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM source: ; see mk_m212_ld_shift.c source: source: source: ; TEST A INPUTS, GRAY CODE PATTERN source: source: ; ENABLE A INPUTS source: 1 changed: 1 step 3 11111111111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; LOAD FFs FROM INPUT A source: source: 000001 changed: 00000 step 4 10000011111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 5 10000011111111010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 6 10000011111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000011 changed: 1 step 7 10000111111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 8 10000111111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 9 10000111111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000010 changed: 0 step 10 10000101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 11 10000101111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 12 10000101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000110 changed: 1 step 13 10001101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 14 10001101111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 15 10001101111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000111 changed: 1 step 16 10001111111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 17 10001111111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 18 10001111111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000101 changed: 0 step 19 10001011111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 20 10001011111111010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 21 10001011111111010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000100 changed: 0 step 22 10001001111111010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 23 10001001111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 24 10001001111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001100 changed: 1 step 25 10011001111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 26 10011001111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 27 10011001111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001101 changed: 1 step 28 10011011111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 29 10011011111111010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 30 10011011111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001111 changed: 1 step 31 10011111111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 32 10011111111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 33 10011111111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001110 changed: 0 step 34 10011101111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 35 10011101111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 36 10011101111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001010 changed: 0 step 37 10010101111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 38 10010101111111010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 39 10010101111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001011 changed: 1 step 40 10010111111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 41 10010111111111010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 42 10010111111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001001 changed: 0 step 43 10010011111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 44 10010011111111010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 45 10010011111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001000 changed: 0 step 46 10010001111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 47 10010001111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 48 10010001111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011000 changed: 1 step 49 10110001111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 50 10110001111111010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 51 10110001111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011001 changed: 1 step 52 10110011111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 53 10110011111111010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 54 10110011111111010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011011 changed: 1 step 55 10110111111111010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 56 10110111111111010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 57 10110111111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011010 changed: 0 step 58 10110101111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 59 10110101111111010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 60 10110101111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011110 changed: 1 step 61 10111101111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 62 10111101111111010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 63 10111101111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011111 changed: 1 step 64 10111111111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 65 10111111111111010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 66 10111111111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011101 changed: 0 step 67 10111011111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 68 10111011111111010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 69 10111011111111010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011100 changed: 0 step 70 10111001111111010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 71 10111001111111010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 72 10111001111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010100 changed: 0 step 73 10101001111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 74 10101001111111010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 75 10101001111111010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010101 changed: 1 step 76 10101011111111010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 77 10101011111111010101000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 78 10101011111111010100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010111 changed: 1 step 79 10101111111111010100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 80 10101111111111010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 81 10101111111111010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010110 changed: 0 step 82 10101101111111010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 83 10101101111111010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 84 10101101111111010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010010 changed: 0 step 85 10100101111111010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 86 10100101111111010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 87 10100101111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010011 changed: 1 step 88 10100111111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 89 10100111111111010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 90 10100111111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010001 changed: 0 step 91 10100011111111010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 92 10100011111111010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 93 10100011111111010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010000 changed: 0 step 94 10100001111111010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 95 10100001111111010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 96 10100001111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110000 changed: 1 step 97 11100001111111010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 98 11100001111111010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 99 11100001111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110001 changed: 1 step 100 11100011111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 101 11100011111111010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 102 11100011111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110011 changed: 1 step 103 11100111111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 104 11100111111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 105 11100111111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110010 changed: 0 step 106 11100101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 107 11100101111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 108 11100101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110110 changed: 1 step 109 11101101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 110 11101101111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 111 11101101111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110111 changed: 1 step 112 11101111111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 113 11101111111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 114 11101111111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110101 changed: 0 step 115 11101011111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 116 11101011111111010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 117 11101011111111010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110100 changed: 0 step 118 11101001111111010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 119 11101001111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 120 11101001111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111100 changed: 1 step 121 11111001111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 122 11111001111111010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 123 11111001111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111101 changed: 1 step 124 11111011111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 125 11111011111111010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 126 11111011111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111111 changed: 1 step 127 11111111111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 128 11111111111111010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 129 11111111111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111110 changed: 0 step 130 11111101111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 131 11111101111111010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 132 11111101111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111010 changed: 0 step 133 11110101111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 134 11110101111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 135 11110101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111011 changed: 1 step 136 11110111111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 137 11110111111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 138 11110111111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111001 changed: 0 step 139 11110011111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 140 11110011111111010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 141 11110011111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111000 changed: 0 step 142 11110001111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 143 11110001111111010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 144 11110001111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101000 changed: 0 step 145 11010001111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 146 11010001111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 147 11010001111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101001 changed: 1 step 148 11010011111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 149 11010011111111010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 150 11010011111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101011 changed: 1 step 151 11010111111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 152 11010111111111010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 153 11010111111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101010 changed: 0 step 154 11010101111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 155 11010101111111010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 156 11010101111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101110 changed: 1 step 157 11011101111111010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 158 11011101111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 159 11011101111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101111 changed: 1 step 160 11011111111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 161 11011111111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 162 11011111111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101101 changed: 0 step 163 11011011111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 164 11011011111111010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 165 11011011111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101100 changed: 0 step 166 11011001111111010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 167 11011001111111010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 168 11011001111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100100 changed: 0 step 169 11001001111111010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 170 11001001111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 171 11001001111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100101 changed: 1 step 172 11001011111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 173 11001011111111010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 174 11001011111111010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100111 changed: 1 step 175 11001111111111010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 176 11001111111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 177 11001111111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100110 changed: 0 step 178 11001101111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 179 11001101111111010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 180 11001101111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100010 changed: 0 step 181 11000101111111010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 182 11000101111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 183 11000101111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100011 changed: 1 step 184 11000111111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 185 11000111111111010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 186 11000111111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100001 changed: 0 step 187 11000011111111010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 188 11000011111111010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 189 11000011111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100000 changed: 0 step 190 11000001111111010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 191 11000001111111010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 192 11000001111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000000 changed: 0 step 193 10000001111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 194 10000001111111010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 195 10000001111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: ; DISABLE A INPUTS source: 0 changed: 0 step 196 10000000111111010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: source: ; TEST B INPUTS source: source: ; ENABLE B INPUTS source: 1 changed: 1 step 197 10000000111111110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; LOAD FFs FROM INPUT B source: source: 000001 changed: 00000 step 198 10000000000001110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 199 10000000000001110101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 200 10000000000001110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000011 changed: 1 step 201 10000000000011110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 202 10000000000011110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 203 10000000000011110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000010 changed: 0 step 204 10000000000010110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 205 10000000000010110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 206 10000000000010110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000110 changed: 1 step 207 10000000000110110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 208 10000000000110110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 209 10000000000110110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000111 changed: 1 step 210 10000000000111110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 211 10000000000111110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 212 10000000000111110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000101 changed: 0 step 213 10000000000101110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 214 10000000000101110101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 215 10000000000101110100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000100 changed: 0 step 216 10000000000100110100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 217 10000000000100110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 218 10000000000100110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001100 changed: 1 step 219 10000000001100110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 220 10000000001100110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 221 10000000001100110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001101 changed: 1 step 222 10000000001101110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 223 10000000001101110101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 224 10000000001101110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001111 changed: 1 step 225 10000000001111110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 226 10000000001111110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 227 10000000001111110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001110 changed: 0 step 228 10000000001110110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 229 10000000001110110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 230 10000000001110110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001010 changed: 0 step 231 10000000001010110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 232 10000000001010110101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 233 10000000001010110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001011 changed: 1 step 234 10000000001011110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 235 10000000001011110101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 236 10000000001011110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001001 changed: 0 step 237 10000000001001110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 238 10000000001001110101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 239 10000000001001110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 001000 changed: 0 step 240 10000000001000110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 241 10000000001000110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 242 10000000001000110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011000 changed: 1 step 243 10000000011000110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 244 10000000011000110101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 245 10000000011000110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011001 changed: 1 step 246 10000000011001110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 247 10000000011001110101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 248 10000000011001110100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011011 changed: 1 step 249 10000000011011110100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 250 10000000011011110101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 251 10000000011011110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011010 changed: 0 step 252 10000000011010110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 253 10000000011010110101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 254 10000000011010110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011110 changed: 1 step 255 10000000011110110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 256 10000000011110110101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 257 10000000011110110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011111 changed: 1 step 258 10000000011111110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 259 10000000011111110101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 260 10000000011111110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011101 changed: 0 step 261 10000000011101110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 262 10000000011101110101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 263 10000000011101110100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 011100 changed: 0 step 264 10000000011100110100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 265 10000000011100110101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 266 10000000011100110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010100 changed: 0 step 267 10000000010100110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 268 10000000010100110101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 269 10000000010100110100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010101 changed: 1 step 270 10000000010101110100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 271 10000000010101110101000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 272 10000000010101110100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010111 changed: 1 step 273 10000000010111110100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 274 10000000010111110101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 275 10000000010111110100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010110 changed: 0 step 276 10000000010110110100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 277 10000000010110110101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 278 10000000010110110100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010010 changed: 0 step 279 10000000010010110100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 280 10000000010010110101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 281 10000000010010110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010011 changed: 1 step 282 10000000010011110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 283 10000000010011110101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 284 10000000010011110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010001 changed: 0 step 285 10000000010001110100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 286 10000000010001110101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 287 10000000010001110100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 010000 changed: 0 step 288 10000000010000110100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 289 10000000010000110101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 290 10000000010000110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110000 changed: 1 step 291 10000000110000110100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 292 10000000110000110101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 293 10000000110000110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110001 changed: 1 step 294 10000000110001110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 295 10000000110001110101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 296 10000000110001110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110011 changed: 1 step 297 10000000110011110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 298 10000000110011110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 299 10000000110011110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110010 changed: 0 step 300 10000000110010110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 301 10000000110010110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 302 10000000110010110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110110 changed: 1 step 303 10000000110110110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 304 10000000110110110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 305 10000000110110110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110111 changed: 1 step 306 10000000110111110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 307 10000000110111110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 308 10000000110111110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110101 changed: 0 step 309 10000000110101110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 310 10000000110101110101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 311 10000000110101110100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 110100 changed: 0 step 312 10000000110100110100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 313 10000000110100110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 314 10000000110100110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111100 changed: 1 step 315 10000000111100110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 316 10000000111100110101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 317 10000000111100110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111101 changed: 1 step 318 10000000111101110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 319 10000000111101110101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 320 10000000111101110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111111 changed: 1 step 321 10000000111111110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 322 10000000111111110101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 323 10000000111111110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111110 changed: 0 step 324 10000000111110110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 325 10000000111110110101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 326 10000000111110110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111010 changed: 0 step 327 10000000111010110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 328 10000000111010110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 329 10000000111010110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111011 changed: 1 step 330 10000000111011110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 331 10000000111011110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 332 10000000111011110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111001 changed: 0 step 333 10000000111001110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 334 10000000111001110101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 335 10000000111001110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 111000 changed: 0 step 336 10000000111000110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 337 10000000111000110101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 338 10000000111000110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101000 changed: 0 step 339 10000000101000110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 340 10000000101000110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 341 10000000101000110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101001 changed: 1 step 342 10000000101001110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 343 10000000101001110101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 344 10000000101001110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101011 changed: 1 step 345 10000000101011110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 346 10000000101011110101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 347 10000000101011110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101010 changed: 0 step 348 10000000101010110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 349 10000000101010110101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 350 10000000101010110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101110 changed: 1 step 351 10000000101110110100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 352 10000000101110110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 353 10000000101110110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101111 changed: 1 step 354 10000000101111110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 355 10000000101111110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 356 10000000101111110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101101 changed: 0 step 357 10000000101101110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 358 10000000101101110101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 359 10000000101101110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 101100 changed: 0 step 360 10000000101100110100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 361 10000000101100110101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 362 10000000101100110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100100 changed: 0 step 363 10000000100100110100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 364 10000000100100110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 365 10000000100100110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100101 changed: 1 step 366 10000000100101110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 367 10000000100101110101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 368 10000000100101110100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100111 changed: 1 step 369 10000000100111110100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 370 10000000100111110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 371 10000000100111110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100110 changed: 0 step 372 10000000100110110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 373 10000000100110110101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 374 10000000100110110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100010 changed: 0 step 375 10000000100010110100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 376 10000000100010110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 377 10000000100010110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100011 changed: 1 step 378 10000000100011110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 379 10000000100011110101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 380 10000000100011110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100001 changed: 0 step 381 10000000100001110100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 382 10000000100001110101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 383 10000000100001110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 100000 changed: 0 step 384 10000000100000110100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 385 10000000100000110101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 386 10000000100000110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 000000 changed: 0 step 387 10000000000000110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 388 10000000000000110101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 changed: 0 step 389 10000000000000110100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: ; DISABLE B INPUTS source: 0 changed: 0 step 390 10000000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 391 10000000000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 11 step 392 10000011000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 393 10000011000000000101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 394 10000010000000001100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 395 10000010000000001101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 396 10000010000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 1 step 397 10000111000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 398 10000111000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 399 10000110000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 400 10000110000000001101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 401 10000110000000000100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 01 step 402 10000101000000000100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 403 10000101000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 404 10000100000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 405 10000100000000001101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 406 10000100000000000100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 407 10001101000000000100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 408 10001101000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 409 10001100000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 410 10001100000000001101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 411 10001100000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 412 10001111000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 413 10001111000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 414 10001110000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 415 10001110000000001101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 416 10001110000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 417 10001011000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 418 10001011000000000101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 419 10001010000000001100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 420 10001010000000001101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 421 10001010000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 422 10001001000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 423 10001001000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 424 10001000000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 425 10001000000000001101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 426 10001000000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 427 10011001000000000100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 428 10011001000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 429 10011000000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 430 10011000000000001101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 431 10011000000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 432 10011011000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 433 10011011000000000101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 434 10011010000000001100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 435 10011010000000001101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 436 10011010000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 437 10011111000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 438 10011111000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 439 10011110000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 440 10011110000000001101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 441 10011110000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011101 changed: 01 step 442 10011101000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 443 10011101000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 444 10011100000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 445 10011100000000001101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 446 10011100000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: 0 1 step 447 10010101000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 448 10010101000000000101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 449 10010100000000001100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 450 10010100000000001101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 451 10010100000000000100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 11 step 452 10010111000000000100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 453 10010111000000000101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 454 10010110000000001100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 455 10010110000000001101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 456 10010110000000000100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 1 step 457 10010011000000000100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 458 10010011000000000101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 459 10010010000000001100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 460 10010010000000001101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 461 10010010000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 01 step 462 10010001000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 463 10010001000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 464 10010000000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 465 10010000000000001101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 466 10010000000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 1 step 467 10110001000000000100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 468 10110001000000000101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 469 10110000000000001100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 470 10110000000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 471 10110000000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 11 step 472 10110011000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 473 10110011000000000101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 474 10110010000000001100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 475 10110010000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 476 10110010000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 1 step 477 10110111000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 478 10110111000000000101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 479 10110110000000001100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 480 10110110000000001101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 481 10110110000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 01 step 482 10110101000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 483 10110101000000000101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 484 10110100000000001100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 485 10110100000000001101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 486 10110100000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 487 10111101000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 488 10111101000000000101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 489 10111100000000001100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 490 10111100000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 491 10111100000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111111 changed: 11 step 492 10111111000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 493 10111111000000000101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 494 10111110000000001100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 495 10111110000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 496 10111110000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111011 changed: 0 1 step 497 10111011000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 498 10111011000000000101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 499 10111010000000001100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 500 10111010000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 501 10111010000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 502 10111001000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 503 10111001000000000101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 504 10111000000000001100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 505 10111000000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 506 10111000000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 507 10101001000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 508 10101001000000000101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 509 10101000000000001100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 510 10101000000000001101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 511 10101000000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 512 10101011000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 513 10101011000000000101000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 514 10101010000000001100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 515 10101010000000001101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 516 10101010000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 517 10101111000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 518 10101111000000000101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 519 10101110000000001100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 520 10101110000000001101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 521 10101110000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 522 10101101000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 523 10101101000000000101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 524 10101100000000001100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 525 10101100000000001101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 526 10101100000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 527 10100101000000000100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 528 10100101000000000101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 529 10100100000000001100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 530 10100100000000001101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 531 10100100000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 11 step 532 10100111000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 533 10100111000000000101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 534 10100110000000001100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 535 10100110000000001101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 536 10100110000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 1 step 537 10100011000000000100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 538 10100011000000000101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 539 10100010000000001100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 540 10100010000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 541 10100010000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 01 step 542 10100001000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 543 10100001000000000101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 544 10100000000000001100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 545 10100000000000001101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 546 10100000000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 1 step 547 11100001000000000100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 548 11100001000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 549 11100000000000001100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 550 11100000000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 551 11100000000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 11 step 552 11100011000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 553 11100011000000000101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 554 11100010000000001100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 555 11100010000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 556 11100010000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 1 step 557 11100111000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 558 11100111000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 559 11100110000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 560 11100110000000001101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 561 11100110000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 01 step 562 11100101000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 563 11100101000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 564 11100100000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 565 11100100000000001101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 566 11100100000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 567 11101101000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 568 11101101000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 569 11101100000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 570 11101100000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 571 11101100000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 572 11101111000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 573 11101111000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 574 11101110000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 575 11101110000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 576 11101110000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 577 11101011000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 578 11101011000000000101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 579 11101010000000001100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 580 11101010000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 581 11101010000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 582 11101001000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 583 11101001000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 584 11101000000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 585 11101000000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 586 11101000000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 587 11111001000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 588 11111001000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 589 11111000000000001100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 590 11111000000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 591 11111000000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 592 11111011000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 593 11111011000000000101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 594 11111010000000001100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 595 11111010000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 596 11111010000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 597 11111111000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 598 11111111000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 599 11111110000000001100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 600 11111110000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 601 11111110000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111101 changed: 01 step 602 11111101000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 603 11111101000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 604 11111100000000001100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 605 11111100000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 606 11111100000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: 0 1 step 607 11110101000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 608 11110101000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 609 11110100000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 610 11110100000000001101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 611 11110100000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 11 step 612 11110111000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 613 11110111000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 614 11110110000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 615 11110110000000001101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 616 11110110000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 1 step 617 11110011000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 618 11110011000000000101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 619 11110010000000001100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 620 11110010000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 621 11110010000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 01 step 622 11110001000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 623 11110001000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 624 11110000000000001100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 625 11110000000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 626 11110000000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 1 step 627 11010001000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 628 11010001000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 629 11010000000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 630 11010000000000001101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 631 11010000000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 11 step 632 11010011000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 633 11010011000000000101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 634 11010010000000001100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 635 11010010000000001101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 636 11010010000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 1 step 637 11010111000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 638 11010111000000000101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 639 11010110000000001100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 640 11010110000000001101000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 641 11010110000000000100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 01 step 642 11010101000000000100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 643 11010101000000000101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 644 11010100000000001100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 645 11010100000000001101000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 646 11010100000000000100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 647 11011101000000000100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 648 11011101000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 649 11011100000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 650 11011100000000001101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 651 11011100000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011111 changed: 11 step 652 11011111000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 653 11011111000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 654 11011110000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 655 11011110000000001101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 656 11011110000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011011 changed: 0 1 step 657 11011011000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 658 11011011000000000101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 659 11011010000000001100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 660 11011010000000001101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 661 11011010000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 662 11011001000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 663 11011001000000000101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 664 11011000000000001100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 665 11011000000000001101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 666 11011000000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 667 11001001000000000100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 668 11001001000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 669 11001000000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 670 11001000000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 671 11001000000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 672 11001011000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 673 11001011000000000101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 674 11001010000000001100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 675 11001010000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 676 11001010000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 677 11001111000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 678 11001111000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 679 11001110000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 680 11001110000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 681 11001110000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 682 11001101000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 683 11001101000000000101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 684 11001100000000001100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 685 11001100000000001101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 686 11001100000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 687 11000101000000000100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 688 11000101000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 689 11000100000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 690 11000100000000001101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 691 11000100000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 11 step 692 11000111000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 693 11000111000000000101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 694 11000110000000001100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 695 11000110000000001101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 696 11000110000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 1 step 697 11000011000000000100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 698 11000011000000000101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 699 11000010000000001100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 700 11000010000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 701 11000010000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 01 step 702 11000001000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 703 11000001000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 704 11000000000000001100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 705 11000000000000001101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 706 11000000000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 1 step 707 10000001000000000100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 708 10000001000000000101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 709 10000000000000001100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 710 10000000000000001101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 711 10000000000000000100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 712 10000000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 11 step 713 10000011000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 714 10000011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 715 10000010000000011100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 716 10000010000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 717 10000010000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 1 step 718 10000111000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 719 10000111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 720 10000110000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 721 10000110000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 722 10000110000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 01 step 723 10000101000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 724 10000101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 725 10000100000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 726 10000100000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 727 10000100000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 728 10001101000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 729 10001101000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 730 10001100000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 731 10001100000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 732 10001100000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 733 10001111000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 734 10001111000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 735 10001110000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 736 10001110000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 737 10001110000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 738 10001011000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 739 10001011000000010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 740 10001010000000011100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 741 10001010000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 742 10001010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 743 10001001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 744 10001001000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 745 10001000000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 746 10001000000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 747 10001000000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 748 10011001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 749 10011001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 750 10011000000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 751 10011000000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 752 10011000000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 753 10011011000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 754 10011011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 755 10011010000000011100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 756 10011010000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 757 10011010000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 758 10011111000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 759 10011111000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 760 10011110000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 761 10011110000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 762 10011110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011101 changed: 01 step 763 10011101000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 764 10011101000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 765 10011100000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 766 10011100000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 767 10011100000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: 0 1 step 768 10010101000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 769 10010101000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 770 10010100000000011100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 771 10010100000000011101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 772 10010100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 11 step 773 10010111000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 774 10010111000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 775 10010110000000011100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 776 10010110000000011101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 777 10010110000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 1 step 778 10010011000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 779 10010011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 780 10010010000000011100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 781 10010010000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 782 10010010000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 01 step 783 10010001000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 784 10010001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 785 10010000000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 786 10010000000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 787 10010000000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 1 step 788 10110001000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 789 10110001000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 790 10110000000000011100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 791 10110000000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 792 10110000000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 11 step 793 10110011000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 794 10110011000000010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 795 10110010000000011100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 796 10110010000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 797 10110010000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 1 step 798 10110111000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 799 10110111000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 800 10110110000000011100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 801 10110110000000011101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 802 10110110000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 01 step 803 10110101000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 804 10110101000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 805 10110100000000011100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 806 10110100000000011101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 807 10110100000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 808 10111101000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 809 10111101000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 810 10111100000000011100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 811 10111100000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 812 10111100000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111111 changed: 11 step 813 10111111000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 814 10111111000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 815 10111110000000011100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 816 10111110000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 817 10111110000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111011 changed: 0 1 step 818 10111011000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 819 10111011000000010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 820 10111010000000011100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 821 10111010000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 822 10111010000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 823 10111001000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 824 10111001000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 825 10111000000000011100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 826 10111000000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 827 10111000000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 828 10101001000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 829 10101001000000010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 830 10101000000000011100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 831 10101000000000011101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 832 10101000000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 833 10101011000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 834 10101011000000010101000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 835 10101010000000011100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 836 10101010000000011101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 837 10101010000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 838 10101111000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 839 10101111000000010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 840 10101110000000011100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 841 10101110000000011101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 842 10101110000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 843 10101101000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 844 10101101000000010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 845 10101100000000011100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 846 10101100000000011101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 847 10101100000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 848 10100101000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 849 10100101000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 850 10100100000000011100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 851 10100100000000011101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 852 10100100000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 11 step 853 10100111000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 854 10100111000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 855 10100110000000011100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 856 10100110000000011101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 857 10100110000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 1 step 858 10100011000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 859 10100011000000010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 860 10100010000000011100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 861 10100010000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 862 10100010000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 01 step 863 10100001000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 864 10100001000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 865 10100000000000011100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 866 10100000000000011101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 867 10100000000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 1 step 868 11100001000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 869 11100001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 870 11100000000000011100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 871 11100000000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 872 11100000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 11 step 873 11100011000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 874 11100011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 875 11100010000000011100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 876 11100010000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 877 11100010000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 1 step 878 11100111000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 879 11100111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 880 11100110000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 881 11100110000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 882 11100110000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 01 step 883 11100101000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 884 11100101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 885 11100100000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 886 11100100000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 887 11100100000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 888 11101101000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 889 11101101000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 890 11101100000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 891 11101100000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 892 11101100000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 893 11101111000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 894 11101111000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 895 11101110000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 896 11101110000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 897 11101110000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 898 11101011000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 899 11101011000000010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 900 11101010000000011100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 901 11101010000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 902 11101010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 903 11101001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 904 11101001000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 905 11101000000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 906 11101000000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 907 11101000000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 908 11111001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 909 11111001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 910 11111000000000011100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 911 11111000000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 912 11111000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 913 11111011000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 914 11111011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 915 11111010000000011100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 916 11111010000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 917 11111010000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 918 11111111000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 919 11111111000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 920 11111110000000011100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 921 11111110000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 922 11111110000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111101 changed: 01 step 923 11111101000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 924 11111101000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 925 11111100000000011100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 926 11111100000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 927 11111100000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: 0 1 step 928 11110101000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 929 11110101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 930 11110100000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 931 11110100000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 932 11110100000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 11 step 933 11110111000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 934 11110111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 935 11110110000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 936 11110110000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 937 11110110000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 1 step 938 11110011000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 939 11110011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 940 11110010000000011100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 941 11110010000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 942 11110010000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 01 step 943 11110001000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 944 11110001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 945 11110000000000011100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 946 11110000000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 947 11110000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 1 step 948 11010001000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 949 11010001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 950 11010000000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 951 11010000000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 952 11010000000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 11 step 953 11010011000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 954 11010011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 955 11010010000000011100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 956 11010010000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 957 11010010000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 1 step 958 11010111000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 959 11010111000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 960 11010110000000011100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 961 11010110000000011101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 962 11010110000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 01 step 963 11010101000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 964 11010101000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 965 11010100000000011100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 966 11010100000000011101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 967 11010100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 968 11011101000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 969 11011101000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 970 11011100000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 971 11011100000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 972 11011100000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011111 changed: 11 step 973 11011111000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 974 11011111000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 975 11011110000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 976 11011110000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 977 11011110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011011 changed: 0 1 step 978 11011011000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 979 11011011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 980 11011010000000011100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 981 11011010000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 982 11011010000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 983 11011001000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 984 11011001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 985 11011000000000011100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 986 11011000000000011101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 987 11011000000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 988 11001001000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 989 11001001000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 990 11001000000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 991 11001000000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 992 11001000000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 993 11001011000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 994 11001011000000010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 995 11001010000000011100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 996 11001010000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 997 11001010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 998 11001111000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 999 11001111000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 1000 11001110000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 1001 11001110000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1002 11001110000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 1003 11001101000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 1004 11001101000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 1005 11001100000000011100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 1006 11001100000000011101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1007 11001100000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 1008 11000101000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 1009 11000101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 1010 11000100000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 1011 11000100000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1012 11000100000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 11 step 1013 11000111000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 1014 11000111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 1015 11000110000000011100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 1016 11000110000000011101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1017 11000110000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 1 step 1018 11000011000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 1019 11000011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 1020 11000010000000011100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1021 11000010000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1022 11000010000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 01 step 1023 11000001000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1024 11000001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 1025 11000000000000011100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1026 11000000000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1027 11000000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 1 step 1028 10000001000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 1029 10000001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 1 0 changed: 0 1 0 step 1030 10000000000000011100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1031 10000000000000011101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1032 10000000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 1033 10000000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 11 step 1034 10000011000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 1035 10000011000000010001000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1036 10000010000000010010000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 1037 10000010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1038 10000010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 1 step 1039 10000111000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 1040 10000111000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1041 10000110000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 1042 10000110000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1043 10000110000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 01 step 1044 10000101000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 1045 10000101000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1046 10000100000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 1047 10000100000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1048 10000100000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 1049 10001101000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 1050 10001101000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1051 10001100000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 1052 10001100000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1053 10001100000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 1054 10001111000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 1055 10001111000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1056 10001110000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 1057 10001110000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1058 10001110000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 1059 10001011000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 1060 10001011000000010001000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1061 10001010000000010010000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 1062 10001010000000010011000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1063 10001010000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 1064 10001001000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 1065 10001001000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1066 10001000000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 1067 10001000000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1068 10001000000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 1069 10011001000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 1070 10011001000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1071 10011000000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 1072 10011000000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1073 10011000000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 1074 10011011000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 1075 10011011000000010001000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1076 10011010000000010010000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 1077 10011010000000010011000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1078 10011010000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 1079 10011111000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 1080 10011111000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1081 10011110000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 1082 10011110000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1083 10011110000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011101 changed: 01 step 1084 10011101000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 1085 10011101000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1086 10011100000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 1087 10011100000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1088 10011100000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: 0 1 step 1089 10010101000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 1090 10010101000000010001000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1091 10010100000000010010000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 1092 10010100000000010011000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1093 10010100000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 11 step 1094 10010111000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 1095 10010111000000010001000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1096 10010110000000010010000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 1097 10010110000000010011000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1098 10010110000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 1 step 1099 10010011000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 1100 10010011000000010001000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1101 10010010000000010010000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 1102 10010010000000010011000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1103 10010010000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 01 step 1104 10010001000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 1105 10010001000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1106 10010000000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 1107 10010000000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1108 10010000000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 1 step 1109 10110001000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 1110 10110001000000010001000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1111 10110000000000010010000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1112 10110000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1113 10110000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 11 step 1114 10110011000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 1115 10110011000000010001000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1116 10110010000000010010000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 1117 10110010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1118 10110010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 1 step 1119 10110111000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 1120 10110111000000010001000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1121 10110110000000010010000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 1122 10110110000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1123 10110110000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 01 step 1124 10110101000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 1125 10110101000000010001000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1126 10110100000000010010000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 1127 10110100000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1128 10110100000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 1129 10111101000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 1130 10111101000000010001000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1131 10111100000000010010000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 1132 10111100000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1133 10111100000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111111 changed: 11 step 1134 10111111000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 1135 10111111000000010001000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1136 10111110000000010010000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 1137 10111110000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1138 10111110000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111011 changed: 0 1 step 1139 10111011000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 1140 10111011000000010001000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1141 10111010000000010010000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 1142 10111010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1143 10111010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 1144 10111001000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 1145 10111001000000010001000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1146 10111000000000010010000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 1147 10111000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1148 10111000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 1149 10101001000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 1150 10101001000000010001000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1151 10101000000000010010000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 1152 10101000000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1153 10101000000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 1154 10101011000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 1155 10101011000000010001000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1156 10101010000000010010000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 1157 10101010000000010011000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1158 10101010000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 1159 10101111000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 1160 10101111000000010001000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1161 10101110000000010010000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 1162 10101110000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1163 10101110000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 1164 10101101000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 1165 10101101000000010001000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1166 10101100000000010010000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 1167 10101100000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1168 10101100000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 1169 10100101000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 1170 10100101000000010001000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1171 10100100000000010010000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 1172 10100100000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1173 10100100000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 11 step 1174 10100111000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 1175 10100111000000010001000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1176 10100110000000010010000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 1177 10100110000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1178 10100110000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 1 step 1179 10100011000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 1180 10100011000000010001000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1181 10100010000000010010000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 1182 10100010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1183 10100010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 01 step 1184 10100001000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 1185 10100001000000010001000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1186 10100000000000010010000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1187 10100000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1188 10100000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 1 step 1189 11100001000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1190 11100001000000010001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1191 11100000000000010010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1192 11100000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1193 11100000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 11 step 1194 11100011000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 1195 11100011000000010001000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1196 11100010000000010010000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 1197 11100010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1198 11100010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 1 step 1199 11100111000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 1200 11100111000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1201 11100110000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 1202 11100110000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1203 11100110000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 01 step 1204 11100101000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 1205 11100101000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1206 11100100000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 1207 11100100000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1208 11100100000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 1209 11101101000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 1210 11101101000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1211 11101100000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 1212 11101100000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1213 11101100000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 1214 11101111000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 1215 11101111000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1216 11101110000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 1217 11101110000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1218 11101110000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 1219 11101011000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 1220 11101011000000010001000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1221 11101010000000010010000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 1222 11101010000000010011000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1223 11101010000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 1224 11101001000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 1225 11101001000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1226 11101000000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 1227 11101000000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1228 11101000000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 1229 11111001000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 1230 11111001000000010001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1231 11111000000000010010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 1232 11111000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1233 11111000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 1234 11111011000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 1235 11111011000000010001000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1236 11111010000000010010000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 1237 11111010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1238 11111010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 1239 11111111000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 1240 11111111000000010001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1241 11111110000000010010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 1242 11111110000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1243 11111110000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111101 changed: 01 step 1244 11111101000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 1245 11111101000000010001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1246 11111100000000010010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 1247 11111100000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1248 11111100000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: 0 1 step 1249 11110101000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 1250 11110101000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1251 11110100000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 1252 11110100000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1253 11110100000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 11 step 1254 11110111000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 1255 11110111000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1256 11110110000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 1257 11110110000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1258 11110110000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 1 step 1259 11110011000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 1260 11110011000000010001000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1261 11110010000000010010000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 1262 11110010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1263 11110010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 01 step 1264 11110001000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 1265 11110001000000010001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1266 11110000000000010010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1267 11110000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1268 11110000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 1 step 1269 11010001000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 1270 11010001000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1271 11010000000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 1272 11010000000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1273 11010000000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 11 step 1274 11010011000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 1275 11010011000000010001000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1276 11010010000000010010000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 1277 11010010000000010011000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1278 11010010000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 1 step 1279 11010111000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 1280 11010111000000010001000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1281 11010110000000010010000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 1282 11010110000000010011000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1283 11010110000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 01 step 1284 11010101000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 1285 11010101000000010001000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1286 11010100000000010010000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 1287 11010100000000010011000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1288 11010100000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 1289 11011101000000010000000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 1290 11011101000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1291 11011100000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 1292 11011100000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1293 11011100000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011111 changed: 11 step 1294 11011111000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 1295 11011111000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1296 11011110000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 1297 11011110000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1298 11011110000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011011 changed: 0 1 step 1299 11011011000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 1300 11011011000000010001000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1301 11011010000000010010000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 1302 11011010000000010011000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1303 11011010000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 1304 11011001000000010000000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 1305 11011001000000010001000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1306 11011000000000010010000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 1307 11011000000000010011000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1308 11011000000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 1309 11001001000000010000000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 1310 11001001000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1311 11001000000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 1312 11001000000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1313 11001000000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 1314 11001011000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 1315 11001011000000010001000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1316 11001010000000010010000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 1317 11001010000000010011000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1318 11001010000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 1319 11001111000000010000000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 1320 11001111000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1321 11001110000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 1322 11001110000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1323 11001110000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 1324 11001101000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 1325 11001101000000010001000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1326 11001100000000010010000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 1327 11001100000000010011000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1328 11001100000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 1329 11000101000000010000000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 1330 11000101000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1331 11000100000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 1332 11000100000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1333 11000100000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 11 step 1334 11000111000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 1335 11000111000000010001000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1336 11000110000000010010000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 1337 11000110000000010011000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1338 11000110000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 1 step 1339 11000011000000010000000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 1340 11000011000000010001000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1341 11000010000000010010000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 1342 11000010000000010011000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1343 11000010000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 01 step 1344 11000001000000010000000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1345 11000001000000010001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1346 11000000000000010010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 1347 11000000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1348 11000000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 1 step 1349 10000001000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 1350 10000001000000010001000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1351 10000000000000010010000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 1352 10000000000000010011000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1353 10000000000000010000000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 1354 10000000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 11 step 1355 10000011000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 1356 10000011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1357 10000010000000010110000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 1358 10000010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1359 10000010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000111 changed: 1 1 step 1360 10000111000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 1361 10000111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1362 10000110000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 1363 10000110000000010111000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1364 10000110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000101 changed: 01 step 1365 10000101000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 step 1366 10000101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1367 10000100000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 1368 10000100000000010111000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1369 10000100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001101 changed: 1 1 step 1370 10001101000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101001 changed: 1 step 1371 10001101000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1372 10001100000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 1373 10001100000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1374 10001100000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 1375 10001111000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 1376 10001111000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1377 10001110000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 1378 10001110000000010111000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1379 10001110000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 1380 10001011000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 1381 10001011000000010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1382 10001010000000010110000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 1383 10001010000000010111000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1384 10001010000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 1385 10001001000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100101 changed: 1 step 1386 10001001000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1387 10001000000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 1388 10001000000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1389 10001000000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 1390 10011001000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100101 changed: 1 step 1391 10011001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1392 10011000000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 1393 10011000000000010111000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1394 10011000000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 1395 10011011000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 1396 10011011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1397 10011010000000010110000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 1398 10011010000000010111000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1399 10011010000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 1400 10011111000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 1401 10011111000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1402 10011110000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 1403 10011110000000010111000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1404 10011110000000010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011101 changed: 01 step 1405 10011101000000010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101001 changed: 1 step 1406 10011101000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1407 10011100000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 1408 10011100000000010111000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1409 10011100000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010101 changed: 0 1 step 1410 10010101000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 step 1411 10010101000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1412 10010100000000010110000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 1413 10010100000000010111000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1414 10010100000000010100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010111 changed: 11 step 1415 10010111000000010100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 1416 10010111000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1417 10010110000000010110000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 1418 10010110000000010111000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1419 10010110000000010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010011 changed: 0 1 step 1420 10010011000000010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 1421 10010011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1422 10010010000000010110000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 1423 10010010000000010111000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1424 10010010000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0010001 changed: 01 step 1425 10010001000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 step 1426 10010001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1427 10010000000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 1428 10010000000000010111000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1429 10010000000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110001 changed: 1 1 step 1430 10110001000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 step 1431 10110001000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1432 10110000000000010110000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 1433 10110000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1434 10110000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110011 changed: 11 step 1435 10110011000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 1436 10110011000000010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1437 10110010000000010110000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 1438 10110010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1439 10110010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110111 changed: 1 1 step 1440 10110111000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 1441 10110111000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1442 10110110000000010110000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 1443 10110110000000010111000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1444 10110110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0110101 changed: 01 step 1445 10110101000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 step 1446 10110101000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1447 10110100000000010110000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 1448 10110100000000010111000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1449 10110100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111101 changed: 1 1 step 1450 10111101000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101001 changed: 1 step 1451 10111101000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1452 10111100000000010110000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 1453 10111100000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1454 10111100000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111111 changed: 11 step 1455 10111111000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 1456 10111111000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1457 10111110000000010110000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 1458 10111110000000010111000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1459 10111110000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111011 changed: 0 1 step 1460 10111011000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 1461 10111011000000010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1462 10111010000000010110000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 1463 10111010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1464 10111010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 1465 10111001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100101 changed: 1 step 1466 10111001000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1467 10111000000000010110000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 1468 10111000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1469 10111000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 1470 10101001000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100101 changed: 1 step 1471 10101001000000010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1472 10101000000000010110000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 1473 10101000000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1474 10101000000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 1475 10101011000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 1476 10101011000000010101000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1477 10101010000000010110000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 1478 10101010000000010111000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1479 10101010000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 1480 10101111000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 1481 10101111000000010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1482 10101110000000010110000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 1483 10101110000000010111000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1484 10101110000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 1485 10101101000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101001 changed: 1 step 1486 10101101000000010101000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1487 10101100000000010110000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 1488 10101100000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1489 10101100000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 1490 10100101000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 1 step 1491 10100101000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1492 10100100000000010110000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 1493 10100100000000010111000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1494 10100100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100111 changed: 11 step 1495 10100111000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 1496 10100111000000010101000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1497 10100110000000010110000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 1498 10100110000000010111000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1499 10100110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100011 changed: 0 1 step 1500 10100011000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 1501 10100011000000010101000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1502 10100010000000010110000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 1503 10100010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1504 10100010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100001 changed: 01 step 1505 10100001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010101 changed: 1 step 1506 10100001000000010101000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1507 10100000000000010110000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 1508 10100000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1509 10100000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100001 changed: 1 1 step 1510 11100001000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010101 changed: 1 step 1511 11100001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1512 11100000000000010110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 1513 11100000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1514 11100000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100011 changed: 11 step 1515 11100011000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 1516 11100011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1517 11100010000000010110000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 1518 11100010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1519 11100010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100111 changed: 1 1 step 1520 11100111000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 1521 11100111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1522 11100110000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 1523 11100110000000010111000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1524 11100110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101 changed: 01 step 1525 11100101000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 step 1526 11100101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1527 11100100000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 1528 11100100000000010111000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1529 11100100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101101 changed: 1 1 step 1530 11101101000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101001 changed: 1 step 1531 11101101000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1532 11101100000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 1533 11101100000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1534 11101100000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 1535 11101111000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 1536 11101111000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1537 11101110000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 1538 11101110000000010111000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1539 11101110000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 1540 11101011000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 1541 11101011000000010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1542 11101010000000010110000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 1543 11101010000000010111000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1544 11101010000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 1545 11101001000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100101 changed: 1 step 1546 11101001000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1547 11101000000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 1548 11101000000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1549 11101000000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 1550 11111001000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100101 changed: 1 step 1551 11111001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1552 11111000000000010110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 1553 11111000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1554 11111000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 1555 11111011000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 1556 11111011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1557 11111010000000010110000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 1558 11111010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1559 11111010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 1560 11111111000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 1561 11111111000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1562 11111110000000010110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101010 changed: 1 step 1563 11111110000000010111000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1564 11111110000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111101 changed: 01 step 1565 11111101000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010101001 changed: 1 step 1566 11111101000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1567 11111100000000010110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010100110 changed: 1 step 1568 11111100000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1569 11111100000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110101 changed: 0 1 step 1570 11110101000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 step 1571 11110101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1572 11110100000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001100110 changed: 1 step 1573 11110100000000010111000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1574 11110100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110111 changed: 11 step 1575 11110111000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 step 1576 11110111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1577 11110110000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001101010 changed: 1 step 1578 11110110000000010111000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1579 11110110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110011 changed: 0 1 step 1580 11110011000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 step 1581 11110011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1582 11110010000000010110000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 step 1583 11110010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1584 11110010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1110001 changed: 01 step 1585 11110001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 1586 11110001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1587 11110000000000010110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001010110 changed: 1 step 1588 11110000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1589 11110000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010001 changed: 0 1 step 1590 11010001000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 step 1591 11010001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1592 11010000000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001010110 changed: 1 step 1593 11010000000000010111000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1594 11010000000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010011 changed: 11 step 1595 11010011000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 step 1596 11010011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1597 11010010000000010110000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 1 step 1598 11010010000000010111000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1599 11010010000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010111 changed: 1 1 step 1600 11010111000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 step 1601 11010111000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1602 11010110000000010110000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001101010 changed: 1 step 1603 11010110000000010111000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1604 11010110000000010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101 changed: 01 step 1605 11010101000000010100000000000000 fail ^^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 step 1606 11010101000000010101000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1607 11010100000000010110000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001100110 changed: 1 step 1608 11010100000000010111000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1609 11010100000000010100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011101 changed: 1 1 step 1610 11011101000000010100000000000000 fail ^^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101001 changed: 1 step 1611 11011101000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1612 11011100000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010100110 changed: 1 step 1613 11011100000000010111000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1614 11011100000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011111 changed: 11 step 1615 11011111000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110101010 changed: 1 step 1616 11011111000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1617 11011110000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010101010 changed: 1 step 1618 11011110000000010111000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1619 11011110000000010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011011 changed: 0 1 step 1620 11011011000000010100000000000000 fail ^^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100110 changed: 1 step 1621 11011011000000010101000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1622 11011010000000010110000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 step 1623 11011010000000010111000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1624 11011010000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 1625 11011001000000010100000000000000 fail ^^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110100101 changed: 1 step 1626 11011001000000010101000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1627 11011000000000010110000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 step 1628 11011000000000010111000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1629 11011000000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 1630 11001001000000010100000000000000 fail ^^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100101 changed: 1 step 1631 11001001000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1632 11001000000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 step 1633 11001000000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1634 11001000000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 1635 11001011000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101100110 changed: 1 step 1636 11001011000000010101000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1637 11001010000000010110000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 step 1638 11001010000000010111000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1639 11001010000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 1640 11001111000000010100000000000000 fail ^ ^^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101010 changed: 1 step 1641 11001111000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1642 11001110000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110101010 changed: 1 step 1643 11001110000000010111000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1644 11001110000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 1645 11001101000000010100000000000000 fail ^ ^^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101101001 changed: 1 step 1646 11001101000000010101000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1647 11001100000000010110000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110100110 changed: 1 step 1648 11001100000000010111000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1649 11001100000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 1650 11000101000000010100000000000000 fail ^ ^^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 1 step 1651 11000101000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1652 11000100000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101100110 changed: 1 step 1653 11000100000000010111000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1654 11000100000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000111 changed: 11 step 1655 11000111000000010100000000000000 fail ^ ^ ^^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 1 step 1656 11000111000000010101000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1657 11000110000000010110000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101101010 changed: 1 step 1658 11000110000000010111000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1659 11000110000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000011 changed: 0 1 step 1660 11000011000000010100000000000000 fail ^ ^ ^^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010110 changed: 1 step 1661 11000011000000010101000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1662 11000010000000010110000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 1663 11000010000000010111000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1664 11000010000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000001 changed: 01 step 1665 11000001000000010100000000000000 fail ^ ^ ^ ^^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101010101 changed: 1 step 1666 11000001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1667 11000000000000010110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 1668 11000000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1669 11000000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0000001 changed: 0 1 step 1670 10000001000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010101 changed: 1 step 1671 10000001000000010101000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 10 changed: 0 10 step 1672 10000000000000010110000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101010110 changed: 1 step 1673 10000000000000010111000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1674 10000000000000010100000000000000 fail ^ ^ ^ ^ ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: source: ; end of SECTION GENERATED BY A PROGRAM source: source: source: ; CLEAR FFs source: 0 010101010101 changed: 0 step 1675 00000000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1 changed: 1 step 1676 10000000000000010100000000000000 fail ^ ^ ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: source: 11111110111111010100010101010101 changed: 111111 111111 step 1677 11111110111111010100000000000000 fail ^ ^ ^ ^ ^ ^ test 8: *** FAIL *************************** 1677 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail OOOOOOOOOOOO all fails OOOOOOOOOOOO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 8, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: ; CLEAR-N, NO ENABLES source: 01111110111111010100010101010101 changed: 0 step 1 01111110111111010100000000000000 fail ^ ^ ^ ^ ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails OOOOOOOOOOOO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 8, total passes 0 Main menu Fri Jun 30 19:19:07 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 19:19:09 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: ; CLEAR-N, NO ENABLES source: 01111110111111010100010101010101 changed: step 1 01111110111111010100010101010101 source: 1 changed: 1 step 2 11111110111111010100010101010101 source: source: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM source: ; see mk_m212_ld_shift.c source: source: source: ; TEST A INPUTS, GRAY CODE PATTERN source: source: ; ENABLE A INPUTS source: 1 changed: 1 step 3 11111111111111010100010101010101 source: ; LOAD FFs FROM INPUT A source: source: 000001 changed: 00000 step 4 10000011111111010100010101010101 source: 1010101010110 changed: 1 10 step 5 10000011111111010101010101010110 source: 0 changed: 0 step 6 10000011111111010100010101010110 source: 000011 changed: 1 step 7 10000111111111010100010101010110 source: 1010101011010 changed: 1 10 step 8 10000111111111010101010101011010 source: 0 changed: 0 step 9 10000111111111010100010101011010 source: 000010 changed: 0 step 10 10000101111111010100010101011010 source: 1010101011001 changed: 1 01 step 11 10000101111111010101010101011001 source: 0 changed: 0 step 12 10000101111111010100010101011001 source: 000110 changed: 1 step 13 10001101111111010100010101011001 source: 1010101101001 changed: 1 10 step 14 10001101111111010101010101101001 source: 0 changed: 0 step 15 10001101111111010100010101101001 source: 000111 changed: 1 step 16 10001111111111010100010101101001 source: 1010101101010 changed: 1 10 step 17 10001111111111010101010101101010 source: 0 changed: 0 step 18 10001111111111010100010101101010 source: 000101 changed: 0 step 19 10001011111111010100010101101010 source: 1010101100110 changed: 1 01 step 20 10001011111111010101010101100110 source: 0 changed: 0 step 21 10001011111111010100010101100110 source: 000100 changed: 0 step 22 10001001111111010100010101100110 source: 1010101100101 changed: 1 01 step 23 10001001111111010101010101100101 source: 0 changed: 0 step 24 10001001111111010100010101100101 source: 001100 changed: 1 step 25 10011001111111010100010101100101 source: 1010110100101 changed: 1 10 step 26 10011001111111010101010110100101 source: 0 changed: 0 step 27 10011001111111010100010110100101 source: 001101 changed: 1 step 28 10011011111111010100010110100101 source: 1010110100110 changed: 1 10 step 29 10011011111111010101010110100110 source: 0 changed: 0 step 30 10011011111111010100010110100110 source: 001111 changed: 1 step 31 10011111111111010100010110100110 source: 1010110101010 changed: 1 10 step 32 10011111111111010101010110101010 source: 0 changed: 0 step 33 10011111111111010100010110101010 source: 001110 changed: 0 step 34 10011101111111010100010110101010 source: 1010110101001 changed: 1 01 step 35 10011101111111010101010110101001 source: 0 changed: 0 step 36 10011101111111010100010110101001 source: 001010 changed: 0 step 37 10010101111111010100010110101001 source: 1010110011001 changed: 1 01 step 38 10010101111111010101010110011001 source: 0 changed: 0 step 39 10010101111111010100010110011001 source: 001011 changed: 1 step 40 10010111111111010100010110011001 source: 1010110011010 changed: 1 10 step 41 10010111111111010101010110011010 source: 0 changed: 0 step 42 10010111111111010100010110011010 source: 001001 changed: 0 step 43 10010011111111010100010110011010 source: 1010110010110 changed: 1 01 step 44 10010011111111010101010110010110 source: 0 changed: 0 step 45 10010011111111010100010110010110 source: 001000 changed: 0 step 46 10010001111111010100010110010110 source: 1010110010101 changed: 1 01 step 47 10010001111111010101010110010101 source: 0 changed: 0 step 48 10010001111111010100010110010101 source: 011000 changed: 1 step 49 10110001111111010100010110010101 source: 1011010010101 changed: 1 10 step 50 10110001111111010101011010010101 source: 0 changed: 0 step 51 10110001111111010100011010010101 source: 011001 changed: 1 step 52 10110011111111010100011010010101 source: 1011010010110 changed: 1 10 step 53 10110011111111010101011010010110 source: 0 changed: 0 step 54 10110011111111010100011010010110 source: 011011 changed: 1 step 55 10110111111111010100011010010110 source: 1011010011010 changed: 1 10 step 56 10110111111111010101011010011010 source: 0 changed: 0 step 57 10110111111111010100011010011010 source: 011010 changed: 0 step 58 10110101111111010100011010011010 source: 1011010011001 changed: 1 01 step 59 10110101111111010101011010011001 source: 0 changed: 0 step 60 10110101111111010100011010011001 source: 011110 changed: 1 step 61 10111101111111010100011010011001 source: 1011010101001 changed: 1 10 step 62 10111101111111010101011010101001 source: 0 changed: 0 step 63 10111101111111010100011010101001 source: 011111 changed: 1 step 64 10111111111111010100011010101001 source: 1011010101010 changed: 1 10 step 65 10111111111111010101011010101010 source: 0 changed: 0 step 66 10111111111111010100011010101010 source: 011101 changed: 0 step 67 10111011111111010100011010101010 source: 1011010100110 changed: 1 01 step 68 10111011111111010101011010100110 source: 0 changed: 0 step 69 10111011111111010100011010100110 source: 011100 changed: 0 step 70 10111001111111010100011010100110 source: 1011010100101 changed: 1 01 step 71 10111001111111010101011010100101 source: 0 changed: 0 step 72 10111001111111010100011010100101 source: 010100 changed: 0 step 73 10101001111111010100011010100101 source: 1011001100101 changed: 1 01 step 74 10101001111111010101011001100101 source: 0 changed: 0 step 75 10101001111111010100011001100101 source: 010101 changed: 1 step 76 10101011111111010100011001100101 source: 1011001100110 changed: 1 10 step 77 10101011111111010101011001100110 source: 0 changed: 0 step 78 10101011111111010100011001100110 source: 010111 changed: 1 step 79 10101111111111010100011001100110 source: 1011001101010 changed: 1 10 step 80 10101111111111010101011001101010 source: 0 changed: 0 step 81 10101111111111010100011001101010 source: 010110 changed: 0 step 82 10101101111111010100011001101010 source: 1011001101001 changed: 1 01 step 83 10101101111111010101011001101001 source: 0 changed: 0 step 84 10101101111111010100011001101001 source: 010010 changed: 0 step 85 10100101111111010100011001101001 source: 1011001011001 changed: 1 01 step 86 10100101111111010101011001011001 source: 0 changed: 0 step 87 10100101111111010100011001011001 source: 010011 changed: 1 step 88 10100111111111010100011001011001 source: 1011001011010 changed: 1 10 step 89 10100111111111010101011001011010 source: 0 changed: 0 step 90 10100111111111010100011001011010 source: 010001 changed: 0 step 91 10100011111111010100011001011010 source: 1011001010110 changed: 1 01 step 92 10100011111111010101011001010110 source: 0 changed: 0 step 93 10100011111111010100011001010110 source: 010000 changed: 0 step 94 10100001111111010100011001010110 source: 1011001010101 changed: 1 01 step 95 10100001111111010101011001010101 source: 0 changed: 0 step 96 10100001111111010100011001010101 source: 110000 changed: 1 step 97 11100001111111010100011001010101 source: 1101001010101 changed: 110 step 98 11100001111111010101101001010101 source: 0 changed: 0 step 99 11100001111111010100101001010101 source: 110001 changed: 1 step 100 11100011111111010100101001010101 source: 1101001010110 changed: 1 10 step 101 11100011111111010101101001010110 source: 0 changed: 0 step 102 11100011111111010100101001010110 source: 110011 changed: 1 step 103 11100111111111010100101001010110 source: 1101001011010 changed: 1 10 step 104 11100111111111010101101001011010 source: 0 changed: 0 step 105 11100111111111010100101001011010 source: 110010 changed: 0 step 106 11100101111111010100101001011010 source: 1101001011001 changed: 1 01 step 107 11100101111111010101101001011001 source: 0 changed: 0 step 108 11100101111111010100101001011001 source: 110110 changed: 1 step 109 11101101111111010100101001011001 source: 1101001101001 changed: 1 10 step 110 11101101111111010101101001101001 source: 0 changed: 0 step 111 11101101111111010100101001101001 source: 110111 changed: 1 step 112 11101111111111010100101001101001 source: 1101001101010 changed: 1 10 step 113 11101111111111010101101001101010 source: 0 changed: 0 step 114 11101111111111010100101001101010 source: 110101 changed: 0 step 115 11101011111111010100101001101010 source: 1101001100110 changed: 1 01 step 116 11101011111111010101101001100110 source: 0 changed: 0 step 117 11101011111111010100101001100110 source: 110100 changed: 0 step 118 11101001111111010100101001100110 source: 1101001100101 changed: 1 01 step 119 11101001111111010101101001100101 source: 0 changed: 0 step 120 11101001111111010100101001100101 source: 111100 changed: 1 step 121 11111001111111010100101001100101 source: 1101010100101 changed: 1 10 step 122 11111001111111010101101010100101 source: 0 changed: 0 step 123 11111001111111010100101010100101 source: 111101 changed: 1 step 124 11111011111111010100101010100101 source: 1101010100110 changed: 1 10 step 125 11111011111111010101101010100110 source: 0 changed: 0 step 126 11111011111111010100101010100110 source: 111111 changed: 1 step 127 11111111111111010100101010100110 source: 1101010101010 changed: 1 10 step 128 11111111111111010101101010101010 source: 0 changed: 0 step 129 11111111111111010100101010101010 source: 111110 changed: 0 step 130 11111101111111010100101010101010 source: 1101010101001 changed: 1 01 step 131 11111101111111010101101010101001 source: 0 changed: 0 step 132 11111101111111010100101010101001 source: 111010 changed: 0 step 133 11110101111111010100101010101001 source: 1101010011001 changed: 1 01 step 134 11110101111111010101101010011001 source: 0 changed: 0 step 135 11110101111111010100101010011001 source: 111011 changed: 1 step 136 11110111111111010100101010011001 source: 1101010011010 changed: 1 10 step 137 11110111111111010101101010011010 source: 0 changed: 0 step 138 11110111111111010100101010011010 source: 111001 changed: 0 step 139 11110011111111010100101010011010 source: 1101010010110 changed: 1 01 step 140 11110011111111010101101010010110 source: 0 changed: 0 step 141 11110011111111010100101010010110 source: 111000 changed: 0 step 142 11110001111111010100101010010110 source: 1101010010101 changed: 1 01 step 143 11110001111111010101101010010101 source: 0 changed: 0 step 144 11110001111111010100101010010101 source: 101000 changed: 0 step 145 11010001111111010100101010010101 source: 1100110010101 changed: 1 01 step 146 11010001111111010101100110010101 source: 0 changed: 0 step 147 11010001111111010100100110010101 source: 101001 changed: 1 step 148 11010011111111010100100110010101 source: 1100110010110 changed: 1 10 step 149 11010011111111010101100110010110 source: 0 changed: 0 step 150 11010011111111010100100110010110 source: 101011 changed: 1 step 151 11010111111111010100100110010110 source: 1100110011010 changed: 1 10 step 152 11010111111111010101100110011010 source: 0 changed: 0 step 153 11010111111111010100100110011010 source: 101010 changed: 0 step 154 11010101111111010100100110011010 source: 1100110011001 changed: 1 01 step 155 11010101111111010101100110011001 source: 0 changed: 0 step 156 11010101111111010100100110011001 source: 101110 changed: 1 step 157 11011101111111010100100110011001 source: 1100110101001 changed: 1 10 step 158 11011101111111010101100110101001 source: 0 changed: 0 step 159 11011101111111010100100110101001 source: 101111 changed: 1 step 160 11011111111111010100100110101001 source: 1100110101010 changed: 1 10 step 161 11011111111111010101100110101010 source: 0 changed: 0 step 162 11011111111111010100100110101010 source: 101101 changed: 0 step 163 11011011111111010100100110101010 source: 1100110100110 changed: 1 01 step 164 11011011111111010101100110100110 source: 0 changed: 0 step 165 11011011111111010100100110100110 source: 101100 changed: 0 step 166 11011001111111010100100110100110 source: 1100110100101 changed: 1 01 step 167 11011001111111010101100110100101 source: 0 changed: 0 step 168 11011001111111010100100110100101 source: 100100 changed: 0 step 169 11001001111111010100100110100101 source: 1100101100101 changed: 1 01 step 170 11001001111111010101100101100101 source: 0 changed: 0 step 171 11001001111111010100100101100101 source: 100101 changed: 1 step 172 11001011111111010100100101100101 source: 1100101100110 changed: 1 10 step 173 11001011111111010101100101100110 source: 0 changed: 0 step 174 11001011111111010100100101100110 source: 100111 changed: 1 step 175 11001111111111010100100101100110 source: 1100101101010 changed: 1 10 step 176 11001111111111010101100101101010 source: 0 changed: 0 step 177 11001111111111010100100101101010 source: 100110 changed: 0 step 178 11001101111111010100100101101010 source: 1100101101001 changed: 1 01 step 179 11001101111111010101100101101001 source: 0 changed: 0 step 180 11001101111111010100100101101001 source: 100010 changed: 0 step 181 11000101111111010100100101101001 source: 1100101011001 changed: 1 01 step 182 11000101111111010101100101011001 source: 0 changed: 0 step 183 11000101111111010100100101011001 source: 100011 changed: 1 step 184 11000111111111010100100101011001 source: 1100101011010 changed: 1 10 step 185 11000111111111010101100101011010 source: 0 changed: 0 step 186 11000111111111010100100101011010 source: 100001 changed: 0 step 187 11000011111111010100100101011010 source: 1100101010110 changed: 1 01 step 188 11000011111111010101100101010110 source: 0 changed: 0 step 189 11000011111111010100100101010110 source: 100000 changed: 0 step 190 11000001111111010100100101010110 source: 1100101010101 changed: 1 01 step 191 11000001111111010101100101010101 source: 0 changed: 0 step 192 11000001111111010100100101010101 source: 000000 changed: 0 step 193 10000001111111010100100101010101 source: 1010101010101 changed: 101 step 194 10000001111111010101010101010101 source: 0 changed: 0 step 195 10000001111111010100010101010101 source: source: ; DISABLE A INPUTS source: 0 changed: 0 step 196 10000000111111010100010101010101 source: source: source: ; TEST B INPUTS source: source: ; ENABLE B INPUTS source: 1 changed: 1 step 197 10000000111111110100010101010101 source: ; LOAD FFs FROM INPUT B source: source: 000001 changed: 00000 step 198 10000000000001110100010101010101 source: 1010101010110 changed: 1 10 step 199 10000000000001110101010101010110 source: 0 changed: 0 step 200 10000000000001110100010101010110 source: 000011 changed: 1 step 201 10000000000011110100010101010110 source: 1010101011010 changed: 1 10 step 202 10000000000011110101010101011010 source: 0 changed: 0 step 203 10000000000011110100010101011010 source: 000010 changed: 0 step 204 10000000000010110100010101011010 source: 1010101011001 changed: 1 01 step 205 10000000000010110101010101011001 source: 0 changed: 0 step 206 10000000000010110100010101011001 source: 000110 changed: 1 step 207 10000000000110110100010101011001 source: 1010101101001 changed: 1 10 step 208 10000000000110110101010101101001 source: 0 changed: 0 step 209 10000000000110110100010101101001 source: 000111 changed: 1 step 210 10000000000111110100010101101001 source: 1010101101010 changed: 1 10 step 211 10000000000111110101010101101010 source: 0 changed: 0 step 212 10000000000111110100010101101010 source: 000101 changed: 0 step 213 10000000000101110100010101101010 source: 1010101100110 changed: 1 01 step 214 10000000000101110101010101100110 source: 0 changed: 0 step 215 10000000000101110100010101100110 source: 000100 changed: 0 step 216 10000000000100110100010101100110 source: 1010101100101 changed: 1 01 step 217 10000000000100110101010101100101 source: 0 changed: 0 step 218 10000000000100110100010101100101 source: 001100 changed: 1 step 219 10000000001100110100010101100101 source: 1010110100101 changed: 1 10 step 220 10000000001100110101010110100101 source: 0 changed: 0 step 221 10000000001100110100010110100101 source: 001101 changed: 1 step 222 10000000001101110100010110100101 source: 1010110100110 changed: 1 10 step 223 10000000001101110101010110100110 source: 0 changed: 0 step 224 10000000001101110100010110100110 source: 001111 changed: 1 step 225 10000000001111110100010110100110 source: 1010110101010 changed: 1 10 step 226 10000000001111110101010110101010 source: 0 changed: 0 step 227 10000000001111110100010110101010 source: 001110 changed: 0 step 228 10000000001110110100010110101010 source: 1010110101001 changed: 1 01 step 229 10000000001110110101010110101001 source: 0 changed: 0 step 230 10000000001110110100010110101001 source: 001010 changed: 0 step 231 10000000001010110100010110101001 source: 1010110011001 changed: 1 01 step 232 10000000001010110101010110011001 source: 0 changed: 0 step 233 10000000001010110100010110011001 source: 001011 changed: 1 step 234 10000000001011110100010110011001 source: 1010110011010 changed: 1 10 step 235 10000000001011110101010110011010 source: 0 changed: 0 step 236 10000000001011110100010110011010 source: 001001 changed: 0 step 237 10000000001001110100010110011010 source: 1010110010110 changed: 1 01 step 238 10000000001001110101010110010110 source: 0 changed: 0 step 239 10000000001001110100010110010110 source: 001000 changed: 0 step 240 10000000001000110100010110010110 source: 1010110010101 changed: 1 01 step 241 10000000001000110101010110010101 source: 0 changed: 0 step 242 10000000001000110100010110010101 source: 011000 changed: 1 step 243 10000000011000110100010110010101 source: 1011010010101 changed: 1 10 step 244 10000000011000110101011010010101 source: 0 changed: 0 step 245 10000000011000110100011010010101 source: 011001 changed: 1 step 246 10000000011001110100011010010101 source: 1011010010110 changed: 1 10 step 247 10000000011001110101011010010110 source: 0 changed: 0 step 248 10000000011001110100011010010110 source: 011011 changed: 1 step 249 10000000011011110100011010010110 source: 1011010011010 changed: 1 10 step 250 10000000011011110101011010011010 source: 0 changed: 0 step 251 10000000011011110100011010011010 source: 011010 changed: 0 step 252 10000000011010110100011010011010 source: 1011010011001 changed: 1 01 step 253 10000000011010110101011010011001 source: 0 changed: 0 step 254 10000000011010110100011010011001 source: 011110 changed: 1 step 255 10000000011110110100011010011001 source: 1011010101001 changed: 1 10 step 256 10000000011110110101011010101001 source: 0 changed: 0 step 257 10000000011110110100011010101001 source: 011111 changed: 1 step 258 10000000011111110100011010101001 source: 1011010101010 changed: 1 10 step 259 10000000011111110101011010101010 source: 0 changed: 0 step 260 10000000011111110100011010101010 source: 011101 changed: 0 step 261 10000000011101110100011010101010 source: 1011010100110 changed: 1 01 step 262 10000000011101110101011010100110 source: 0 changed: 0 step 263 10000000011101110100011010100110 source: 011100 changed: 0 step 264 10000000011100110100011010100110 source: 1011010100101 changed: 1 01 step 265 10000000011100110101011010100101 source: 0 changed: 0 step 266 10000000011100110100011010100101 source: 010100 changed: 0 step 267 10000000010100110100011010100101 source: 1011001100101 changed: 1 01 step 268 10000000010100110101011001100101 source: 0 changed: 0 step 269 10000000010100110100011001100101 source: 010101 changed: 1 step 270 10000000010101110100011001100101 source: 1011001100110 changed: 1 10 step 271 10000000010101110101011001100110 source: 0 changed: 0 step 272 10000000010101110100011001100110 source: 010111 changed: 1 step 273 10000000010111110100011001100110 source: 1011001101010 changed: 1 10 step 274 10000000010111110101011001101010 source: 0 changed: 0 step 275 10000000010111110100011001101010 source: 010110 changed: 0 step 276 10000000010110110100011001101010 source: 1011001101001 changed: 1 01 step 277 10000000010110110101011001101001 source: 0 changed: 0 step 278 10000000010110110100011001101001 source: 010010 changed: 0 step 279 10000000010010110100011001101001 source: 1011001011001 changed: 1 01 step 280 10000000010010110101011001011001 source: 0 changed: 0 step 281 10000000010010110100011001011001 source: 010011 changed: 1 step 282 10000000010011110100011001011001 source: 1011001011010 changed: 1 10 step 283 10000000010011110101011001011010 source: 0 changed: 0 step 284 10000000010011110100011001011010 source: 010001 changed: 0 step 285 10000000010001110100011001011010 source: 1011001010110 changed: 1 01 step 286 10000000010001110101011001010110 source: 0 changed: 0 step 287 10000000010001110100011001010110 source: 010000 changed: 0 step 288 10000000010000110100011001010110 source: 1011001010101 changed: 1 01 step 289 10000000010000110101011001010101 source: 0 changed: 0 step 290 10000000010000110100011001010101 source: 110000 changed: 1 step 291 10000000110000110100011001010101 source: 1101001010101 changed: 110 step 292 10000000110000110101101001010101 source: 0 changed: 0 step 293 10000000110000110100101001010101 source: 110001 changed: 1 step 294 10000000110001110100101001010101 source: 1101001010110 changed: 1 10 step 295 10000000110001110101101001010110 source: 0 changed: 0 step 296 10000000110001110100101001010110 source: 110011 changed: 1 step 297 10000000110011110100101001010110 source: 1101001011010 changed: 1 10 step 298 10000000110011110101101001011010 source: 0 changed: 0 step 299 10000000110011110100101001011010 source: 110010 changed: 0 step 300 10000000110010110100101001011010 source: 1101001011001 changed: 1 01 step 301 10000000110010110101101001011001 source: 0 changed: 0 step 302 10000000110010110100101001011001 source: 110110 changed: 1 step 303 10000000110110110100101001011001 source: 1101001101001 changed: 1 10 step 304 10000000110110110101101001101001 source: 0 changed: 0 step 305 10000000110110110100101001101001 source: 110111 changed: 1 step 306 10000000110111110100101001101001 source: 1101001101010 changed: 1 10 step 307 10000000110111110101101001101010 source: 0 changed: 0 step 308 10000000110111110100101001101010 source: 110101 changed: 0 step 309 10000000110101110100101001101010 source: 1101001100110 changed: 1 01 step 310 10000000110101110101101001100110 source: 0 changed: 0 step 311 10000000110101110100101001100110 source: 110100 changed: 0 step 312 10000000110100110100101001100110 source: 1101001100101 changed: 1 01 step 313 10000000110100110101101001100101 source: 0 changed: 0 step 314 10000000110100110100101001100101 source: 111100 changed: 1 step 315 10000000111100110100101001100101 source: 1101010100101 changed: 1 10 step 316 10000000111100110101101010100101 source: 0 changed: 0 step 317 10000000111100110100101010100101 source: 111101 changed: 1 step 318 10000000111101110100101010100101 source: 1101010100110 changed: 1 10 step 319 10000000111101110101101010100110 source: 0 changed: 0 step 320 10000000111101110100101010100110 source: 111111 changed: 1 step 321 10000000111111110100101010100110 source: 1101010101010 changed: 1 10 step 322 10000000111111110101101010101010 source: 0 changed: 0 step 323 10000000111111110100101010101010 source: 111110 changed: 0 step 324 10000000111110110100101010101010 source: 1101010101001 changed: 1 01 step 325 10000000111110110101101010101001 source: 0 changed: 0 step 326 10000000111110110100101010101001 source: 111010 changed: 0 step 327 10000000111010110100101010101001 source: 1101010011001 changed: 1 01 step 328 10000000111010110101101010011001 source: 0 changed: 0 step 329 10000000111010110100101010011001 source: 111011 changed: 1 step 330 10000000111011110100101010011001 source: 1101010011010 changed: 1 10 step 331 10000000111011110101101010011010 source: 0 changed: 0 step 332 10000000111011110100101010011010 source: 111001 changed: 0 step 333 10000000111001110100101010011010 source: 1101010010110 changed: 1 01 step 334 10000000111001110101101010010110 source: 0 changed: 0 step 335 10000000111001110100101010010110 source: 111000 changed: 0 step 336 10000000111000110100101010010110 source: 1101010010101 changed: 1 01 step 337 10000000111000110101101010010101 source: 0 changed: 0 step 338 10000000111000110100101010010101 source: 101000 changed: 0 step 339 10000000101000110100101010010101 source: 1100110010101 changed: 1 01 step 340 10000000101000110101100110010101 source: 0 changed: 0 step 341 10000000101000110100100110010101 source: 101001 changed: 1 step 342 10000000101001110100100110010101 source: 1100110010110 changed: 1 10 step 343 10000000101001110101100110010110 source: 0 changed: 0 step 344 10000000101001110100100110010110 source: 101011 changed: 1 step 345 10000000101011110100100110010110 source: 1100110011010 changed: 1 10 step 346 10000000101011110101100110011010 source: 0 changed: 0 step 347 10000000101011110100100110011010 source: 101010 changed: 0 step 348 10000000101010110100100110011010 source: 1100110011001 changed: 1 01 step 349 10000000101010110101100110011001 source: 0 changed: 0 step 350 10000000101010110100100110011001 source: 101110 changed: 1 step 351 10000000101110110100100110011001 source: 1100110101001 changed: 1 10 step 352 10000000101110110101100110101001 source: 0 changed: 0 step 353 10000000101110110100100110101001 source: 101111 changed: 1 step 354 10000000101111110100100110101001 source: 1100110101010 changed: 1 10 step 355 10000000101111110101100110101010 source: 0 changed: 0 step 356 10000000101111110100100110101010 source: 101101 changed: 0 step 357 10000000101101110100100110101010 source: 1100110100110 changed: 1 01 step 358 10000000101101110101100110100110 source: 0 changed: 0 step 359 10000000101101110100100110100110 source: 101100 changed: 0 step 360 10000000101100110100100110100110 source: 1100110100101 changed: 1 01 step 361 10000000101100110101100110100101 source: 0 changed: 0 step 362 10000000101100110100100110100101 source: 100100 changed: 0 step 363 10000000100100110100100110100101 source: 1100101100101 changed: 1 01 step 364 10000000100100110101100101100101 source: 0 changed: 0 step 365 10000000100100110100100101100101 source: 100101 changed: 1 step 366 10000000100101110100100101100101 source: 1100101100110 changed: 1 10 step 367 10000000100101110101100101100110 source: 0 changed: 0 step 368 10000000100101110100100101100110 source: 100111 changed: 1 step 369 10000000100111110100100101100110 source: 1100101101010 changed: 1 10 step 370 10000000100111110101100101101010 source: 0 changed: 0 step 371 10000000100111110100100101101010 source: 100110 changed: 0 step 372 10000000100110110100100101101010 source: 1100101101001 changed: 1 01 step 373 10000000100110110101100101101001 source: 0 changed: 0 step 374 10000000100110110100100101101001 source: 100010 changed: 0 step 375 10000000100010110100100101101001 source: 1100101011001 changed: 1 01 step 376 10000000100010110101100101011001 source: 0 changed: 0 step 377 10000000100010110100100101011001 source: 100011 changed: 1 step 378 10000000100011110100100101011001 source: 1100101011010 changed: 1 10 step 379 10000000100011110101100101011010 source: 0 changed: 0 step 380 10000000100011110100100101011010 source: 100001 changed: 0 step 381 10000000100001110100100101011010 source: 1100101010110 changed: 1 01 step 382 10000000100001110101100101010110 source: 0 changed: 0 step 383 10000000100001110100100101010110 source: 100000 changed: 0 step 384 10000000100000110100100101010110 source: 1100101010101 changed: 1 01 step 385 10000000100000110101100101010101 source: 0 changed: 0 step 386 10000000100000110100100101010101 source: 000000 changed: 0 step 387 10000000000000110100100101010101 source: 1010101010101 changed: 101 step 388 10000000000000110101010101010101 source: 0 changed: 0 step 389 10000000000000110100010101010101 source: source: ; DISABLE B INPUTS source: 0 changed: 0 step 390 10000000000000010100010101010101 source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 391 10000000000000000100010101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 11 step 392 10000011000000000100010101010101 source: 1010101010110 changed: 1 10 step 393 10000011000000000101010101010110 source: 0 1 0 changed: 0 1 0 step 394 10000010000000001100010101010110 source: 1010101010101 changed: 1 01 step 395 10000010000000001101010101010101 source: 0 0 changed: 0 0 step 396 10000010000000000100010101010101 source: 0000111 changed: 1 1 step 397 10000111000000000100010101010101 source: 1010101011010 changed: 1 1010 step 398 10000111000000000101010101011010 source: 0 1 0 changed: 0 1 0 step 399 10000110000000001100010101011010 source: 1010101010110 changed: 1 01 step 400 10000110000000001101010101010110 source: 0 0 changed: 0 0 step 401 10000110000000000100010101010110 source: 0000101 changed: 01 step 402 10000101000000000100010101010110 source: 1010101011001 changed: 1 1001 step 403 10000101000000000101010101011001 source: 0 1 0 changed: 0 1 0 step 404 10000100000000001100010101011001 source: 1010101010110 changed: 1 0110 step 405 10000100000000001101010101010110 source: 0 0 changed: 0 0 step 406 10000100000000000100010101010110 source: 0001101 changed: 1 1 step 407 10001101000000000100010101010110 source: 1010101101001 changed: 1 101001 step 408 10001101000000000101010101101001 source: 0 1 0 changed: 0 1 0 step 409 10001100000000001100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 10 step 410 10001100000000001101010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 411 10001100000000000100010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 412 10001111000000000100010101101010 fail ^^ source: 1010101101010 changed: 1 step 413 10001111000000000101010101101010 source: 0 1 0 changed: 0 1 0 step 414 10001110000000001100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 415 10001110000000001101010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 416 10001110000000000100010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 417 10001011000000000100010101101010 fail ^^ source: 1010101100110 changed: 1 01 step 418 10001011000000000101010101100110 source: 0 1 0 changed: 0 1 0 step 419 10001010000000001100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 1001 step 420 10001010000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 421 10001010000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 422 10001001000000000100010101101001 fail ^^ source: 1010101100101 changed: 1 01 step 423 10001001000000000101010101100101 source: 0 1 0 changed: 0 1 0 step 424 10001000000000001100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 10 step 425 10001000000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 426 10001000000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 427 10011001000000000100010101101001 fail ^^ source: 1010110100101 changed: 1 10 01 step 428 10011001000000000101010110100101 source: 0 1 0 changed: 0 1 0 step 429 10011000000000001100010110100101 source: 1010101101001 changed: 1 01 10 step 430 10011000000000001101010101101001 source: 0 0 changed: 0 0 step 431 10011000000000000100010101101001 source: 0011011 changed: 11 step 432 10011011000000000100010101101001 source: 1010110100110 changed: 1 10 0110 step 433 10011011000000000101010110100110 source: 0 1 0 changed: 0 1 0 step 434 10011010000000001100010110100110 source: 1010101101001 changed: 1 01 1001 step 435 10011010000000001101010101101001 source: 0 0 changed: 0 0 step 436 10011010000000000100010101101001 source: 0011111 changed: 1 1 step 437 10011111000000000100010101101001 source: 1010110101010 changed: 1 10 10 step 438 10011111000000000101010110101010 source: 0 1 0 changed: 0 1 0 step 439 10011110000000001100010110101010 source: 1010101101010 changed: 1 01 step 440 10011110000000001101010101101010 source: 0 0 changed: 0 0 step 441 10011110000000000100010101101010 source: 0011101 changed: 01 step 442 10011101000000000100010101101010 source: 1010110101001 changed: 1 10 01 step 443 10011101000000000101010110101001 source: 0 1 0 changed: 0 1 0 step 444 10011100000000001100010110101001 source: 1010101101010 changed: 1 01 10 step 445 10011100000000001101010101101010 source: 0 0 changed: 0 0 step 446 10011100000000000100010101101010 source: 0010101 changed: 0 1 step 447 10010101000000000100010101101010 source: 1010110011001 changed: 1 1001 01 step 448 10010101000000000101010110011001 source: 0 1 0 changed: 0 1 0 step 449 10010100000000001100010110011001 source: 1010101100110 changed: 1 01100110 step 450 10010100000000001101010101100110 source: 0 0 changed: 0 0 step 451 10010100000000000100010101100110 source: 0010111 changed: 11 step 452 10010111000000000100010101100110 source: 1010110011010 changed: 1 100110 step 453 10010111000000000101010110011010 source: 0 1 0 changed: 0 1 0 step 454 10010110000000001100010110011010 source: 1010101100110 changed: 1 011001 step 455 10010110000000001101010101100110 source: 0 0 changed: 0 0 step 456 10010110000000000100010101100110 source: 0010011 changed: 0 1 step 457 10010011000000000100010101100110 source: 1010110010110 changed: 1 1001 step 458 10010011000000000101010110010110 source: 0 1 0 changed: 0 1 0 step 459 10010010000000001100010110010110 source: 1010101100101 changed: 1 0110 01 step 460 10010010000000001101010101100101 source: 0 0 changed: 0 0 step 461 10010010000000000100010101100101 source: 0010001 changed: 01 step 462 10010001000000000100010101100101 source: 1010110010101 changed: 1 1001 step 463 10010001000000000101010110010101 source: 0 1 0 changed: 0 1 0 step 464 10010000000000001100010110010101 source: 1010101100101 changed: 1 0110 step 465 10010000000000001101010101100101 source: 0 0 changed: 0 0 step 466 10010000000000000100010101100101 source: 0110001 changed: 1 1 step 467 10110001000000000100010101100101 source: 1011010010101 changed: 1 101001 step 468 10110001000000000101011010010101 source: 0 1 0 changed: 0 1 0 step 469 10110000000000001100011010010101 source: 1010110100101 changed: 1 01 10 step 470 10110000000000001101010110100101 source: 0 0 changed: 0 0 step 471 10110000000000000100010110100101 source: 0110011 changed: 11 step 472 10110011000000000100010110100101 source: 1011010010110 changed: 1 10 01 10 step 473 10110011000000000101011010010110 source: 0 1 0 changed: 0 1 0 step 474 10110010000000001100011010010110 source: 1010110100101 changed: 1 01 10 01 step 475 10110010000000001101010110100101 source: 0 0 changed: 0 0 step 476 10110010000000000100010110100101 source: 0110111 changed: 1 1 step 477 10110111000000000100010110100101 source: 1011010011010 changed: 1 10 011010 step 478 10110111000000000101011010011010 source: 0 1 0 changed: 0 1 0 step 479 10110110000000001100011010011010 source: 1010110100110 changed: 1 01 1001 step 480 10110110000000001101010110100110 source: 0 0 changed: 0 0 step 481 10110110000000000100010110100110 source: 0110101 changed: 01 step 482 10110101000000000100010110100110 source: 1011010011001 changed: 1 10 011001 step 483 10110101000000000101011010011001 source: 0 1 0 changed: 0 1 0 step 484 10110100000000001100011010011001 source: 1010110100110 changed: 1 01 100110 step 485 10110100000000001101010110100110 source: 0 0 changed: 0 0 step 486 10110100000000000100010110100110 source: 0111101 changed: 1 1 step 487 10111101000000000100010110100110 source: 1011010101001 changed: 1 10 1001 step 488 10111101000000000101011010101001 source: 0 1 0 changed: 0 1 0 step 489 10111100000000001100011010101001 source: 1010110101010 changed: 1 01 10 step 490 10111100000000001101010110101010 source: 0 0 changed: 0 0 step 491 10111100000000000100010110101010 source: 0111111 changed: 11 step 492 10111111000000000100010110101010 source: 1011010101010 changed: 1 10 step 493 10111111000000000101011010101010 source: 0 1 0 changed: 0 1 0 step 494 10111110000000001100011010101010 source: 1010110101010 changed: 1 01 step 495 10111110000000001101010110101010 source: 0 0 changed: 0 0 step 496 10111110000000000100010110101010 source: 0111011 changed: 0 1 step 497 10111011000000000100010110101010 source: 1011010100110 changed: 1 10 01 step 498 10111011000000000101011010100110 source: 0 1 0 changed: 0 1 0 step 499 10111010000000001100011010100110 source: 1010110101001 changed: 1 01 1001 step 500 10111010000000001101010110101001 source: 0 0 changed: 0 0 step 501 10111010000000000100010110101001 source: 0111001 changed: 01 step 502 10111001000000000100010110101001 source: 1011010100101 changed: 1 10 01 step 503 10111001000000000101011010100101 source: 0 1 0 changed: 0 1 0 step 504 10111000000000001100011010100101 source: 1010110101001 changed: 1 01 10 step 505 10111000000000001101010110101001 source: 0 0 changed: 0 0 step 506 10111000000000000100010110101001 source: 0101001 changed: 0 1 step 507 10101001000000000100010110101001 source: 1011001100101 changed: 1 1001 01 step 508 10101001000000000101011001100101 source: 0 1 0 changed: 0 1 0 step 509 10101000000000001100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 0110 10 step 510 10101000000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 511 10101000000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 512 10101011000000000100010110101001 fail ^^ source: 1011001100110 changed: 1 1001 0110 step 513 10101011000000000101011001100110 source: 0 1 0 changed: 0 1 0 step 514 10101010000000001100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 0110 1001 step 515 10101010000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 516 10101010000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 517 10101111000000000100010110101001 fail ^^ source: 1011001101010 changed: 1 1001 10 step 518 10101111000000000101011001101010 source: 0 1 0 changed: 0 1 0 step 519 10101110000000001100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 0110 step 520 10101110000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 521 10101110000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 522 10101101000000000100010110101010 fail ^^ source: 1011001101001 changed: 1 1001 01 step 523 10101101000000000101011001101001 source: 0 1 0 changed: 0 1 0 step 524 10101100000000001100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 0110 10 step 525 10101100000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 526 10101100000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 527 10100101000000000100010110101010 fail ^^ source: 1011001011001 changed: 1 100101 01 step 528 10100101000000000101011001011001 source: 0 1 0 changed: 0 1 0 step 529 10100100000000001100011001011001 source: 1010110010110 changed: 1 0110 0110 step 530 10100100000000001101010110010110 source: 0 0 changed: 0 0 step 531 10100100000000000100010110010110 source: 0100111 changed: 11 step 532 10100111000000000100010110010110 source: 1011001011010 changed: 1 1001 10 step 533 10100111000000000101011001011010 source: 0 1 0 changed: 0 1 0 step 534 10100110000000001100011001011010 source: 1010110010110 changed: 1 0110 01 step 535 10100110000000001101010110010110 source: 0 0 changed: 0 0 step 536 10100110000000000100010110010110 source: 0100011 changed: 0 1 step 537 10100011000000000100010110010110 source: 1011001010110 changed: 1 1001 step 538 10100011000000000101011001010110 source: 0 1 0 changed: 0 1 0 step 539 10100010000000001100011001010110 source: 1010110010101 changed: 1 0110 01 step 540 10100010000000001101010110010101 source: 0 0 changed: 0 0 step 541 10100010000000000100010110010101 source: 0100001 changed: 01 step 542 10100001000000000100010110010101 source: 1011001010101 changed: 1 1001 step 543 10100001000000000101011001010101 source: 0 1 0 changed: 0 1 0 step 544 10100000000000001100011001010101 source: 1010110010101 changed: 1 0110 step 545 10100000000000001101010110010101 source: 0 0 changed: 0 0 step 546 10100000000000000100010110010101 source: 1100001 changed: 1 1 step 547 11100001000000000100010110010101 source: 1101001010101 changed: 1101001 step 548 11100001000000000101101001010101 source: 0 1 0 changed: 0 1 0 step 549 11100000000000001100101001010101 source: 1011010010101 changed: 101 10 step 550 11100000000000001101011010010101 source: 0 0 changed: 0 0 step 551 11100000000000000100011010010101 source: 1100011 changed: 11 step 552 11100011000000000100011010010101 source: 1101001010110 changed: 110 01 10 step 553 11100011000000000101101001010110 source: 0 1 0 changed: 0 1 0 step 554 11100010000000001100101001010110 source: 1011010010101 changed: 101 10 01 step 555 11100010000000001101011010010101 source: 0 0 changed: 0 0 step 556 11100010000000000100011010010101 source: 1100111 changed: 1 1 step 557 11100111000000000100011010010101 source: 1101001011010 changed: 110 01 1010 step 558 11100111000000000101101001011010 source: 0 1 0 changed: 0 1 0 step 559 11100110000000001100101001011010 source: 1011010010110 changed: 101 10 01 step 560 11100110000000001101011010010110 source: 0 0 changed: 0 0 step 561 11100110000000000100011010010110 source: 1100101 changed: 01 step 562 11100101000000000100011010010110 source: 1101001011001 changed: 110 01 1001 step 563 11100101000000000101101001011001 source: 0 1 0 changed: 0 1 0 step 564 11100100000000001100101001011001 source: 1011010010110 changed: 101 10 0110 step 565 11100100000000001101011010010110 source: 0 0 changed: 0 0 step 566 11100100000000000100011010010110 source: 1101101 changed: 1 1 step 567 11101101000000000100011010010110 source: 1101001101001 changed: 110 01101001 step 568 11101101000000000101101001101001 source: 0 1 0 changed: 0 1 0 step 569 11101100000000001100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 101 10 10 step 570 11101100000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 571 11101100000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 572 11101111000000000100011010101010 fail ^^ source: 1101001101010 changed: 110 01 step 573 11101111000000000101101001101010 source: 0 1 0 changed: 0 1 0 step 574 11101110000000001100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 101 10 step 575 11101110000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 576 11101110000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 577 11101011000000000100011010101010 fail ^^ source: 1101001100110 changed: 110 01 01 step 578 11101011000000000101101001100110 source: 0 1 0 changed: 0 1 0 step 579 11101010000000001100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 101 10 1001 step 580 11101010000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 581 11101010000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 582 11101001000000000100011010101001 fail ^^ source: 1101001100101 changed: 110 01 01 step 583 11101001000000000101101001100101 source: 0 1 0 changed: 0 1 0 step 584 11101000000000001100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 101 10 10 step 585 11101000000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 586 11101000000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 587 11111001000000000100011010101001 fail ^^ source: 1101010100101 changed: 110 01 step 588 11111001000000000101101010100101 source: 0 1 0 changed: 0 1 0 step 589 11111000000000001100101010100101 source: 1011010101001 changed: 101 10 step 590 11111000000000001101011010101001 source: 0 0 changed: 0 0 step 591 11111000000000000100011010101001 source: 1111011 changed: 11 step 592 11111011000000000100011010101001 source: 1101010100110 changed: 110 0110 step 593 11111011000000000101101010100110 source: 0 1 0 changed: 0 1 0 step 594 11111010000000001100101010100110 source: 1011010101001 changed: 101 1001 step 595 11111010000000001101011010101001 source: 0 0 changed: 0 0 step 596 11111010000000000100011010101001 source: 1111111 changed: 1 1 step 597 11111111000000000100011010101001 source: 1101010101010 changed: 110 10 step 598 11111111000000000101101010101010 source: 0 1 0 changed: 0 1 0 step 599 11111110000000001100101010101010 source: 1011010101010 changed: 101 step 600 11111110000000001101011010101010 source: 0 0 changed: 0 0 step 601 11111110000000000100011010101010 source: 1111101 changed: 01 step 602 11111101000000000100011010101010 source: 1101010101001 changed: 110 01 step 603 11111101000000000101101010101001 source: 0 1 0 changed: 0 1 0 step 604 11111100000000001100101010101001 source: 1011010101010 changed: 101 10 step 605 11111100000000001101011010101010 source: 0 0 changed: 0 0 step 606 11111100000000000100011010101010 source: 1110101 changed: 0 1 step 607 11110101000000000100011010101010 source: 1101010011001 changed: 110 01 01 step 608 11110101000000000101101010011001 source: 0 1 0 changed: 0 1 0 step 609 11110100000000001100101010011001 source: 1011010100110 changed: 101 100110 step 610 11110100000000001101011010100110 source: 0 0 changed: 0 0 step 611 11110100000000000100011010100110 source: 1110111 changed: 11 step 612 11110111000000000100011010100110 source: 1101010011010 changed: 110 0110 step 613 11110111000000000101101010011010 source: 0 1 0 changed: 0 1 0 step 614 11110110000000001100101010011010 source: 1011010100110 changed: 101 1001 step 615 11110110000000001101011010100110 source: 0 0 changed: 0 0 step 616 11110110000000000100011010100110 source: 1110011 changed: 0 1 step 617 11110011000000000100011010100110 source: 1101010010110 changed: 110 01 step 618 11110011000000000101101010010110 source: 0 1 0 changed: 0 1 0 step 619 11110010000000001100101010010110 source: 1011010100101 changed: 101 10 01 step 620 11110010000000001101011010100101 source: 0 0 changed: 0 0 step 621 11110010000000000100011010100101 source: 1110001 changed: 01 step 622 11110001000000000100011010100101 source: 1101010010101 changed: 110 01 step 623 11110001000000000101101010010101 source: 0 1 0 changed: 0 1 0 step 624 11110000000000001100101010010101 source: 1011010100101 changed: 101 10 step 625 11110000000000001101011010100101 source: 0 0 changed: 0 0 step 626 11110000000000000100011010100101 source: 1010001 changed: 0 1 step 627 11010001000000000100011010100101 source: 1100110010101 changed: 11001 01 step 628 11010001000000000101100110010101 source: 0 1 0 changed: 0 1 0 step 629 11010000000000001100100110010101 source: 1011001100101 changed: 101100110 step 630 11010000000000001101011001100101 source: 0 0 changed: 0 0 step 631 11010000000000000100011001100101 source: 1010011 changed: 11 step 632 11010011000000000100011001100101 source: 1100110010110 changed: 110011001 10 step 633 11010011000000000101100110010110 source: 0 1 0 changed: 0 1 0 step 634 11010010000000001100100110010110 source: 1011001100101 changed: 101100110 01 step 635 11010010000000001101011001100101 source: 0 0 changed: 0 0 step 636 11010010000000000100011001100101 source: 1010111 changed: 1 1 step 637 11010111000000000100011001100101 source: 1100110011010 changed: 1100110011010 step 638 11010111000000000101100110011010 source: 0 1 0 changed: 0 1 0 step 639 11010110000000001100100110011010 source: 1011001100110 changed: 10110011001 step 640 11010110000000001101011001100110 source: 0 0 changed: 0 0 step 641 11010110000000000100011001100110 source: 1010101 changed: 01 step 642 11010101000000000100011001100110 source: 1100110011001 changed: 1100110011001 step 643 11010101000000000101100110011001 source: 0 1 0 changed: 0 1 0 step 644 11010100000000001100100110011001 source: 1011001100110 changed: 1011001100110 step 645 11010100000000001101011001100110 source: 0 0 changed: 0 0 step 646 11010100000000000100011001100110 source: 1011101 changed: 1 1 step 647 11011101000000000100011001100110 source: 1100110101001 changed: 1100110 1001 step 648 11011101000000000101100110101001 source: 0 1 0 changed: 0 1 0 step 649 11011100000000001100100110101001 source: 1011001101010 changed: 1011001 10 step 650 11011100000000001101011001101010 source: 0 0 changed: 0 0 step 651 11011100000000000100011001101010 source: 1011111 changed: 11 step 652 11011111000000000100011001101010 source: 1100110101010 changed: 1100110 step 653 11011111000000000101100110101010 source: 0 1 0 changed: 0 1 0 step 654 11011110000000001100100110101010 source: 1011001101010 changed: 1011001 step 655 11011110000000001101011001101010 source: 0 0 changed: 0 0 step 656 11011110000000000100011001101010 source: 1011011 changed: 0 1 step 657 11011011000000000100011001101010 source: 1100110100110 changed: 1100110 01 step 658 11011011000000000101100110100110 source: 0 1 0 changed: 0 1 0 step 659 11011010000000001100100110100110 source: 1011001101001 changed: 1011001 1001 step 660 11011010000000001101011001101001 source: 0 0 changed: 0 0 step 661 11011010000000000100011001101001 source: 1011001 changed: 01 step 662 11011001000000000100011001101001 source: 1100110100101 changed: 1100110 01 step 663 11011001000000000101100110100101 source: 0 1 0 changed: 0 1 0 step 664 11011000000000001100100110100101 source: 1011001101001 changed: 1011001 10 step 665 11011000000000001101011001101001 source: 0 0 changed: 0 0 step 666 11011000000000000100011001101001 source: 1001001 changed: 0 1 step 667 11001001000000000100011001101001 source: 1100101100101 changed: 11001 01 step 668 11001001000000000101100101100101 source: 0 1 0 changed: 0 1 0 step 669 11001000000000001100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 10110 10 step 670 11001000000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 671 11001000000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 672 11001011000000000100011001101001 fail ^^ source: 1100101100110 changed: 11001 0110 step 673 11001011000000000101100101100110 source: 0 1 0 changed: 0 1 0 step 674 11001010000000001100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 10110 1001 step 675 11001010000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 676 11001010000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 677 11001111000000000100011001101001 fail ^^ source: 1100101101010 changed: 11001 10 step 678 11001111000000000101100101101010 source: 0 1 0 changed: 0 1 0 step 679 11001110000000001100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 10110 step 680 11001110000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 681 11001110000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 682 11001101000000000100011001101010 fail ^^ source: 1100101101001 changed: 11001 01 step 683 11001101000000000101100101101001 source: 0 1 0 changed: 0 1 0 step 684 11001100000000001100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 10110 10 step 685 11001100000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 686 11001100000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 687 11000101000000000100011001101010 fail ^^ source: 1100101011001 changed: 11001 01 01 step 688 11000101000000000101100101011001 source: 0 1 0 changed: 0 1 0 step 689 11000100000000001100100101011001 source: 1011001010110 changed: 10110 0110 step 690 11000100000000001101011001010110 source: 0 0 changed: 0 0 step 691 11000100000000000100011001010110 source: 1000111 changed: 11 step 692 11000111000000000100011001010110 source: 1100101011010 changed: 11001 10 step 693 11000111000000000101100101011010 source: 0 1 0 changed: 0 1 0 step 694 11000110000000001100100101011010 source: 1011001010110 changed: 10110 01 step 695 11000110000000001101011001010110 source: 0 0 changed: 0 0 step 696 11000110000000000100011001010110 source: 1000011 changed: 0 1 step 697 11000011000000000100011001010110 source: 1100101010110 changed: 11001 step 698 11000011000000000101100101010110 source: 0 1 0 changed: 0 1 0 step 699 11000010000000001100100101010110 source: 1011001010101 changed: 10110 01 step 700 11000010000000001101011001010101 source: 0 0 changed: 0 0 step 701 11000010000000000100011001010101 source: 1000001 changed: 01 step 702 11000001000000000100011001010101 source: 1100101010101 changed: 11001 step 703 11000001000000000101100101010101 source: 0 1 0 changed: 0 1 0 step 704 11000000000000001100100101010101 source: 1011001010101 changed: 10110 step 705 11000000000000001101011001010101 source: 0 0 changed: 0 0 step 706 11000000000000000100011001010101 source: 0000001 changed: 0 1 step 707 10000001000000000100011001010101 source: 1010101010101 changed: 1 01 step 708 10000001000000000101010101010101 source: 0 1 0 changed: 0 1 0 step 709 10000000000000001100010101010101 source: 1010101010101 changed: 1 step 710 10000000000000001101010101010101 source: 0 0 changed: 0 0 step 711 10000000000000000100010101010101 source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 712 10000000000000010100010101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 11 step 713 10000011000000010100010101010101 source: 1010101010110 changed: 1 10 step 714 10000011000000010101010101010110 source: 0 1 0 changed: 0 1 0 step 715 10000010000000011100010101010110 source: 1100101010101 changed: 110 01 step 716 10000010000000011101100101010101 source: 0 0 changed: 0 0 step 717 10000010000000010100100101010101 source: 0000111 changed: 1 1 step 718 10000111000000010100100101010101 source: 1010101011010 changed: 101 1010 step 719 10000111000000010101010101011010 source: 0 1 0 changed: 0 1 0 step 720 10000110000000011100010101011010 source: 1100101010110 changed: 110 01 step 721 10000110000000011101100101010110 source: 0 0 changed: 0 0 step 722 10000110000000010100100101010110 source: 0000101 changed: 01 step 723 10000101000000010100100101010110 source: 1010101011001 changed: 101 1001 step 724 10000101000000010101010101011001 source: 0 1 0 changed: 0 1 0 step 725 10000100000000011100010101011001 source: 1100101010110 changed: 110 0110 step 726 10000100000000011101100101010110 source: 0 0 changed: 0 0 step 727 10000100000000010100100101010110 source: 0001101 changed: 1 1 step 728 10001101000000010100100101010110 source: 1010101101001 changed: 101 101001 step 729 10001101000000010101010101101001 source: 0 1 0 changed: 0 1 0 step 730 10001100000000011100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 110 10 step 731 10001100000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 732 10001100000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 733 10001111000000010100100101101010 fail ^^ source: 1010101101010 changed: 101 step 734 10001111000000010101010101101010 source: 0 1 0 changed: 0 1 0 step 735 10001110000000011100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 110 step 736 10001110000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 737 10001110000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 738 10001011000000010100100101101010 fail ^^ source: 1010101100110 changed: 101 01 step 739 10001011000000010101010101100110 source: 0 1 0 changed: 0 1 0 step 740 10001010000000011100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 110 1001 step 741 10001010000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 742 10001010000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 743 10001001000000010100100101101001 fail ^^ source: 1010101100101 changed: 101 01 step 744 10001001000000010101010101100101 source: 0 1 0 changed: 0 1 0 step 745 10001000000000011100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 110 10 step 746 10001000000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 747 10001000000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 748 10011001000000010100100101101001 fail ^^ source: 1010110100101 changed: 101 10 01 step 749 10011001000000010101010110100101 source: 0 1 0 changed: 0 1 0 step 750 10011000000000011100010110100101 source: 1100101101001 changed: 110 01 10 step 751 10011000000000011101100101101001 source: 0 0 changed: 0 0 step 752 10011000000000010100100101101001 source: 0011011 changed: 11 step 753 10011011000000010100100101101001 source: 1010110100110 changed: 101 10 0110 step 754 10011011000000010101010110100110 source: 0 1 0 changed: 0 1 0 step 755 10011010000000011100010110100110 source: 1100101101001 changed: 110 01 1001 step 756 10011010000000011101100101101001 source: 0 0 changed: 0 0 step 757 10011010000000010100100101101001 source: 0011111 changed: 1 1 step 758 10011111000000010100100101101001 source: 1010110101010 changed: 101 10 10 step 759 10011111000000010101010110101010 source: 0 1 0 changed: 0 1 0 step 760 10011110000000011100010110101010 source: 1100101101010 changed: 110 01 step 761 10011110000000011101100101101010 source: 0 0 changed: 0 0 step 762 10011110000000010100100101101010 source: 0011101 changed: 01 step 763 10011101000000010100100101101010 source: 1010110101001 changed: 101 10 01 step 764 10011101000000010101010110101001 source: 0 1 0 changed: 0 1 0 step 765 10011100000000011100010110101001 source: 1100101101010 changed: 110 01 10 step 766 10011100000000011101100101101010 source: 0 0 changed: 0 0 step 767 10011100000000010100100101101010 source: 0010101 changed: 0 1 step 768 10010101000000010100100101101010 source: 1010110011001 changed: 101 1001 01 step 769 10010101000000010101010110011001 source: 0 1 0 changed: 0 1 0 step 770 10010100000000011100010110011001 source: 1100101100110 changed: 110 01100110 step 771 10010100000000011101100101100110 source: 0 0 changed: 0 0 step 772 10010100000000010100100101100110 source: 0010111 changed: 11 step 773 10010111000000010100100101100110 source: 1010110011010 changed: 101 100110 step 774 10010111000000010101010110011010 source: 0 1 0 changed: 0 1 0 step 775 10010110000000011100010110011010 source: 1100101100110 changed: 110 011001 step 776 10010110000000011101100101100110 source: 0 0 changed: 0 0 step 777 10010110000000010100100101100110 source: 0010011 changed: 0 1 step 778 10010011000000010100100101100110 source: 1010110010110 changed: 101 1001 step 779 10010011000000010101010110010110 source: 0 1 0 changed: 0 1 0 step 780 10010010000000011100010110010110 source: 1100101100101 changed: 110 0110 01 step 781 10010010000000011101100101100101 source: 0 0 changed: 0 0 step 782 10010010000000010100100101100101 source: 0010001 changed: 01 step 783 10010001000000010100100101100101 source: 1010110010101 changed: 101 1001 step 784 10010001000000010101010110010101 source: 0 1 0 changed: 0 1 0 step 785 10010000000000011100010110010101 source: 1100101100101 changed: 110 0110 step 786 10010000000000011101100101100101 source: 0 0 changed: 0 0 step 787 10010000000000010100100101100101 source: 0110001 changed: 1 1 step 788 10110001000000010100100101100101 source: 1011010010101 changed: 101101001 step 789 10110001000000010101011010010101 source: 0 1 0 changed: 0 1 0 step 790 10110000000000011100011010010101 source: 1100110100101 changed: 11001 10 step 791 10110000000000011101100110100101 source: 0 0 changed: 0 0 step 792 10110000000000010100100110100101 source: 0110011 changed: 11 step 793 10110011000000010100100110100101 source: 1011010010110 changed: 10110 01 10 step 794 10110011000000010101011010010110 source: 0 1 0 changed: 0 1 0 step 795 10110010000000011100011010010110 source: 1100110100101 changed: 11001 10 01 step 796 10110010000000011101100110100101 source: 0 0 changed: 0 0 step 797 10110010000000010100100110100101 source: 0110111 changed: 1 1 step 798 10110111000000010100100110100101 source: 1011010011010 changed: 10110 011010 step 799 10110111000000010101011010011010 source: 0 1 0 changed: 0 1 0 step 800 10110110000000011100011010011010 source: 1100110100110 changed: 11001 1001 step 801 10110110000000011101100110100110 source: 0 0 changed: 0 0 step 802 10110110000000010100100110100110 source: 0110101 changed: 01 step 803 10110101000000010100100110100110 source: 1011010011001 changed: 10110 011001 step 804 10110101000000010101011010011001 source: 0 1 0 changed: 0 1 0 step 805 10110100000000011100011010011001 source: 1100110100110 changed: 11001 100110 step 806 10110100000000011101100110100110 source: 0 0 changed: 0 0 step 807 10110100000000010100100110100110 source: 0111101 changed: 1 1 step 808 10111101000000010100100110100110 source: 1011010101001 changed: 10110 1001 step 809 10111101000000010101011010101001 source: 0 1 0 changed: 0 1 0 step 810 10111100000000011100011010101001 source: 1100110101010 changed: 11001 10 step 811 10111100000000011101100110101010 source: 0 0 changed: 0 0 step 812 10111100000000010100100110101010 source: 0111111 changed: 11 step 813 10111111000000010100100110101010 source: 1011010101010 changed: 10110 step 814 10111111000000010101011010101010 source: 0 1 0 changed: 0 1 0 step 815 10111110000000011100011010101010 source: 1100110101010 changed: 11001 step 816 10111110000000011101100110101010 source: 0 0 changed: 0 0 step 817 10111110000000010100100110101010 source: 0111011 changed: 0 1 step 818 10111011000000010100100110101010 source: 1011010100110 changed: 10110 01 step 819 10111011000000010101011010100110 source: 0 1 0 changed: 0 1 0 step 820 10111010000000011100011010100110 source: 1100110101001 changed: 11001 1001 step 821 10111010000000011101100110101001 source: 0 0 changed: 0 0 step 822 10111010000000010100100110101001 source: 0111001 changed: 01 step 823 10111001000000010100100110101001 source: 1011010100101 changed: 10110 01 step 824 10111001000000010101011010100101 source: 0 1 0 changed: 0 1 0 step 825 10111000000000011100011010100101 source: 1100110101001 changed: 11001 10 step 826 10111000000000011101100110101001 source: 0 0 changed: 0 0 step 827 10111000000000010100100110101001 source: 0101001 changed: 0 1 step 828 10101001000000010100100110101001 source: 1011001100101 changed: 1011001 01 step 829 10101001000000010101011001100101 source: 0 1 0 changed: 0 1 0 step 830 10101000000000011100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110 10 step 831 10101000000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 832 10101000000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 833 10101011000000010100100110101001 fail ^^ source: 1011001100110 changed: 1011001 0110 step 834 10101011000000010101011001100110 source: 0 1 0 changed: 0 1 0 step 835 10101010000000011100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110 1001 step 836 10101010000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 837 10101010000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 838 10101111000000010100100110101001 fail ^^ source: 1011001101010 changed: 1011001 10 step 839 10101111000000010101011001101010 source: 0 1 0 changed: 0 1 0 step 840 10101110000000011100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1100110 step 841 10101110000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 842 10101110000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 843 10101101000000010100100110101010 fail ^^ source: 1011001101001 changed: 1011001 01 step 844 10101101000000010101011001101001 source: 0 1 0 changed: 0 1 0 step 845 10101100000000011100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1100110 10 step 846 10101100000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 847 10101100000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 848 10100101000000010100100110101010 fail ^^ source: 1011001011001 changed: 101100101 01 step 849 10100101000000010101011001011001 source: 0 1 0 changed: 0 1 0 step 850 10100100000000011100011001011001 source: 1100110010110 changed: 1100110 0110 step 851 10100100000000011101100110010110 source: 0 0 changed: 0 0 step 852 10100100000000010100100110010110 source: 0100111 changed: 11 step 853 10100111000000010100100110010110 source: 1011001011010 changed: 1011001 10 step 854 10100111000000010101011001011010 source: 0 1 0 changed: 0 1 0 step 855 10100110000000011100011001011010 source: 1100110010110 changed: 1100110 01 step 856 10100110000000011101100110010110 source: 0 0 changed: 0 0 step 857 10100110000000010100100110010110 source: 0100011 changed: 0 1 step 858 10100011000000010100100110010110 source: 1011001010110 changed: 1011001 step 859 10100011000000010101011001010110 source: 0 1 0 changed: 0 1 0 step 860 10100010000000011100011001010110 source: 1100110010101 changed: 1100110 01 step 861 10100010000000011101100110010101 source: 0 0 changed: 0 0 step 862 10100010000000010100100110010101 source: 0100001 changed: 01 step 863 10100001000000010100100110010101 source: 1011001010101 changed: 1011001 step 864 10100001000000010101011001010101 source: 0 1 0 changed: 0 1 0 step 865 10100000000000011100011001010101 source: 1100110010101 changed: 1100110 step 866 10100000000000011101100110010101 source: 0 0 changed: 0 0 step 867 10100000000000010100100110010101 source: 1100001 changed: 1 1 step 868 11100001000000010100100110010101 source: 1101001010101 changed: 1 1001 step 869 11100001000000010101101001010101 source: 0 1 0 changed: 0 1 0 step 870 11100000000000011100101001010101 source: 1101010010101 changed: 1 10 step 871 11100000000000011101101010010101 source: 0 0 changed: 0 0 step 872 11100000000000010100101010010101 source: 1100011 changed: 11 step 873 11100011000000010100101010010101 source: 1101001010110 changed: 1 01 10 step 874 11100011000000010101101001010110 source: 0 1 0 changed: 0 1 0 step 875 11100010000000011100101001010110 source: 1101010010101 changed: 1 10 01 step 876 11100010000000011101101010010101 source: 0 0 changed: 0 0 step 877 11100010000000010100101010010101 source: 1100111 changed: 1 1 step 878 11100111000000010100101010010101 source: 1101001011010 changed: 1 01 1010 step 879 11100111000000010101101001011010 source: 0 1 0 changed: 0 1 0 step 880 11100110000000011100101001011010 source: 1101010010110 changed: 1 10 01 step 881 11100110000000011101101010010110 source: 0 0 changed: 0 0 step 882 11100110000000010100101010010110 source: 1100101 changed: 01 step 883 11100101000000010100101010010110 source: 1101001011001 changed: 1 01 1001 step 884 11100101000000010101101001011001 source: 0 1 0 changed: 0 1 0 step 885 11100100000000011100101001011001 source: 1101010010110 changed: 1 10 0110 step 886 11100100000000011101101010010110 source: 0 0 changed: 0 0 step 887 11100100000000010100101010010110 source: 1101101 changed: 1 1 step 888 11101101000000010100101010010110 source: 1101001101001 changed: 1 01101001 step 889 11101101000000010101101001101001 source: 0 1 0 changed: 0 1 0 step 890 11101100000000011100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 10 10 step 891 11101100000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 892 11101100000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 893 11101111000000010100101010101010 fail ^^ source: 1101001101010 changed: 1 01 step 894 11101111000000010101101001101010 source: 0 1 0 changed: 0 1 0 step 895 11101110000000011100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 10 step 896 11101110000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 897 11101110000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 898 11101011000000010100101010101010 fail ^^ source: 1101001100110 changed: 1 01 01 step 899 11101011000000010101101001100110 source: 0 1 0 changed: 0 1 0 step 900 11101010000000011100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 10 1001 step 901 11101010000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 902 11101010000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 903 11101001000000010100101010101001 fail ^^ source: 1101001100101 changed: 1 01 01 step 904 11101001000000010101101001100101 source: 0 1 0 changed: 0 1 0 step 905 11101000000000011100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 10 10 step 906 11101000000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 907 11101000000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 908 11111001000000010100101010101001 fail ^^ source: 1101010100101 changed: 1 01 step 909 11111001000000010101101010100101 source: 0 1 0 changed: 0 1 0 step 910 11111000000000011100101010100101 source: 1101010101001 changed: 1 10 step 911 11111000000000011101101010101001 source: 0 0 changed: 0 0 step 912 11111000000000010100101010101001 source: 1111011 changed: 11 step 913 11111011000000010100101010101001 source: 1101010100110 changed: 1 0110 step 914 11111011000000010101101010100110 source: 0 1 0 changed: 0 1 0 step 915 11111010000000011100101010100110 source: 1101010101001 changed: 1 1001 step 916 11111010000000011101101010101001 source: 0 0 changed: 0 0 step 917 11111010000000010100101010101001 source: 1111111 changed: 1 1 step 918 11111111000000010100101010101001 source: 1101010101010 changed: 1 10 step 919 11111111000000010101101010101010 source: 0 1 0 changed: 0 1 0 step 920 11111110000000011100101010101010 source: 1101010101010 changed: 1 step 921 11111110000000011101101010101010 source: 0 0 changed: 0 0 step 922 11111110000000010100101010101010 source: 1111101 changed: 01 step 923 11111101000000010100101010101010 source: 1101010101001 changed: 1 01 step 924 11111101000000010101101010101001 source: 0 1 0 changed: 0 1 0 step 925 11111100000000011100101010101001 source: 1101010101010 changed: 1 10 step 926 11111100000000011101101010101010 source: 0 0 changed: 0 0 step 927 11111100000000010100101010101010 source: 1110101 changed: 0 1 step 928 11110101000000010100101010101010 source: 1101010011001 changed: 1 01 01 step 929 11110101000000010101101010011001 source: 0 1 0 changed: 0 1 0 step 930 11110100000000011100101010011001 source: 1101010100110 changed: 1 100110 step 931 11110100000000011101101010100110 source: 0 0 changed: 0 0 step 932 11110100000000010100101010100110 source: 1110111 changed: 11 step 933 11110111000000010100101010100110 source: 1101010011010 changed: 1 0110 step 934 11110111000000010101101010011010 source: 0 1 0 changed: 0 1 0 step 935 11110110000000011100101010011010 source: 1101010100110 changed: 1 1001 step 936 11110110000000011101101010100110 source: 0 0 changed: 0 0 step 937 11110110000000010100101010100110 source: 1110011 changed: 0 1 step 938 11110011000000010100101010100110 source: 1101010010110 changed: 1 01 step 939 11110011000000010101101010010110 source: 0 1 0 changed: 0 1 0 step 940 11110010000000011100101010010110 source: 1101010100101 changed: 1 10 01 step 941 11110010000000011101101010100101 source: 0 0 changed: 0 0 step 942 11110010000000010100101010100101 source: 1110001 changed: 01 step 943 11110001000000010100101010100101 source: 1101010010101 changed: 1 01 step 944 11110001000000010101101010010101 source: 0 1 0 changed: 0 1 0 step 945 11110000000000011100101010010101 source: 1101010100101 changed: 1 10 step 946 11110000000000011101101010100101 source: 0 0 changed: 0 0 step 947 11110000000000010100101010100101 source: 1010001 changed: 0 1 step 948 11010001000000010100101010100101 source: 1100110010101 changed: 1 01 01 step 949 11010001000000010101100110010101 source: 0 1 0 changed: 0 1 0 step 950 11010000000000011100100110010101 source: 1101001100101 changed: 1 100110 step 951 11010000000000011101101001100101 source: 0 0 changed: 0 0 step 952 11010000000000010100101001100101 source: 1010011 changed: 11 step 953 11010011000000010100101001100101 source: 1100110010110 changed: 1 011001 10 step 954 11010011000000010101100110010110 source: 0 1 0 changed: 0 1 0 step 955 11010010000000011100100110010110 source: 1101001100101 changed: 1 100110 01 step 956 11010010000000011101101001100101 source: 0 0 changed: 0 0 step 957 11010010000000010100101001100101 source: 1010111 changed: 1 1 step 958 11010111000000010100101001100101 source: 1100110011010 changed: 1 0110011010 step 959 11010111000000010101100110011010 source: 0 1 0 changed: 0 1 0 step 960 11010110000000011100100110011010 source: 1101001100110 changed: 1 10011001 step 961 11010110000000011101101001100110 source: 0 0 changed: 0 0 step 962 11010110000000010100101001100110 source: 1010101 changed: 01 step 963 11010101000000010100101001100110 source: 1100110011001 changed: 1 0110011001 step 964 11010101000000010101100110011001 source: 0 1 0 changed: 0 1 0 step 965 11010100000000011100100110011001 source: 1101001100110 changed: 1 1001100110 step 966 11010100000000011101101001100110 source: 0 0 changed: 0 0 step 967 11010100000000010100101001100110 source: 1011101 changed: 1 1 step 968 11011101000000010100101001100110 source: 1100110101001 changed: 1 0110 1001 step 969 11011101000000010101100110101001 source: 0 1 0 changed: 0 1 0 step 970 11011100000000011100100110101001 source: 1101001101010 changed: 1 1001 10 step 971 11011100000000011101101001101010 source: 0 0 changed: 0 0 step 972 11011100000000010100101001101010 source: 1011111 changed: 11 step 973 11011111000000010100101001101010 source: 1100110101010 changed: 1 0110 step 974 11011111000000010101100110101010 source: 0 1 0 changed: 0 1 0 step 975 11011110000000011100100110101010 source: 1101001101010 changed: 1 1001 step 976 11011110000000011101101001101010 source: 0 0 changed: 0 0 step 977 11011110000000010100101001101010 source: 1011011 changed: 0 1 step 978 11011011000000010100101001101010 source: 1100110100110 changed: 1 0110 01 step 979 11011011000000010101100110100110 source: 0 1 0 changed: 0 1 0 step 980 11011010000000011100100110100110 source: 1101001101001 changed: 1 1001 1001 step 981 11011010000000011101101001101001 source: 0 0 changed: 0 0 step 982 11011010000000010100101001101001 source: 1011001 changed: 01 step 983 11011001000000010100101001101001 source: 1100110100101 changed: 1 0110 01 step 984 11011001000000010101100110100101 source: 0 1 0 changed: 0 1 0 step 985 11011000000000011100100110100101 source: 1101001101001 changed: 1 1001 10 step 986 11011000000000011101101001101001 source: 0 0 changed: 0 0 step 987 11011000000000010100101001101001 source: 1001001 changed: 0 1 step 988 11001001000000010100101001101001 source: 1100101100101 changed: 1 01 01 step 989 11001001000000010101100101100101 source: 0 1 0 changed: 0 1 0 step 990 11001000000000011100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 10 10 step 991 11001000000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 992 11001000000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 993 11001011000000010100101001101001 fail ^^ source: 1100101100110 changed: 1 01 0110 step 994 11001011000000010101100101100110 source: 0 1 0 changed: 0 1 0 step 995 11001010000000011100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 10 1001 step 996 11001010000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 997 11001010000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 998 11001111000000010100101001101001 fail ^^ source: 1100101101010 changed: 1 01 10 step 999 11001111000000010101100101101010 source: 0 1 0 changed: 0 1 0 step 1000 11001110000000011100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 step 1001 11001110000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1002 11001110000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 1003 11001101000000010100101001101010 fail ^^ source: 1100101101001 changed: 1 01 01 step 1004 11001101000000010101100101101001 source: 0 1 0 changed: 0 1 0 step 1005 11001100000000011100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 10 step 1006 11001100000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1007 11001100000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 1008 11000101000000010100101001101010 fail ^^ source: 1100101011001 changed: 1 01 01 01 step 1009 11000101000000010101100101011001 source: 0 1 0 changed: 0 1 0 step 1010 11000100000000011100100101011001 source: 1101001010110 changed: 1 10 0110 step 1011 11000100000000011101101001010110 source: 0 0 changed: 0 0 step 1012 11000100000000010100101001010110 source: 1000111 changed: 11 step 1013 11000111000000010100101001010110 source: 1100101011010 changed: 1 01 10 step 1014 11000111000000010101100101011010 source: 0 1 0 changed: 0 1 0 step 1015 11000110000000011100100101011010 source: 1101001010110 changed: 1 10 01 step 1016 11000110000000011101101001010110 source: 0 0 changed: 0 0 step 1017 11000110000000010100101001010110 source: 1000011 changed: 0 1 step 1018 11000011000000010100101001010110 source: 1100101010110 changed: 1 01 step 1019 11000011000000010101100101010110 source: 0 1 0 changed: 0 1 0 step 1020 11000010000000011100100101010110 source: 1101001010101 changed: 1 10 01 step 1021 11000010000000011101101001010101 source: 0 0 changed: 0 0 step 1022 11000010000000010100101001010101 source: 1000001 changed: 01 step 1023 11000001000000010100101001010101 source: 1100101010101 changed: 1 01 step 1024 11000001000000010101100101010101 source: 0 1 0 changed: 0 1 0 step 1025 11000000000000011100100101010101 source: 1101001010101 changed: 1 10 step 1026 11000000000000011101101001010101 source: 0 0 changed: 0 0 step 1027 11000000000000010100101001010101 source: 0000001 changed: 0 1 step 1028 10000001000000010100101001010101 source: 1010101010101 changed: 10101 step 1029 10000001000000010101010101010101 source: 0 1 0 changed: 0 1 0 step 1030 10000000000000011100010101010101 source: 1100101010101 changed: 110 step 1031 10000000000000011101100101010101 source: 0 0 changed: 0 0 step 1032 10000000000000010100100101010101 source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 1033 10000000000000010000100101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 11 step 1034 10000011000000010000100101010101 source: 1010101010110 changed: 101 10 step 1035 10000011000000010001010101010110 source: 0 10 changed: 0 10 step 1036 10000010000000010010010101010110 source: 1010101011001 changed: 1 1001 step 1037 10000010000000010011010101011001 source: 00 changed: 00 step 1038 10000010000000010000010101011001 source: 0000111 changed: 1 1 step 1039 10000111000000010000010101011001 source: 1010101011010 changed: 1 10 step 1040 10000111000000010001010101011010 source: 0 10 changed: 0 10 step 1041 10000110000000010010010101011010 source: 1010101101001 changed: 1 10 01 step 1042 10000110000000010011010101101001 source: 00 changed: 00 step 1043 10000110000000010000010101101001 source: 0000101 changed: 01 step 1044 10000101000000010000010101101001 source: 1010101011001 changed: 1 01 step 1045 10000101000000010001010101011001 source: 0 10 changed: 0 10 step 1046 10000100000000010010010101011001 source: 1010101100101 changed: 1 1001 step 1047 10000100000000010011010101100101 source: 00 changed: 00 step 1048 10000100000000010000010101100101 source: 0001101 changed: 1 1 step 1049 10001101000000010000010101100101 source: 1010101101001 changed: 1 10 step 1050 10001101000000010001010101101001 source: 0 10 changed: 0 10 step 1051 10001100000000010010010101101001 source: 1010110100101 changed: 1 10 01 step 1052 10001100000000010011010110100101 source: 00 changed: 00 step 1053 10001100000000010000010110100101 source: 0001111 changed: 11 step 1054 10001111000000010000010110100101 source: 1010101101010 changed: 1 01 1010 step 1055 10001111000000010001010101101010 source: 0 10 changed: 0 10 step 1056 10001110000000010010010101101010 source: 1010110101001 changed: 1 10 01 step 1057 10001110000000010011010110101001 source: 00 changed: 00 step 1058 10001110000000010000010110101001 source: 0001011 changed: 0 1 step 1059 10001011000000010000010110101001 source: 1010101100110 changed: 1 01 0110 step 1060 10001011000000010001010101100110 source: 0 10 changed: 0 10 step 1061 10001010000000010010010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 10 1001 step 1062 10001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1063 10001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 1064 10001001000000010000010110101001 fail ^^ source: 1010101100101 changed: 1 01 01 step 1065 10001001000000010001010101100101 source: 0 10 changed: 0 10 step 1066 10001000000000010010010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 10 step 1067 10001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1068 10001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 1069 10011001000000010000010110100101 fail ^^ source: 1010110100101 changed: 1 step 1070 10011001000000010001010110100101 source: 0 10 changed: 0 10 step 1071 10011000000000010010010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 10 step 1072 10011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1073 10011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 1074 10011011000000010000011010100101 fail ^^ source: 1010110100110 changed: 1 01 10 step 1075 10011011000000010001010110100110 source: 0 10 changed: 0 10 step 1076 10011010000000010010010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 10 1001 step 1077 10011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1078 10011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 1079 10011111000000010000011010101001 fail ^^ source: 1010110101010 changed: 1 01 10 step 1080 10011111000000010001010110101010 source: 0 10 changed: 0 10 step 1081 10011110000000010010010110101010 source: 1011010101001 changed: 1 10 01 step 1082 10011110000000010011011010101001 source: 00 changed: 00 step 1083 10011110000000010000011010101001 source: 0011101 changed: 01 step 1084 10011101000000010000011010101001 source: 1010110101001 changed: 1 01 step 1085 10011101000000010001010110101001 source: 0 10 changed: 0 10 step 1086 10011100000000010010010110101001 source: 1011010100101 changed: 1 10 01 step 1087 10011100000000010011011010100101 source: 00 changed: 00 step 1088 10011100000000010000011010100101 source: 0010101 changed: 0 1 step 1089 10010101000000010000011010100101 source: 1010110011001 changed: 1 01 0110 step 1090 10010101000000010001010110011001 source: 0 10 changed: 0 10 step 1091 10010100000000010010010110011001 source: 1011001100101 changed: 1 10011001 step 1092 10010100000000010011011001100101 source: 00 changed: 00 step 1093 10010100000000010000011001100101 source: 0010111 changed: 11 step 1094 10010111000000010000011001100101 source: 1010110011010 changed: 1 0110011010 step 1095 10010111000000010001010110011010 source: 0 10 changed: 0 10 step 1096 10010110000000010010010110011010 source: 1011001101001 changed: 1 100110 01 step 1097 10010110000000010011011001101001 source: 00 changed: 00 step 1098 10010110000000010000011001101001 source: 0010011 changed: 0 1 step 1099 10010011000000010000011001101001 source: 1010110010110 changed: 1 0110010110 step 1100 10010011000000010001010110010110 source: 0 10 changed: 0 10 step 1101 10010010000000010010010110010110 source: 1011001011001 changed: 1 1001 1001 step 1102 10010010000000010011011001011001 source: 00 changed: 00 step 1103 10010010000000010000011001011001 source: 0010001 changed: 01 step 1104 10010001000000010000011001011001 source: 1010110010101 changed: 1 0110 01 step 1105 10010001000000010001010110010101 source: 0 10 changed: 0 10 step 1106 10010000000000010010010110010101 source: 1011001010101 changed: 1 1001 step 1107 10010000000000010011011001010101 source: 00 changed: 00 step 1108 10010000000000010000011001010101 source: 0110001 changed: 1 1 step 1109 10110001000000010000011001010101 source: 1011010010101 changed: 1 10 step 1110 10110001000000010001011010010101 source: 0 10 changed: 0 10 step 1111 10110000000000010010011010010101 source: 1101001010101 changed: 110 01 step 1112 10110000000000010011101001010101 source: 00 changed: 00 step 1113 10110000000000010000101001010101 source: 0110011 changed: 11 step 1114 10110011000000010000101001010101 source: 1011010010110 changed: 101 10 10 step 1115 10110011000000010001011010010110 source: 0 10 changed: 0 10 step 1116 10110010000000010010011010010110 source: 1101001011001 changed: 110 01 1001 step 1117 10110010000000010011101001011001 source: 00 changed: 00 step 1118 10110010000000010000101001011001 source: 0110111 changed: 1 1 step 1119 10110111000000010000101001011001 source: 1011010011010 changed: 101 10 10 step 1120 10110111000000010001011010011010 source: 0 10 changed: 0 10 step 1121 10110110000000010010011010011010 source: 1101001101001 changed: 110 0110 01 step 1122 10110110000000010011101001101001 source: 00 changed: 00 step 1123 10110110000000010000101001101001 source: 0110101 changed: 01 step 1124 10110101000000010000101001101001 source: 1011010011001 changed: 101 1001 step 1125 10110101000000010001011010011001 source: 0 10 changed: 0 10 step 1126 10110100000000010010011010011001 source: 1101001100101 changed: 110 011001 step 1127 10110100000000010011101001100101 source: 00 changed: 00 step 1128 10110100000000010000101001100101 source: 0111101 changed: 1 1 step 1129 10111101000000010000101001100101 source: 1011010101001 changed: 101 10 10 step 1130 10111101000000010001011010101001 source: 0 10 changed: 0 10 step 1131 10111100000000010010011010101001 source: 1101010100101 changed: 110 01 step 1132 10111100000000010011101010100101 source: 00 changed: 00 step 1133 10111100000000010000101010100101 source: 0111111 changed: 11 step 1134 10111111000000010000101010100101 source: 1011010101010 changed: 101 1010 step 1135 10111111000000010001011010101010 source: 0 10 changed: 0 10 step 1136 10111110000000010010011010101010 source: 1101010101001 changed: 110 01 step 1137 10111110000000010011101010101001 source: 00 changed: 00 step 1138 10111110000000010000101010101001 source: 0111011 changed: 0 1 step 1139 10111011000000010000101010101001 source: 1011010100110 changed: 101 0110 step 1140 10111011000000010001011010100110 source: 0 10 changed: 0 10 step 1141 10111010000000010010011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 110 1001 step 1142 10111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1143 10111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 1144 10111001000000010000101010101001 fail ^^ source: 1011010100101 changed: 101 01 step 1145 10111001000000010001011010100101 source: 0 10 changed: 0 10 step 1146 10111000000000010010011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 110 step 1147 10111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1148 10111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 1149 10101001000000010000101010100101 fail ^^ source: 1011001100101 changed: 101 01 step 1150 10101001000000010001011001100101 source: 0 10 changed: 0 10 step 1151 10101000000000010010011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1100110 step 1152 10101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1153 10101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 1154 10101011000000010000100110100101 fail ^^ source: 1011001100110 changed: 1011001 10 step 1155 10101011000000010001011001100110 source: 0 10 changed: 0 10 step 1156 10101010000000010010011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110 1001 step 1157 10101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1158 10101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 1159 10101111000000010000100110101001 fail ^^ source: 1011001101010 changed: 1011001 10 step 1160 10101111000000010001011001101010 source: 0 10 changed: 0 10 step 1161 10101110000000010010011001101010 source: 1100110101001 changed: 1100110 01 step 1162 10101110000000010011100110101001 source: 00 changed: 00 step 1163 10101110000000010000100110101001 source: 0101101 changed: 01 step 1164 10101101000000010000100110101001 source: 1011001101001 changed: 1011001 step 1165 10101101000000010001011001101001 source: 0 10 changed: 0 10 step 1166 10101100000000010010011001101001 source: 1100110100101 changed: 1100110 01 step 1167 10101100000000010011100110100101 source: 00 changed: 00 step 1168 10101100000000010000100110100101 source: 0100101 changed: 0 1 step 1169 10100101000000010000100110100101 source: 1011001011001 changed: 10110010110 step 1170 10100101000000010001011001011001 source: 0 10 changed: 0 10 step 1171 10100100000000010010011001011001 source: 1100101100101 changed: 11001 1001 step 1172 10100100000000010011100101100101 source: 00 changed: 00 step 1173 10100100000000010000100101100101 source: 0100111 changed: 11 step 1174 10100111000000010000100101100101 source: 1011001011010 changed: 10110 011010 step 1175 10100111000000010001011001011010 source: 0 10 changed: 0 10 step 1176 10100110000000010010011001011010 source: 1100101101001 changed: 11001 10 01 step 1177 10100110000000010011100101101001 source: 00 changed: 00 step 1178 10100110000000010000100101101001 source: 0100011 changed: 0 1 step 1179 10100011000000010000100101101001 source: 1011001010110 changed: 10110 010110 step 1180 10100011000000010001011001010110 source: 0 10 changed: 0 10 step 1181 10100010000000010010011001010110 source: 1100101011001 changed: 11001 1001 step 1182 10100010000000010011100101011001 source: 00 changed: 00 step 1183 10100010000000010000100101011001 source: 0100001 changed: 01 step 1184 10100001000000010000100101011001 source: 1011001010101 changed: 10110 01 step 1185 10100001000000010001011001010101 source: 0 10 changed: 0 10 step 1186 10100000000000010010011001010101 source: 1100101010101 changed: 11001 step 1187 10100000000000010011100101010101 source: 00 changed: 00 step 1188 10100000000000010000100101010101 source: 1100001 changed: 1 1 step 1189 11100001000000010000100101010101 source: 1101001010101 changed: 1 10 step 1190 11100001000000010001101001010101 source: 0 10 changed: 0 10 step 1191 11100000000000010010101001010101 source: 1100101010101 changed: 1 01 step 1192 11100000000000010011100101010101 source: 00 changed: 00 step 1193 11100000000000010000100101010101 source: 1100011 changed: 11 step 1194 11100011000000010000100101010101 source: 1101001010110 changed: 1 10 10 step 1195 11100011000000010001101001010110 source: 0 10 changed: 0 10 step 1196 11100010000000010010101001010110 source: 1100101011001 changed: 1 01 1001 step 1197 11100010000000010011100101011001 source: 00 changed: 00 step 1198 11100010000000010000100101011001 source: 1100111 changed: 1 1 step 1199 11100111000000010000100101011001 source: 1101001011010 changed: 1 10 10 step 1200 11100111000000010001101001011010 source: 0 10 changed: 0 10 step 1201 11100110000000010010101001011010 source: 1100101101001 changed: 1 01 10 01 step 1202 11100110000000010011100101101001 source: 00 changed: 00 step 1203 11100110000000010000100101101001 source: 1100101 changed: 01 step 1204 11100101000000010000100101101001 source: 1101001011001 changed: 1 10 01 step 1205 11100101000000010001101001011001 source: 0 10 changed: 0 10 step 1206 11100100000000010010101001011001 source: 1100101100101 changed: 1 01 1001 step 1207 11100100000000010011100101100101 source: 00 changed: 00 step 1208 11100100000000010000100101100101 source: 1101101 changed: 1 1 step 1209 11101101000000010000100101100101 source: 1101001101001 changed: 1 10 10 step 1210 11101101000000010001101001101001 source: 0 10 changed: 0 10 step 1211 11101100000000010010101001101001 source: 1100110100101 changed: 1 0110 01 step 1212 11101100000000010011100110100101 source: 00 changed: 00 step 1213 11101100000000010000100110100101 source: 1101111 changed: 11 step 1214 11101111000000010000100110100101 source: 1101001101010 changed: 1 1001 1010 step 1215 11101111000000010001101001101010 source: 0 10 changed: 0 10 step 1216 11101110000000010010101001101010 source: 1100110101001 changed: 1 0110 01 step 1217 11101110000000010011100110101001 source: 00 changed: 00 step 1218 11101110000000010000100110101001 source: 1101011 changed: 0 1 step 1219 11101011000000010000100110101001 source: 1101001100110 changed: 1 1001 0110 step 1220 11101011000000010001101001100110 source: 0 10 changed: 0 10 step 1221 11101010000000010010101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 0110 1001 step 1222 11101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1223 11101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 1224 11101001000000010000100110101001 fail ^^ source: 1101001100101 changed: 1 1001 01 step 1225 11101001000000010001101001100101 source: 0 10 changed: 0 10 step 1226 11101000000000010010101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 0110 step 1227 11101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1228 11101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 1229 11111001000000010000100110100101 fail ^^ source: 1101010100101 changed: 1 10 step 1230 11111001000000010001101010100101 source: 0 10 changed: 0 10 step 1231 11111000000000010010101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 1232 11111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1233 11111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 1234 11111011000000010000101010100101 fail ^^ source: 1101010100110 changed: 1 10 step 1235 11111011000000010001101010100110 source: 0 10 changed: 0 10 step 1236 11111010000000010010101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 1001 step 1237 11111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1238 11111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 1239 11111111000000010000101010101001 fail ^^ source: 1101010101010 changed: 1 10 step 1240 11111111000000010001101010101010 source: 0 10 changed: 0 10 step 1241 11111110000000010010101010101010 source: 1101010101001 changed: 1 01 step 1242 11111110000000010011101010101001 source: 00 changed: 00 step 1243 11111110000000010000101010101001 source: 1111101 changed: 01 step 1244 11111101000000010000101010101001 source: 1101010101001 changed: 1 step 1245 11111101000000010001101010101001 source: 0 10 changed: 0 10 step 1246 11111100000000010010101010101001 source: 1101010100101 changed: 1 01 step 1247 11111100000000010011101010100101 source: 00 changed: 00 step 1248 11111100000000010000101010100101 source: 1110101 changed: 0 1 step 1249 11110101000000010000101010100101 source: 1101010011001 changed: 1 0110 step 1250 11110101000000010001101010011001 source: 0 10 changed: 0 10 step 1251 11110100000000010010101010011001 source: 1101001100101 changed: 1 011001 step 1252 11110100000000010011101001100101 source: 00 changed: 00 step 1253 11110100000000010000101001100101 source: 1110111 changed: 11 step 1254 11110111000000010000101001100101 source: 1101010011010 changed: 1 10011010 step 1255 11110111000000010001101010011010 source: 0 10 changed: 0 10 step 1256 11110110000000010010101010011010 source: 1101001101001 changed: 1 0110 01 step 1257 11110110000000010011101001101001 source: 00 changed: 00 step 1258 11110110000000010000101001101001 source: 1110011 changed: 0 1 step 1259 11110011000000010000101001101001 source: 1101010010110 changed: 1 10010110 step 1260 11110011000000010001101010010110 source: 0 10 changed: 0 10 step 1261 11110010000000010010101010010110 source: 1101001011001 changed: 1 01 1001 step 1262 11110010000000010011101001011001 source: 00 changed: 00 step 1263 11110010000000010000101001011001 source: 1110001 changed: 01 step 1264 11110001000000010000101001011001 source: 1101010010101 changed: 1 10 01 step 1265 11110001000000010001101010010101 source: 0 10 changed: 0 10 step 1266 11110000000000010010101010010101 source: 1101001010101 changed: 1 01 step 1267 11110000000000010011101001010101 source: 00 changed: 00 step 1268 11110000000000010000101001010101 source: 1010001 changed: 0 1 step 1269 11010001000000010000101001010101 source: 1100110010101 changed: 1 0110 step 1270 11010001000000010001100110010101 source: 0 10 changed: 0 10 step 1271 11010000000000010010100110010101 source: 1011001010101 changed: 1011001 step 1272 11010000000000010011011001010101 source: 00 changed: 00 step 1273 11010000000000010000011001010101 source: 1010011 changed: 11 step 1274 11010011000000010000011001010101 source: 1100110010110 changed: 1100110 10 step 1275 11010011000000010001100110010110 source: 0 10 changed: 0 10 step 1276 11010010000000010010100110010110 source: 1011001011001 changed: 1011001 1001 step 1277 11010010000000010011011001011001 source: 00 changed: 00 step 1278 11010010000000010000011001011001 source: 1010111 changed: 1 1 step 1279 11010111000000010000011001011001 source: 1100110011010 changed: 1100110 10 step 1280 11010111000000010001100110011010 source: 0 10 changed: 0 10 step 1281 11010110000000010010100110011010 source: 1011001101001 changed: 101100110 01 step 1282 11010110000000010011011001101001 source: 00 changed: 00 step 1283 11010110000000010000011001101001 source: 1010101 changed: 01 step 1284 11010101000000010000011001101001 source: 1100110011001 changed: 110011001 step 1285 11010101000000010001100110011001 source: 0 10 changed: 0 10 step 1286 11010100000000010010100110011001 source: 1011001100101 changed: 10110011001 step 1287 11010100000000010011011001100101 source: 00 changed: 00 step 1288 11010100000000010000011001100101 source: 1011101 changed: 1 1 step 1289 11011101000000010000011001100101 source: 1100110101001 changed: 1100110 10 step 1290 11011101000000010001100110101001 source: 0 10 changed: 0 10 step 1291 11011100000000010010100110101001 source: 1011010100101 changed: 10110 01 step 1292 11011100000000010011011010100101 source: 00 changed: 00 step 1293 11011100000000010000011010100101 source: 1011111 changed: 11 step 1294 11011111000000010000011010100101 source: 1100110101010 changed: 11001 1010 step 1295 11011111000000010001100110101010 source: 0 10 changed: 0 10 step 1296 11011110000000010010100110101010 source: 1011010101001 changed: 10110 01 step 1297 11011110000000010011011010101001 source: 00 changed: 00 step 1298 11011110000000010000011010101001 source: 1011011 changed: 0 1 step 1299 11011011000000010000011010101001 source: 1100110100110 changed: 11001 0110 step 1300 11011011000000010001100110100110 source: 0 10 changed: 0 10 step 1301 11011010000000010010100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 10110 1001 step 1302 11011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1303 11011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 1304 11011001000000010000011010101001 fail ^^ source: 1100110100101 changed: 11001 01 step 1305 11011001000000010001100110100101 source: 0 10 changed: 0 10 step 1306 11011000000000010010100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 10110 step 1307 11011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1308 11011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 1309 11001001000000010000011010100101 fail ^^ source: 1100101100101 changed: 1100101 step 1310 11001001000000010001100101100101 source: 0 10 changed: 0 10 step 1311 11001000000000010010100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 101 10 step 1312 11001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1313 11001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 1314 11001011000000010000010110100101 fail ^^ source: 1100101100110 changed: 110 01 10 step 1315 11001011000000010001100101100110 source: 0 10 changed: 0 10 step 1316 11001010000000010010100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 101 10 1001 step 1317 11001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1318 11001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 1319 11001111000000010000010110101001 fail ^^ source: 1100101101010 changed: 110 01 10 step 1320 11001111000000010001100101101010 source: 0 10 changed: 0 10 step 1321 11001110000000010010100101101010 source: 1010110101001 changed: 101 10 01 step 1322 11001110000000010011010110101001 source: 00 changed: 00 step 1323 11001110000000010000010110101001 source: 1001101 changed: 01 step 1324 11001101000000010000010110101001 source: 1100101101001 changed: 110 01 step 1325 11001101000000010001100101101001 source: 0 10 changed: 0 10 step 1326 11001100000000010010100101101001 source: 1010110100101 changed: 101 10 01 step 1327 11001100000000010011010110100101 source: 00 changed: 00 step 1328 11001100000000010000010110100101 source: 1000101 changed: 0 1 step 1329 11000101000000010000010110100101 source: 1100101011001 changed: 110 010110 step 1330 11000101000000010001100101011001 source: 0 10 changed: 0 10 step 1331 11000100000000010010100101011001 source: 1010101100101 changed: 101 1001 step 1332 11000100000000010011010101100101 source: 00 changed: 00 step 1333 11000100000000010000010101100101 source: 1000111 changed: 11 step 1334 11000111000000010000010101100101 source: 1100101011010 changed: 110 011010 step 1335 11000111000000010001100101011010 source: 0 10 changed: 0 10 step 1336 11000110000000010010100101011010 source: 1010101101001 changed: 101 10 01 step 1337 11000110000000010011010101101001 source: 00 changed: 00 step 1338 11000110000000010000010101101001 source: 1000011 changed: 0 1 step 1339 11000011000000010000010101101001 source: 1100101010110 changed: 110 010110 step 1340 11000011000000010001100101010110 source: 0 10 changed: 0 10 step 1341 11000010000000010010100101010110 source: 1010101011001 changed: 101 1001 step 1342 11000010000000010011010101011001 source: 00 changed: 00 step 1343 11000010000000010000010101011001 source: 1000001 changed: 01 step 1344 11000001000000010000010101011001 source: 1100101010101 changed: 110 01 step 1345 11000001000000010001100101010101 source: 0 10 changed: 0 10 step 1346 11000000000000010010100101010101 source: 1010101010101 changed: 101 step 1347 11000000000000010011010101010101 source: 00 changed: 00 step 1348 11000000000000010000010101010101 source: 0000001 changed: 0 1 step 1349 10000001000000010000010101010101 source: 1010101010101 changed: 1 step 1350 10000001000000010001010101010101 source: 0 10 changed: 0 10 step 1351 10000000000000010010010101010101 source: 1010101010101 changed: 1 step 1352 10000000000000010011010101010101 source: 00 changed: 00 step 1353 10000000000000010000010101010101 source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 1354 10000000000000010100010101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 11 step 1355 10000011000000010100010101010101 source: 1010101010110 changed: 1 10 step 1356 10000011000000010101010101010110 source: 0 10 changed: 0 10 step 1357 10000010000000010110010101010110 source: 1010101011010 changed: 1 10 step 1358 10000010000000010111010101011010 source: 00 changed: 00 step 1359 10000010000000010100010101011010 source: 0000111 changed: 1 1 step 1360 10000111000000010100010101011010 source: 1010101011010 changed: 1 step 1361 10000111000000010101010101011010 source: 0 10 changed: 0 10 step 1362 10000110000000010110010101011010 source: 1010101101010 changed: 1 10 step 1363 10000110000000010111010101101010 source: 00 changed: 00 step 1364 10000110000000010100010101101010 source: 0000101 changed: 01 step 1365 10000101000000010100010101101010 source: 1010101011001 changed: 1 01 01 step 1366 10000101000000010101010101011001 source: 0 10 changed: 0 10 step 1367 10000100000000010110010101011001 source: 1010101100110 changed: 1 100110 step 1368 10000100000000010111010101100110 source: 00 changed: 00 step 1369 10000100000000010100010101100110 source: 0001101 changed: 1 1 step 1370 10001101000000010100010101100110 source: 1010101101001 changed: 1 1001 step 1371 10001101000000010101010101101001 source: 0 10 changed: 0 10 step 1372 10001100000000010110010101101001 source: 1010110100110 changed: 1 10 0110 step 1373 10001100000000010111010110100110 source: 00 changed: 00 step 1374 10001100000000010100010110100110 source: 0001111 changed: 11 step 1375 10001111000000010100010110100110 source: 1010101101010 changed: 1 01 10 step 1376 10001111000000010101010101101010 source: 0 10 changed: 0 10 step 1377 10001110000000010110010101101010 source: 1010110101010 changed: 1 10 step 1378 10001110000000010111010110101010 source: 00 changed: 00 step 1379 10001110000000010100010110101010 source: 0001011 changed: 0 1 step 1380 10001011000000010100010110101010 source: 1010101100110 changed: 1 01 01 step 1381 10001011000000010101010101100110 source: 0 10 changed: 0 10 step 1382 10001010000000010110010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 10 10 step 1383 10001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1384 10001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 1385 10001001000000010100010110101010 fail ^^ source: 1010101100101 changed: 1 01 0101 step 1386 10001001000000010101010101100101 source: 0 10 changed: 0 10 step 1387 10001000000000010110010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 10 10 step 1388 10001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1389 10001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 1390 10011001000000010100010110100110 fail ^^ source: 1010110100101 changed: 1 01 step 1391 10011001000000010101010110100101 source: 0 10 changed: 0 10 step 1392 10011000000000010110010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 10 10 step 1393 10011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1394 10011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 1395 10011011000000010100011010100110 fail ^^ source: 1010110100110 changed: 1 01 step 1396 10011011000000010101010110100110 source: 0 10 changed: 0 10 step 1397 10011010000000010110010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 10 10 step 1398 10011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1399 10011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 1400 10011111000000010100011010101010 fail ^^ source: 1010110101010 changed: 1 01 step 1401 10011111000000010101010110101010 source: 0 10 changed: 0 10 step 1402 10011110000000010110010110101010 source: 1011010101010 changed: 1 10 step 1403 10011110000000010111011010101010 source: 00 changed: 00 step 1404 10011110000000010100011010101010 source: 0011101 changed: 01 step 1405 10011101000000010100011010101010 source: 1010110101001 changed: 1 01 01 step 1406 10011101000000010101010110101001 source: 0 10 changed: 0 10 step 1407 10011100000000010110010110101001 source: 1011010100110 changed: 1 10 0110 step 1408 10011100000000010111011010100110 source: 00 changed: 00 step 1409 10011100000000010100011010100110 source: 0010101 changed: 0 1 step 1410 10010101000000010100011010100110 source: 1010110011001 changed: 1 01 011001 step 1411 10010101000000010101010110011001 source: 0 10 changed: 0 10 step 1412 10010100000000010110010110011001 source: 1011001100110 changed: 1 1001100110 step 1413 10010100000000010111011001100110 source: 00 changed: 00 step 1414 10010100000000010100011001100110 source: 0010111 changed: 11 step 1415 10010111000000010100011001100110 source: 1010110011010 changed: 1 01100110 step 1416 10010111000000010101010110011010 source: 0 10 changed: 0 10 step 1417 10010110000000010110010110011010 source: 1011001101010 changed: 1 100110 step 1418 10010110000000010111011001101010 source: 00 changed: 00 step 1419 10010110000000010100011001101010 source: 0010011 changed: 0 1 step 1420 10010011000000010100011001101010 source: 1010110010110 changed: 1 01100101 step 1421 10010011000000010101010110010110 source: 0 10 changed: 0 10 step 1422 10010010000000010110010110010110 source: 1011001011010 changed: 1 1001 10 step 1423 10010010000000010111011001011010 source: 00 changed: 00 step 1424 10010010000000010100011001011010 source: 0010001 changed: 01 step 1425 10010001000000010100011001011010 source: 1010110010101 changed: 1 0110 0101 step 1426 10010001000000010101010110010101 source: 0 10 changed: 0 10 step 1427 10010000000000010110010110010101 source: 1011001010110 changed: 1 1001 10 step 1428 10010000000000010111011001010110 source: 00 changed: 00 step 1429 10010000000000010100011001010110 source: 0110001 changed: 1 1 step 1430 10110001000000010100011001010110 source: 1011010010101 changed: 1 10 01 step 1431 10110001000000010101011010010101 source: 0 10 changed: 0 10 step 1432 10110000000000010110011010010101 source: 1101001010110 changed: 110 01 10 step 1433 10110000000000010111101001010110 source: 00 changed: 00 step 1434 10110000000000010100101001010110 source: 0110011 changed: 11 step 1435 10110011000000010100101001010110 source: 1011010010110 changed: 101 10 step 1436 10110011000000010101011010010110 source: 0 10 changed: 0 10 step 1437 10110010000000010110011010010110 source: 1101001011010 changed: 110 01 10 step 1438 10110010000000010111101001011010 source: 00 changed: 00 step 1439 10110010000000010100101001011010 source: 0110111 changed: 1 1 step 1440 10110111000000010100101001011010 source: 1011010011010 changed: 101 10 step 1441 10110111000000010101011010011010 source: 0 10 changed: 0 10 step 1442 10110110000000010110011010011010 source: 1101001101010 changed: 110 0110 step 1443 10110110000000010111101001101010 source: 00 changed: 00 step 1444 10110110000000010100101001101010 source: 0110101 changed: 01 step 1445 10110101000000010100101001101010 source: 1011010011001 changed: 101 1001 01 step 1446 10110101000000010101011010011001 source: 0 10 changed: 0 10 step 1447 10110100000000010110011010011001 source: 1101001100110 changed: 110 01100110 step 1448 10110100000000010111101001100110 source: 00 changed: 00 step 1449 10110100000000010100101001100110 source: 0111101 changed: 1 1 step 1450 10111101000000010100101001100110 source: 1011010101001 changed: 101 10 1001 step 1451 10111101000000010101011010101001 source: 0 10 changed: 0 10 step 1452 10111100000000010110011010101001 source: 1101010100110 changed: 110 0110 step 1453 10111100000000010111101010100110 source: 00 changed: 00 step 1454 10111100000000010100101010100110 source: 0111111 changed: 11 step 1455 10111111000000010100101010100110 source: 1011010101010 changed: 101 10 step 1456 10111111000000010101011010101010 source: 0 10 changed: 0 10 step 1457 10111110000000010110011010101010 source: 1101010101010 changed: 110 step 1458 10111110000000010111101010101010 source: 00 changed: 00 step 1459 10111110000000010100101010101010 source: 0111011 changed: 0 1 step 1460 10111011000000010100101010101010 source: 1011010100110 changed: 101 01 step 1461 10111011000000010101011010100110 source: 0 10 changed: 0 10 step 1462 10111010000000010110011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 110 10 step 1463 10111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1464 10111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 1465 10111001000000010100101010101010 fail ^^ source: 1011010100101 changed: 101 0101 step 1466 10111001000000010101011010100101 source: 0 10 changed: 0 10 step 1467 10111000000000010110011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 110 10 step 1468 10111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1469 10111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 1470 10101001000000010100101010100110 fail ^^ source: 1011001100101 changed: 101 01 01 step 1471 10101001000000010101011001100101 source: 0 10 changed: 0 10 step 1472 10101000000000010110011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1100110 10 step 1473 10101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1474 10101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 1475 10101011000000010100100110100110 fail ^^ source: 1011001100110 changed: 1011001 step 1476 10101011000000010101011001100110 source: 0 10 changed: 0 10 step 1477 10101010000000010110011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1100110 10 step 1478 10101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1479 10101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 1480 10101111000000010100100110101010 fail ^^ source: 1011001101010 changed: 1011001 step 1481 10101111000000010101011001101010 source: 0 10 changed: 0 10 step 1482 10101110000000010110011001101010 source: 1100110101010 changed: 1100110 step 1483 10101110000000010111100110101010 source: 00 changed: 00 step 1484 10101110000000010100100110101010 source: 0101101 changed: 01 step 1485 10101101000000010100100110101010 source: 1011001101001 changed: 1011001 01 step 1486 10101101000000010101011001101001 source: 0 10 changed: 0 10 step 1487 10101100000000010110011001101001 source: 1100110100110 changed: 1100110 0110 step 1488 10101100000000010111100110100110 source: 00 changed: 00 step 1489 10101100000000010100100110100110 source: 0100101 changed: 0 1 step 1490 10100101000000010100100110100110 source: 1011001011001 changed: 1011001011001 step 1491 10100101000000010101011001011001 source: 0 10 changed: 0 10 step 1492 10100100000000010110011001011001 source: 1100101100110 changed: 11001 100110 step 1493 10100100000000010111100101100110 source: 00 changed: 00 step 1494 10100100000000010100100101100110 source: 0100111 changed: 11 step 1495 10100111000000010100100101100110 source: 1011001011010 changed: 10110 0110 step 1496 10100111000000010101011001011010 source: 0 10 changed: 0 10 step 1497 10100110000000010110011001011010 source: 1100101101010 changed: 11001 10 step 1498 10100110000000010111100101101010 source: 00 changed: 00 step 1499 10100110000000010100100101101010 source: 0100011 changed: 0 1 step 1500 10100011000000010100100101101010 source: 1011001010110 changed: 10110 0101 step 1501 10100011000000010101011001010110 source: 0 10 changed: 0 10 step 1502 10100010000000010110011001010110 source: 1100101011010 changed: 11001 10 step 1503 10100010000000010111100101011010 source: 00 changed: 00 step 1504 10100010000000010100100101011010 source: 0100001 changed: 01 step 1505 10100001000000010100100101011010 source: 1011001010101 changed: 10110 0101 step 1506 10100001000000010101011001010101 source: 0 10 changed: 0 10 step 1507 10100000000000010110011001010101 source: 1100101010110 changed: 11001 10 step 1508 10100000000000010111100101010110 source: 00 changed: 00 step 1509 10100000000000010100100101010110 source: 1100001 changed: 1 1 step 1510 11100001000000010100100101010110 source: 1101001010101 changed: 1 10 01 step 1511 11100001000000010101101001010101 source: 0 10 changed: 0 10 step 1512 11100000000000010110101001010101 source: 1100101010110 changed: 1 01 10 step 1513 11100000000000010111100101010110 source: 00 changed: 00 step 1514 11100000000000010100100101010110 source: 1100011 changed: 11 step 1515 11100011000000010100100101010110 source: 1101001010110 changed: 1 10 step 1516 11100011000000010101101001010110 source: 0 10 changed: 0 10 step 1517 11100010000000010110101001010110 source: 1100101011010 changed: 1 01 10 step 1518 11100010000000010111100101011010 source: 00 changed: 00 step 1519 11100010000000010100100101011010 source: 1100111 changed: 1 1 step 1520 11100111000000010100100101011010 source: 1101001011010 changed: 1 10 step 1521 11100111000000010101101001011010 source: 0 10 changed: 0 10 step 1522 11100110000000010110101001011010 source: 1100101101010 changed: 1 01 10 step 1523 11100110000000010111100101101010 source: 00 changed: 00 step 1524 11100110000000010100100101101010 source: 1100101 changed: 01 step 1525 11100101000000010100100101101010 source: 1101001011001 changed: 1 10 01 01 step 1526 11100101000000010101101001011001 source: 0 10 changed: 0 10 step 1527 11100100000000010110101001011001 source: 1100101100110 changed: 1 01 100110 step 1528 11100100000000010111100101100110 source: 00 changed: 00 step 1529 11100100000000010100100101100110 source: 1101101 changed: 1 1 step 1530 11101101000000010100100101100110 source: 1101001101001 changed: 1 10 1001 step 1531 11101101000000010101101001101001 source: 0 10 changed: 0 10 step 1532 11101100000000010110101001101001 source: 1100110100110 changed: 1 0110 0110 step 1533 11101100000000010111100110100110 source: 00 changed: 00 step 1534 11101100000000010100100110100110 source: 1101111 changed: 11 step 1535 11101111000000010100100110100110 source: 1101001101010 changed: 1 1001 10 step 1536 11101111000000010101101001101010 source: 0 10 changed: 0 10 step 1537 11101110000000010110101001101010 source: 1100110101010 changed: 1 0110 step 1538 11101110000000010111100110101010 source: 00 changed: 00 step 1539 11101110000000010100100110101010 source: 1101011 changed: 0 1 step 1540 11101011000000010100100110101010 source: 1101001100110 changed: 1 1001 01 step 1541 11101011000000010101101001100110 source: 0 10 changed: 0 10 step 1542 11101010000000010110101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 0110 10 step 1543 11101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1544 11101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 1545 11101001000000010100100110101010 fail ^^ source: 1101001100101 changed: 1 1001 0101 step 1546 11101001000000010101101001100101 source: 0 10 changed: 0 10 step 1547 11101000000000010110101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 0110 10 step 1548 11101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1549 11101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 1550 11111001000000010100100110100110 fail ^^ source: 1101010100101 changed: 1 10 01 step 1551 11111001000000010101101010100101 source: 0 10 changed: 0 10 step 1552 11111000000000010110101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 10 step 1553 11111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1554 11111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 1555 11111011000000010100101010100110 fail ^^ source: 1101010100110 changed: 1 step 1556 11111011000000010101101010100110 source: 0 10 changed: 0 10 step 1557 11111010000000010110101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 10 step 1558 11111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1559 11111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 1560 11111111000000010100101010101010 fail ^^ source: 1101010101010 changed: 1 step 1561 11111111000000010101101010101010 source: 0 10 changed: 0 10 step 1562 11111110000000010110101010101010 source: 1101010101010 changed: 1 step 1563 11111110000000010111101010101010 source: 00 changed: 00 step 1564 11111110000000010100101010101010 source: 1111101 changed: 01 step 1565 11111101000000010100101010101010 source: 1101010101001 changed: 1 01 step 1566 11111101000000010101101010101001 source: 0 10 changed: 0 10 step 1567 11111100000000010110101010101001 source: 1101010100110 changed: 1 0110 step 1568 11111100000000010111101010100110 source: 00 changed: 00 step 1569 11111100000000010100101010100110 source: 1110101 changed: 0 1 step 1570 11110101000000010100101010100110 source: 1101010011001 changed: 1 011001 step 1571 11110101000000010101101010011001 source: 0 10 changed: 0 10 step 1572 11110100000000010110101010011001 source: 1101001100110 changed: 1 01100110 step 1573 11110100000000010111101001100110 source: 00 changed: 00 step 1574 11110100000000010100101001100110 source: 1110111 changed: 11 step 1575 11110111000000010100101001100110 source: 1101010011010 changed: 1 100110 step 1576 11110111000000010101101010011010 source: 0 10 changed: 0 10 step 1577 11110110000000010110101010011010 source: 1101001101010 changed: 1 0110 step 1578 11110110000000010111101001101010 source: 00 changed: 00 step 1579 11110110000000010100101001101010 source: 1110011 changed: 0 1 step 1580 11110011000000010100101001101010 source: 1101010010110 changed: 1 100101 step 1581 11110011000000010101101010010110 source: 0 10 changed: 0 10 step 1582 11110010000000010110101010010110 source: 1101001011010 changed: 1 01 10 step 1583 11110010000000010111101001011010 source: 00 changed: 00 step 1584 11110010000000010100101001011010 source: 1110001 changed: 01 step 1585 11110001000000010100101001011010 source: 1101010010101 changed: 1 10 0101 step 1586 11110001000000010101101010010101 source: 0 10 changed: 0 10 step 1587 11110000000000010110101010010101 source: 1101001010110 changed: 1 01 10 step 1588 11110000000000010111101001010110 source: 00 changed: 00 step 1589 11110000000000010100101001010110 source: 1010001 changed: 0 1 step 1590 11010001000000010100101001010110 source: 1100110010101 changed: 1 0110 01 step 1591 11010001000000010101100110010101 source: 0 10 changed: 0 10 step 1592 11010000000000010110100110010101 source: 1011001010110 changed: 1011001 10 step 1593 11010000000000010111011001010110 source: 00 changed: 00 step 1594 11010000000000010100011001010110 source: 1010011 changed: 11 step 1595 11010011000000010100011001010110 source: 1100110010110 changed: 1100110 step 1596 11010011000000010101100110010110 source: 0 10 changed: 0 10 step 1597 11010010000000010110100110010110 source: 1011001011010 changed: 1011001 10 step 1598 11010010000000010111011001011010 source: 00 changed: 00 step 1599 11010010000000010100011001011010 source: 1010111 changed: 1 1 step 1600 11010111000000010100011001011010 source: 1100110011010 changed: 1100110 step 1601 11010111000000010101100110011010 source: 0 10 changed: 0 10 step 1602 11010110000000010110100110011010 source: 1011001101010 changed: 101100110 step 1603 11010110000000010111011001101010 source: 00 changed: 00 step 1604 11010110000000010100011001101010 source: 1010101 changed: 01 step 1605 11010101000000010100011001101010 source: 1100110011001 changed: 110011001 01 step 1606 11010101000000010101100110011001 source: 0 10 changed: 0 10 step 1607 11010100000000010110100110011001 source: 1011001100110 changed: 1011001100110 step 1608 11010100000000010111011001100110 source: 00 changed: 00 step 1609 11010100000000010100011001100110 source: 1011101 changed: 1 1 step 1610 11011101000000010100011001100110 source: 1100110101001 changed: 1100110 1001 step 1611 11011101000000010101100110101001 source: 0 10 changed: 0 10 step 1612 11011100000000010110100110101001 source: 1011010100110 changed: 10110 0110 step 1613 11011100000000010111011010100110 source: 00 changed: 00 step 1614 11011100000000010100011010100110 source: 1011111 changed: 11 step 1615 11011111000000010100011010100110 source: 1100110101010 changed: 11001 10 step 1616 11011111000000010101100110101010 source: 0 10 changed: 0 10 step 1617 11011110000000010110100110101010 source: 1011010101010 changed: 10110 step 1618 11011110000000010111011010101010 source: 00 changed: 00 step 1619 11011110000000010100011010101010 source: 1011011 changed: 0 1 step 1620 11011011000000010100011010101010 source: 1100110100110 changed: 11001 01 step 1621 11011011000000010101100110100110 source: 0 10 changed: 0 10 step 1622 11011010000000010110100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 10110 10 step 1623 11011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1624 11011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 1625 11011001000000010100011010101010 fail ^^ source: 1100110100101 changed: 11001 0101 step 1626 11011001000000010101100110100101 source: 0 10 changed: 0 10 step 1627 11011000000000010110100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 10110 10 step 1628 11011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1629 11011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 1630 11001001000000010100011010100110 fail ^^ source: 1100101100101 changed: 1100101 01 step 1631 11001001000000010101100101100101 source: 0 10 changed: 0 10 step 1632 11001000000000010110100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 101 10 10 step 1633 11001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1634 11001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 1635 11001011000000010100010110100110 fail ^^ source: 1100101100110 changed: 110 01 step 1636 11001011000000010101100101100110 source: 0 10 changed: 0 10 step 1637 11001010000000010110100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 101 10 10 step 1638 11001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1639 11001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 1640 11001111000000010100010110101010 fail ^^ source: 1100101101010 changed: 110 01 step 1641 11001111000000010101100101101010 source: 0 10 changed: 0 10 step 1642 11001110000000010110100101101010 source: 1010110101010 changed: 101 10 step 1643 11001110000000010111010110101010 source: 00 changed: 00 step 1644 11001110000000010100010110101010 source: 1001101 changed: 01 step 1645 11001101000000010100010110101010 source: 1100101101001 changed: 110 01 01 step 1646 11001101000000010101100101101001 source: 0 10 changed: 0 10 step 1647 11001100000000010110100101101001 source: 1010110100110 changed: 101 10 0110 step 1648 11001100000000010111010110100110 source: 00 changed: 00 step 1649 11001100000000010100010110100110 source: 1000101 changed: 0 1 step 1650 11000101000000010100010110100110 source: 1100101011001 changed: 110 01011001 step 1651 11000101000000010101100101011001 source: 0 10 changed: 0 10 step 1652 11000100000000010110100101011001 source: 1010101100110 changed: 101 100110 step 1653 11000100000000010111010101100110 source: 00 changed: 00 step 1654 11000100000000010100010101100110 source: 1000111 changed: 11 step 1655 11000111000000010100010101100110 source: 1100101011010 changed: 110 0110 step 1656 11000111000000010101100101011010 source: 0 10 changed: 0 10 step 1657 11000110000000010110100101011010 source: 1010101101010 changed: 101 10 step 1658 11000110000000010111010101101010 source: 00 changed: 00 step 1659 11000110000000010100010101101010 source: 1000011 changed: 0 1 step 1660 11000011000000010100010101101010 source: 1100101010110 changed: 110 0101 step 1661 11000011000000010101100101010110 source: 0 10 changed: 0 10 step 1662 11000010000000010110100101010110 source: 1010101011010 changed: 101 10 step 1663 11000010000000010111010101011010 source: 00 changed: 00 step 1664 11000010000000010100010101011010 source: 1000001 changed: 01 step 1665 11000001000000010100010101011010 source: 1100101010101 changed: 110 0101 step 1666 11000001000000010101100101010101 source: 0 10 changed: 0 10 step 1667 11000000000000010110100101010101 source: 1010101010110 changed: 101 10 step 1668 11000000000000010111010101010110 source: 00 changed: 00 step 1669 11000000000000010100010101010110 source: 0000001 changed: 0 1 step 1670 10000001000000010100010101010110 source: 1010101010101 changed: 1 01 step 1671 10000001000000010101010101010101 source: 0 10 changed: 0 10 step 1672 10000000000000010110010101010101 source: 1010101010110 changed: 1 10 step 1673 10000000000000010111010101010110 source: 00 changed: 00 step 1674 10000000000000010100010101010110 source: source: source: ; end of SECTION GENERATED BY A PROGRAM source: source: source: ; CLEAR FFs source: 0 010101010101 changed: 0 01 step 1675 00000000000000010100010101010101 source: 1 changed: 1 step 1676 10000000000000010100010101010101 source: source: 11111110111111010100010101010101 changed: 111111 111111 step 1677 11111110111111010100010101010101 test 1: *** FAIL *************************** 192 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; CLEAR-N, NO ENABLES source: 01111110111111010100010101010101 changed: 0 step 1 01111110111111010100010101010101 source: 1 changed: 1 step 2 11111110111111010100010101010101 source: source: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM source: ; see mk_m212_ld_shift.c source: source: source: ; TEST A INPUTS, GRAY CODE PATTERN source: source: ; ENABLE A INPUTS source: 1 changed: 1 step 3 11111111111111010100010101010101 source: ; LOAD FFs FROM INPUT A source: source: 000001 changed: 00000 step 4 10000011111111010100010101010101 source: 1010101010110 changed: 1 10 step 5 10000011111111010101010101010110 source: 0 changed: 0 step 6 10000011111111010100010101010110 source: 000011 changed: 1 step 7 10000111111111010100010101010110 source: 1010101011010 changed: 1 10 step 8 10000111111111010101010101011010 source: 0 changed: 0 step 9 10000111111111010100010101011010 source: 000010 changed: 0 step 10 10000101111111010100010101011010 source: 1010101011001 changed: 1 01 step 11 10000101111111010101010101011001 source: 0 changed: 0 step 12 10000101111111010100010101011001 source: 000110 changed: 1 step 13 10001101111111010100010101011001 source: 1010101101001 changed: 1 10 step 14 10001101111111010101010101101001 source: 0 changed: 0 step 15 10001101111111010100010101101001 source: 000111 changed: 1 step 16 10001111111111010100010101101001 source: 1010101101010 changed: 1 10 step 17 10001111111111010101010101101010 source: 0 changed: 0 step 18 10001111111111010100010101101010 source: 000101 changed: 0 step 19 10001011111111010100010101101010 source: 1010101100110 changed: 1 01 step 20 10001011111111010101010101100110 source: 0 changed: 0 step 21 10001011111111010100010101100110 source: 000100 changed: 0 step 22 10001001111111010100010101100110 source: 1010101100101 changed: 1 01 step 23 10001001111111010101010101100101 source: 0 changed: 0 step 24 10001001111111010100010101100101 source: 001100 changed: 1 step 25 10011001111111010100010101100101 source: 1010110100101 changed: 1 10 step 26 10011001111111010101010110100101 source: 0 changed: 0 step 27 10011001111111010100010110100101 source: 001101 changed: 1 step 28 10011011111111010100010110100101 source: 1010110100110 changed: 1 10 step 29 10011011111111010101010110100110 source: 0 changed: 0 step 30 10011011111111010100010110100110 source: 001111 changed: 1 step 31 10011111111111010100010110100110 source: 1010110101010 changed: 1 10 step 32 10011111111111010101010110101010 source: 0 changed: 0 step 33 10011111111111010100010110101010 source: 001110 changed: 0 step 34 10011101111111010100010110101010 source: 1010110101001 changed: 1 01 step 35 10011101111111010101010110101001 source: 0 changed: 0 step 36 10011101111111010100010110101001 source: 001010 changed: 0 step 37 10010101111111010100010110101001 source: 1010110011001 changed: 1 01 step 38 10010101111111010101010110011001 source: 0 changed: 0 step 39 10010101111111010100010110011001 source: 001011 changed: 1 step 40 10010111111111010100010110011001 source: 1010110011010 changed: 1 10 step 41 10010111111111010101010110011010 source: 0 changed: 0 step 42 10010111111111010100010110011010 source: 001001 changed: 0 step 43 10010011111111010100010110011010 source: 1010110010110 changed: 1 01 step 44 10010011111111010101010110010110 source: 0 changed: 0 step 45 10010011111111010100010110010110 source: 001000 changed: 0 step 46 10010001111111010100010110010110 source: 1010110010101 changed: 1 01 step 47 10010001111111010101010110010101 source: 0 changed: 0 step 48 10010001111111010100010110010101 source: 011000 changed: 1 step 49 10110001111111010100010110010101 source: 1011010010101 changed: 1 10 step 50 10110001111111010101011010010101 source: 0 changed: 0 step 51 10110001111111010100011010010101 source: 011001 changed: 1 step 52 10110011111111010100011010010101 source: 1011010010110 changed: 1 10 step 53 10110011111111010101011010010110 source: 0 changed: 0 step 54 10110011111111010100011010010110 source: 011011 changed: 1 step 55 10110111111111010100011010010110 source: 1011010011010 changed: 1 10 step 56 10110111111111010101011010011010 source: 0 changed: 0 step 57 10110111111111010100011010011010 source: 011010 changed: 0 step 58 10110101111111010100011010011010 source: 1011010011001 changed: 1 01 step 59 10110101111111010101011010011001 source: 0 changed: 0 step 60 10110101111111010100011010011001 source: 011110 changed: 1 step 61 10111101111111010100011010011001 source: 1011010101001 changed: 1 10 step 62 10111101111111010101011010101001 source: 0 changed: 0 step 63 10111101111111010100011010101001 source: 011111 changed: 1 step 64 10111111111111010100011010101001 source: 1011010101010 changed: 1 10 step 65 10111111111111010101011010101010 source: 0 changed: 0 step 66 10111111111111010100011010101010 source: 011101 changed: 0 step 67 10111011111111010100011010101010 source: 1011010100110 changed: 1 01 step 68 10111011111111010101011010100110 source: 0 changed: 0 step 69 10111011111111010100011010100110 source: 011100 changed: 0 step 70 10111001111111010100011010100110 source: 1011010100101 changed: 1 01 step 71 10111001111111010101011010100101 source: 0 changed: 0 step 72 10111001111111010100011010100101 source: 010100 changed: 0 step 73 10101001111111010100011010100101 source: 1011001100101 changed: 1 01 step 74 10101001111111010101011001100101 source: 0 changed: 0 step 75 10101001111111010100011001100101 source: 010101 changed: 1 step 76 10101011111111010100011001100101 source: 1011001100110 changed: 1 10 step 77 10101011111111010101011001100110 source: 0 changed: 0 step 78 10101011111111010100011001100110 source: 010111 changed: 1 step 79 10101111111111010100011001100110 source: 1011001101010 changed: 1 10 step 80 10101111111111010101011001101010 source: 0 changed: 0 step 81 10101111111111010100011001101010 source: 010110 changed: 0 step 82 10101101111111010100011001101010 source: 1011001101001 changed: 1 01 step 83 10101101111111010101011001101001 source: 0 changed: 0 step 84 10101101111111010100011001101001 source: 010010 changed: 0 step 85 10100101111111010100011001101001 source: 1011001011001 changed: 1 01 step 86 10100101111111010101011001011001 source: 0 changed: 0 step 87 10100101111111010100011001011001 source: 010011 changed: 1 step 88 10100111111111010100011001011001 source: 1011001011010 changed: 1 10 step 89 10100111111111010101011001011010 source: 0 changed: 0 step 90 10100111111111010100011001011010 source: 010001 changed: 0 step 91 10100011111111010100011001011010 source: 1011001010110 changed: 1 01 step 92 10100011111111010101011001010110 source: 0 changed: 0 step 93 10100011111111010100011001010110 source: 010000 changed: 0 step 94 10100001111111010100011001010110 source: 1011001010101 changed: 1 01 step 95 10100001111111010101011001010101 source: 0 changed: 0 step 96 10100001111111010100011001010101 source: 110000 changed: 1 step 97 11100001111111010100011001010101 source: 1101001010101 changed: 110 step 98 11100001111111010101101001010101 source: 0 changed: 0 step 99 11100001111111010100101001010101 source: 110001 changed: 1 step 100 11100011111111010100101001010101 source: 1101001010110 changed: 1 10 step 101 11100011111111010101101001010110 source: 0 changed: 0 step 102 11100011111111010100101001010110 source: 110011 changed: 1 step 103 11100111111111010100101001010110 source: 1101001011010 changed: 1 10 step 104 11100111111111010101101001011010 source: 0 changed: 0 step 105 11100111111111010100101001011010 source: 110010 changed: 0 step 106 11100101111111010100101001011010 source: 1101001011001 changed: 1 01 step 107 11100101111111010101101001011001 source: 0 changed: 0 step 108 11100101111111010100101001011001 source: 110110 changed: 1 step 109 11101101111111010100101001011001 source: 1101001101001 changed: 1 10 step 110 11101101111111010101101001101001 source: 0 changed: 0 step 111 11101101111111010100101001101001 source: 110111 changed: 1 step 112 11101111111111010100101001101001 source: 1101001101010 changed: 1 10 step 113 11101111111111010101101001101010 source: 0 changed: 0 step 114 11101111111111010100101001101010 source: 110101 changed: 0 step 115 11101011111111010100101001101010 source: 1101001100110 changed: 1 01 step 116 11101011111111010101101001100110 source: 0 changed: 0 step 117 11101011111111010100101001100110 source: 110100 changed: 0 step 118 11101001111111010100101001100110 source: 1101001100101 changed: 1 01 step 119 11101001111111010101101001100101 source: 0 changed: 0 step 120 11101001111111010100101001100101 source: 111100 changed: 1 step 121 11111001111111010100101001100101 source: 1101010100101 changed: 1 10 step 122 11111001111111010101101010100101 source: 0 changed: 0 step 123 11111001111111010100101010100101 source: 111101 changed: 1 step 124 11111011111111010100101010100101 source: 1101010100110 changed: 1 10 step 125 11111011111111010101101010100110 source: 0 changed: 0 step 126 11111011111111010100101010100110 source: 111111 changed: 1 step 127 11111111111111010100101010100110 source: 1101010101010 changed: 1 10 step 128 11111111111111010101101010101010 source: 0 changed: 0 step 129 11111111111111010100101010101010 source: 111110 changed: 0 step 130 11111101111111010100101010101010 source: 1101010101001 changed: 1 01 step 131 11111101111111010101101010101001 source: 0 changed: 0 step 132 11111101111111010100101010101001 source: 111010 changed: 0 step 133 11110101111111010100101010101001 source: 1101010011001 changed: 1 01 step 134 11110101111111010101101010011001 source: 0 changed: 0 step 135 11110101111111010100101010011001 source: 111011 changed: 1 step 136 11110111111111010100101010011001 source: 1101010011010 changed: 1 10 step 137 11110111111111010101101010011010 source: 0 changed: 0 step 138 11110111111111010100101010011010 source: 111001 changed: 0 step 139 11110011111111010100101010011010 source: 1101010010110 changed: 1 01 step 140 11110011111111010101101010010110 source: 0 changed: 0 step 141 11110011111111010100101010010110 source: 111000 changed: 0 step 142 11110001111111010100101010010110 source: 1101010010101 changed: 1 01 step 143 11110001111111010101101010010101 source: 0 changed: 0 step 144 11110001111111010100101010010101 source: 101000 changed: 0 step 145 11010001111111010100101010010101 source: 1100110010101 changed: 1 01 step 146 11010001111111010101100110010101 source: 0 changed: 0 step 147 11010001111111010100100110010101 source: 101001 changed: 1 step 148 11010011111111010100100110010101 source: 1100110010110 changed: 1 10 step 149 11010011111111010101100110010110 source: 0 changed: 0 step 150 11010011111111010100100110010110 source: 101011 changed: 1 step 151 11010111111111010100100110010110 source: 1100110011010 changed: 1 10 step 152 11010111111111010101100110011010 source: 0 changed: 0 step 153 11010111111111010100100110011010 source: 101010 changed: 0 step 154 11010101111111010100100110011010 source: 1100110011001 changed: 1 01 step 155 11010101111111010101100110011001 source: 0 changed: 0 step 156 11010101111111010100100110011001 source: 101110 changed: 1 step 157 11011101111111010100100110011001 source: 1100110101001 changed: 1 10 step 158 11011101111111010101100110101001 source: 0 changed: 0 step 159 11011101111111010100100110101001 source: 101111 changed: 1 step 160 11011111111111010100100110101001 source: 1100110101010 changed: 1 10 step 161 11011111111111010101100110101010 source: 0 changed: 0 step 162 11011111111111010100100110101010 source: 101101 changed: 0 step 163 11011011111111010100100110101010 source: 1100110100110 changed: 1 01 step 164 11011011111111010101100110100110 source: 0 changed: 0 step 165 11011011111111010100100110100110 source: 101100 changed: 0 step 166 11011001111111010100100110100110 source: 1100110100101 changed: 1 01 step 167 11011001111111010101100110100101 source: 0 changed: 0 step 168 11011001111111010100100110100101 source: 100100 changed: 0 step 169 11001001111111010100100110100101 source: 1100101100101 changed: 1 01 step 170 11001001111111010101100101100101 source: 0 changed: 0 step 171 11001001111111010100100101100101 source: 100101 changed: 1 step 172 11001011111111010100100101100101 source: 1100101100110 changed: 1 10 step 173 11001011111111010101100101100110 source: 0 changed: 0 step 174 11001011111111010100100101100110 source: 100111 changed: 1 step 175 11001111111111010100100101100110 source: 1100101101010 changed: 1 10 step 176 11001111111111010101100101101010 source: 0 changed: 0 step 177 11001111111111010100100101101010 source: 100110 changed: 0 step 178 11001101111111010100100101101010 source: 1100101101001 changed: 1 01 step 179 11001101111111010101100101101001 source: 0 changed: 0 step 180 11001101111111010100100101101001 source: 100010 changed: 0 step 181 11000101111111010100100101101001 source: 1100101011001 changed: 1 01 step 182 11000101111111010101100101011001 source: 0 changed: 0 step 183 11000101111111010100100101011001 source: 100011 changed: 1 step 184 11000111111111010100100101011001 source: 1100101011010 changed: 1 10 step 185 11000111111111010101100101011010 source: 0 changed: 0 step 186 11000111111111010100100101011010 source: 100001 changed: 0 step 187 11000011111111010100100101011010 source: 1100101010110 changed: 1 01 step 188 11000011111111010101100101010110 source: 0 changed: 0 step 189 11000011111111010100100101010110 source: 100000 changed: 0 step 190 11000001111111010100100101010110 source: 1100101010101 changed: 1 01 step 191 11000001111111010101100101010101 source: 0 changed: 0 step 192 11000001111111010100100101010101 source: 000000 changed: 0 step 193 10000001111111010100100101010101 source: 1010101010101 changed: 101 step 194 10000001111111010101010101010101 source: 0 changed: 0 step 195 10000001111111010100010101010101 source: source: ; DISABLE A INPUTS source: 0 changed: 0 step 196 10000000111111010100010101010101 source: source: source: ; TEST B INPUTS source: source: ; ENABLE B INPUTS source: 1 changed: 1 step 197 10000000111111110100010101010101 source: ; LOAD FFs FROM INPUT B source: source: 000001 changed: 00000 step 198 10000000000001110100010101010101 source: 1010101010110 changed: 1 10 step 199 10000000000001110101010101010110 source: 0 changed: 0 step 200 10000000000001110100010101010110 source: 000011 changed: 1 step 201 10000000000011110100010101010110 source: 1010101011010 changed: 1 10 step 202 10000000000011110101010101011010 source: 0 changed: 0 step 203 10000000000011110100010101011010 source: 000010 changed: 0 step 204 10000000000010110100010101011010 source: 1010101011001 changed: 1 01 step 205 10000000000010110101010101011001 source: 0 changed: 0 step 206 10000000000010110100010101011001 source: 000110 changed: 1 step 207 10000000000110110100010101011001 source: 1010101101001 changed: 1 10 step 208 10000000000110110101010101101001 source: 0 changed: 0 step 209 10000000000110110100010101101001 source: 000111 changed: 1 step 210 10000000000111110100010101101001 source: 1010101101010 changed: 1 10 step 211 10000000000111110101010101101010 source: 0 changed: 0 step 212 10000000000111110100010101101010 source: 000101 changed: 0 step 213 10000000000101110100010101101010 source: 1010101100110 changed: 1 01 step 214 10000000000101110101010101100110 source: 0 changed: 0 step 215 10000000000101110100010101100110 source: 000100 changed: 0 step 216 10000000000100110100010101100110 source: 1010101100101 changed: 1 01 step 217 10000000000100110101010101100101 source: 0 changed: 0 step 218 10000000000100110100010101100101 source: 001100 changed: 1 step 219 10000000001100110100010101100101 source: 1010110100101 changed: 1 10 step 220 10000000001100110101010110100101 source: 0 changed: 0 step 221 10000000001100110100010110100101 source: 001101 changed: 1 step 222 10000000001101110100010110100101 source: 1010110100110 changed: 1 10 step 223 10000000001101110101010110100110 source: 0 changed: 0 step 224 10000000001101110100010110100110 source: 001111 changed: 1 step 225 10000000001111110100010110100110 source: 1010110101010 changed: 1 10 step 226 10000000001111110101010110101010 source: 0 changed: 0 step 227 10000000001111110100010110101010 source: 001110 changed: 0 step 228 10000000001110110100010110101010 source: 1010110101001 changed: 1 01 step 229 10000000001110110101010110101001 source: 0 changed: 0 step 230 10000000001110110100010110101001 source: 001010 changed: 0 step 231 10000000001010110100010110101001 source: 1010110011001 changed: 1 01 step 232 10000000001010110101010110011001 source: 0 changed: 0 step 233 10000000001010110100010110011001 source: 001011 changed: 1 step 234 10000000001011110100010110011001 source: 1010110011010 changed: 1 10 step 235 10000000001011110101010110011010 source: 0 changed: 0 step 236 10000000001011110100010110011010 source: 001001 changed: 0 step 237 10000000001001110100010110011010 source: 1010110010110 changed: 1 01 step 238 10000000001001110101010110010110 source: 0 changed: 0 step 239 10000000001001110100010110010110 source: 001000 changed: 0 step 240 10000000001000110100010110010110 source: 1010110010101 changed: 1 01 step 241 10000000001000110101010110010101 source: 0 changed: 0 step 242 10000000001000110100010110010101 source: 011000 changed: 1 step 243 10000000011000110100010110010101 source: 1011010010101 changed: 1 10 step 244 10000000011000110101011010010101 source: 0 changed: 0 step 245 10000000011000110100011010010101 source: 011001 changed: 1 step 246 10000000011001110100011010010101 source: 1011010010110 changed: 1 10 step 247 10000000011001110101011010010110 source: 0 changed: 0 step 248 10000000011001110100011010010110 source: 011011 changed: 1 step 249 10000000011011110100011010010110 source: 1011010011010 changed: 1 10 step 250 10000000011011110101011010011010 source: 0 changed: 0 step 251 10000000011011110100011010011010 source: 011010 changed: 0 step 252 10000000011010110100011010011010 source: 1011010011001 changed: 1 01 step 253 10000000011010110101011010011001 source: 0 changed: 0 step 254 10000000011010110100011010011001 source: 011110 changed: 1 step 255 10000000011110110100011010011001 source: 1011010101001 changed: 1 10 step 256 10000000011110110101011010101001 source: 0 changed: 0 step 257 10000000011110110100011010101001 source: 011111 changed: 1 step 258 10000000011111110100011010101001 source: 1011010101010 changed: 1 10 step 259 10000000011111110101011010101010 source: 0 changed: 0 step 260 10000000011111110100011010101010 source: 011101 changed: 0 step 261 10000000011101110100011010101010 source: 1011010100110 changed: 1 01 step 262 10000000011101110101011010100110 source: 0 changed: 0 step 263 10000000011101110100011010100110 source: 011100 changed: 0 step 264 10000000011100110100011010100110 source: 1011010100101 changed: 1 01 step 265 10000000011100110101011010100101 source: 0 changed: 0 step 266 10000000011100110100011010100101 source: 010100 changed: 0 step 267 10000000010100110100011010100101 source: 1011001100101 changed: 1 01 step 268 10000000010100110101011001100101 source: 0 changed: 0 step 269 10000000010100110100011001100101 source: 010101 changed: 1 step 270 10000000010101110100011001100101 source: 1011001100110 changed: 1 10 step 271 10000000010101110101011001100110 source: 0 changed: 0 step 272 10000000010101110100011001100110 source: 010111 changed: 1 step 273 10000000010111110100011001100110 source: 1011001101010 changed: 1 10 step 274 10000000010111110101011001101010 source: 0 changed: 0 step 275 10000000010111110100011001101010 source: 010110 changed: 0 step 276 10000000010110110100011001101010 source: 1011001101001 changed: 1 01 step 277 10000000010110110101011001101001 source: 0 changed: 0 step 278 10000000010110110100011001101001 source: 010010 changed: 0 step 279 10000000010010110100011001101001 source: 1011001011001 changed: 1 01 step 280 10000000010010110101011001011001 source: 0 changed: 0 step 281 10000000010010110100011001011001 source: 010011 changed: 1 step 282 10000000010011110100011001011001 source: 1011001011010 changed: 1 10 step 283 10000000010011110101011001011010 source: 0 changed: 0 step 284 10000000010011110100011001011010 source: 010001 changed: 0 step 285 10000000010001110100011001011010 source: 1011001010110 changed: 1 01 step 286 10000000010001110101011001010110 source: 0 changed: 0 step 287 10000000010001110100011001010110 source: 010000 changed: 0 step 288 10000000010000110100011001010110 source: 1011001010101 changed: 1 01 step 289 10000000010000110101011001010101 source: 0 changed: 0 step 290 10000000010000110100011001010101 source: 110000 changed: 1 step 291 10000000110000110100011001010101 source: 1101001010101 changed: 110 step 292 10000000110000110101101001010101 source: 0 changed: 0 step 293 10000000110000110100101001010101 source: 110001 changed: 1 step 294 10000000110001110100101001010101 source: 1101001010110 changed: 1 10 step 295 10000000110001110101101001010110 source: 0 changed: 0 step 296 10000000110001110100101001010110 source: 110011 changed: 1 step 297 10000000110011110100101001010110 source: 1101001011010 changed: 1 10 step 298 10000000110011110101101001011010 source: 0 changed: 0 step 299 10000000110011110100101001011010 source: 110010 changed: 0 step 300 10000000110010110100101001011010 source: 1101001011001 changed: 1 01 step 301 10000000110010110101101001011001 source: 0 changed: 0 step 302 10000000110010110100101001011001 source: 110110 changed: 1 step 303 10000000110110110100101001011001 source: 1101001101001 changed: 1 10 step 304 10000000110110110101101001101001 source: 0 changed: 0 step 305 10000000110110110100101001101001 source: 110111 changed: 1 step 306 10000000110111110100101001101001 source: 1101001101010 changed: 1 10 step 307 10000000110111110101101001101010 source: 0 changed: 0 step 308 10000000110111110100101001101010 source: 110101 changed: 0 step 309 10000000110101110100101001101010 source: 1101001100110 changed: 1 01 step 310 10000000110101110101101001100110 source: 0 changed: 0 step 311 10000000110101110100101001100110 source: 110100 changed: 0 step 312 10000000110100110100101001100110 source: 1101001100101 changed: 1 01 step 313 10000000110100110101101001100101 source: 0 changed: 0 step 314 10000000110100110100101001100101 source: 111100 changed: 1 step 315 10000000111100110100101001100101 source: 1101010100101 changed: 1 10 step 316 10000000111100110101101010100101 source: 0 changed: 0 step 317 10000000111100110100101010100101 source: 111101 changed: 1 step 318 10000000111101110100101010100101 source: 1101010100110 changed: 1 10 step 319 10000000111101110101101010100110 source: 0 changed: 0 step 320 10000000111101110100101010100110 source: 111111 changed: 1 step 321 10000000111111110100101010100110 source: 1101010101010 changed: 1 10 step 322 10000000111111110101101010101010 source: 0 changed: 0 step 323 10000000111111110100101010101010 source: 111110 changed: 0 step 324 10000000111110110100101010101010 source: 1101010101001 changed: 1 01 step 325 10000000111110110101101010101001 source: 0 changed: 0 step 326 10000000111110110100101010101001 source: 111010 changed: 0 step 327 10000000111010110100101010101001 source: 1101010011001 changed: 1 01 step 328 10000000111010110101101010011001 source: 0 changed: 0 step 329 10000000111010110100101010011001 source: 111011 changed: 1 step 330 10000000111011110100101010011001 source: 1101010011010 changed: 1 10 step 331 10000000111011110101101010011010 source: 0 changed: 0 step 332 10000000111011110100101010011010 source: 111001 changed: 0 step 333 10000000111001110100101010011010 source: 1101010010110 changed: 1 01 step 334 10000000111001110101101010010110 source: 0 changed: 0 step 335 10000000111001110100101010010110 source: 111000 changed: 0 step 336 10000000111000110100101010010110 source: 1101010010101 changed: 1 01 step 337 10000000111000110101101010010101 source: 0 changed: 0 step 338 10000000111000110100101010010101 source: 101000 changed: 0 step 339 10000000101000110100101010010101 source: 1100110010101 changed: 1 01 step 340 10000000101000110101100110010101 source: 0 changed: 0 step 341 10000000101000110100100110010101 source: 101001 changed: 1 step 342 10000000101001110100100110010101 source: 1100110010110 changed: 1 10 step 343 10000000101001110101100110010110 source: 0 changed: 0 step 344 10000000101001110100100110010110 source: 101011 changed: 1 step 345 10000000101011110100100110010110 source: 1100110011010 changed: 1 10 step 346 10000000101011110101100110011010 source: 0 changed: 0 step 347 10000000101011110100100110011010 source: 101010 changed: 0 step 348 10000000101010110100100110011010 source: 1100110011001 changed: 1 01 step 349 10000000101010110101100110011001 source: 0 changed: 0 step 350 10000000101010110100100110011001 source: 101110 changed: 1 step 351 10000000101110110100100110011001 source: 1100110101001 changed: 1 10 step 352 10000000101110110101100110101001 source: 0 changed: 0 step 353 10000000101110110100100110101001 source: 101111 changed: 1 step 354 10000000101111110100100110101001 source: 1100110101010 changed: 1 10 step 355 10000000101111110101100110101010 source: 0 changed: 0 step 356 10000000101111110100100110101010 source: 101101 changed: 0 step 357 10000000101101110100100110101010 source: 1100110100110 changed: 1 01 step 358 10000000101101110101100110100110 source: 0 changed: 0 step 359 10000000101101110100100110100110 source: 101100 changed: 0 step 360 10000000101100110100100110100110 source: 1100110100101 changed: 1 01 step 361 10000000101100110101100110100101 source: 0 changed: 0 step 362 10000000101100110100100110100101 source: 100100 changed: 0 step 363 10000000100100110100100110100101 source: 1100101100101 changed: 1 01 step 364 10000000100100110101100101100101 source: 0 changed: 0 step 365 10000000100100110100100101100101 source: 100101 changed: 1 step 366 10000000100101110100100101100101 source: 1100101100110 changed: 1 10 step 367 10000000100101110101100101100110 source: 0 changed: 0 step 368 10000000100101110100100101100110 source: 100111 changed: 1 step 369 10000000100111110100100101100110 source: 1100101101010 changed: 1 10 step 370 10000000100111110101100101101010 source: 0 changed: 0 step 371 10000000100111110100100101101010 source: 100110 changed: 0 step 372 10000000100110110100100101101010 source: 1100101101001 changed: 1 01 step 373 10000000100110110101100101101001 source: 0 changed: 0 step 374 10000000100110110100100101101001 source: 100010 changed: 0 step 375 10000000100010110100100101101001 source: 1100101011001 changed: 1 01 step 376 10000000100010110101100101011001 source: 0 changed: 0 step 377 10000000100010110100100101011001 source: 100011 changed: 1 step 378 10000000100011110100100101011001 source: 1100101011010 changed: 1 10 step 379 10000000100011110101100101011010 source: 0 changed: 0 step 380 10000000100011110100100101011010 source: 100001 changed: 0 step 381 10000000100001110100100101011010 source: 1100101010110 changed: 1 01 step 382 10000000100001110101100101010110 source: 0 changed: 0 step 383 10000000100001110100100101010110 source: 100000 changed: 0 step 384 10000000100000110100100101010110 source: 1100101010101 changed: 1 01 step 385 10000000100000110101100101010101 source: 0 changed: 0 step 386 10000000100000110100100101010101 source: 000000 changed: 0 step 387 10000000000000110100100101010101 source: 1010101010101 changed: 101 step 388 10000000000000110101010101010101 source: 0 changed: 0 step 389 10000000000000110100010101010101 source: source: ; DISABLE B INPUTS source: 0 changed: 0 step 390 10000000000000010100010101010101 source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 391 10000000000000000100010101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 11 step 392 10000011000000000100010101010101 source: 1010101010110 changed: 1 10 step 393 10000011000000000101010101010110 source: 0 1 0 changed: 0 1 0 step 394 10000010000000001100010101010110 source: 1010101010101 changed: 1 01 step 395 10000010000000001101010101010101 source: 0 0 changed: 0 0 step 396 10000010000000000100010101010101 source: 0000111 changed: 1 1 step 397 10000111000000000100010101010101 source: 1010101011010 changed: 1 1010 step 398 10000111000000000101010101011010 source: 0 1 0 changed: 0 1 0 step 399 10000110000000001100010101011010 source: 1010101010110 changed: 1 01 step 400 10000110000000001101010101010110 source: 0 0 changed: 0 0 step 401 10000110000000000100010101010110 source: 0000101 changed: 01 step 402 10000101000000000100010101010110 source: 1010101011001 changed: 1 1001 step 403 10000101000000000101010101011001 source: 0 1 0 changed: 0 1 0 step 404 10000100000000001100010101011001 source: 1010101010110 changed: 1 0110 step 405 10000100000000001101010101010110 source: 0 0 changed: 0 0 step 406 10000100000000000100010101010110 source: 0001101 changed: 1 1 step 407 10001101000000000100010101010110 source: 1010101101001 changed: 1 101001 step 408 10001101000000000101010101101001 source: 0 1 0 changed: 0 1 0 step 409 10001100000000001100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 10 step 410 10001100000000001101010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 411 10001100000000000100010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 412 10001111000000000100010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 1010101101010 changed: 1 step 413 10001111000000000101010101101010 source: 0 1 0 changed: 0 1 0 step 414 10001110000000001100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 step 415 10001110000000001101010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 416 10001110000000000100010101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 417 10001011000000000100010101101010 fail ^^ source: 1010101100110 changed: 1 01 step 418 10001011000000000101010101100110 source: 0 1 0 changed: 0 1 0 step 419 10001010000000001100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 1001 step 420 10001010000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 421 10001010000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 422 10001001000000000100010101101001 fail ^^ source: 1010101100101 changed: 1 01 step 423 10001001000000000101010101100101 source: 0 1 0 changed: 0 1 0 step 424 10001000000000001100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011001 changed: 1 10 step 425 10001000000000001101010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 426 10001000000000000100010101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 427 10011001000000000100010101101001 fail ^^ source: 1010110100101 changed: 1 10 01 step 428 10011001000000000101010110100101 source: 0 1 0 changed: 0 1 0 step 429 10011000000000001100010110100101 source: 1010101101001 changed: 1 01 10 step 430 10011000000000001101010101101001 source: 0 0 changed: 0 0 step 431 10011000000000000100010101101001 source: 0011011 changed: 11 step 432 10011011000000000100010101101001 source: 1010110100110 changed: 1 10 0110 step 433 10011011000000000101010110100110 source: 0 1 0 changed: 0 1 0 step 434 10011010000000001100010110100110 source: 1010101101001 changed: 1 01 1001 step 435 10011010000000001101010101101001 source: 0 0 changed: 0 0 step 436 10011010000000000100010101101001 source: 0011111 changed: 1 1 step 437 10011111000000000100010101101001 source: 1010110101010 changed: 1 10 10 step 438 10011111000000000101010110101010 source: 0 1 0 changed: 0 1 0 step 439 10011110000000001100010110101010 source: 1010101101010 changed: 1 01 step 440 10011110000000001101010101101010 source: 0 0 changed: 0 0 step 441 10011110000000000100010101101010 source: 0011101 changed: 01 step 442 10011101000000000100010101101010 source: 1010110101001 changed: 1 10 01 step 443 10011101000000000101010110101001 source: 0 1 0 changed: 0 1 0 step 444 10011100000000001100010110101001 source: 1010101101010 changed: 1 01 10 step 445 10011100000000001101010101101010 source: 0 0 changed: 0 0 step 446 10011100000000000100010101101010 source: 0010101 changed: 0 1 step 447 10010101000000000100010101101010 source: 1010110011001 changed: 1 1001 01 step 448 10010101000000000101010110011001 source: 0 1 0 changed: 0 1 0 step 449 10010100000000001100010110011001 source: 1010101100110 changed: 1 01100110 step 450 10010100000000001101010101100110 source: 0 0 changed: 0 0 step 451 10010100000000000100010101100110 source: 0010111 changed: 11 step 452 10010111000000000100010101100110 source: 1010110011010 changed: 1 100110 step 453 10010111000000000101010110011010 source: 0 1 0 changed: 0 1 0 step 454 10010110000000001100010110011010 source: 1010101100110 changed: 1 011001 step 455 10010110000000001101010101100110 source: 0 0 changed: 0 0 step 456 10010110000000000100010101100110 source: 0010011 changed: 0 1 step 457 10010011000000000100010101100110 source: 1010110010110 changed: 1 1001 step 458 10010011000000000101010110010110 source: 0 1 0 changed: 0 1 0 step 459 10010010000000001100010110010110 source: 1010101100101 changed: 1 0110 01 step 460 10010010000000001101010101100101 source: 0 0 changed: 0 0 step 461 10010010000000000100010101100101 source: 0010001 changed: 01 step 462 10010001000000000100010101100101 source: 1010110010101 changed: 1 1001 step 463 10010001000000000101010110010101 source: 0 1 0 changed: 0 1 0 step 464 10010000000000001100010110010101 source: 1010101100101 changed: 1 0110 step 465 10010000000000001101010101100101 source: 0 0 changed: 0 0 step 466 10010000000000000100010101100101 source: 0110001 changed: 1 1 step 467 10110001000000000100010101100101 source: 1011010010101 changed: 1 101001 step 468 10110001000000000101011010010101 source: 0 1 0 changed: 0 1 0 step 469 10110000000000001100011010010101 source: 1010110100101 changed: 1 01 10 step 470 10110000000000001101010110100101 source: 0 0 changed: 0 0 step 471 10110000000000000100010110100101 source: 0110011 changed: 11 step 472 10110011000000000100010110100101 source: 1011010010110 changed: 1 10 01 10 step 473 10110011000000000101011010010110 source: 0 1 0 changed: 0 1 0 step 474 10110010000000001100011010010110 source: 1010110100101 changed: 1 01 10 01 step 475 10110010000000001101010110100101 source: 0 0 changed: 0 0 step 476 10110010000000000100010110100101 source: 0110111 changed: 1 1 step 477 10110111000000000100010110100101 source: 1011010011010 changed: 1 10 011010 step 478 10110111000000000101011010011010 source: 0 1 0 changed: 0 1 0 step 479 10110110000000001100011010011010 source: 1010110100110 changed: 1 01 1001 step 480 10110110000000001101010110100110 source: 0 0 changed: 0 0 step 481 10110110000000000100010110100110 source: 0110101 changed: 01 step 482 10110101000000000100010110100110 source: 1011010011001 changed: 1 10 011001 step 483 10110101000000000101011010011001 source: 0 1 0 changed: 0 1 0 step 484 10110100000000001100011010011001 source: 1010110100110 changed: 1 01 100110 step 485 10110100000000001101010110100110 source: 0 0 changed: 0 0 step 486 10110100000000000100010110100110 source: 0111101 changed: 1 1 step 487 10111101000000000100010110100110 source: 1011010101001 changed: 1 10 1001 step 488 10111101000000000101011010101001 source: 0 1 0 changed: 0 1 0 step 489 10111100000000001100011010101001 source: 1010110101010 changed: 1 01 10 step 490 10111100000000001101010110101010 source: 0 0 changed: 0 0 step 491 10111100000000000100010110101010 source: 0111111 changed: 11 step 492 10111111000000000100010110101010 source: 1011010101010 changed: 1 10 step 493 10111111000000000101011010101010 source: 0 1 0 changed: 0 1 0 step 494 10111110000000001100011010101010 source: 1010110101010 changed: 1 01 step 495 10111110000000001101010110101010 source: 0 0 changed: 0 0 step 496 10111110000000000100010110101010 source: 0111011 changed: 0 1 step 497 10111011000000000100010110101010 source: 1011010100110 changed: 1 10 01 step 498 10111011000000000101011010100110 source: 0 1 0 changed: 0 1 0 step 499 10111010000000001100011010100110 source: 1010110101001 changed: 1 01 1001 step 500 10111010000000001101010110101001 source: 0 0 changed: 0 0 step 501 10111010000000000100010110101001 source: 0111001 changed: 01 step 502 10111001000000000100010110101001 source: 1011010100101 changed: 1 10 01 step 503 10111001000000000101011010100101 source: 0 1 0 changed: 0 1 0 step 504 10111000000000001100011010100101 source: 1010110101001 changed: 1 01 10 step 505 10111000000000001101010110101001 source: 0 0 changed: 0 0 step 506 10111000000000000100010110101001 source: 0101001 changed: 0 1 step 507 10101001000000000100010110101001 source: 1011001100101 changed: 1 1001 01 step 508 10101001000000000101011001100101 source: 0 1 0 changed: 0 1 0 step 509 10101000000000001100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 0110 10 step 510 10101000000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 511 10101000000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 512 10101011000000000100010110101001 fail ^^ source: 1011001100110 changed: 1 1001 0110 step 513 10101011000000000101011001100110 source: 0 1 0 changed: 0 1 0 step 514 10101010000000001100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 0110 1001 step 515 10101010000000001101010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 516 10101010000000000100010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 517 10101111000000000100010110101001 fail ^^ source: 1011001101010 changed: 1 1001 10 step 518 10101111000000000101011001101010 source: 0 1 0 changed: 0 1 0 step 519 10101110000000001100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 0110 step 520 10101110000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 521 10101110000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 522 10101101000000000100010110101010 fail ^^ source: 1011001101001 changed: 1 1001 01 step 523 10101101000000000101011001101001 source: 0 1 0 changed: 0 1 0 step 524 10101100000000001100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 0110 10 step 525 10101100000000001101010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 526 10101100000000000100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 527 10100101000000000100010110101010 fail ^^ source: 1011001011001 changed: 1 100101 01 step 528 10100101000000000101011001011001 source: 0 1 0 changed: 0 1 0 step 529 10100100000000001100011001011001 source: 1010110010110 changed: 1 0110 0110 step 530 10100100000000001101010110010110 source: 0 0 changed: 0 0 step 531 10100100000000000100010110010110 source: 0100111 changed: 11 step 532 10100111000000000100010110010110 source: 1011001011010 changed: 1 1001 10 step 533 10100111000000000101011001011010 source: 0 1 0 changed: 0 1 0 step 534 10100110000000001100011001011010 source: 1010110010110 changed: 1 0110 01 step 535 10100110000000001101010110010110 source: 0 0 changed: 0 0 step 536 10100110000000000100010110010110 source: 0100011 changed: 0 1 step 537 10100011000000000100010110010110 source: 1011001010110 changed: 1 1001 step 538 10100011000000000101011001010110 source: 0 1 0 changed: 0 1 0 step 539 10100010000000001100011001010110 source: 1010110010101 changed: 1 0110 01 step 540 10100010000000001101010110010101 source: 0 0 changed: 0 0 step 541 10100010000000000100010110010101 source: 0100001 changed: 01 step 542 10100001000000000100010110010101 source: 1011001010101 changed: 1 1001 step 543 10100001000000000101011001010101 source: 0 1 0 changed: 0 1 0 step 544 10100000000000001100011001010101 source: 1010110010101 changed: 1 0110 step 545 10100000000000001101010110010101 source: 0 0 changed: 0 0 step 546 10100000000000000100010110010101 source: 1100001 changed: 1 1 step 547 11100001000000000100010110010101 source: 1101001010101 changed: 1101001 step 548 11100001000000000101101001010101 source: 0 1 0 changed: 0 1 0 step 549 11100000000000001100101001010101 source: 1011010010101 changed: 101 10 step 550 11100000000000001101011010010101 source: 0 0 changed: 0 0 step 551 11100000000000000100011010010101 source: 1100011 changed: 11 step 552 11100011000000000100011010010101 source: 1101001010110 changed: 110 01 10 step 553 11100011000000000101101001010110 source: 0 1 0 changed: 0 1 0 step 554 11100010000000001100101001010110 source: 1011010010101 changed: 101 10 01 step 555 11100010000000001101011010010101 source: 0 0 changed: 0 0 step 556 11100010000000000100011010010101 source: 1100111 changed: 1 1 step 557 11100111000000000100011010010101 source: 1101001011010 changed: 110 01 1010 step 558 11100111000000000101101001011010 source: 0 1 0 changed: 0 1 0 step 559 11100110000000001100101001011010 source: 1011010010110 changed: 101 10 01 step 560 11100110000000001101011010010110 source: 0 0 changed: 0 0 step 561 11100110000000000100011010010110 source: 1100101 changed: 01 step 562 11100101000000000100011010010110 source: 1101001011001 changed: 110 01 1001 step 563 11100101000000000101101001011001 source: 0 1 0 changed: 0 1 0 step 564 11100100000000001100101001011001 source: 1011010010110 changed: 101 10 0110 step 565 11100100000000001101011010010110 source: 0 0 changed: 0 0 step 566 11100100000000000100011010010110 source: 1101101 changed: 1 1 step 567 11101101000000000100011010010110 source: 1101001101001 changed: 110 01101001 step 568 11101101000000000101101001101001 source: 0 1 0 changed: 0 1 0 step 569 11101100000000001100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 101 10 10 step 570 11101100000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 571 11101100000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 572 11101111000000000100011010101010 fail ^^ source: 1101001101010 changed: 110 01 step 573 11101111000000000101101001101010 source: 0 1 0 changed: 0 1 0 step 574 11101110000000001100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 101 10 step 575 11101110000000001101011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 576 11101110000000000100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 577 11101011000000000100011010101010 fail ^^ source: 1101001100110 changed: 110 01 01 step 578 11101011000000000101101001100110 source: 0 1 0 changed: 0 1 0 step 579 11101010000000001100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 101 10 1001 step 580 11101010000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 581 11101010000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 582 11101001000000000100011010101001 fail ^^ source: 1101001100101 changed: 110 01 01 step 583 11101001000000000101101001100101 source: 0 1 0 changed: 0 1 0 step 584 11101000000000001100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 101 10 10 step 585 11101000000000001101011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 586 11101000000000000100011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 587 11111001000000000100011010101001 fail ^^ source: 1101010100101 changed: 110 01 step 588 11111001000000000101101010100101 source: 0 1 0 changed: 0 1 0 step 589 11111000000000001100101010100101 source: 1011010101001 changed: 101 10 step 590 11111000000000001101011010101001 source: 0 0 changed: 0 0 step 591 11111000000000000100011010101001 source: 1111011 changed: 11 step 592 11111011000000000100011010101001 source: 1101010100110 changed: 110 0110 step 593 11111011000000000101101010100110 source: 0 1 0 changed: 0 1 0 step 594 11111010000000001100101010100110 source: 1011010101001 changed: 101 1001 step 595 11111010000000001101011010101001 source: 0 0 changed: 0 0 step 596 11111010000000000100011010101001 source: 1111111 changed: 1 1 step 597 11111111000000000100011010101001 source: 1101010101010 changed: 110 10 step 598 11111111000000000101101010101010 source: 0 1 0 changed: 0 1 0 step 599 11111110000000001100101010101010 source: 1011010101010 changed: 101 step 600 11111110000000001101011010101010 source: 0 0 changed: 0 0 step 601 11111110000000000100011010101010 source: 1111101 changed: 01 step 602 11111101000000000100011010101010 source: 1101010101001 changed: 110 01 step 603 11111101000000000101101010101001 source: 0 1 0 changed: 0 1 0 step 604 11111100000000001100101010101001 source: 1011010101010 changed: 101 10 step 605 11111100000000001101011010101010 source: 0 0 changed: 0 0 step 606 11111100000000000100011010101010 source: 1110101 changed: 0 1 step 607 11110101000000000100011010101010 source: 1101010011001 changed: 110 01 01 step 608 11110101000000000101101010011001 source: 0 1 0 changed: 0 1 0 step 609 11110100000000001100101010011001 source: 1011010100110 changed: 101 100110 step 610 11110100000000001101011010100110 source: 0 0 changed: 0 0 step 611 11110100000000000100011010100110 source: 1110111 changed: 11 step 612 11110111000000000100011010100110 source: 1101010011010 changed: 110 0110 step 613 11110111000000000101101010011010 source: 0 1 0 changed: 0 1 0 step 614 11110110000000001100101010011010 source: 1011010100110 changed: 101 1001 step 615 11110110000000001101011010100110 source: 0 0 changed: 0 0 step 616 11110110000000000100011010100110 source: 1110011 changed: 0 1 step 617 11110011000000000100011010100110 source: 1101010010110 changed: 110 01 step 618 11110011000000000101101010010110 source: 0 1 0 changed: 0 1 0 step 619 11110010000000001100101010010110 source: 1011010100101 changed: 101 10 01 step 620 11110010000000001101011010100101 source: 0 0 changed: 0 0 step 621 11110010000000000100011010100101 source: 1110001 changed: 01 step 622 11110001000000000100011010100101 source: 1101010010101 changed: 110 01 step 623 11110001000000000101101010010101 source: 0 1 0 changed: 0 1 0 step 624 11110000000000001100101010010101 source: 1011010100101 changed: 101 10 step 625 11110000000000001101011010100101 source: 0 0 changed: 0 0 step 626 11110000000000000100011010100101 source: 1010001 changed: 0 1 step 627 11010001000000000100011010100101 source: 1100110010101 changed: 11001 01 step 628 11010001000000000101100110010101 source: 0 1 0 changed: 0 1 0 step 629 11010000000000001100100110010101 source: 1011001100101 changed: 101100110 step 630 11010000000000001101011001100101 source: 0 0 changed: 0 0 step 631 11010000000000000100011001100101 source: 1010011 changed: 11 step 632 11010011000000000100011001100101 source: 1100110010110 changed: 110011001 10 step 633 11010011000000000101100110010110 source: 0 1 0 changed: 0 1 0 step 634 11010010000000001100100110010110 source: 1011001100101 changed: 101100110 01 step 635 11010010000000001101011001100101 source: 0 0 changed: 0 0 step 636 11010010000000000100011001100101 source: 1010111 changed: 1 1 step 637 11010111000000000100011001100101 source: 1100110011010 changed: 1100110011010 step 638 11010111000000000101100110011010 source: 0 1 0 changed: 0 1 0 step 639 11010110000000001100100110011010 source: 1011001100110 changed: 10110011001 step 640 11010110000000001101011001100110 source: 0 0 changed: 0 0 step 641 11010110000000000100011001100110 source: 1010101 changed: 01 step 642 11010101000000000100011001100110 source: 1100110011001 changed: 1100110011001 step 643 11010101000000000101100110011001 source: 0 1 0 changed: 0 1 0 step 644 11010100000000001100100110011001 source: 1011001100110 changed: 1011001100110 step 645 11010100000000001101011001100110 source: 0 0 changed: 0 0 step 646 11010100000000000100011001100110 source: 1011101 changed: 1 1 step 647 11011101000000000100011001100110 source: 1100110101001 changed: 1100110 1001 step 648 11011101000000000101100110101001 source: 0 1 0 changed: 0 1 0 step 649 11011100000000001100100110101001 source: 1011001101010 changed: 1011001 10 step 650 11011100000000001101011001101010 source: 0 0 changed: 0 0 step 651 11011100000000000100011001101010 source: 1011111 changed: 11 step 652 11011111000000000100011001101010 source: 1100110101010 changed: 1100110 step 653 11011111000000000101100110101010 source: 0 1 0 changed: 0 1 0 step 654 11011110000000001100100110101010 source: 1011001101010 changed: 1011001 step 655 11011110000000001101011001101010 source: 0 0 changed: 0 0 step 656 11011110000000000100011001101010 source: 1011011 changed: 0 1 step 657 11011011000000000100011001101010 source: 1100110100110 changed: 1100110 01 step 658 11011011000000000101100110100110 source: 0 1 0 changed: 0 1 0 step 659 11011010000000001100100110100110 source: 1011001101001 changed: 1011001 1001 step 660 11011010000000001101011001101001 source: 0 0 changed: 0 0 step 661 11011010000000000100011001101001 source: 1011001 changed: 01 step 662 11011001000000000100011001101001 source: 1100110100101 changed: 1100110 01 step 663 11011001000000000101100110100101 source: 0 1 0 changed: 0 1 0 step 664 11011000000000001100100110100101 source: 1011001101001 changed: 1011001 10 step 665 11011000000000001101011001101001 source: 0 0 changed: 0 0 step 666 11011000000000000100011001101001 source: 1001001 changed: 0 1 step 667 11001001000000000100011001101001 source: 1100101100101 changed: 11001 01 step 668 11001001000000000101100101100101 source: 0 1 0 changed: 0 1 0 step 669 11001000000000001100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 10110 10 step 670 11001000000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 671 11001000000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 672 11001011000000000100011001101001 fail ^^ source: 1100101100110 changed: 11001 0110 step 673 11001011000000000101100101100110 source: 0 1 0 changed: 0 1 0 step 674 11001010000000001100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011001 changed: 10110 1001 step 675 11001010000000001101011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 676 11001010000000000100011001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 677 11001111000000000100011001101001 fail ^^ source: 1100101101010 changed: 11001 10 step 678 11001111000000000101100101101010 source: 0 1 0 changed: 0 1 0 step 679 11001110000000001100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 10110 step 680 11001110000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 681 11001110000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 682 11001101000000000100011001101010 fail ^^ source: 1100101101001 changed: 11001 01 step 683 11001101000000000101100101101001 source: 0 1 0 changed: 0 1 0 step 684 11001100000000001100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001011010 changed: 10110 10 step 685 11001100000000001101011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 686 11001100000000000100011001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 687 11000101000000000100011001101010 fail ^^ source: 1100101011001 changed: 11001 01 01 step 688 11000101000000000101100101011001 source: 0 1 0 changed: 0 1 0 step 689 11000100000000001100100101011001 source: 1011001010110 changed: 10110 0110 step 690 11000100000000001101011001010110 source: 0 0 changed: 0 0 step 691 11000100000000000100011001010110 source: 1000111 changed: 11 step 692 11000111000000000100011001010110 source: 1100101011010 changed: 11001 10 step 693 11000111000000000101100101011010 source: 0 1 0 changed: 0 1 0 step 694 11000110000000001100100101011010 source: 1011001010110 changed: 10110 01 step 695 11000110000000001101011001010110 source: 0 0 changed: 0 0 step 696 11000110000000000100011001010110 source: 1000011 changed: 0 1 step 697 11000011000000000100011001010110 source: 1100101010110 changed: 11001 step 698 11000011000000000101100101010110 source: 0 1 0 changed: 0 1 0 step 699 11000010000000001100100101010110 source: 1011001010101 changed: 10110 01 step 700 11000010000000001101011001010101 source: 0 0 changed: 0 0 step 701 11000010000000000100011001010101 source: 1000001 changed: 01 step 702 11000001000000000100011001010101 source: 1100101010101 changed: 11001 step 703 11000001000000000101100101010101 source: 0 1 0 changed: 0 1 0 step 704 11000000000000001100100101010101 source: 1011001010101 changed: 10110 step 705 11000000000000001101011001010101 source: 0 0 changed: 0 0 step 706 11000000000000000100011001010101 source: 0000001 changed: 0 1 step 707 10000001000000000100011001010101 source: 1010101010101 changed: 1 01 step 708 10000001000000000101010101010101 source: 0 1 0 changed: 0 1 0 step 709 10000000000000001100010101010101 source: 1010101010101 changed: 1 step 710 10000000000000001101010101010101 source: 0 0 changed: 0 0 step 711 10000000000000000100010101010101 source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 712 10000000000000010100010101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 11 step 713 10000011000000010100010101010101 source: 1010101010110 changed: 1 10 step 714 10000011000000010101010101010110 source: 0 1 0 changed: 0 1 0 step 715 10000010000000011100010101010110 source: 1100101010101 changed: 110 01 step 716 10000010000000011101100101010101 source: 0 0 changed: 0 0 step 717 10000010000000010100100101010101 source: 0000111 changed: 1 1 step 718 10000111000000010100100101010101 source: 1010101011010 changed: 101 1010 step 719 10000111000000010101010101011010 source: 0 1 0 changed: 0 1 0 step 720 10000110000000011100010101011010 source: 1100101010110 changed: 110 01 step 721 10000110000000011101100101010110 source: 0 0 changed: 0 0 step 722 10000110000000010100100101010110 source: 0000101 changed: 01 step 723 10000101000000010100100101010110 source: 1010101011001 changed: 101 1001 step 724 10000101000000010101010101011001 source: 0 1 0 changed: 0 1 0 step 725 10000100000000011100010101011001 source: 1100101010110 changed: 110 0110 step 726 10000100000000011101100101010110 source: 0 0 changed: 0 0 step 727 10000100000000010100100101010110 source: 0001101 changed: 1 1 step 728 10001101000000010100100101010110 source: 1010101101001 changed: 101 101001 step 729 10001101000000010101010101101001 source: 0 1 0 changed: 0 1 0 step 730 10001100000000011100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 110 10 step 731 10001100000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 732 10001100000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001111 changed: 11 step 733 10001111000000010100100101101010 fail ^^ source: 1010101101010 changed: 101 step 734 10001111000000010101010101101010 source: 0 1 0 changed: 0 1 0 step 735 10001110000000011100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011010 changed: 110 step 736 10001110000000011101100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 737 10001110000000010100100101101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001011 changed: 0 1 step 738 10001011000000010100100101101010 fail ^^ source: 1010101100110 changed: 101 01 step 739 10001011000000010101010101100110 source: 0 1 0 changed: 0 1 0 step 740 10001010000000011100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 110 1001 step 741 10001010000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 742 10001010000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 743 10001001000000010100100101101001 fail ^^ source: 1010101100101 changed: 101 01 step 744 10001001000000010101010101100101 source: 0 1 0 changed: 0 1 0 step 745 10001000000000011100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100101011001 changed: 110 10 step 746 10001000000000011101100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 747 10001000000000010100100101101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 748 10011001000000010100100101101001 fail ^^ source: 1010110100101 changed: 101 10 01 step 749 10011001000000010101010110100101 source: 0 1 0 changed: 0 1 0 step 750 10011000000000011100010110100101 source: 1100101101001 changed: 110 01 10 step 751 10011000000000011101100101101001 source: 0 0 changed: 0 0 step 752 10011000000000010100100101101001 source: 0011011 changed: 11 step 753 10011011000000010100100101101001 source: 1010110100110 changed: 101 10 0110 step 754 10011011000000010101010110100110 source: 0 1 0 changed: 0 1 0 step 755 10011010000000011100010110100110 source: 1100101101001 changed: 110 01 1001 step 756 10011010000000011101100101101001 source: 0 0 changed: 0 0 step 757 10011010000000010100100101101001 source: 0011111 changed: 1 1 step 758 10011111000000010100100101101001 source: 1010110101010 changed: 101 10 10 step 759 10011111000000010101010110101010 source: 0 1 0 changed: 0 1 0 step 760 10011110000000011100010110101010 source: 1100101101010 changed: 110 01 step 761 10011110000000011101100101101010 source: 0 0 changed: 0 0 step 762 10011110000000010100100101101010 source: 0011101 changed: 01 step 763 10011101000000010100100101101010 source: 1010110101001 changed: 101 10 01 step 764 10011101000000010101010110101001 source: 0 1 0 changed: 0 1 0 step 765 10011100000000011100010110101001 source: 1100101101010 changed: 110 01 10 step 766 10011100000000011101100101101010 source: 0 0 changed: 0 0 step 767 10011100000000010100100101101010 source: 0010101 changed: 0 1 step 768 10010101000000010100100101101010 source: 1010110011001 changed: 101 1001 01 step 769 10010101000000010101010110011001 source: 0 1 0 changed: 0 1 0 step 770 10010100000000011100010110011001 source: 1100101100110 changed: 110 01100110 step 771 10010100000000011101100101100110 source: 0 0 changed: 0 0 step 772 10010100000000010100100101100110 source: 0010111 changed: 11 step 773 10010111000000010100100101100110 source: 1010110011010 changed: 101 100110 step 774 10010111000000010101010110011010 source: 0 1 0 changed: 0 1 0 step 775 10010110000000011100010110011010 source: 1100101100110 changed: 110 011001 step 776 10010110000000011101100101100110 source: 0 0 changed: 0 0 step 777 10010110000000010100100101100110 source: 0010011 changed: 0 1 step 778 10010011000000010100100101100110 source: 1010110010110 changed: 101 1001 step 779 10010011000000010101010110010110 source: 0 1 0 changed: 0 1 0 step 780 10010010000000011100010110010110 source: 1100101100101 changed: 110 0110 01 step 781 10010010000000011101100101100101 source: 0 0 changed: 0 0 step 782 10010010000000010100100101100101 source: 0010001 changed: 01 step 783 10010001000000010100100101100101 source: 1010110010101 changed: 101 1001 step 784 10010001000000010101010110010101 source: 0 1 0 changed: 0 1 0 step 785 10010000000000011100010110010101 source: 1100101100101 changed: 110 0110 step 786 10010000000000011101100101100101 source: 0 0 changed: 0 0 step 787 10010000000000010100100101100101 source: 0110001 changed: 1 1 step 788 10110001000000010100100101100101 source: 1011010010101 changed: 101101001 step 789 10110001000000010101011010010101 source: 0 1 0 changed: 0 1 0 step 790 10110000000000011100011010010101 source: 1100110100101 changed: 11001 10 step 791 10110000000000011101100110100101 source: 0 0 changed: 0 0 step 792 10110000000000010100100110100101 source: 0110011 changed: 11 step 793 10110011000000010100100110100101 source: 1011010010110 changed: 10110 01 10 step 794 10110011000000010101011010010110 source: 0 1 0 changed: 0 1 0 step 795 10110010000000011100011010010110 source: 1100110100101 changed: 11001 10 01 step 796 10110010000000011101100110100101 source: 0 0 changed: 0 0 step 797 10110010000000010100100110100101 source: 0110111 changed: 1 1 step 798 10110111000000010100100110100101 source: 1011010011010 changed: 10110 011010 step 799 10110111000000010101011010011010 source: 0 1 0 changed: 0 1 0 step 800 10110110000000011100011010011010 source: 1100110100110 changed: 11001 1001 step 801 10110110000000011101100110100110 source: 0 0 changed: 0 0 step 802 10110110000000010100100110100110 source: 0110101 changed: 01 step 803 10110101000000010100100110100110 source: 1011010011001 changed: 10110 011001 step 804 10110101000000010101011010011001 source: 0 1 0 changed: 0 1 0 step 805 10110100000000011100011010011001 source: 1100110100110 changed: 11001 100110 step 806 10110100000000011101100110100110 source: 0 0 changed: 0 0 step 807 10110100000000010100100110100110 source: 0111101 changed: 1 1 step 808 10111101000000010100100110100110 source: 1011010101001 changed: 10110 1001 step 809 10111101000000010101011010101001 source: 0 1 0 changed: 0 1 0 step 810 10111100000000011100011010101001 source: 1100110101010 changed: 11001 10 step 811 10111100000000011101100110101010 source: 0 0 changed: 0 0 step 812 10111100000000010100100110101010 source: 0111111 changed: 11 step 813 10111111000000010100100110101010 source: 1011010101010 changed: 10110 step 814 10111111000000010101011010101010 source: 0 1 0 changed: 0 1 0 step 815 10111110000000011100011010101010 source: 1100110101010 changed: 11001 step 816 10111110000000011101100110101010 source: 0 0 changed: 0 0 step 817 10111110000000010100100110101010 source: 0111011 changed: 0 1 step 818 10111011000000010100100110101010 source: 1011010100110 changed: 10110 01 step 819 10111011000000010101011010100110 source: 0 1 0 changed: 0 1 0 step 820 10111010000000011100011010100110 source: 1100110101001 changed: 11001 1001 step 821 10111010000000011101100110101001 source: 0 0 changed: 0 0 step 822 10111010000000010100100110101001 source: 0111001 changed: 01 step 823 10111001000000010100100110101001 source: 1011010100101 changed: 10110 01 step 824 10111001000000010101011010100101 source: 0 1 0 changed: 0 1 0 step 825 10111000000000011100011010100101 source: 1100110101001 changed: 11001 10 step 826 10111000000000011101100110101001 source: 0 0 changed: 0 0 step 827 10111000000000010100100110101001 source: 0101001 changed: 0 1 step 828 10101001000000010100100110101001 source: 1011001100101 changed: 1011001 01 step 829 10101001000000010101011001100101 source: 0 1 0 changed: 0 1 0 step 830 10101000000000011100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110 10 step 831 10101000000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 832 10101000000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 833 10101011000000010100100110101001 fail ^^ source: 1011001100110 changed: 1011001 0110 step 834 10101011000000010101011001100110 source: 0 1 0 changed: 0 1 0 step 835 10101010000000011100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110 1001 step 836 10101010000000011101100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 837 10101010000000010100100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 838 10101111000000010100100110101001 fail ^^ source: 1011001101010 changed: 1011001 10 step 839 10101111000000010101011001101010 source: 0 1 0 changed: 0 1 0 step 840 10101110000000011100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1100110 step 841 10101110000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 842 10101110000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101101 changed: 01 step 843 10101101000000010100100110101010 fail ^^ source: 1011001101001 changed: 1011001 01 step 844 10101101000000010101011001101001 source: 0 1 0 changed: 0 1 0 step 845 10101100000000011100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1100110 10 step 846 10101100000000011101100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 847 10101100000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0100101 changed: 0 1 step 848 10100101000000010100100110101010 fail ^^ source: 1011001011001 changed: 101100101 01 step 849 10100101000000010101011001011001 source: 0 1 0 changed: 0 1 0 step 850 10100100000000011100011001011001 source: 1100110010110 changed: 1100110 0110 step 851 10100100000000011101100110010110 source: 0 0 changed: 0 0 step 852 10100100000000010100100110010110 source: 0100111 changed: 11 step 853 10100111000000010100100110010110 source: 1011001011010 changed: 1011001 10 step 854 10100111000000010101011001011010 source: 0 1 0 changed: 0 1 0 step 855 10100110000000011100011001011010 source: 1100110010110 changed: 1100110 01 step 856 10100110000000011101100110010110 source: 0 0 changed: 0 0 step 857 10100110000000010100100110010110 source: 0100011 changed: 0 1 step 858 10100011000000010100100110010110 source: 1011001010110 changed: 1011001 step 859 10100011000000010101011001010110 source: 0 1 0 changed: 0 1 0 step 860 10100010000000011100011001010110 source: 1100110010101 changed: 1100110 01 step 861 10100010000000011101100110010101 source: 0 0 changed: 0 0 step 862 10100010000000010100100110010101 source: 0100001 changed: 01 step 863 10100001000000010100100110010101 source: 1011001010101 changed: 1011001 step 864 10100001000000010101011001010101 source: 0 1 0 changed: 0 1 0 step 865 10100000000000011100011001010101 source: 1100110010101 changed: 1100110 step 866 10100000000000011101100110010101 source: 0 0 changed: 0 0 step 867 10100000000000010100100110010101 source: 1100001 changed: 1 1 step 868 11100001000000010100100110010101 source: 1101001010101 changed: 1 1001 step 869 11100001000000010101101001010101 source: 0 1 0 changed: 0 1 0 step 870 11100000000000011100101001010101 source: 1101010010101 changed: 1 10 step 871 11100000000000011101101010010101 source: 0 0 changed: 0 0 step 872 11100000000000010100101010010101 source: 1100011 changed: 11 step 873 11100011000000010100101010010101 source: 1101001010110 changed: 1 01 10 step 874 11100011000000010101101001010110 source: 0 1 0 changed: 0 1 0 step 875 11100010000000011100101001010110 source: 1101010010101 changed: 1 10 01 step 876 11100010000000011101101010010101 source: 0 0 changed: 0 0 step 877 11100010000000010100101010010101 source: 1100111 changed: 1 1 step 878 11100111000000010100101010010101 source: 1101001011010 changed: 1 01 1010 step 879 11100111000000010101101001011010 source: 0 1 0 changed: 0 1 0 step 880 11100110000000011100101001011010 source: 1101010010110 changed: 1 10 01 step 881 11100110000000011101101010010110 source: 0 0 changed: 0 0 step 882 11100110000000010100101010010110 source: 1100101 changed: 01 step 883 11100101000000010100101010010110 source: 1101001011001 changed: 1 01 1001 step 884 11100101000000010101101001011001 source: 0 1 0 changed: 0 1 0 step 885 11100100000000011100101001011001 source: 1101010010110 changed: 1 10 0110 step 886 11100100000000011101101010010110 source: 0 0 changed: 0 0 step 887 11100100000000010100101010010110 source: 1101101 changed: 1 1 step 888 11101101000000010100101010010110 source: 1101001101001 changed: 1 01101001 step 889 11101101000000010101101001101001 source: 0 1 0 changed: 0 1 0 step 890 11101100000000011100101001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 10 10 step 891 11101100000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 892 11101100000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101111 changed: 11 step 893 11101111000000010100101010101010 fail ^^ source: 1101001101010 changed: 1 01 step 894 11101111000000010101101001101010 source: 0 1 0 changed: 0 1 0 step 895 11101110000000011100101001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 10 step 896 11101110000000011101101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 897 11101110000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101011 changed: 0 1 step 898 11101011000000010100101010101010 fail ^^ source: 1101001100110 changed: 1 01 01 step 899 11101011000000010101101001100110 source: 0 1 0 changed: 0 1 0 step 900 11101010000000011100101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 10 1001 step 901 11101010000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 902 11101010000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 903 11101001000000010100101010101001 fail ^^ source: 1101001100101 changed: 1 01 01 step 904 11101001000000010101101001100101 source: 0 1 0 changed: 0 1 0 step 905 11101000000000011100101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 10 10 step 906 11101000000000011101101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 907 11101000000000010100101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 908 11111001000000010100101010101001 fail ^^ source: 1101010100101 changed: 1 01 step 909 11111001000000010101101010100101 source: 0 1 0 changed: 0 1 0 step 910 11111000000000011100101010100101 source: 1101010101001 changed: 1 10 step 911 11111000000000011101101010101001 source: 0 0 changed: 0 0 step 912 11111000000000010100101010101001 source: 1111011 changed: 11 step 913 11111011000000010100101010101001 source: 1101010100110 changed: 1 0110 step 914 11111011000000010101101010100110 source: 0 1 0 changed: 0 1 0 step 915 11111010000000011100101010100110 source: 1101010101001 changed: 1 1001 step 916 11111010000000011101101010101001 source: 0 0 changed: 0 0 step 917 11111010000000010100101010101001 source: 1111111 changed: 1 1 step 918 11111111000000010100101010101001 source: 1101010101010 changed: 1 10 step 919 11111111000000010101101010101010 source: 0 1 0 changed: 0 1 0 step 920 11111110000000011100101010101010 source: 1101010101010 changed: 1 step 921 11111110000000011101101010101010 source: 0 0 changed: 0 0 step 922 11111110000000010100101010101010 source: 1111101 changed: 01 step 923 11111101000000010100101010101010 source: 1101010101001 changed: 1 01 step 924 11111101000000010101101010101001 source: 0 1 0 changed: 0 1 0 step 925 11111100000000011100101010101001 source: 1101010101010 changed: 1 10 step 926 11111100000000011101101010101010 source: 0 0 changed: 0 0 step 927 11111100000000010100101010101010 source: 1110101 changed: 0 1 step 928 11110101000000010100101010101010 source: 1101010011001 changed: 1 01 01 step 929 11110101000000010101101010011001 source: 0 1 0 changed: 0 1 0 step 930 11110100000000011100101010011001 source: 1101010100110 changed: 1 100110 step 931 11110100000000011101101010100110 source: 0 0 changed: 0 0 step 932 11110100000000010100101010100110 source: 1110111 changed: 11 step 933 11110111000000010100101010100110 source: 1101010011010 changed: 1 0110 step 934 11110111000000010101101010011010 source: 0 1 0 changed: 0 1 0 step 935 11110110000000011100101010011010 source: 1101010100110 changed: 1 1001 step 936 11110110000000011101101010100110 source: 0 0 changed: 0 0 step 937 11110110000000010100101010100110 source: 1110011 changed: 0 1 step 938 11110011000000010100101010100110 source: 1101010010110 changed: 1 01 step 939 11110011000000010101101010010110 source: 0 1 0 changed: 0 1 0 step 940 11110010000000011100101010010110 source: 1101010100101 changed: 1 10 01 step 941 11110010000000011101101010100101 source: 0 0 changed: 0 0 step 942 11110010000000010100101010100101 source: 1110001 changed: 01 step 943 11110001000000010100101010100101 source: 1101010010101 changed: 1 01 step 944 11110001000000010101101010010101 source: 0 1 0 changed: 0 1 0 step 945 11110000000000011100101010010101 source: 1101010100101 changed: 1 10 step 946 11110000000000011101101010100101 source: 0 0 changed: 0 0 step 947 11110000000000010100101010100101 source: 1010001 changed: 0 1 step 948 11010001000000010100101010100101 source: 1100110010101 changed: 1 01 01 step 949 11010001000000010101100110010101 source: 0 1 0 changed: 0 1 0 step 950 11010000000000011100100110010101 source: 1101001100101 changed: 1 100110 step 951 11010000000000011101101001100101 source: 0 0 changed: 0 0 step 952 11010000000000010100101001100101 source: 1010011 changed: 11 step 953 11010011000000010100101001100101 source: 1100110010110 changed: 1 011001 10 step 954 11010011000000010101100110010110 source: 0 1 0 changed: 0 1 0 step 955 11010010000000011100100110010110 source: 1101001100101 changed: 1 100110 01 step 956 11010010000000011101101001100101 source: 0 0 changed: 0 0 step 957 11010010000000010100101001100101 source: 1010111 changed: 1 1 step 958 11010111000000010100101001100101 source: 1100110011010 changed: 1 0110011010 step 959 11010111000000010101100110011010 source: 0 1 0 changed: 0 1 0 step 960 11010110000000011100100110011010 source: 1101001100110 changed: 1 10011001 step 961 11010110000000011101101001100110 source: 0 0 changed: 0 0 step 962 11010110000000010100101001100110 source: 1010101 changed: 01 step 963 11010101000000010100101001100110 source: 1100110011001 changed: 1 0110011001 step 964 11010101000000010101100110011001 source: 0 1 0 changed: 0 1 0 step 965 11010100000000011100100110011001 source: 1101001100110 changed: 1 1001100110 step 966 11010100000000011101101001100110 source: 0 0 changed: 0 0 step 967 11010100000000010100101001100110 source: 1011101 changed: 1 1 step 968 11011101000000010100101001100110 source: 1100110101001 changed: 1 0110 1001 step 969 11011101000000010101100110101001 source: 0 1 0 changed: 0 1 0 step 970 11011100000000011100100110101001 source: 1101001101010 changed: 1 1001 10 step 971 11011100000000011101101001101010 source: 0 0 changed: 0 0 step 972 11011100000000010100101001101010 source: 1011111 changed: 11 step 973 11011111000000010100101001101010 source: 1100110101010 changed: 1 0110 step 974 11011111000000010101100110101010 source: 0 1 0 changed: 0 1 0 step 975 11011110000000011100100110101010 source: 1101001101010 changed: 1 1001 step 976 11011110000000011101101001101010 source: 0 0 changed: 0 0 step 977 11011110000000010100101001101010 source: 1011011 changed: 0 1 step 978 11011011000000010100101001101010 source: 1100110100110 changed: 1 0110 01 step 979 11011011000000010101100110100110 source: 0 1 0 changed: 0 1 0 step 980 11011010000000011100100110100110 source: 1101001101001 changed: 1 1001 1001 step 981 11011010000000011101101001101001 source: 0 0 changed: 0 0 step 982 11011010000000010100101001101001 source: 1011001 changed: 01 step 983 11011001000000010100101001101001 source: 1100110100101 changed: 1 0110 01 step 984 11011001000000010101100110100101 source: 0 1 0 changed: 0 1 0 step 985 11011000000000011100100110100101 source: 1101001101001 changed: 1 1001 10 step 986 11011000000000011101101001101001 source: 0 0 changed: 0 0 step 987 11011000000000010100101001101001 source: 1001001 changed: 0 1 step 988 11001001000000010100101001101001 source: 1100101100101 changed: 1 01 01 step 989 11001001000000010101100101100101 source: 0 1 0 changed: 0 1 0 step 990 11001000000000011100100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 10 10 step 991 11001000000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 992 11001000000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 993 11001011000000010100101001101001 fail ^^ source: 1100101100110 changed: 1 01 0110 step 994 11001011000000010101100101100110 source: 0 1 0 changed: 0 1 0 step 995 11001010000000011100100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011001 changed: 1 10 1001 step 996 11001010000000011101101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 997 11001010000000010100101001101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 998 11001111000000010100101001101001 fail ^^ source: 1100101101010 changed: 1 01 10 step 999 11001111000000010101100101101010 source: 0 1 0 changed: 0 1 0 step 1000 11001110000000011100100101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 step 1001 11001110000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1002 11001110000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001101 changed: 01 step 1003 11001101000000010100101001101010 fail ^^ source: 1100101101001 changed: 1 01 01 step 1004 11001101000000010101100101101001 source: 0 1 0 changed: 0 1 0 step 1005 11001100000000011100100101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001011010 changed: 1 10 10 step 1006 11001100000000011101101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 1007 11001100000000010100101001101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1000101 changed: 0 1 step 1008 11000101000000010100101001101010 fail ^^ source: 1100101011001 changed: 1 01 01 01 step 1009 11000101000000010101100101011001 source: 0 1 0 changed: 0 1 0 step 1010 11000100000000011100100101011001 source: 1101001010110 changed: 1 10 0110 step 1011 11000100000000011101101001010110 source: 0 0 changed: 0 0 step 1012 11000100000000010100101001010110 source: 1000111 changed: 11 step 1013 11000111000000010100101001010110 source: 1100101011010 changed: 1 01 10 step 1014 11000111000000010101100101011010 source: 0 1 0 changed: 0 1 0 step 1015 11000110000000011100100101011010 source: 1101001010110 changed: 1 10 01 step 1016 11000110000000011101101001010110 source: 0 0 changed: 0 0 step 1017 11000110000000010100101001010110 source: 1000011 changed: 0 1 step 1018 11000011000000010100101001010110 source: 1100101010110 changed: 1 01 step 1019 11000011000000010101100101010110 source: 0 1 0 changed: 0 1 0 step 1020 11000010000000011100100101010110 source: 1101001010101 changed: 1 10 01 step 1021 11000010000000011101101001010101 source: 0 0 changed: 0 0 step 1022 11000010000000010100101001010101 source: 1000001 changed: 01 step 1023 11000001000000010100101001010101 source: 1100101010101 changed: 1 01 step 1024 11000001000000010101100101010101 source: 0 1 0 changed: 0 1 0 step 1025 11000000000000011100100101010101 source: 1101001010101 changed: 1 10 step 1026 11000000000000011101101001010101 source: 0 0 changed: 0 0 step 1027 11000000000000010100101001010101 source: 0000001 changed: 0 1 step 1028 10000001000000010100101001010101 source: 1010101010101 changed: 10101 step 1029 10000001000000010101010101010101 source: 0 1 0 changed: 0 1 0 step 1030 10000000000000011100010101010101 source: 1100101010101 changed: 110 step 1031 10000000000000011101100101010101 source: 0 0 changed: 0 0 step 1032 10000000000000010100100101010101 source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 1033 10000000000000010000100101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 11 step 1034 10000011000000010000100101010101 source: 1010101010110 changed: 101 10 step 1035 10000011000000010001010101010110 source: 0 10 changed: 0 10 step 1036 10000010000000010010010101010110 source: 1010101011001 changed: 1 1001 step 1037 10000010000000010011010101011001 source: 00 changed: 00 step 1038 10000010000000010000010101011001 source: 0000111 changed: 1 1 step 1039 10000111000000010000010101011001 source: 1010101011010 changed: 1 10 step 1040 10000111000000010001010101011010 source: 0 10 changed: 0 10 step 1041 10000110000000010010010101011010 source: 1010101101001 changed: 1 10 01 step 1042 10000110000000010011010101101001 source: 00 changed: 00 step 1043 10000110000000010000010101101001 source: 0000101 changed: 01 step 1044 10000101000000010000010101101001 source: 1010101011001 changed: 1 01 step 1045 10000101000000010001010101011001 source: 0 10 changed: 0 10 step 1046 10000100000000010010010101011001 source: 1010101100101 changed: 1 1001 step 1047 10000100000000010011010101100101 source: 00 changed: 00 step 1048 10000100000000010000010101100101 source: 0001101 changed: 1 1 step 1049 10001101000000010000010101100101 source: 1010101101001 changed: 1 10 step 1050 10001101000000010001010101101001 source: 0 10 changed: 0 10 step 1051 10001100000000010010010101101001 source: 1010110100101 changed: 1 10 01 step 1052 10001100000000010011010110100101 source: 00 changed: 00 step 1053 10001100000000010000010110100101 source: 0001111 changed: 11 step 1054 10001111000000010000010110100101 source: 1010101101010 changed: 1 01 1010 step 1055 10001111000000010001010101101010 source: 0 10 changed: 0 10 step 1056 10001110000000010010010101101010 source: 1010110101001 changed: 1 10 01 step 1057 10001110000000010011010110101001 source: 00 changed: 00 step 1058 10001110000000010000010110101001 source: 0001011 changed: 0 1 step 1059 10001011000000010000010110101001 source: 1010101100110 changed: 1 01 0110 step 1060 10001011000000010001010101100110 source: 0 10 changed: 0 10 step 1061 10001010000000010010010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 1 10 1001 step 1062 10001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1063 10001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 1064 10001001000000010000010110101001 fail ^^ source: 1010101100101 changed: 1 01 01 step 1065 10001001000000010001010101100101 source: 0 10 changed: 0 10 step 1066 10001000000000010010010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 1 10 step 1067 10001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1068 10001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 1069 10011001000000010000010110100101 fail ^^ source: 1010110100101 changed: 1 step 1070 10011001000000010001010110100101 source: 0 10 changed: 0 10 step 1071 10011000000000010010010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 1 10 step 1072 10011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1073 10011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 1074 10011011000000010000011010100101 fail ^^ source: 1010110100110 changed: 1 01 10 step 1075 10011011000000010001010110100110 source: 0 10 changed: 0 10 step 1076 10011010000000010010010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 1 10 1001 step 1077 10011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1078 10011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 1079 10011111000000010000011010101001 fail ^^ source: 1010110101010 changed: 1 01 10 step 1080 10011111000000010001010110101010 source: 0 10 changed: 0 10 step 1081 10011110000000010010010110101010 source: 1011010101001 changed: 1 10 01 step 1082 10011110000000010011011010101001 source: 00 changed: 00 step 1083 10011110000000010000011010101001 source: 0011101 changed: 01 step 1084 10011101000000010000011010101001 source: 1010110101001 changed: 1 01 step 1085 10011101000000010001010110101001 source: 0 10 changed: 0 10 step 1086 10011100000000010010010110101001 source: 1011010100101 changed: 1 10 01 step 1087 10011100000000010011011010100101 source: 00 changed: 00 step 1088 10011100000000010000011010100101 source: 0010101 changed: 0 1 step 1089 10010101000000010000011010100101 source: 1010110011001 changed: 1 01 0110 step 1090 10010101000000010001010110011001 source: 0 10 changed: 0 10 step 1091 10010100000000010010010110011001 source: 1011001100101 changed: 1 10011001 step 1092 10010100000000010011011001100101 source: 00 changed: 00 step 1093 10010100000000010000011001100101 source: 0010111 changed: 11 step 1094 10010111000000010000011001100101 source: 1010110011010 changed: 1 0110011010 step 1095 10010111000000010001010110011010 source: 0 10 changed: 0 10 step 1096 10010110000000010010010110011010 source: 1011001101001 changed: 1 100110 01 step 1097 10010110000000010011011001101001 source: 00 changed: 00 step 1098 10010110000000010000011001101001 source: 0010011 changed: 0 1 step 1099 10010011000000010000011001101001 source: 1010110010110 changed: 1 0110010110 step 1100 10010011000000010001010110010110 source: 0 10 changed: 0 10 step 1101 10010010000000010010010110010110 source: 1011001011001 changed: 1 1001 1001 step 1102 10010010000000010011011001011001 source: 00 changed: 00 step 1103 10010010000000010000011001011001 source: 0010001 changed: 01 step 1104 10010001000000010000011001011001 source: 1010110010101 changed: 1 0110 01 step 1105 10010001000000010001010110010101 source: 0 10 changed: 0 10 step 1106 10010000000000010010010110010101 source: 1011001010101 changed: 1 1001 step 1107 10010000000000010011011001010101 source: 00 changed: 00 step 1108 10010000000000010000011001010101 source: 0110001 changed: 1 1 step 1109 10110001000000010000011001010101 source: 1011010010101 changed: 1 10 step 1110 10110001000000010001011010010101 source: 0 10 changed: 0 10 step 1111 10110000000000010010011010010101 source: 1101001010101 changed: 110 01 step 1112 10110000000000010011101001010101 source: 00 changed: 00 step 1113 10110000000000010000101001010101 source: 0110011 changed: 11 step 1114 10110011000000010000101001010101 source: 1011010010110 changed: 101 10 10 step 1115 10110011000000010001011010010110 source: 0 10 changed: 0 10 step 1116 10110010000000010010011010010110 source: 1101001011001 changed: 110 01 1001 step 1117 10110010000000010011101001011001 source: 00 changed: 00 step 1118 10110010000000010000101001011001 source: 0110111 changed: 1 1 step 1119 10110111000000010000101001011001 source: 1011010011010 changed: 101 10 10 step 1120 10110111000000010001011010011010 source: 0 10 changed: 0 10 step 1121 10110110000000010010011010011010 source: 1101001101001 changed: 110 0110 01 step 1122 10110110000000010011101001101001 source: 00 changed: 00 step 1123 10110110000000010000101001101001 source: 0110101 changed: 01 step 1124 10110101000000010000101001101001 source: 1011010011001 changed: 101 1001 step 1125 10110101000000010001011010011001 source: 0 10 changed: 0 10 step 1126 10110100000000010010011010011001 source: 1101001100101 changed: 110 011001 step 1127 10110100000000010011101001100101 source: 00 changed: 00 step 1128 10110100000000010000101001100101 source: 0111101 changed: 1 1 step 1129 10111101000000010000101001100101 source: 1011010101001 changed: 101 10 10 step 1130 10111101000000010001011010101001 source: 0 10 changed: 0 10 step 1131 10111100000000010010011010101001 source: 1101010100101 changed: 110 01 step 1132 10111100000000010011101010100101 source: 00 changed: 00 step 1133 10111100000000010000101010100101 source: 0111111 changed: 11 step 1134 10111111000000010000101010100101 source: 1011010101010 changed: 101 1010 step 1135 10111111000000010001011010101010 source: 0 10 changed: 0 10 step 1136 10111110000000010010011010101010 source: 1101010101001 changed: 110 01 step 1137 10111110000000010011101010101001 source: 00 changed: 00 step 1138 10111110000000010000101010101001 source: 0111011 changed: 0 1 step 1139 10111011000000010000101010101001 source: 1011010100110 changed: 101 0110 step 1140 10111011000000010001011010100110 source: 0 10 changed: 0 10 step 1141 10111010000000010010011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 110 1001 step 1142 10111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1143 10111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 1144 10111001000000010000101010101001 fail ^^ source: 1011010100101 changed: 101 01 step 1145 10111001000000010001011010100101 source: 0 10 changed: 0 10 step 1146 10111000000000010010011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 110 step 1147 10111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1148 10111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 1149 10101001000000010000101010100101 fail ^^ source: 1011001100101 changed: 101 01 step 1150 10101001000000010001011001100101 source: 0 10 changed: 0 10 step 1151 10101000000000010010011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1100110 step 1152 10101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1153 10101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 1154 10101011000000010000100110100101 fail ^^ source: 1011001100110 changed: 1011001 10 step 1155 10101011000000010001011001100110 source: 0 10 changed: 0 10 step 1156 10101010000000010010011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1100110 1001 step 1157 10101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1158 10101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 1159 10101111000000010000100110101001 fail ^^ source: 1011001101010 changed: 1011001 10 step 1160 10101111000000010001011001101010 source: 0 10 changed: 0 10 step 1161 10101110000000010010011001101010 source: 1100110101001 changed: 1100110 01 step 1162 10101110000000010011100110101001 source: 00 changed: 00 step 1163 10101110000000010000100110101001 source: 0101101 changed: 01 step 1164 10101101000000010000100110101001 source: 1011001101001 changed: 1011001 step 1165 10101101000000010001011001101001 source: 0 10 changed: 0 10 step 1166 10101100000000010010011001101001 source: 1100110100101 changed: 1100110 01 step 1167 10101100000000010011100110100101 source: 00 changed: 00 step 1168 10101100000000010000100110100101 source: 0100101 changed: 0 1 step 1169 10100101000000010000100110100101 source: 1011001011001 changed: 10110010110 step 1170 10100101000000010001011001011001 source: 0 10 changed: 0 10 step 1171 10100100000000010010011001011001 source: 1100101100101 changed: 11001 1001 step 1172 10100100000000010011100101100101 source: 00 changed: 00 step 1173 10100100000000010000100101100101 source: 0100111 changed: 11 step 1174 10100111000000010000100101100101 source: 1011001011010 changed: 10110 011010 step 1175 10100111000000010001011001011010 source: 0 10 changed: 0 10 step 1176 10100110000000010010011001011010 source: 1100101101001 changed: 11001 10 01 step 1177 10100110000000010011100101101001 source: 00 changed: 00 step 1178 10100110000000010000100101101001 source: 0100011 changed: 0 1 step 1179 10100011000000010000100101101001 source: 1011001010110 changed: 10110 010110 step 1180 10100011000000010001011001010110 source: 0 10 changed: 0 10 step 1181 10100010000000010010011001010110 source: 1100101011001 changed: 11001 1001 step 1182 10100010000000010011100101011001 source: 00 changed: 00 step 1183 10100010000000010000100101011001 source: 0100001 changed: 01 step 1184 10100001000000010000100101011001 source: 1011001010101 changed: 10110 01 step 1185 10100001000000010001011001010101 source: 0 10 changed: 0 10 step 1186 10100000000000010010011001010101 source: 1100101010101 changed: 11001 step 1187 10100000000000010011100101010101 source: 00 changed: 00 step 1188 10100000000000010000100101010101 source: 1100001 changed: 1 1 step 1189 11100001000000010000100101010101 source: 1101001010101 changed: 1 10 step 1190 11100001000000010001101001010101 source: 0 10 changed: 0 10 step 1191 11100000000000010010101001010101 source: 1100101010101 changed: 1 01 step 1192 11100000000000010011100101010101 source: 00 changed: 00 step 1193 11100000000000010000100101010101 source: 1100011 changed: 11 step 1194 11100011000000010000100101010101 source: 1101001010110 changed: 1 10 10 step 1195 11100011000000010001101001010110 source: 0 10 changed: 0 10 step 1196 11100010000000010010101001010110 source: 1100101011001 changed: 1 01 1001 step 1197 11100010000000010011100101011001 source: 00 changed: 00 step 1198 11100010000000010000100101011001 source: 1100111 changed: 1 1 step 1199 11100111000000010000100101011001 source: 1101001011010 changed: 1 10 10 step 1200 11100111000000010001101001011010 source: 0 10 changed: 0 10 step 1201 11100110000000010010101001011010 source: 1100101101001 changed: 1 01 10 01 step 1202 11100110000000010011100101101001 source: 00 changed: 00 step 1203 11100110000000010000100101101001 source: 1100101 changed: 01 step 1204 11100101000000010000100101101001 source: 1101001011001 changed: 1 10 01 step 1205 11100101000000010001101001011001 source: 0 10 changed: 0 10 step 1206 11100100000000010010101001011001 source: 1100101100101 changed: 1 01 1001 step 1207 11100100000000010011100101100101 source: 00 changed: 00 step 1208 11100100000000010000100101100101 source: 1101101 changed: 1 1 step 1209 11101101000000010000100101100101 source: 1101001101001 changed: 1 10 10 step 1210 11101101000000010001101001101001 source: 0 10 changed: 0 10 step 1211 11101100000000010010101001101001 source: 1100110100101 changed: 1 0110 01 step 1212 11101100000000010011100110100101 source: 00 changed: 00 step 1213 11101100000000010000100110100101 source: 1101111 changed: 11 step 1214 11101111000000010000100110100101 source: 1101001101010 changed: 1 1001 1010 step 1215 11101111000000010001101001101010 source: 0 10 changed: 0 10 step 1216 11101110000000010010101001101010 source: 1100110101001 changed: 1 0110 01 step 1217 11101110000000010011100110101001 source: 00 changed: 00 step 1218 11101110000000010000100110101001 source: 1101011 changed: 0 1 step 1219 11101011000000010000100110101001 source: 1101001100110 changed: 1 1001 0110 step 1220 11101011000000010001101001100110 source: 0 10 changed: 0 10 step 1221 11101010000000010010101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011001 changed: 1 0110 1001 step 1222 11101010000000010011100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1223 11101010000000010000100110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 1224 11101001000000010000100110101001 fail ^^ source: 1101001100101 changed: 1 1001 01 step 1225 11101001000000010001101001100101 source: 0 10 changed: 0 10 step 1226 11101000000000010010101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010101 changed: 1 0110 step 1227 11101000000000010011100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1228 11101000000000010000100110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 1229 11111001000000010000100110100101 fail ^^ source: 1101010100101 changed: 1 10 step 1230 11111001000000010001101010100101 source: 0 10 changed: 0 10 step 1231 11111000000000010010101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010101 changed: 1 step 1232 11111000000000010011101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1233 11111000000000010000101010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 1234 11111011000000010000101010100101 fail ^^ source: 1101010100110 changed: 1 10 step 1235 11111011000000010001101010100110 source: 0 10 changed: 0 10 step 1236 11111010000000010010101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011001 changed: 1 1001 step 1237 11111010000000010011101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1238 11111010000000010000101010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 1239 11111111000000010000101010101001 fail ^^ source: 1101010101010 changed: 1 10 step 1240 11111111000000010001101010101010 source: 0 10 changed: 0 10 step 1241 11111110000000010010101010101010 source: 1101010101001 changed: 1 01 step 1242 11111110000000010011101010101001 source: 00 changed: 00 step 1243 11111110000000010000101010101001 source: 1111101 changed: 01 step 1244 11111101000000010000101010101001 source: 1101010101001 changed: 1 step 1245 11111101000000010001101010101001 source: 0 10 changed: 0 10 step 1246 11111100000000010010101010101001 source: 1101010100101 changed: 1 01 step 1247 11111100000000010011101010100101 source: 00 changed: 00 step 1248 11111100000000010000101010100101 source: 1110101 changed: 0 1 step 1249 11110101000000010000101010100101 source: 1101010011001 changed: 1 0110 step 1250 11110101000000010001101010011001 source: 0 10 changed: 0 10 step 1251 11110100000000010010101010011001 source: 1101001100101 changed: 1 011001 step 1252 11110100000000010011101001100101 source: 00 changed: 00 step 1253 11110100000000010000101001100101 source: 1110111 changed: 11 step 1254 11110111000000010000101001100101 source: 1101010011010 changed: 1 10011010 step 1255 11110111000000010001101010011010 source: 0 10 changed: 0 10 step 1256 11110110000000010010101010011010 source: 1101001101001 changed: 1 0110 01 step 1257 11110110000000010011101001101001 source: 00 changed: 00 step 1258 11110110000000010000101001101001 source: 1110011 changed: 0 1 step 1259 11110011000000010000101001101001 source: 1101010010110 changed: 1 10010110 step 1260 11110011000000010001101010010110 source: 0 10 changed: 0 10 step 1261 11110010000000010010101010010110 source: 1101001011001 changed: 1 01 1001 step 1262 11110010000000010011101001011001 source: 00 changed: 00 step 1263 11110010000000010000101001011001 source: 1110001 changed: 01 step 1264 11110001000000010000101001011001 source: 1101010010101 changed: 1 10 01 step 1265 11110001000000010001101010010101 source: 0 10 changed: 0 10 step 1266 11110000000000010010101010010101 source: 1101001010101 changed: 1 01 step 1267 11110000000000010011101001010101 source: 00 changed: 00 step 1268 11110000000000010000101001010101 source: 1010001 changed: 0 1 step 1269 11010001000000010000101001010101 source: 1100110010101 changed: 1 0110 step 1270 11010001000000010001100110010101 source: 0 10 changed: 0 10 step 1271 11010000000000010010100110010101 source: 1011001010101 changed: 1011001 step 1272 11010000000000010011011001010101 source: 00 changed: 00 step 1273 11010000000000010000011001010101 source: 1010011 changed: 11 step 1274 11010011000000010000011001010101 source: 1100110010110 changed: 1100110 10 step 1275 11010011000000010001100110010110 source: 0 10 changed: 0 10 step 1276 11010010000000010010100110010110 source: 1011001011001 changed: 1011001 1001 step 1277 11010010000000010011011001011001 source: 00 changed: 00 step 1278 11010010000000010000011001011001 source: 1010111 changed: 1 1 step 1279 11010111000000010000011001011001 source: 1100110011010 changed: 1100110 10 step 1280 11010111000000010001100110011010 source: 0 10 changed: 0 10 step 1281 11010110000000010010100110011010 source: 1011001101001 changed: 101100110 01 step 1282 11010110000000010011011001101001 source: 00 changed: 00 step 1283 11010110000000010000011001101001 source: 1010101 changed: 01 step 1284 11010101000000010000011001101001 source: 1100110011001 changed: 110011001 step 1285 11010101000000010001100110011001 source: 0 10 changed: 0 10 step 1286 11010100000000010010100110011001 source: 1011001100101 changed: 10110011001 step 1287 11010100000000010011011001100101 source: 00 changed: 00 step 1288 11010100000000010000011001100101 source: 1011101 changed: 1 1 step 1289 11011101000000010000011001100101 source: 1100110101001 changed: 1100110 10 step 1290 11011101000000010001100110101001 source: 0 10 changed: 0 10 step 1291 11011100000000010010100110101001 source: 1011010100101 changed: 10110 01 step 1292 11011100000000010011011010100101 source: 00 changed: 00 step 1293 11011100000000010000011010100101 source: 1011111 changed: 11 step 1294 11011111000000010000011010100101 source: 1100110101010 changed: 11001 1010 step 1295 11011111000000010001100110101010 source: 0 10 changed: 0 10 step 1296 11011110000000010010100110101010 source: 1011010101001 changed: 10110 01 step 1297 11011110000000010011011010101001 source: 00 changed: 00 step 1298 11011110000000010000011010101001 source: 1011011 changed: 0 1 step 1299 11011011000000010000011010101001 source: 1100110100110 changed: 11001 0110 step 1300 11011011000000010001100110100110 source: 0 10 changed: 0 10 step 1301 11011010000000010010100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011001 changed: 10110 1001 step 1302 11011010000000010011011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1303 11011010000000010000011010101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 1304 11011001000000010000011010101001 fail ^^ source: 1100110100101 changed: 11001 01 step 1305 11011001000000010001100110100101 source: 0 10 changed: 0 10 step 1306 11011000000000010010100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010101 changed: 10110 step 1307 11011000000000010011011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1308 11011000000000010000011010100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 1309 11001001000000010000011010100101 fail ^^ source: 1100101100101 changed: 1100101 step 1310 11001001000000010001100101100101 source: 0 10 changed: 0 10 step 1311 11001000000000010010100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010101 changed: 101 10 step 1312 11001000000000010011010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1313 11001000000000010000010110100101 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 1314 11001011000000010000010110100101 fail ^^ source: 1100101100110 changed: 110 01 10 step 1315 11001011000000010001100101100110 source: 0 10 changed: 0 10 step 1316 11001010000000010010100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011001 changed: 101 10 1001 step 1317 11001010000000010011010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1318 11001010000000010000010110101001 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 1319 11001111000000010000010110101001 fail ^^ source: 1100101101010 changed: 110 01 10 step 1320 11001111000000010001100101101010 source: 0 10 changed: 0 10 step 1321 11001110000000010010100101101010 source: 1010110101001 changed: 101 10 01 step 1322 11001110000000010011010110101001 source: 00 changed: 00 step 1323 11001110000000010000010110101001 source: 1001101 changed: 01 step 1324 11001101000000010000010110101001 source: 1100101101001 changed: 110 01 step 1325 11001101000000010001100101101001 source: 0 10 changed: 0 10 step 1326 11001100000000010010100101101001 source: 1010110100101 changed: 101 10 01 step 1327 11001100000000010011010110100101 source: 00 changed: 00 step 1328 11001100000000010000010110100101 source: 1000101 changed: 0 1 step 1329 11000101000000010000010110100101 source: 1100101011001 changed: 110 010110 step 1330 11000101000000010001100101011001 source: 0 10 changed: 0 10 step 1331 11000100000000010010100101011001 source: 1010101100101 changed: 101 1001 step 1332 11000100000000010011010101100101 source: 00 changed: 00 step 1333 11000100000000010000010101100101 source: 1000111 changed: 11 step 1334 11000111000000010000010101100101 source: 1100101011010 changed: 110 011010 step 1335 11000111000000010001100101011010 source: 0 10 changed: 0 10 step 1336 11000110000000010010100101011010 source: 1010101101001 changed: 101 10 01 step 1337 11000110000000010011010101101001 source: 00 changed: 00 step 1338 11000110000000010000010101101001 source: 1000011 changed: 0 1 step 1339 11000011000000010000010101101001 source: 1100101010110 changed: 110 010110 step 1340 11000011000000010001100101010110 source: 0 10 changed: 0 10 step 1341 11000010000000010010100101010110 source: 1010101011001 changed: 101 1001 step 1342 11000010000000010011010101011001 source: 00 changed: 00 step 1343 11000010000000010000010101011001 source: 1000001 changed: 01 step 1344 11000001000000010000010101011001 source: 1100101010101 changed: 110 01 step 1345 11000001000000010001100101010101 source: 0 10 changed: 0 10 step 1346 11000000000000010010100101010101 source: 1010101010101 changed: 101 step 1347 11000000000000010011010101010101 source: 00 changed: 00 step 1348 11000000000000010000010101010101 source: 0000001 changed: 0 1 step 1349 10000001000000010000010101010101 source: 1010101010101 changed: 1 step 1350 10000001000000010001010101010101 source: 0 10 changed: 0 10 step 1351 10000000000000010010010101010101 source: 1010101010101 changed: 1 step 1352 10000000000000010011010101010101 source: 00 changed: 00 step 1353 10000000000000010000010101010101 source: source: source: ; TEST SHIFT L (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ONE source: 1 changed: 1 step 1354 10000000000000010100010101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT source: 0000011 changed: 11 step 1355 10000011000000010100010101010101 source: 1010101010110 changed: 1 10 step 1356 10000011000000010101010101010110 source: 0 10 changed: 0 10 step 1357 10000010000000010110010101010110 source: 1010101011010 changed: 1 10 step 1358 10000010000000010111010101011010 source: 00 changed: 00 step 1359 10000010000000010100010101011010 source: 0000111 changed: 1 1 step 1360 10000111000000010100010101011010 source: 1010101011010 changed: 1 step 1361 10000111000000010101010101011010 source: 0 10 changed: 0 10 step 1362 10000110000000010110010101011010 source: 1010101101010 changed: 1 10 step 1363 10000110000000010111010101101010 source: 00 changed: 00 step 1364 10000110000000010100010101101010 source: 0000101 changed: 01 step 1365 10000101000000010100010101101010 source: 1010101011001 changed: 1 01 01 step 1366 10000101000000010101010101011001 source: 0 10 changed: 0 10 step 1367 10000100000000010110010101011001 source: 1010101100110 changed: 1 100110 step 1368 10000100000000010111010101100110 source: 00 changed: 00 step 1369 10000100000000010100010101100110 source: 0001101 changed: 1 1 step 1370 10001101000000010100010101100110 source: 1010101101001 changed: 1 1001 step 1371 10001101000000010101010101101001 source: 0 10 changed: 0 10 step 1372 10001100000000010110010101101001 source: 1010110100110 changed: 1 10 0110 step 1373 10001100000000010111010110100110 source: 00 changed: 00 step 1374 10001100000000010100010110100110 source: 0001111 changed: 11 step 1375 10001111000000010100010110100110 source: 1010101101010 changed: 1 01 10 step 1376 10001111000000010101010101101010 source: 0 10 changed: 0 10 step 1377 10001110000000010110010101101010 source: 1010110101010 changed: 1 10 step 1378 10001110000000010111010110101010 source: 00 changed: 00 step 1379 10001110000000010100010110101010 source: 0001011 changed: 0 1 step 1380 10001011000000010100010110101010 source: 1010101100110 changed: 1 01 01 step 1381 10001011000000010101010101100110 source: 0 10 changed: 0 10 step 1382 10001010000000010110010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 1 10 10 step 1383 10001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1384 10001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0001001 changed: 01 step 1385 10001001000000010100010110101010 fail ^^ source: 1010101100101 changed: 1 01 0101 step 1386 10001001000000010101010101100101 source: 0 10 changed: 0 10 step 1387 10001000000000010110010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 1 10 10 step 1388 10001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1389 10001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011001 changed: 1 1 step 1390 10011001000000010100010110100110 fail ^^ source: 1010110100101 changed: 1 01 step 1391 10011001000000010101010110100101 source: 0 10 changed: 0 10 step 1392 10011000000000010110010110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 1 10 10 step 1393 10011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1394 10011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011011 changed: 11 step 1395 10011011000000010100011010100110 fail ^^ source: 1010110100110 changed: 1 01 step 1396 10011011000000010101010110100110 source: 0 10 changed: 0 10 step 1397 10011010000000010110010110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 1 10 10 step 1398 10011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1399 10011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0011111 changed: 1 1 step 1400 10011111000000010100011010101010 fail ^^ source: 1010110101010 changed: 1 01 step 1401 10011111000000010101010110101010 source: 0 10 changed: 0 10 step 1402 10011110000000010110010110101010 source: 1011010101010 changed: 1 10 step 1403 10011110000000010111011010101010 source: 00 changed: 00 step 1404 10011110000000010100011010101010 source: 0011101 changed: 01 step 1405 10011101000000010100011010101010 source: 1010110101001 changed: 1 01 01 step 1406 10011101000000010101010110101001 source: 0 10 changed: 0 10 step 1407 10011100000000010110010110101001 source: 1011010100110 changed: 1 10 0110 step 1408 10011100000000010111011010100110 source: 00 changed: 00 step 1409 10011100000000010100011010100110 source: 0010101 changed: 0 1 step 1410 10010101000000010100011010100110 source: 1010110011001 changed: 1 01 011001 step 1411 10010101000000010101010110011001 source: 0 10 changed: 0 10 step 1412 10010100000000010110010110011001 source: 1011001100110 changed: 1 1001100110 step 1413 10010100000000010111011001100110 source: 00 changed: 00 step 1414 10010100000000010100011001100110 source: 0010111 changed: 11 step 1415 10010111000000010100011001100110 source: 1010110011010 changed: 1 01100110 step 1416 10010111000000010101010110011010 source: 0 10 changed: 0 10 step 1417 10010110000000010110010110011010 source: 1011001101010 changed: 1 100110 step 1418 10010110000000010111011001101010 source: 00 changed: 00 step 1419 10010110000000010100011001101010 source: 0010011 changed: 0 1 step 1420 10010011000000010100011001101010 source: 1010110010110 changed: 1 01100101 step 1421 10010011000000010101010110010110 source: 0 10 changed: 0 10 step 1422 10010010000000010110010110010110 source: 1011001011010 changed: 1 1001 10 step 1423 10010010000000010111011001011010 source: 00 changed: 00 step 1424 10010010000000010100011001011010 source: 0010001 changed: 01 step 1425 10010001000000010100011001011010 source: 1010110010101 changed: 1 0110 0101 step 1426 10010001000000010101010110010101 source: 0 10 changed: 0 10 step 1427 10010000000000010110010110010101 source: 1011001010110 changed: 1 1001 10 step 1428 10010000000000010111011001010110 source: 00 changed: 00 step 1429 10010000000000010100011001010110 source: 0110001 changed: 1 1 step 1430 10110001000000010100011001010110 source: 1011010010101 changed: 1 10 01 step 1431 10110001000000010101011010010101 source: 0 10 changed: 0 10 step 1432 10110000000000010110011010010101 source: 1101001010110 changed: 110 01 10 step 1433 10110000000000010111101001010110 source: 00 changed: 00 step 1434 10110000000000010100101001010110 source: 0110011 changed: 11 step 1435 10110011000000010100101001010110 source: 1011010010110 changed: 101 10 step 1436 10110011000000010101011010010110 source: 0 10 changed: 0 10 step 1437 10110010000000010110011010010110 source: 1101001011010 changed: 110 01 10 step 1438 10110010000000010111101001011010 source: 00 changed: 00 step 1439 10110010000000010100101001011010 source: 0110111 changed: 1 1 step 1440 10110111000000010100101001011010 source: 1011010011010 changed: 101 10 step 1441 10110111000000010101011010011010 source: 0 10 changed: 0 10 step 1442 10110110000000010110011010011010 source: 1101001101010 changed: 110 0110 step 1443 10110110000000010111101001101010 source: 00 changed: 00 step 1444 10110110000000010100101001101010 source: 0110101 changed: 01 step 1445 10110101000000010100101001101010 source: 1011010011001 changed: 101 1001 01 step 1446 10110101000000010101011010011001 source: 0 10 changed: 0 10 step 1447 10110100000000010110011010011001 source: 1101001100110 changed: 110 01100110 step 1448 10110100000000010111101001100110 source: 00 changed: 00 step 1449 10110100000000010100101001100110 source: 0111101 changed: 1 1 step 1450 10111101000000010100101001100110 source: 1011010101001 changed: 101 10 1001 step 1451 10111101000000010101011010101001 source: 0 10 changed: 0 10 step 1452 10111100000000010110011010101001 source: 1101010100110 changed: 110 0110 step 1453 10111100000000010111101010100110 source: 00 changed: 00 step 1454 10111100000000010100101010100110 source: 0111111 changed: 11 step 1455 10111111000000010100101010100110 source: 1011010101010 changed: 101 10 step 1456 10111111000000010101011010101010 source: 0 10 changed: 0 10 step 1457 10111110000000010110011010101010 source: 1101010101010 changed: 110 step 1458 10111110000000010111101010101010 source: 00 changed: 00 step 1459 10111110000000010100101010101010 source: 0111011 changed: 0 1 step 1460 10111011000000010100101010101010 source: 1011010100110 changed: 101 01 step 1461 10111011000000010101011010100110 source: 0 10 changed: 0 10 step 1462 10111010000000010110011010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 110 10 step 1463 10111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1464 10111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0111001 changed: 01 step 1465 10111001000000010100101010101010 fail ^^ source: 1011010100101 changed: 101 0101 step 1466 10111001000000010101011010100101 source: 0 10 changed: 0 10 step 1467 10111000000000010110011010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 110 10 step 1468 10111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1469 10111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101001 changed: 0 1 step 1470 10101001000000010100101010100110 fail ^^ source: 1011001100101 changed: 101 01 01 step 1471 10101001000000010101011001100101 source: 0 10 changed: 0 10 step 1472 10101000000000010110011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1100110 10 step 1473 10101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1474 10101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101011 changed: 11 step 1475 10101011000000010100100110100110 fail ^^ source: 1011001100110 changed: 1011001 step 1476 10101011000000010101011001100110 source: 0 10 changed: 0 10 step 1477 10101010000000010110011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1100110 10 step 1478 10101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1479 10101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0101111 changed: 1 1 step 1480 10101111000000010100100110101010 fail ^^ source: 1011001101010 changed: 1011001 step 1481 10101111000000010101011001101010 source: 0 10 changed: 0 10 step 1482 10101110000000010110011001101010 source: 1100110101010 changed: 1100110 step 1483 10101110000000010111100110101010 source: 00 changed: 00 step 1484 10101110000000010100100110101010 source: 0101101 changed: 01 step 1485 10101101000000010100100110101010 source: 1011001101001 changed: 1011001 01 step 1486 10101101000000010101011001101001 source: 0 10 changed: 0 10 step 1487 10101100000000010110011001101001 source: 1100110100110 changed: 1100110 0110 step 1488 10101100000000010111100110100110 source: 00 changed: 00 step 1489 10101100000000010100100110100110 source: 0100101 changed: 0 1 step 1490 10100101000000010100100110100110 source: 1011001011001 changed: 1011001011001 step 1491 10100101000000010101011001011001 source: 0 10 changed: 0 10 step 1492 10100100000000010110011001011001 source: 1100101100110 changed: 11001 100110 step 1493 10100100000000010111100101100110 source: 00 changed: 00 step 1494 10100100000000010100100101100110 source: 0100111 changed: 11 step 1495 10100111000000010100100101100110 source: 1011001011010 changed: 10110 0110 step 1496 10100111000000010101011001011010 source: 0 10 changed: 0 10 step 1497 10100110000000010110011001011010 source: 1100101101010 changed: 11001 10 step 1498 10100110000000010111100101101010 source: 00 changed: 00 step 1499 10100110000000010100100101101010 source: 0100011 changed: 0 1 step 1500 10100011000000010100100101101010 source: 1011001010110 changed: 10110 0101 step 1501 10100011000000010101011001010110 source: 0 10 changed: 0 10 step 1502 10100010000000010110011001010110 source: 1100101011010 changed: 11001 10 step 1503 10100010000000010111100101011010 source: 00 changed: 00 step 1504 10100010000000010100100101011010 source: 0100001 changed: 01 step 1505 10100001000000010100100101011010 source: 1011001010101 changed: 10110 0101 step 1506 10100001000000010101011001010101 source: 0 10 changed: 0 10 step 1507 10100000000000010110011001010101 source: 1100101010110 changed: 11001 10 step 1508 10100000000000010111100101010110 source: 00 changed: 00 step 1509 10100000000000010100100101010110 source: 1100001 changed: 1 1 step 1510 11100001000000010100100101010110 source: 1101001010101 changed: 1 10 01 step 1511 11100001000000010101101001010101 source: 0 10 changed: 0 10 step 1512 11100000000000010110101001010101 source: 1100101010110 changed: 1 01 10 step 1513 11100000000000010111100101010110 source: 00 changed: 00 step 1514 11100000000000010100100101010110 source: 1100011 changed: 11 step 1515 11100011000000010100100101010110 source: 1101001010110 changed: 1 10 step 1516 11100011000000010101101001010110 source: 0 10 changed: 0 10 step 1517 11100010000000010110101001010110 source: 1100101011010 changed: 1 01 10 step 1518 11100010000000010111100101011010 source: 00 changed: 00 step 1519 11100010000000010100100101011010 source: 1100111 changed: 1 1 step 1520 11100111000000010100100101011010 source: 1101001011010 changed: 1 10 step 1521 11100111000000010101101001011010 source: 0 10 changed: 0 10 step 1522 11100110000000010110101001011010 source: 1100101101010 changed: 1 01 10 step 1523 11100110000000010111100101101010 source: 00 changed: 00 step 1524 11100110000000010100100101101010 source: 1100101 changed: 01 step 1525 11100101000000010100100101101010 source: 1101001011001 changed: 1 10 01 01 step 1526 11100101000000010101101001011001 source: 0 10 changed: 0 10 step 1527 11100100000000010110101001011001 source: 1100101100110 changed: 1 01 100110 step 1528 11100100000000010111100101100110 source: 00 changed: 00 step 1529 11100100000000010100100101100110 source: 1101101 changed: 1 1 step 1530 11101101000000010100100101100110 source: 1101001101001 changed: 1 10 1001 step 1531 11101101000000010101101001101001 source: 0 10 changed: 0 10 step 1532 11101100000000010110101001101001 source: 1100110100110 changed: 1 0110 0110 step 1533 11101100000000010111100110100110 source: 00 changed: 00 step 1534 11101100000000010100100110100110 source: 1101111 changed: 11 step 1535 11101111000000010100100110100110 source: 1101001101010 changed: 1 1001 10 step 1536 11101111000000010101101001101010 source: 0 10 changed: 0 10 step 1537 11101110000000010110101001101010 source: 1100110101010 changed: 1 0110 step 1538 11101110000000010111100110101010 source: 00 changed: 00 step 1539 11101110000000010100100110101010 source: 1101011 changed: 0 1 step 1540 11101011000000010100100110101010 source: 1101001100110 changed: 1 1001 01 step 1541 11101011000000010101101001100110 source: 0 10 changed: 0 10 step 1542 11101010000000010110101001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110011010 changed: 1 0110 10 step 1543 11101010000000010111100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1544 11101010000000010100100110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101001 changed: 01 step 1545 11101001000000010100100110101010 fail ^^ source: 1101001100101 changed: 1 1001 0101 step 1546 11101001000000010101101001100101 source: 0 10 changed: 0 10 step 1547 11101000000000010110101001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1100110010110 changed: 1 0110 10 step 1548 11101000000000010111100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1549 11101000000000010100100110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111001 changed: 1 1 step 1550 11111001000000010100100110100110 fail ^^ source: 1101010100101 changed: 1 10 01 step 1551 11111001000000010101101010100101 source: 0 10 changed: 0 10 step 1552 11111000000000010110101010100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010010110 changed: 1 10 step 1553 11111000000000010111101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1554 11111000000000010100101010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111011 changed: 11 step 1555 11111011000000010100101010100110 fail ^^ source: 1101010100110 changed: 1 step 1556 11111011000000010101101010100110 source: 0 10 changed: 0 10 step 1557 11111010000000010110101010100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1101010011010 changed: 1 10 step 1558 11111010000000010111101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1559 11111010000000010100101010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1111111 changed: 1 1 step 1560 11111111000000010100101010101010 fail ^^ source: 1101010101010 changed: 1 step 1561 11111111000000010101101010101010 source: 0 10 changed: 0 10 step 1562 11111110000000010110101010101010 source: 1101010101010 changed: 1 step 1563 11111110000000010111101010101010 source: 00 changed: 00 step 1564 11111110000000010100101010101010 source: 1111101 changed: 01 step 1565 11111101000000010100101010101010 source: 1101010101001 changed: 1 01 step 1566 11111101000000010101101010101001 source: 0 10 changed: 0 10 step 1567 11111100000000010110101010101001 source: 1101010100110 changed: 1 0110 step 1568 11111100000000010111101010100110 source: 00 changed: 00 step 1569 11111100000000010100101010100110 source: 1110101 changed: 0 1 step 1570 11110101000000010100101010100110 source: 1101010011001 changed: 1 011001 step 1571 11110101000000010101101010011001 source: 0 10 changed: 0 10 step 1572 11110100000000010110101010011001 source: 1101001100110 changed: 1 01100110 step 1573 11110100000000010111101001100110 source: 00 changed: 00 step 1574 11110100000000010100101001100110 source: 1110111 changed: 11 step 1575 11110111000000010100101001100110 source: 1101010011010 changed: 1 100110 step 1576 11110111000000010101101010011010 source: 0 10 changed: 0 10 step 1577 11110110000000010110101010011010 source: 1101001101010 changed: 1 0110 step 1578 11110110000000010111101001101010 source: 00 changed: 00 step 1579 11110110000000010100101001101010 source: 1110011 changed: 0 1 step 1580 11110011000000010100101001101010 source: 1101010010110 changed: 1 100101 step 1581 11110011000000010101101010010110 source: 0 10 changed: 0 10 step 1582 11110010000000010110101010010110 source: 1101001011010 changed: 1 01 10 step 1583 11110010000000010111101001011010 source: 00 changed: 00 step 1584 11110010000000010100101001011010 source: 1110001 changed: 01 step 1585 11110001000000010100101001011010 source: 1101010010101 changed: 1 10 0101 step 1586 11110001000000010101101010010101 source: 0 10 changed: 0 10 step 1587 11110000000000010110101010010101 source: 1101001010110 changed: 1 01 10 step 1588 11110000000000010111101001010110 source: 00 changed: 00 step 1589 11110000000000010100101001010110 source: 1010001 changed: 0 1 step 1590 11010001000000010100101001010110 source: 1100110010101 changed: 1 0110 01 step 1591 11010001000000010101100110010101 source: 0 10 changed: 0 10 step 1592 11010000000000010110100110010101 source: 1011001010110 changed: 1011001 10 step 1593 11010000000000010111011001010110 source: 00 changed: 00 step 1594 11010000000000010100011001010110 source: 1010011 changed: 11 step 1595 11010011000000010100011001010110 source: 1100110010110 changed: 1100110 step 1596 11010011000000010101100110010110 source: 0 10 changed: 0 10 step 1597 11010010000000010110100110010110 source: 1011001011010 changed: 1011001 10 step 1598 11010010000000010111011001011010 source: 00 changed: 00 step 1599 11010010000000010100011001011010 source: 1010111 changed: 1 1 step 1600 11010111000000010100011001011010 source: 1100110011010 changed: 1100110 step 1601 11010111000000010101100110011010 source: 0 10 changed: 0 10 step 1602 11010110000000010110100110011010 source: 1011001101010 changed: 101100110 step 1603 11010110000000010111011001101010 source: 00 changed: 00 step 1604 11010110000000010100011001101010 source: 1010101 changed: 01 step 1605 11010101000000010100011001101010 source: 1100110011001 changed: 110011001 01 step 1606 11010101000000010101100110011001 source: 0 10 changed: 0 10 step 1607 11010100000000010110100110011001 source: 1011001100110 changed: 1011001100110 step 1608 11010100000000010111011001100110 source: 00 changed: 00 step 1609 11010100000000010100011001100110 source: 1011101 changed: 1 1 step 1610 11011101000000010100011001100110 source: 1100110101001 changed: 1100110 1001 step 1611 11011101000000010101100110101001 source: 0 10 changed: 0 10 step 1612 11011100000000010110100110101001 source: 1011010100110 changed: 10110 0110 step 1613 11011100000000010111011010100110 source: 00 changed: 00 step 1614 11011100000000010100011010100110 source: 1011111 changed: 11 step 1615 11011111000000010100011010100110 source: 1100110101010 changed: 11001 10 step 1616 11011111000000010101100110101010 source: 0 10 changed: 0 10 step 1617 11011110000000010110100110101010 source: 1011010101010 changed: 10110 step 1618 11011110000000010111011010101010 source: 00 changed: 00 step 1619 11011110000000010100011010101010 source: 1011011 changed: 0 1 step 1620 11011011000000010100011010101010 source: 1100110100110 changed: 11001 01 step 1621 11011011000000010101100110100110 source: 0 10 changed: 0 10 step 1622 11011010000000010110100110100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010011010 changed: 10110 10 step 1623 11011010000000010111011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1624 11011010000000010100011010101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011001 changed: 01 step 1625 11011001000000010100011010101010 fail ^^ source: 1100110100101 changed: 11001 0101 step 1626 11011001000000010101100110100101 source: 0 10 changed: 0 10 step 1627 11011000000000010110100110100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1011010010110 changed: 10110 10 step 1628 11011000000000010111011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1629 11011000000000010100011010100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001001 changed: 0 1 step 1630 11001001000000010100011010100110 fail ^^ source: 1100101100101 changed: 1100101 01 step 1631 11001001000000010101100101100101 source: 0 10 changed: 0 10 step 1632 11001000000000010110100101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110010110 changed: 101 10 10 step 1633 11001000000000010111010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1634 11001000000000010100010110100110 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001011 changed: 11 step 1635 11001011000000010100010110100110 fail ^^ source: 1100101100110 changed: 110 01 step 1636 11001011000000010101100101100110 source: 0 10 changed: 0 10 step 1637 11001010000000010110100101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010110011010 changed: 101 10 10 step 1638 11001010000000010111010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 00 changed: 00 step 1639 11001010000000010100010110101010 fail ^^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1001111 changed: 1 1 step 1640 11001111000000010100010110101010 fail ^^ source: 1100101101010 changed: 110 01 step 1641 11001111000000010101100101101010 source: 0 10 changed: 0 10 step 1642 11001110000000010110100101101010 source: 1010110101010 changed: 101 10 step 1643 11001110000000010111010110101010 source: 00 changed: 00 step 1644 11001110000000010100010110101010 source: 1001101 changed: 01 step 1645 11001101000000010100010110101010 source: 1100101101001 changed: 110 01 01 step 1646 11001101000000010101100101101001 source: 0 10 changed: 0 10 step 1647 11001100000000010110100101101001 source: 1010110100110 changed: 101 10 0110 step 1648 11001100000000010111010110100110 source: 00 changed: 00 step 1649 11001100000000010100010110100110 source: 1000101 changed: 0 1 step 1650 11000101000000010100010110100110 source: 1100101011001 changed: 110 01011001 step 1651 11000101000000010101100101011001 source: 0 10 changed: 0 10 step 1652 11000100000000010110100101011001 source: 1010101100110 changed: 101 100110 step 1653 11000100000000010111010101100110 source: 00 changed: 00 step 1654 11000100000000010100010101100110 source: 1000111 changed: 11 step 1655 11000111000000010100010101100110 source: 1100101011010 changed: 110 0110 step 1656 11000111000000010101100101011010 source: 0 10 changed: 0 10 step 1657 11000110000000010110100101011010 source: 1010101101010 changed: 101 10 step 1658 11000110000000010111010101101010 source: 00 changed: 00 step 1659 11000110000000010100010101101010 source: 1000011 changed: 0 1 step 1660 11000011000000010100010101101010 source: 1100101010110 changed: 110 0101 step 1661 11000011000000010101100101010110 source: 0 10 changed: 0 10 step 1662 11000010000000010110100101010110 source: 1010101011010 changed: 101 10 step 1663 11000010000000010111010101011010 source: 00 changed: 00 step 1664 11000010000000010100010101011010 source: 1000001 changed: 01 step 1665 11000001000000010100010101011010 source: 1100101010101 changed: 110 0101 step 1666 11000001000000010101100101010101 source: 0 10 changed: 0 10 step 1667 11000000000000010110100101010101 source: 1010101010110 changed: 101 10 step 1668 11000000000000010111010101010110 source: 00 changed: 00 step 1669 11000000000000010100010101010110 source: 0000001 changed: 0 1 step 1670 10000001000000010100010101010110 source: 1010101010101 changed: 1 01 step 1671 10000001000000010101010101010101 source: 0 10 changed: 0 10 step 1672 10000000000000010110010101010101 source: 1010101010110 changed: 1 10 step 1673 10000000000000010111010101010110 source: 00 changed: 00 step 1674 10000000000000010100010101010110 source: source: source: ; end of SECTION GENERATED BY A PROGRAM source: source: source: ; CLEAR FFs source: 0 010101010101 changed: 0 01 step 1675 00000000000000010100010101010101 source: 1 changed: 1 step 1676 10000000000000010100010101010101 source: source: 11111110111111010100010101010101 changed: 111111 111111 step 1677 11111110111111010100010101010101 test 2: *** FAIL *************************** 192 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO this fail OO all fails OO was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; CLEAR-N, NO ENABLES source: 01111110111111010100010101010101 changed: 0 step 1 01111110111111010100010101010101 source: 1 changed: 1 step 2 11111110111111010100010101010101 source: source: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM source: ; see mk_m212_ld_shift.c source: source: source: ; TEST A INPUTS, GRAY CODE PATTERN source: source: ; ENABLE A INPUTS source: 1 changed: 1 step 3 11111111111111010100010101010101 source: ; LOAD FFs FROM INPUT A source: source: 000001 changed: 00000 step 4 10000011111111010100010101010101 source: 1010101010110 changed: 1 10 step 5 10000011111111010101010101010110 source: 0 changed: 0 step 6 10000011111111010100010101010110 source: 000011 changed: 1 step 7 10000111111111010100010101010110 source: 1010101011010 changed: 1 10 step 8 10000111111111010101010101011010 source: 0 changed: 0 step 9 10000111111111010100010101011010 source: 000010 changed: 0 step 10 10000101111111010100010101011010 source: 1010101011001 changed: 1 01 step 11 10000101111111010101010101011001 source: 0 changed: 0 step 12 10000101111111010100010101011001 source: 000110 changed: 1 step 13 10001101111111010100010101011001 source: 1010101101001 changed: 1 10 step 14 10001101111111010101010101101001 source: 0 changed: 0 step 15 10001101111111010100010101101001 source: 000111 changed: 1 step 16 10001111111111010100010101101001 source: 1010101101010 changed: 1 10 step 17 10001111111111010101010101101010 source: 0 changed: 0 step 18 10001111111111010100010101101010 source: 000101 changed: 0 step 19 10001011111111010100010101101010 source: 1010101100110 changed: 1 01 step 20 10001011111111010101010101100110 source: 0 changed: 0 step 21 10001011111111010100010101100110 source: 000100 changed: 0 step 22 10001001111111010100010101100110 source: 1010101100101 changed: 1 01 step 23 10001001111111010101010101100101 source: 0 changed: 0 step 24 10001001111111010100010101100101 source: 001100 changed: 1 step 25 10011001111111010100010101100101 source: 1010110100101 changed: 1 10 step 26 10011001111111010101010110100101 source: 0 changed: 0 step 27 10011001111111010100010110100101 source: 001101 changed: 1 step 28 10011011111111010100010110100101 source: 1010110100110 changed: 1 10 step 29 10011011111111010101010110100110 source: 0 changed: 0 step 30 10011011111111010100010110100110 source: 001111 changed: 1 step 31 10011111111111010100010110100110 source: 1010110101010 changed: 1 10 step 32 10011111111111010101010110101010 source: 0 changed: 0 step 33 10011111111111010100010110101010 source: 001110 changed: 0 step 34 10011101111111010100010110101010 source: 1010110101001 changed: 1 01 step 35 10011101111111010101010110101001 source: 0 changed: 0 step 36 10011101111111010100010110101001 source: 001010 changed: 0 step 37 10010101111111010100010110101001 source: 1010110011001 changed: 1 01 step 38 10010101111111010101010110011001 source: 0 changed: 0 step 39 10010101111111010100010110011001 source: 001011 changed: 1 step 40 10010111111111010100010110011001 source: 1010110011010 changed: 1 10 step 41 10010111111111010101010110011010 source: 0 changed: 0 step 42 10010111111111010100010110011010 source: 001001 changed: 0 step 43 10010011111111010100010110011010 source: 1010110010110 changed: 1 01 step 44 10010011111111010101010110010110 source: 0 changed: 0 step 45 10010011111111010100010110010110 source: 001000 changed: 0 step 46 10010001111111010100010110010110 source: 1010110010101 changed: 1 01 step 47 10010001111111010101010110010101 source: 0 changed: 0 step 48 10010001111111010100010110010101 source: 011000 changed: 1 step 49 10110001111111010100010110010101 source: 1011010010101 changed: 1 10 step 50 10110001111111010101011010010101 source: 0 changed: 0 step 51 10110001111111010100011010010101 source: 011001 changed: 1 step 52 10110011111111010100011010010101 source: 1011010010110 changed: 1 10 step 53 10110011111111010101011010010110 source: 0 changed: 0 step 54 10110011111111010100011010010110 source: 011011 changed: 1 step 55 10110111111111010100011010010110 source: 1011010011010 changed: 1 10 step 56 10110111111111010101011010011010 source: 0 changed: 0 step 57 10110111111111010100011010011010 source: 011010 changed: 0 step 58 10110101111111010100011010011010 source: 1011010011001 changed: 1 01 step 59 10110101111111010101011010011001 source: 0 changed: 0 step 60 10110101111111010100011010011001 source: 011110 changed: 1 step 61 10111101111111010100011010011001 source: 1011010101001 changed: 1 10 step 62 10111101111111010101011010101001 source: 0 changed: 0 step 63 10111101111111010100011010101001 source: 011111 changed: 1 step 64 10111111111111010100011010101001 source: 1011010101010 changed: 1 10 step 65 10111111111111010101011010101010 source: 0 changed: 0 step 66 10111111111111010100011010101010 source: 011101 changed: 0 step 67 10111011111111010100011010101010 source: 1011010100110 changed: 1 01 step 68 10111011111111010101011010100110 source: 0 changed: 0 step 69 10111011111111010100011010100110 source: 011100 changed: 0 step 70 10111001111111010100011010100110 source: 1011010100101 changed: 1 01 step 71 10111001111111010101011010100101 source: 0 changed: 0 step 72 10111001111111010100011010100101 source: 010100 changed: 0 step 73 10101001111111010100011010100101 source: 1011001100101 changed: 1 01 step 74 10101001111111010101011001100101 source: 0 changed: 0 step 75 10101001111111010100011001100101 source: 010101 changed: 1 step 76 10101011111111010100011001100101 source: 1011001100110 changed: 1 10 step 77 10101011111111010101011001100110 source: 0 changed: 0 step 78 10101011111111010100011001100110 source: 010111 changed: 1 step 79 10101111111111010100011001100110 source: 1011001101010 changed: 1 10 step 80 10101111111111010101011001101010 source: 0 changed: 0 step 81 10101111111111010100011001101010 source: 010110 changed: 0 step 82 10101101111111010100011001101010 source: 1011001101001 changed: 1 01 step 83 10101101111111010101011001101001 source: 0 changed: 0 step 84 10101101111111010100011001101001 source: 010010 changed: 0 step 85 10100101111111010100011001101001 source: 1011001011001 changed: 1 01 step 86 10100101111111010101011001011001 source: 0 changed: 0 step 87 10100101111111010100011001011001 source: 010011 changed: 1 step 88 10100111111111010100011001011001 source: 1011001011010 changed: 1 10 step 89 10100111111111010101011001011010 source: 0 changed: 0 step 90 10100111111111010100011001011010 source: 010001 changed: 0 step 91 10100011111111010100011001011010 source: 1011001010110 changed: 1 01 step 92 10100011111111010101011001010110 source: 0 changed: 0 step 93 10100011111111010100011001010110 source: 010000 changed: 0 step 94 10100001111111010100011001010110 source: 1011001010101 changed: 1 01 step 95 10100001111111010101011001010101 source: 0 changed: 0 step 96 10100001111111010100011001010101 source: 110000 changed: 1 step 97 11100001111111010100011001010101 source: 1101001010101 changed: 110 step 98 11100001111111010101101001010101 source: 0 changed: 0 step 99 11100001111111010100101001010101 source: 110001 changed: 1 step 100 11100011111111010100101001010101 source: 1101001010110 changed: 1 10 step 101 11100011111111010101101001010110 source: 0 changed: 0 step 102 11100011111111010100101001010110 source: 110011 changed: 1 step 103 11100111111111010100101001010110 source: 1101001011010 changed: 1 10 step 104 11100111111111010101101001011010 source: 0 changed: 0 step 105 11100111111111010100101001011010 source: 110010 changed: 0 step 106 11100101111111010100101001011010 source: 1101001011001 changed: 1 01 step 107 11100101111111010101101001011001 source: 0 changed: 0 step 108 11100101111111010100101001011001 source: 110110 changed: 1 step 109 11101101111111010100101001011001 source: 1101001101001 changed: 1 10 step 110 11101101111111010101101001101001 source: 0 changed: 0 step 111 11101101111111010100101001101001 source: 110111 changed: 1 step 112 11101111111111010100101001101001 source: 1101001101010 changed: 1 10 step 113 11101111111111010101101001101010 source: 0 changed: 0 step 114 11101111111111010100101001101010 source: 110101 changed: 0 step 115 11101011111111010100101001101010 source: 1101001100110 changed: 1 01 step 116 11101011111111010101101001100110 source: 0 changed: 0 step 117 11101011111111010100101001100110 source: 110100 changed: 0 step 118 11101001111111010100101001100110 source: 1101001100101 changed: 1 01 step 119 11101001111111010101101001100101 source: 0 changed: 0 step 120 11101001111111010100101001100101 source: 111100 changed: 1 step 121 11111001111111010100101001100101 source: 1101010100101 changed: 1 10 step 122 11111001111111010101101010100101 source: 0 changed: 0 step 123 11111001111111010100101010100101 source: 111101 changed: 1 step 124 11111011111111010100101010100101 source: 1101010100110 changed: 1 10 step 125 11111011111111010101101010100110 source: 0 changed: 0 step 126 11111011111111010100101010100110 source: 111111 changed: 1 step 127 11111111111111010100101010100110 source: 1101010101010 changed: 1 10 step 128 11111111111111010101101010101010 source: 0 changed: 0 step 129 11111111111111010100101010101010 source: 111110 changed: 0 step 130 11111101111111010100101010101010 source: 1101010101001 changed: 1 01 step 131 11111101111111010101101010101001 source: 0 changed: 0 step 132 11111101111111010100101010101001 source: 111010 changed: 0 step 133 11110101111111010100101010101001 source: 1101010011001 changed: 1 01 step 134 11110101111111010101101010011001 source: 0 changed: 0 step 135 11110101111111010100101010011001 source: 111011 changed: 1 step 136 11110111111111010100101010011001 source: 1101010011010 changed: 1 10 step 137 11110111111111010101101010011010 source: 0 changed: 0 step 138 11110111111111010100101010011010 source: 111001 changed: 0 step 139 11110011111111010100101010011010 source: 1101010010110 changed: 1 01 step 140 11110011111111010101101010010110 source: 0 changed: 0 step 141 11110011111111010100101010010110 source: 111000 changed: 0 step 142 11110001111111010100101010010110 source: 1101010010101 changed: 1 01 step 143 11110001111111010101101010010101 source: 0 changed: 0 step 144 11110001111111010100101010010101 source: 101000 changed: 0 step 145 11010001111111010100101010010101 source: 1100110010101 changed: 1 01 step 146 11010001111111010101100110010101 source: 0 changed: 0 step 147 11010001111111010100100110010101 source: 101001 changed: 1 step 148 11010011111111010100100110010101 source: 1100110010110 changed: 1 10 step 149 11010011111111010101100110010110 source: 0 changed: 0 step 150 11010011111111010100100110010110 source: 101011 changed: 1 step 151 11010111111111010100100110010110 source: 1100110011010 changed: 1 10 step 152 11010111111111010101100110011010 source: 0 changed: 0 step 153 11010111111111010100100110011010 source: 101010 changed: 0 step 154 11010101111111010100100110011010 source: 1100110011001 changed: 1 01 step 155 11010101111111010101100110011001 source: 0 changed: 0 step 156 11010101111111010100100110011001 source: 101110 changed: 1 step 157 11011101111111010100100110011001 source: 1100110101001 changed: 1 10 step 158 11011101111111010101100110101001 source: 0 changed: 0 step 159 11011101111111010100100110101001 source: 101111 changed: 1 step 160 11011111111111010100100110101001 source: 1100110101010 changed: 1 10 step 161 11011111111111010101100110101010 source: 0 changed: 0 step 162 11011111111111010100100110101010 source: 101101 changed: 0 step 163 11011011111111010100100110101010 source: 1100110100110 changed: 1 01 step 164 11011011111111010101100110100110 source: 0 changed: 0 step 165 11011011111111010100100110100110 source: 101100 changed: 0 step 166 11011001111111010100100110100110 source: 1100110100101 changed: 1 01 step 167 11011001111111010101100110100101 source: 0 changed: 0 step 168 11011001111111010100100110100101 source: 100100 changed: 0 step 169 11001001111111010100100110100101 source: 1100101100101 changed: 1 01 step 170 11001001111111010101100101100101 source: 0 changed: 0 step 171 11001001111111010100100101100101 source: 100101 changed: 1 step 172 11001011111111010100100101100101 source: 1100101100110 changed: 1 10 step 173 11001011111111010101100101100110 source: 0 changed: 0 step 174 11001011111111010100100101100110 source: 100111 changed: 1 step 175 11001111111111010100100101100110 source: 1100101101010 changed: 1 10 step 176 11001111111111010101100101101010 source: 0 changed: 0 step 177 11001111111111010100100101101010 source: 100110 changed: 0 step 178 11001101111111010100100101101010 source: 1100101101001 changed: 1 01 step 179 11001101111111010101100101101001 source: 0 changed: 0 step 180 11001101111111010100100101101001 source: 100010 changed: 0 step 181 11000101111111010100100101101001 source: 1100101011001 changed: 1 01 step 182 11000101111111010101100101011001 source: 0 changed: 0 step 183 11000101111111010100100101011001 source: 100011 changed: 1 step 184 11000111111111010100100101011001 source: 1100101011010 changed: 1 10 step 185 11000111111111010101100101011010 source: 0 changed: 0 step 186 11000111111111010100100101011010 source: 100001 changed: 0 step 187 11000011111111010100100101011010 source: 1100101010110 changed: 1 01 step 188 11000011111111010101100101010110 source: 0 changed: 0 step 189 11000011111111010100100101010110 source: 100000 changed: 0 step 190 11000001111111010100100101010110 source: 1100101010101 changed: 1 01 step 191 11000001111111010101100101010101 source: 0 changed: 0 step 192 11000001111111010100100101010101 source: 000000 changed: 0 step 193 10000001111111010100100101010101 source: 1010101010101 changed: 101 step 194 10000001111111010101010101010101 source: 0 changed: 0 step 195 10000001111111010100010101010101 source: source: ; DISABLE A INPUTS source: 0 changed: 0 step 196 10000000111111010100010101010101 source: source: source: ; TEST B INPUTS source: source: ; ENABLE B INPUTS source: 1 changed: 1 step 197 10000000111111110100010101010101 source: ; LOAD FFs FROM INPUT B source: source: 000001 changed: 00000 step 198 10000000000001110100010101010101 source: 1010101010110 changed: 1 10 step 199 10000000000001110101010101010110 source: 0 changed: 0 step 200 10000000000001110100010101010110 source: 000011 changed: 1 step 201 10000000000011110100010101010110 source: 1010101011010 changed: 1 10 step 202 10000000000011110101010101011010 source: 0 changed: 0 step 203 10000000000011110100010101011010 source: 000010 changed: 0 step 204 10000000000010110100010101011010 source: 1010101011001 changed: 1 01 step 205 10000000000010110101010101011001 source: 0 changed: 0 step 206 10000000000010110100010101011001 source: 000110 changed: 1 step 207 10000000000110110100010101011001 source: 1010101101001 changed: 1 10 step 208 10000000000110110101010101101001 source: 0 changed: 0 step 209 10000000000110110100010101101001 source: 000111 changed: 1 step 210 10000000000111110100010101101001 source: 1010101101010 changed: 1 10 step 211 10000000000111110101010101101010 source: 0 changed: 0 step 212 10000000000111110100010101101010 source: 000101 changed: 0 step 213 10000000000101110100010101101010 source: 1010101100110 changed: 1 01 step 214 10000000000101110101010101100110 source: 0 changed: 0 step 215 10000000000101110100010101100110 source: 000100 changed: 0 step 216 10000000000100110100010101100110 source: 1010101100101 changed: 1 01 step 217 10000000000100110101010101100101 source: 0 changed: 0 step 218 10000000000100110100010101100101 source: 001100 changed: 1 step 219 10000000001100110100010101100101 source: 1010110100101 changed: 1 10 step 220 10000000001100110101010110100101 source: 0 changed: 0 step 221 10000000001100110100010110100101 source: 001101 changed: 1 step 222 10000000001101110100010110100101 source: 1010110100110 changed: 1 10 step 223 10000000001101110101010110100110 source: 0 changed: 0 step 224 10000000001101110100010110100110 source: 001111 changed: 1 step 225 10000000001111110100010110100110 source: 1010110101010 changed: 1 10 step 226 10000000001111110101010110101010 source: 0 changed: 0 step 227 10000000001111110100010110101010 source: 001110 changed: 0 step 228 10000000001110110100010110101010 source: 1010110101001 changed: 1 01 step 229 10000000001110110101010110101001 source: 0 changed: 0 step 230 10000000001110110100010110101001 source: 001010 changed: 0 step 231 10000000001010110100010110101001 source: 1010110011001 changed: 1 01 step 232 10000000001010110101010110011001 source: 0 changed: 0 step 233 10000000001010110100010110011001 source: 001011 changed: 1 step 234 10000000001011110100010110011001 source: 1010110011010 changed: 1 10 step 235 10000000001011110101010110011010 source: 0 changed: 0 step 236 10000000001011110100010110011010 source: 001001 changed: 0 step 237 10000000001001110100010110011010 source: 1010110010110 changed: 1 01 step 238 10000000001001110101010110010110 source: 0 changed: 0 step 239 10000000001001110100010110010110 source: 001000 changed: 0 step 240 10000000001000110100010110010110 source: 1010110010101 changed: 1 01 step 241 10000000001000110101010110010101 source: 0 changed: 0 step 242 10000000001000110100010110010101 source: 011000 changed: 1 step 243 10000000011000110100010110010101 source: 1011010010101 changed: 1 10 step 244 10000000011000110101011010010101 source: 0 changed: 0 step 245 10000000011000110100011010010101 source: 011001 changed: 1 step 246 10000000011001110100011010010101 source: 1011010010110 changed: 1 10 step 247 10000000011001110101011010010110 source: 0 changed: 0 step 248 10000000011001110100011010010110 source: 011011 changed: 1 step 249 10000000011011110100011010010110 source: 1011010011010 changed: 1 10 step 250 10000000011011110101011010011010 source: 0 changed: 0 step 251 10000000011011110100011010011010 source: 011010 changed: 0 step 252 10000000011010110100011010011010 source: 1011010011001 changed: 1 01 step 253 10000000011010110101011010011001 source: 0 changed: 0 step 254 10000000011010110100011010011001 source: 011110 changed: 1 step 255 10000000011110110100011010011001 source: 1011010101001 changed: 1 10 step 256 10000000011110110101011010101001 source: 0 changed: 0 step 257 10000000011110110100011010101001 source: 011111 changed: 1 step 258 10000000011111110100011010101001 source: 1011010101010 changed: 1 10 step 259 10000000011111110101011010101010 source: 0 changed: 0 step 260 10000000011111110100011010101010 source: 011101 changed: 0 step 261 10000000011101110100011010101010 source: 1011010100110 changed: 1 01 step 262 10000000011101110101011010100110 source: 0 changed: 0 step 263 10000000011101110100011010100110 source: 011100 changed: 0 step 264 10000000011100110100011010100110 source: 1011010100101 changed: 1 01 step 265 10000000011100110101011010100101 source: 0 changed: 0 step 266 10000000011100110100011010100101 source: 010100 changed: 0 step 267 10000000010100110100011010100101 source: 1011001100101 changed: 1 01 step 268 10000000010100110101011001100101 source: 0 changed: 0 step 269 10000000010100110100011001100101 source: 010101 changed: 1 step 270 10000000010101110100011001100101 source: 1011001100110 changed: 1 10 step 271 10000000010101110101011001100110 source: 0 changed: 0 step 272 10000000010101110100011001100110 source: 010111 changed: 1 step 273 10000000010111110100011001100110 source: 1011001101010 changed: 1 10 step 274 10000000010111110101011001101010 source: 0 changed: 0 step 275 10000000010111110100011001101010 source: 010110 changed: 0 step 276 10000000010110110100011001101010 source: 1011001101001 changed: 1 01 step 277 10000000010110110101011001101001 source: 0 changed: 0 step 278 10000000010110110100011001101001 source: 010010 changed: 0 step 279 10000000010010110100011001101001 source: 1011001011001 changed: 1 01 step 280 10000000010010110101011001011001 source: 0 changed: 0 step 281 10000000010010110100011001011001 source: 010011 changed: 1 step 282 10000000010011110100011001011001 source: 1011001011010 changed: 1 10 step 283 10000000010011110101011001011010 source: 0 changed: 0 step 284 10000000010011110100011001011010 source: 010001 changed: 0 step 285 10000000010001110100011001011010 source: 1011001010110 changed: 1 01 step 286 10000000010001110101011001010110 source: 0 changed: 0 step 287 10000000010001110100011001010110 source: 010000 changed: 0 step 288 10000000010000110100011001010110 source: 1011001010101 changed: 1 01 step 289 10000000010000110101011001010101 source: 0 changed: 0 step 290 10000000010000110100011001010101 source: 110000 changed: 1 step 291 10000000110000110100011001010101 source: 1101001010101 changed: 110 step 292 10000000110000110101101001010101 source: 0 changed: 0 step 293 10000000110000110100101001010101 source: 110001 changed: 1 step 294 10000000110001110100101001010101 source: 1101001010110 changed: 1 10 step 295 10000000110001110101101001010110 source: 0 changed: 0 step 296 10000000110001110100101001010110 source: 110011 changed: 1 step 297 10000000110011110100101001010110 source: 1101001011010 changed: 1 10 step 298 10000000110011110101101001011010 source: 0 changed: 0 step 299 10000000110011110100101001011010 source: 110010 changed: 0 step 300 10000000110010110100101001011010 source: 1101001011001 changed: 1 01 step 301 10000000110010110101101001011001 source: 0 changed: 0 step 302 10000000110010110100101001011001 source: 110110 changed: 1 step 303 10000000110110110100101001011001 source: 1101001101001 changed: 1 10 step 304 10000000110110110101101001101001 source: 0 changed: 0 step 305 10000000110110110100101001101001 source: 110111 changed: 1 step 306 10000000110111110100101001101001 source: 1101001101010 changed: 1 10 step 307 10000000110111110101101001101010 source: 0 changed: 0 step 308 10000000110111110100101001101010 source: 110101 changed: 0 step 309 10000000110101110100101001101010 source: 1101001100110 changed: 1 01 step 310 10000000110101110101101001100110 source: 0 changed: 0 step 311 10000000110101110100101001100110 source: 110100 changed: 0 step 312 10000000110100110100101001100110 source: 1101001100101 changed: 1 01 step 313 10000000110100110101101001100101 source: 0 changed: 0 step 314 10000000110100110100101001100101 source: 111100 changed: 1 step 315 10000000111100110100101001100101 source: 1101010100101 changed: 1 10 step 316 10000000111100110101101010100101 source: 0 changed: 0 step 317 10000000111100110100101010100101 source: 111101 changed: 1 step 318 10000000111101110100101010100101 source: 1101010100110 changed: 1 10 step 319 10000000111101110101101010100110 source: 0 changed: 0 step 320 10000000111101110100101010100110 source: 111111 changed: 1 step 321 10000000111111110100101010100110 source: 1101010101010 changed: 1 10 step 322 10000000111111110101101010101010 source: 0 changed: 0 step 323 10000000111111110100101010101010 source: 111110 changed: 0 step 324 10000000111110110100101010101010 source: 1101010101001 changed: 1 01 step 325 10000000111110110101101010101001 source: 0 changed: 0 step 326 10000000111110110100101010101001 source: 111010 changed: 0 step 327 10000000111010110100101010101001 source: 1101010011001 changed: 1 01 step 328 10000000111010110101101010011001 source: 0 changed: 0 step 329 10000000111010110100101010011001 source: 111011 changed: 1 step 330 10000000111011110100101010011001 source: 1101010011010 changed: 1 10 step 331 10000000111011110101101010011010 source: 0 changed: 0 step 332 10000000111011110100101010011010 source: 111001 changed: 0 step 333 10000000111001110100101010011010 source: 1101010010110 changed: 1 01 step 334 10000000111001110101101010010110 source: 0 changed: 0 step 335 10000000111001110100101010010110 source: 111000 changed: 0 step 336 10000000111000110100101010010110 source: 1101010010101 changed: 1 01 step 337 10000000111000110101101010010101 source: 0 changed: 0 step 338 10000000111000110100101010010101 source: 101000 changed: 0 step 339 10000000101000110100101010010101 source: 1100110010101 changed: 1 01 step 340 10000000101000110101100110010101 source: 0 changed: 0 step 341 10000000101000110100100110010101 source: 101001 changed: 1 step 342 10000000101001110100100110010101 source: 1100110010110 changed: 1 10 step 343 10000000101001110101100110010110 source: 0 changed: 0 step 344 10000000101001110100100110010110 source: 101011 changed: 1 step 345 10000000101011110100100110010110 source: 1100110011010 changed: 1 10 step 346 10000000101011110101100110011010 source: 0 changed: 0 step 347 10000000101011110100100110011010 source: 101010 changed: 0 step 348 10000000101010110100100110011010 source: 1100110011001 changed: 1 01 step 349 10000000101010110101100110011001 source: 0 changed: 0 step 350 10000000101010110100100110011001 source: 101110 changed: 1 step 351 10000000101110110100100110011001 source: 1100110101001 changed: 1 10 step 352 10000000101110110101100110101001 source: 0 changed: 0 step 353 10000000101110110100100110101001 source: 101111 changed: 1 step 354 10000000101111110100100110101001 source: 1100110101010 changed: 1 10 step 355 10000000101111110101100110101010 source: 0 changed: 0 step 356 10000000101111110100100110101010 source: 101101 changed: 0 step 357 10000000101101110100100110101010 source: 1100110100110 changed: 1 01 step 358 10000000101101110101100110100110 source: 0 changed: 0 step 359 10000000101101110100100110100110 source: 101100 changed: 0 step 360 10000000101100110100100110100110 source: 1100110100101 changed: 1 01 step 361 10000000101100110101100110100101 source: 0 changed: 0 step 362 10000000101100110100100110100101 source: 100100 changed: 0 step 363 10000000100100110100100110100101 source: 1100101100101 changed: 1 01 step 364 10000000100100110101100101100101 source: 0 changed: 0 step 365 10000000100100110100100101100101 source: 100101 changed: 1 step 366 10000000100101110100100101100101 source: 1100101100110 changed: 1 10 step 367 10000000100101110101100101100110 source: 0 changed: 0 step 368 10000000100101110100100101100110 source: 100111 changed: 1 step 369 10000000100111110100100101100110 source: 1100101101010 changed: 1 10 step 370 10000000100111110101100101101010 source: 0 changed: 0 step 371 10000000100111110100100101101010 source: 100110 changed: 0 step 372 10000000100110110100100101101010 source: 1100101101001 changed: 1 01 step 373 10000000100110110101100101101001 source: 0 changed: 0 step 374 10000000100110110100100101101001 source: 100010 changed: 0 step 375 10000000100010110100100101101001 source: 1100101011001 changed: 1 01 step 376 10000000100010110101100101011001 source: 0 changed: 0 step 377 10000000100010110100100101011001 source: 100011 changed: 1 step 378 10000000100011110100100101011001 source: 1100101011010 changed: 1 10 step 379 10000000100011110101100101011010 source: 0 changed: 0 step 380 10000000100011110100100101011010 source: 100001 changed: 0 step 381 10000000100001110100100101011010 source: 1100101010110 changed: 1 01 step 382 10000000100001110101100101010110 source: 0 changed: 0 step 383 10000000100001110100100101010110 source: 100000 changed: 0 step 384 10000000100000110100100101010110 source: 1100101010101 changed: 1 01 step 385 10000000100000110101100101010101 source: 0 changed: 0 step 386 10000000100000110100100101010101 source: 000000 changed: 0 step 387 10000000000000110100100101010101 source: 1010101010101 changed: 101 step 388 10000000000000110101010101010101 source: 0 changed: 0 step 389 10000000000000110100010101010101 source: source: ; DISABLE B INPUTS source: 0 changed: 0 step 390 10000000000000010100010101010101 source: source: source: ; TEST SHIFT R (LOAD VIA A INPUTS) source: source: ; SHIFT IN A ZERO source: 0 changed: 0 step 391 10000000000000000100010101010101 source: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS source: ; ENABLE SHIFT RIGHT, SHIFT, DISABLE SHIFT RIGHT source: 0000011 changed: 11 step 392 10000011000000000100010101010101 source: 1010101010110 changed: 1 10 step 393 10000011000000000101010101010110 source: 0 1 0 changed: 0 1 0 step 394 10000010000000001100010101010110 source: 1010101010101 changed: 1 01 step 395 10000010000000001101010101010101 source: 0 0 changed: 0 0 step 396 10000010000000000100010101010101 source: 0000111 changed: 1 1 step 397 10000111000000000100010101010101 source: 1010101011010 changed: 1 1010 step 398 10000111000000000101010101011010 source: 0 1 0 changed: 0 1 0 step 399 10000110000000001100010101011010 source: 1010101010110 changed: 1 01 step 400 10000110000000001101010101010110 source: 0 0 changed: 0 0 step 401 10000110000000000100010101010110 source: 0000101 changed: 01 step 402 10000101000000000100010101010110 source: 1010101011001 changed: 1 1001 step 403 10000101000000000101010101011001 source: 0 1 0 changed: 0 1 0 step 404 10000100000000001100010101011001 source: 1010101010110 changed: 1 0110 step 405 10000100000000001101010101010110 source: 0 0 changed: 0 0 step 406 10000100000000000100010101010110 source: 0001101 changed: 1 1 step 407 10001101000000000100010101010110 source: 1010101101001 changed: 1 101001 step 408 10001101000000000101010101101001 source: 0 1 0 changed: 0 1 0 step 409 10001100000000001100010101101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 1010101011010 changed: 1 10 step 410 10001100000000001101010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO source: 0 0 changed: 0 0 step 411 10001100000000000100010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 412 10001111000000000100010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 413 10001111000000000101010101101010 step 414 10001110000000001100010101101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 step 415 10001110000000001101010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 416 10001110000000000100010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 417 10001011000000000100010101101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 418 10001011000000000101010101100110 step 419 10001010000000001100010101100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1001 step 420 10001010000000001101010101101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 421 10001010000000000100010101101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 422 10001001000000000100010101101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 423 10001001000000000101010101100101 step 424 10001000000000001100010101100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 10 step 425 10001000000000001101010101101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 426 10001000000000000100010101101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 427 10011001000000000100010101101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 428 10011001000000000101010110100101 step 429 10011000000000001100010110100101 step 430 10011000000000001101010101101001 step 431 10011000000000000100010101101001 step 432 10011011000000000100010101101001 step 433 10011011000000000101010110100110 step 434 10011010000000001100010110100110 step 435 10011010000000001101010101101001 step 436 10011010000000000100010101101001 step 437 10011111000000000100010101101001 step 438 10011111000000000101010110101010 step 439 10011110000000001100010110101010 step 440 10011110000000001101010101101010 step 441 10011110000000000100010101101010 step 442 10011101000000000100010101101010 step 443 10011101000000000101010110101001 step 444 10011100000000001100010110101001 step 445 10011100000000001101010101101010 step 446 10011100000000000100010101101010 step 447 10010101000000000100010101101010 step 448 10010101000000000101010110011001 step 449 10010100000000001100010110011001 step 450 10010100000000001101010101100110 step 451 10010100000000000100010101100110 step 452 10010111000000000100010101100110 step 453 10010111000000000101010110011010 step 454 10010110000000001100010110011010 step 455 10010110000000001101010101100110 step 456 10010110000000000100010101100110 step 457 10010011000000000100010101100110 step 458 10010011000000000101010110010110 step 459 10010010000000001100010110010110 step 460 10010010000000001101010101100101 step 461 10010010000000000100010101100101 step 462 10010001000000000100010101100101 step 463 10010001000000000101010110010101 step 464 10010000000000001100010110010101 step 465 10010000000000001101010101100101 step 466 10010000000000000100010101100101 step 467 10110001000000000100010101100101 step 468 10110001000000000101011010010101 step 469 10110000000000001100011010010101 step 470 10110000000000001101010110100101 step 471 10110000000000000100010110100101 step 472 10110011000000000100010110100101 step 473 10110011000000000101011010010110 step 474 10110010000000001100011010010110 step 475 10110010000000001101010110100101 step 476 10110010000000000100010110100101 step 477 10110111000000000100010110100101 step 478 10110111000000000101011010011010 step 479 10110110000000001100011010011010 step 480 10110110000000001101010110100110 step 481 10110110000000000100010110100110 step 482 10110101000000000100010110100110 step 483 10110101000000000101011010011001 step 484 10110100000000001100011010011001 step 485 10110100000000001101010110100110 step 486 10110100000000000100010110100110 step 487 10111101000000000100010110100110 step 488 10111101000000000101011010101001 step 489 10111100000000001100011010101001 step 490 10111100000000001101010110101010 step 491 10111100000000000100010110101010 step 492 10111111000000000100010110101010 step 493 10111111000000000101011010101010 step 494 10111110000000001100011010101010 step 495 10111110000000001101010110101010 step 496 10111110000000000100010110101010 step 497 10111011000000000100010110101010 step 498 10111011000000000101011010100110 step 499 10111010000000001100011010100110 step 500 10111010000000001101010110101001 step 501 10111010000000000100010110101001 step 502 10111001000000000100010110101001 step 503 10111001000000000101011010100101 step 504 10111000000000001100011010100101 step 505 10111000000000001101010110101001 step 506 10111000000000000100010110101001 step 507 10101001000000000100010110101001 step 508 10101001000000000101011001100101 step 509 10101000000000001100011001100101 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 510 10101000000000001101010110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 511 10101000000000000100010110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 11 step 512 10101011000000000100010110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 513 10101011000000000101011001100110 step 514 10101010000000001100011001100110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 1001 step 515 10101010000000001101010110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 516 10101010000000000100010110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 1 step 517 10101111000000000100010110101001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 518 10101111000000000101011001101010 step 519 10101110000000001100011001101010 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 step 520 10101110000000001101010110101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 521 10101110000000000100010110101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 01 step 522 10101101000000000100010110101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 523 10101101000000000101011001101001 step 524 10101100000000001100011001101001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 1 0110 10 step 525 10101100000000001101010110101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 0 step 526 10101100000000000100010110101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO changed: 0 1 step 527 10100101000000000100010110101010 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails OO was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 2, total passes 0 Main menu Fri Jun 30 19:47:19 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m304.tst reading test file: tests\m304.tst comment: M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. comment: comment: USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. comment: comment: PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AF1 OUT-A, comment: NEGATIVE PULSE ON AH1 OUT-A-N comment: PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AJ1 OUT-B, comment: NEGATIVE PULSE ON AK1 OUT-B-N. comment: PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AL1 OUT-C, comment: NEGATIVE PULSE ON AM1 OUT-C-N. comment: PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) comment: POSITIVE PULSE ON AP1 OUT-D, comment: NEGATIVE PULSE ON AN1 OUT-D-N. comment: comment: TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE comment: INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE comment: TRIGGER. comment: pins: PINS pins: 1 I AD1 E2-13 INPUT A1 (LOW TRIGGERS) pins: 2 I AD2 E2-12 INPUT A2 (LOW TRIGGERS) pins: 3 O AF1 E1-08 OUTPUT A POSITIVE PULSE pins: 4 O AH1 E1-06 OUTPUT A-N NEGATIVE PULSE pins: 5 I AE1 E2-10 INPUT B1 (LOW TRIGGERS) pins: 6 I AE2 E2-09 INPUT B2 (LOW TRIGGERS) pins: 7 O AJ1 E3-08 OUTPUT B POSITIVE PULSE pins: 8 O AK1 E3-06 OUTPUT B-N NEGATIVE PULSE pins: 9 I AS1 E7-01 INPUT C1 (LOW TRIGGERS) pins: 10 I AS2 E7-02 INPUT C2 (LOW TRIGGERS) pins: 11 O AL1 E5-08 OUTPUT C POSITIVE PULSE pins: 12 O AM1 E5-06 OUTPUT C-N NEGATIVE PULSE pins: 13 I AR1 E7-04 INPUT D1 (LOW TRIGGERS) pins: 14 I AR2 E7-05 INPUT D2 (LOW TRIGGERS) pins: 15 O AP1 E6-06 OUTPUT D POSITIVE PULSE pins: 16 O AN1 E6-08 OUTPUT D-N NEGATIVE PULSE pins: direction: IIOOIIOOIIOOIIOO test 1: 1101110111011101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 2: 0101 test 3: 1101 comment: ; PULSE OUTPUT A (PULSE IS TOO QUICK TO SEE) test 4: 1001 test 5: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 6: 0101 test 7: 1101 comment: ; PULSE OUTPUT B (PULSE IS TOO QUICK TO SEE) test 8: 1001 test 9: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 10: 0101 test 11: 1101 comment: ; PULSE OUTPUT C (PULSE IS TOO QUICK TO SEE) test 12: 1001 test 13: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 14: 0101 test 15: 1101 comment: ; PULSE OUTPUT D (PULSE IS TOO QUICK TO SEE) test 16: 1001 test 17: 1101 test 18: 1101110111011101 end: END summary column 1: offset 0, mask 0x1000 column 2: offset 0, mask 0x0010 column 3: offset 0, mask 0x0400 column 4: offset 0, mask 0x0200 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0008 column 7: offset 0, mask 0x0100 column 8: offset 1, mask 0x8000 column 9: offset 1, mask 0x0200 column 10: offset 1, mask 0x0040 column 11: offset 1, mask 0x4000 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x0400 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0800 column 16: offset 1, mask 0x1000 direction bits (1=input) 0xE7E7 0xF99F 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x1A18 0xB660 0x0000 0x0000 0x0000 2: 0x0A18 0xB660 0x0000 0x0000 0x0000 3: 0x1A18 0xB660 0x0000 0x0000 0x0000 4: 0x1A08 0xB660 0x0000 0x0000 0x0000 5: 0x1A18 0xB660 0x0000 0x0000 0x0000 6: 0x1218 0xB660 0x0000 0x0000 0x0000 7: 0x1A18 0xB660 0x0000 0x0000 0x0000 8: 0x1A10 0xB660 0x0000 0x0000 0x0000 9: 0x1A18 0xB660 0x0000 0x0000 0x0000 10: 0x1A18 0xB460 0x0000 0x0000 0x0000 11: 0x1A18 0xB660 0x0000 0x0000 0x0000 12: 0x1A18 0xB620 0x0000 0x0000 0x0000 13: 0x1A18 0xB660 0x0000 0x0000 0x0000 14: 0x1A18 0xB260 0x0000 0x0000 0x0000 15: 0x1A18 0xB660 0x0000 0x0000 0x0000 16: 0x1A18 0xB640 0x0000 0x0000 0x0000 17: 0x1A18 0xB660 0x0000 0x0000 0x0000 18: 0x1A18 0xB660 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOOOOOOOOIIG P GII II G P G UUT inputs: 8 UUT outputs: 8 pins used: 16 not used: 50 18 'test steps' 67 lines M304 PCB REV B, SCHEMATIC REV B QUAD ONE SHOT DELAY. USE SINGLE STEP AND OSCILLOSCOPE TO SEE PULSES. PIN AB1 TO +5V -> 100 NS OUTPUT A PULSE (OPEN -> 1 US) POSITIVE PULSE ON AF1 OUT-A, NEGATIVE PULSE ON AH1 OUT-A-N PIN AK2 TO +5V -> 100 NS OUTPUT B PULSE (OPEN -> 1 US) POSITIVE PULSE ON AJ1 OUT-B, NEGATIVE PULSE ON AK1 OUT-B-N. PIN AL2 TO +5V -> 100 NS OUTPUT C PULSE (OPEN -> 1 US) POSITIVE PULSE ON AL1 OUT-C, NEGATIVE PULSE ON AM1 OUT-C-N. PIN AV1 TO +5V -> 100 NS OUTPUT D PULSE (OPEN -> 1 US) POSITIVE PULSE ON AP1 OUT-D, NEGATIVE PULSE ON AN1 OUT-D-N. TO GENERATE AN OUTPUT PULSE, BOTH INPUTS ARE HIGH, THEN ONE OF THE INPUTS GOES LOW (FALLING EDGE) TO TRIGGER A POSITIVE OUTPUT PULSE TRIGGER. PINS Main menu Fri Jun 30 19:47:25 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 19:47:29 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER DDFHEEJKSSLMRRPN SIDE 1211121112111211 DIRECTION IIOOIIOOIIOOIIOO all fails was lo 000 000 000 000 falling vv vv vv vv rising ^^ ^^ ^^ ^^ was hi 11 111 111 111 1 total fails 0, total passes 342 Main menu Fri Jun 30 19:47:34 2017 test file is: tests\m304.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m216.tst reading test file: tests\m216.tst comment: M216 6 FLIP FLOPS comment: pins: PINS pins: 1 I AA1 E1-1 CLEAR-N E1-5/6 E1-8/9 E2-5/6 pins: 2 I AB1 E1-3 CLOCK E1-5/6 pins: 3 I AC1 E1-2 DATA E1-5/6 pins: 4 I AD1 E1-4 SET-N E1-5/6 pins: 5 O AE1 E1-5 Q E1-5/6 pins: 6 O AF1 E1-5 Q-N E1-5/6 pins: 7 I AD2 E1-11 CLOCK E1-8/9 pins: 8 I AE2 E1-12 DATA E1-8/9 pins: 9 I AF2 E1-10 SET-N E1-8/9 pins: 10 O AH2 E1-9 Q E1-8/9 pins: 11 O AJ2 E1-8 Q-N E1-8/9 pins: 12 I AH1 E2-3 CLOCK E2-5/6 pins: 13 I AJ1 E2-2 DATA E2-5/6 pins: 14 I AK1 E2-4 SET-N E2-5/6 pins: 15 O AL1 E2-5 Q E2-5/6 pins: 16 O AM1 E2-6 Q-N E2-5/6 pins: 17 I AK2 E3-13 CLEAR-N E3-8/9 E3-5/6 E2-8/9 pins: 18 I AL2 E3-11 CLOCK E3-8/9 pins: 19 I AM2 E3-12 DATA E3-8/9 pins: 20 I AN2 E3-10 SET-N E3-8/9 pins: 21 O AP2 E3-9 Q E3-8/9 pins: 22 O AR2 E3-8 Q-N E3-8/9 pins: 23 I AN1 E3-3 CLOCK E3-5/6 pins: 24 I AP1 E3-2 DATA E3-5/6 pins: 25 I AR1 E3-4 SET-N E3-5/6 pins: 26 O AS1 E3-5 Q E3-5/6 pins: 27 O AU1 E3-6 Q-N E3-5/6 pins: 28 I AS2 E2-11 CLOCK E2-8/9 pins: 29 I AT2 E2-12 DATA E2-8/9 pins: 30 I AU2 E2-10 SET-N E2-8/9 pins: 31 O AV2 E2-9 Q E2-8/9 pins: 32 O AV1 E2-8 Q-N E2-8/9 pins: direction: IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO test 1: 00001100011000110000110001100011 test 2: 100010 10 10 test 3: 100110 test 4: 110101 test 5: 111101 test 6: 101101 test 7: 111110 test 8: 110110 test 9: 100110 test 10: 000101 11 11 test 11: 100101 10 10 test 12: 100010 test 13: 00001100011000110000110001100011 test 14: 1 1000010 10 test 15: 1 00110 test 16: 1 10101 test 17: 1 11101 test 18: 1 01101 test 19: 1 11110 test 20: 1 10110 test 21: 1 00110 test 22: 0 1100101 11 test 23: 1 1000101 10 test 24: 1 00010 test 25: 00001100011000110000110001100011 test 26: 1 10 1000010 test 27: 1 00110 test 28: 1 10101 test 29: 1 11101 test 30: 1 01101 test 31: 1 11110 test 32: 1 10110 test 33: 1 00110 test 34: 0 11 1100101 test 35: 1 10 1000101 test 36: 1 00010 test 37: 00001100011000110000110001100011 test 38: 100010 10 10 test 39: 100110 test 40: 110101 test 41: 111101 test 42: 101101 test 43: 111110 test 44: 110110 test 45: 100110 test 46: 000101 11 11 test 47: 100101 10 10 test 48: 100010 test 49: 00001100011000110000110001100011 test 50: 1 1000010 10 test 51: 1 00110 test 52: 1 10101 test 53: 1 11101 test 54: 1 01101 test 55: 1 11110 test 56: 1 10110 test 57: 1 00110 test 58: 0 1100101 11 test 59: 1 1000101 10 test 60: 1 00010 test 61: 00001100011000110000110001100011 test 62: 1 10 1000010 test 63: 1 00110 test 64: 1 10101 test 65: 1 11101 test 66: 1 01101 test 67: 1 11110 test 68: 1 10110 test 69: 1 00110 test 70: 0 11 1100101 test 71: 1 10 1000101 test 72: 1 00010 test 73: 00001100011000110000110001100011 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0002 column 11: offset 0, mask 0x0001 column 12: offset 0, mask 0x0200 column 13: offset 0, mask 0x0100 column 14: offset 1, mask 0x8000 column 15: offset 1, mask 0x4000 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x0001 column 18: offset 1, mask 0x0002 column 19: offset 1, mask 0x0004 column 20: offset 1, mask 0x0008 column 21: offset 1, mask 0x0010 column 22: offset 1, mask 0x0020 column 23: offset 1, mask 0x1000 column 24: offset 1, mask 0x0800 column 25: offset 1, mask 0x0400 column 26: offset 1, mask 0x0200 column 27: offset 2, mask 0x8000 column 28: offset 1, mask 0x0040 column 29: offset 1, mask 0x0080 column 30: offset 2, mask 0x0001 column 31: offset 2, mask 0x0002 column 32: offset 2, mask 0x4000 direction bits (1=input) 0x0CE3 0x6330 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0C03 0x6230 0xC002 0x0000 0x0000 2: 0x8802 0x4230 0xC002 0x0000 0x0000 3: 0x9802 0x4230 0xC002 0x0000 0x0000 4: 0xD402 0x4230 0xC002 0x0000 0x0000 5: 0xF402 0x4230 0xC002 0x0000 0x0000 6: 0xB402 0x4230 0xC002 0x0000 0x0000 7: 0xF802 0x4230 0xC002 0x0000 0x0000 8: 0xD802 0x4230 0xC002 0x0000 0x0000 9: 0x9802 0x4230 0xC002 0x0000 0x0000 10: 0x1403 0x6230 0xC002 0x0000 0x0000 11: 0x9402 0x4230 0xC002 0x0000 0x0000 12: 0x8802 0x4230 0xC002 0x0000 0x0000 13: 0x0C03 0x6230 0xC002 0x0000 0x0000 14: 0x8802 0x4230 0xC002 0x0000 0x0000 15: 0x8806 0x4230 0xC002 0x0000 0x0000 16: 0x8815 0x4230 0xC002 0x0000 0x0000 17: 0x881D 0x4230 0xC002 0x0000 0x0000 18: 0x880D 0x4230 0xC002 0x0000 0x0000 19: 0x881E 0x4230 0xC002 0x0000 0x0000 20: 0x8816 0x4230 0xC002 0x0000 0x0000 21: 0x8806 0x4230 0xC002 0x0000 0x0000 22: 0x0C05 0x6230 0xC002 0x0000 0x0000 23: 0x8805 0x4230 0xC002 0x0000 0x0000 24: 0x8802 0x4230 0xC002 0x0000 0x0000 25: 0x0C03 0x6230 0xC002 0x0000 0x0000 26: 0x8802 0x4230 0xC002 0x0000 0x0000 27: 0x8802 0xC230 0xC002 0x0000 0x0000 28: 0x8A02 0xA230 0xC002 0x0000 0x0000 29: 0x8B02 0xA230 0xC002 0x0000 0x0000 30: 0x8902 0xA230 0xC002 0x0000 0x0000 31: 0x8B02 0xC230 0xC002 0x0000 0x0000 32: 0x8A02 0xC230 0xC002 0x0000 0x0000 33: 0x8802 0xC230 0xC002 0x0000 0x0000 34: 0x0C03 0xA230 0xC002 0x0000 0x0000 35: 0x8802 0xA230 0xC002 0x0000 0x0000 36: 0x8802 0x4230 0xC002 0x0000 0x0000 37: 0x0C03 0x6230 0xC002 0x0000 0x0000 38: 0x0C03 0x6211 0x0002 0x0000 0x0000 39: 0x0C03 0x6219 0x0002 0x0000 0x0000 40: 0x0C03 0x622B 0x0002 0x0000 0x0000 41: 0x0C03 0x622F 0x0002 0x0000 0x0000 42: 0x0C03 0x622D 0x0002 0x0000 0x0000 43: 0x0C03 0x621F 0x0002 0x0000 0x0000 44: 0x0C03 0x621B 0x0002 0x0000 0x0000 45: 0x0C03 0x6219 0x0002 0x0000 0x0000 46: 0x0C03 0x6228 0xC002 0x0000 0x0000 47: 0x0C03 0x6229 0x0002 0x0000 0x0000 48: 0x0C03 0x6211 0x0002 0x0000 0x0000 49: 0x0C03 0x6230 0xC002 0x0000 0x0000 50: 0x0C03 0x6211 0x0002 0x0000 0x0000 51: 0x0C03 0x6611 0x0002 0x0000 0x0000 52: 0x0C03 0x7411 0x8002 0x0000 0x0000 53: 0x0C03 0x7C11 0x8002 0x0000 0x0000 54: 0x0C03 0x6C11 0x8002 0x0000 0x0000 55: 0x0C03 0x7E11 0x0002 0x0000 0x0000 56: 0x0C03 0x7611 0x0002 0x0000 0x0000 57: 0x0C03 0x6611 0x0002 0x0000 0x0000 58: 0x0C03 0x6430 0xC002 0x0000 0x0000 59: 0x0C03 0x6411 0x8002 0x0000 0x0000 60: 0x0C03 0x6211 0x0002 0x0000 0x0000 61: 0x0C03 0x6230 0xC002 0x0000 0x0000 62: 0x0C03 0x6211 0x0002 0x0000 0x0000 63: 0x0C03 0x6211 0x0003 0x0000 0x0000 64: 0x0C03 0x6251 0x4001 0x0000 0x0000 65: 0x0C03 0x62D1 0x4001 0x0000 0x0000 66: 0x0C03 0x6291 0x4001 0x0000 0x0000 67: 0x0C03 0x62D1 0x0003 0x0000 0x0000 68: 0x0C03 0x6251 0x0003 0x0000 0x0000 69: 0x0C03 0x6211 0x0003 0x0000 0x0000 70: 0x0C03 0x6230 0xC001 0x0000 0x0000 71: 0x0C03 0x6211 0x4001 0x0000 0x0000 72: 0x0C03 0x6211 0x0002 0x0000 0x0000 73: 0x0C03 0x6230 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOOIIIOOIIIOGOOP GIIIOOIIIIOOIIIO G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 73 'test steps' 111 lines M216 6 FLIP FLOPS PINS Main menu Fri Jun 30 20:01:22 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 20:01:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJHJKLMKLMNPRNPRSUSTUVV SIDE 11111122222111112222221111122221 DIRECTION IIIIOOIIIOOIIIOOIIIIOOIIIOOIIIOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 147 Main menu Fri Jun 30 20:02:54 2017 test file is: tests\m216.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Fri Jun 30 20:02:57 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Fri Jun 30 20:02:59 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 20:03:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 31: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 31, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 32: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 32, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 33: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 33, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 33, total passes 0 Main menu Fri Jun 30 20:05:19 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m212.tst reading test file: tests\m212.tst comment: ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER comment: comment: ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) comment: pins: PINS pins: 1 I AB1 E3-4,10;E6-4,10;E9-4,10 CLEAR-N CLEARS FF0 THRU FF5 pins: 2 I AL2 E1-3 INA0-N pins: 3 I AM2 E2-2 INA1-N pins: 4 I AN2 E4-2 INA2-N pins: 5 I AR2 E5-2 INA3-N pins: 6 I AV1 E7-2 INA4-N pins: 7 I AV2 E8-2 INA5-N pins: 8 I AN1 ENABLE_INPUT_A pins: 9 I AP2 E1-4 INB0-N pins: 10 I AR1 E2-4 INB1-N pins: 11 I AS1 E4-4 INB2-N pins: 12 I AU1 E5-4 INB3-N pins: 13 I AA1 E7-4 INB4-N pins: 14 I AT2 E8-4 INB5-N pins: 15 I AU2 ENABLE_INPUT_B pins: 16 I AM1 E1-1 SHIFT_R_INSERT-N RIGHT SHIFTS INTO FF0 pins: 17 I AL1 ENABLE_R_SHIFT pins: 18 I AS2 E8-9 SHIFT_L_INSERT-N LEFT SHIFTS INTO FF5 pins: 19 I AP1 ENABLE_L_SHIFT pins: 20 I AC1 E3-3,11;E6-3,11;E9-3,11 CLOCK (RISING EDGE) pins: 21 O AD1 E3-6 FF0 pins: 22 O AD2 E3-5 FF0-N pins: 23 O AF1 E3-8 FF1 pins: 24 O AE1 E3-9 FF1-N pins: 25 O AH2 E6-6 FF2 pins: 26 O AE2 E6-5 FF2-N pins: 27 O AH1 E6-8 FF3 pins: 28 O AF2 E6-9 FF3-N pins: 29 O AK2 E9-6 FF4 pins: 30 O AJ2 E9-5 FF4-N pins: 31 O AK1 E9-8 FF5 pins: 32 O AJ1 A9-9 FF5-N pins: direction: IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO comment: ; CLEAR-N, NO ENABLES test 1: 01111110111111010100010101010101 test 2: 1 comment: comment: ; FOLLOWING SECTION IS GENERATED BY A PROGRAM comment: ; see mk_m212_ld_shift.c comment: comment: comment: ; TEST A INPUTS, GRAY CODE PATTERN comment: comment: ; ENABLE A INPUTS test 3: 1 comment: ; LOAD FFs FROM INPUT A comment: test 4: 000001 test 5: 1010101010110 test 6: 0 test 7: 000011 test 8: 1010101011010 test 9: 0 test 10: 000010 test 11: 1010101011001 test 12: 0 test 13: 000110 test 14: 1010101101001 test 15: 0 test 16: 000111 test 17: 1010101101010 test 18: 0 test 19: 000101 test 20: 1010101100110 test 21: 0 test 22: 000100 test 23: 1010101100101 test 24: 0 test 25: 001100 test 26: 1010110100101 test 27: 0 test 28: 001101 test 29: 1010110100110 test 30: 0 test 31: 001111 test 32: 1010110101010 test 33: 0 test 34: 001110 test 35: 1010110101001 test 36: 0 test 37: 001010 test 38: 1010110011001 test 39: 0 test 40: 001011 test 41: 1010110011010 test 42: 0 test 43: 001001 test 44: 1010110010110 test 45: 0 test 46: 001000 test 47: 1010110010101 test 48: 0 test 49: 011000 test 50: 1011010010101 test 51: 0 test 52: 011001 test 53: 1011010010110 test 54: 0 test 55: 011011 test 56: 1011010011010 test 57: 0 test 58: 011010 test 59: 1011010011001 test 60: 0 test 61: 011110 test 62: 1011010101001 test 63: 0 test 64: 011111 test 65: 1011010101010 test 66: 0 test 67: 011101 test 68: 1011010100110 test 69: 0 test 70: 011100 test 71: 1011010100101 test 72: 0 test 73: 010100 test 74: 1011001100101 test 75: 0 test 76: 010101 test 77: 1011001100110 test 78: 0 test 79: 010111 test 80: 1011001101010 test 81: 0 test 82: 010110 test 83: 1011001101001 test 84: 0 test 85: 010010 test 86: 1011001011001 test 87: 0 test 88: 010011 test 89: 1011001011010 test 90: 0 test 91: 010001 test 92: 1011001010110 test 93: 0 test 94: 010000 test 95: 1011001010101 test 96: 0 test 97: 110000 test 98: 1101001010101 test 99: 0 test 100: 110001 test 101: 1101001010110 test 102: 0 test 103: 110011 test 104: 1101001011010 test 105: 0 test 106: 110010 test 107: 1101001011001 test 108: 0 test 109: 110110 test 110: 1101001101001 test 111: 0 test 112: 110111 test 113: 1101001101010 test 114: 0 test 115: 110101 test 116: 1101001100110 test 117: 0 test 118: 110100 test 119: 1101001100101 test 120: 0 test 121: 111100 test 122: 1101010100101 test 123: 0 test 124: 111101 test 125: 1101010100110 test 126: 0 test 127: 111111 test 128: 1101010101010 test 129: 0 test 130: 111110 test 131: 1101010101001 test 132: 0 test 133: 111010 test 134: 1101010011001 test 135: 0 test 136: 111011 test 137: 1101010011010 test 138: 0 test 139: 111001 test 140: 1101010010110 test 141: 0 test 142: 111000 test 143: 1101010010101 test 144: 0 test 145: 101000 test 146: 1100110010101 test 147: 0 test 148: 101001 test 149: 1100110010110 test 150: 0 test 151: 101011 test 152: 1100110011010 test 153: 0 test 154: 101010 test 155: 1100110011001 test 156: 0 test 157: 101110 test 158: 1100110101001 test 159: 0 test 160: 101111 test 161: 1100110101010 test 162: 0 test 163: 101101 test 164: 1100110100110 test 165: 0 test 166: 101100 test 167: 1100110100101 test 168: 0 test 169: 100100 test 170: 1100101100101 test 171: 0 test 172: 100101 test 173: 1100101100110 test 174: 0 test 175: 100111 test 176: 1100101101010 test 177: 0 test 178: 100110 test 179: 1100101101001 test 180: 0 test 181: 100010 test 182: 1100101011001 test 183: 0 test 184: 100011 test 185: 1100101011010 test 186: 0 test 187: 100001 test 188: 1100101010110 test 189: 0 test 190: 100000 test 191: 1100101010101 test 192: 0 test 193: 000000 test 194: 1010101010101 test 195: 0 comment: comment: ; DISABLE A INPUTS test 196: 0 comment: comment: comment: ; TEST B INPUTS comment: comment: ; ENABLE B INPUTS test 197: 1 comment: ; LOAD FFs FROM INPUT B comment: test 198: 000001 test 199: 1010101010110 test 200: 0 test 201: 000011 test 202: 1010101011010 test 203: 0 test 204: 000010 test 205: 1010101011001 test 206: 0 test 207: 000110 test 208: 1010101101001 test 209: 0 test 210: 000111 test 211: 1010101101010 test 212: 0 test 213: 000101 test 214: 1010101100110 test 215: 0 test 216: 000100 test 217: 1010101100101 test 218: 0 test 219: 001100 test 220: 1010110100101 test 221: 0 test 222: 001101 test 223: 1010110100110 test 224: 0 test 225: 001111 test 226: 1010110101010 test 227: 0 test 228: 001110 test 229: 1010110101001 test 230: 0 test 231: 001010 test 232: 1010110011001 test 233: 0 test 234: 001011 test 235: 1010110011010 test 236: 0 test 237: 001001 test 238: 1010110010110 test 239: 0 test 240: 001000 test 241: 1010110010101 test 242: 0 test 243: 011000 test 244: 1011010010101 test 245: 0 test 246: 011001 test 247: 1011010010110 test 248: 0 test 249: 011011 test 250: 1011010011010 test 251: 0 test 252: 011010 test 253: 1011010011001 test 254: 0 test 255: 011110 test 256: 1011010101001 test 257: 0 test 258: 011111 test 259: 1011010101010 test 260: 0 test 261: 011101 test 262: 1011010100110 test 263: 0 test 264: 011100 test 265: 1011010100101 test 266: 0 test 267: 010100 test 268: 1011001100101 test 269: 0 test 270: 010101 test 271: 1011001100110 test 272: 0 test 273: 010111 test 274: 1011001101010 test 275: 0 test 276: 010110 test 277: 1011001101001 test 278: 0 test 279: 010010 test 280: 1011001011001 test 281: 0 test 282: 010011 test 283: 1011001011010 test 284: 0 test 285: 010001 test 286: 1011001010110 test 287: 0 test 288: 010000 test 289: 1011001010101 test 290: 0 test 291: 110000 test 292: 1101001010101 test 293: 0 test 294: 110001 test 295: 1101001010110 test 296: 0 test 297: 110011 test 298: 1101001011010 test 299: 0 test 300: 110010 test 301: 1101001011001 test 302: 0 test 303: 110110 test 304: 1101001101001 test 305: 0 test 306: 110111 test 307: 1101001101010 test 308: 0 test 309: 110101 test 310: 1101001100110 test 311: 0 test 312: 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1010110010101 test 1313: 00 test 1314: 1001011 test 1315: 1100101100110 test 1316: 0 10 test 1317: 1010110011001 test 1318: 00 test 1319: 1001111 test 1320: 1100101101010 test 1321: 0 10 test 1322: 1010110101001 test 1323: 00 test 1324: 1001101 test 1325: 1100101101001 test 1326: 0 10 test 1327: 1010110100101 test 1328: 00 test 1329: 1000101 test 1330: 1100101011001 test 1331: 0 10 test 1332: 1010101100101 test 1333: 00 test 1334: 1000111 test 1335: 1100101011010 test 1336: 0 10 test 1337: 1010101101001 test 1338: 00 test 1339: 1000011 test 1340: 1100101010110 test 1341: 0 10 test 1342: 1010101011001 test 1343: 00 test 1344: 1000001 test 1345: 1100101010101 test 1346: 0 10 test 1347: 1010101010101 test 1348: 00 test 1349: 0000001 test 1350: 1010101010101 test 1351: 0 10 test 1352: 1010101010101 test 1353: 00 comment: comment: comment: ; TEST SHIFT L (LOAD VIA A INPUTS) comment: comment: ; SHIFT IN A ONE test 1354: 1 comment: ; ENABLE A INPUTS, LOAD A, DISABLE A INPUTS comment: ; ENABLE SHIFT LEFT, SHIFT, DISABLE SHIFT LEFT test 1355: 0000011 test 1356: 1010101010110 test 1357: 0 10 test 1358: 1010101011010 test 1359: 00 test 1360: 0000111 test 1361: 1010101011010 test 1362: 0 10 test 1363: 1010101101010 test 1364: 00 test 1365: 0000101 test 1366: 1010101011001 test 1367: 0 10 test 1368: 1010101100110 test 1369: 00 test 1370: 0001101 test 1371: 1010101101001 test 1372: 0 10 test 1373: 1010110100110 test 1374: 00 test 1375: 0001111 test 1376: 1010101101010 test 1377: 0 10 test 1378: 1010110101010 test 1379: 00 test 1380: 0001011 test 1381: 1010101100110 test 1382: 0 10 test 1383: 1010110011010 test 1384: 00 test 1385: 0001001 test 1386: 1010101100101 test 1387: 0 10 test 1388: 1010110010110 test 1389: 00 test 1390: 0011001 test 1391: 1010110100101 test 1392: 0 10 test 1393: 1011010010110 test 1394: 00 test 1395: 0011011 test 1396: 1010110100110 test 1397: 0 10 test 1398: 1011010011010 test 1399: 00 test 1400: 0011111 test 1401: 1010110101010 test 1402: 0 10 test 1403: 1011010101010 test 1404: 00 test 1405: 0011101 test 1406: 1010110101001 test 1407: 0 10 test 1408: 1011010100110 test 1409: 00 test 1410: 0010101 test 1411: 1010110011001 test 1412: 0 10 test 1413: 1011001100110 test 1414: 00 test 1415: 0010111 test 1416: 1010110011010 test 1417: 0 10 test 1418: 1011001101010 test 1419: 00 test 1420: 0010011 test 1421: 1010110010110 test 1422: 0 10 test 1423: 1011001011010 test 1424: 00 test 1425: 0010001 test 1426: 1010110010101 test 1427: 0 10 test 1428: 1011001010110 test 1429: 00 test 1430: 0110001 test 1431: 1011010010101 test 1432: 0 10 test 1433: 1101001010110 test 1434: 00 test 1435: 0110011 test 1436: 1011010010110 test 1437: 0 10 test 1438: 1101001011010 test 1439: 00 test 1440: 0110111 test 1441: 1011010011010 test 1442: 0 10 test 1443: 1101001101010 test 1444: 00 test 1445: 0110101 test 1446: 1011010011001 test 1447: 0 10 test 1448: 1101001100110 test 1449: 00 test 1450: 0111101 test 1451: 1011010101001 test 1452: 0 10 test 1453: 1101010100110 test 1454: 00 test 1455: 0111111 test 1456: 1011010101010 test 1457: 0 10 test 1458: 1101010101010 test 1459: 00 test 1460: 0111011 test 1461: 1011010100110 test 1462: 0 10 test 1463: 1101010011010 test 1464: 00 test 1465: 0111001 test 1466: 1011010100101 test 1467: 0 10 test 1468: 1101010010110 test 1469: 00 test 1470: 0101001 test 1471: 1011001100101 test 1472: 0 10 test 1473: 1100110010110 test 1474: 00 test 1475: 0101011 test 1476: 1011001100110 test 1477: 0 10 test 1478: 1100110011010 test 1479: 00 test 1480: 0101111 test 1481: 1011001101010 test 1482: 0 10 test 1483: 1100110101010 test 1484: 00 test 1485: 0101101 test 1486: 1011001101001 test 1487: 0 10 test 1488: 1100110100110 test 1489: 00 test 1490: 0100101 test 1491: 1011001011001 test 1492: 0 10 test 1493: 1100101100110 test 1494: 00 test 1495: 0100111 test 1496: 1011001011010 test 1497: 0 10 test 1498: 1100101101010 test 1499: 00 test 1500: 0100011 test 1501: 1011001010110 test 1502: 0 10 test 1503: 1100101011010 test 1504: 00 test 1505: 0100001 test 1506: 1011001010101 test 1507: 0 10 test 1508: 1100101010110 test 1509: 00 test 1510: 1100001 test 1511: 1101001010101 test 1512: 0 10 test 1513: 1100101010110 test 1514: 00 test 1515: 1100011 test 1516: 1101001010110 test 1517: 0 10 test 1518: 1100101011010 test 1519: 00 test 1520: 1100111 test 1521: 1101001011010 test 1522: 0 10 test 1523: 1100101101010 test 1524: 00 test 1525: 1100101 test 1526: 1101001011001 test 1527: 0 10 test 1528: 1100101100110 test 1529: 00 test 1530: 1101101 test 1531: 1101001101001 test 1532: 0 10 test 1533: 1100110100110 test 1534: 00 test 1535: 1101111 test 1536: 1101001101010 test 1537: 0 10 test 1538: 1100110101010 test 1539: 00 test 1540: 1101011 test 1541: 1101001100110 test 1542: 0 10 test 1543: 1100110011010 test 1544: 00 test 1545: 1101001 test 1546: 1101001100101 test 1547: 0 10 test 1548: 1100110010110 test 1549: 00 test 1550: 1111001 test 1551: 1101010100101 test 1552: 0 10 test 1553: 1101010010110 test 1554: 00 test 1555: 1111011 test 1556: 1101010100110 test 1557: 0 10 test 1558: 1101010011010 test 1559: 00 test 1560: 1111111 test 1561: 1101010101010 test 1562: 0 10 test 1563: 1101010101010 test 1564: 00 test 1565: 1111101 test 1566: 1101010101001 test 1567: 0 10 test 1568: 1101010100110 test 1569: 00 test 1570: 1110101 test 1571: 1101010011001 test 1572: 0 10 test 1573: 1101001100110 test 1574: 00 test 1575: 1110111 test 1576: 1101010011010 test 1577: 0 10 test 1578: 1101001101010 test 1579: 00 test 1580: 1110011 test 1581: 1101010010110 test 1582: 0 10 test 1583: 1101001011010 test 1584: 00 test 1585: 1110001 test 1586: 1101010010101 test 1587: 0 10 test 1588: 1101001010110 test 1589: 00 test 1590: 1010001 test 1591: 1100110010101 test 1592: 0 10 test 1593: 1011001010110 test 1594: 00 test 1595: 1010011 test 1596: 1100110010110 test 1597: 0 10 test 1598: 1011001011010 test 1599: 00 test 1600: 1010111 test 1601: 1100110011010 test 1602: 0 10 test 1603: 1011001101010 test 1604: 00 test 1605: 1010101 test 1606: 1100110011001 test 1607: 0 10 test 1608: 1011001100110 test 1609: 00 test 1610: 1011101 test 1611: 1100110101001 test 1612: 0 10 test 1613: 1011010100110 test 1614: 00 test 1615: 1011111 test 1616: 1100110101010 test 1617: 0 10 test 1618: 1011010101010 test 1619: 00 test 1620: 1011011 test 1621: 1100110100110 test 1622: 0 10 test 1623: 1011010011010 test 1624: 00 test 1625: 1011001 test 1626: 1100110100101 test 1627: 0 10 test 1628: 1011010010110 test 1629: 00 test 1630: 1001001 test 1631: 1100101100101 test 1632: 0 10 test 1633: 1010110010110 test 1634: 00 test 1635: 1001011 test 1636: 1100101100110 test 1637: 0 10 test 1638: 1010110011010 test 1639: 00 test 1640: 1001111 test 1641: 1100101101010 test 1642: 0 10 test 1643: 1010110101010 test 1644: 00 test 1645: 1001101 test 1646: 1100101101001 test 1647: 0 10 test 1648: 1010110100110 test 1649: 00 test 1650: 1000101 test 1651: 1100101011001 test 1652: 0 10 test 1653: 1010101100110 test 1654: 00 test 1655: 1000111 test 1656: 1100101011010 test 1657: 0 10 test 1658: 1010101101010 test 1659: 00 test 1660: 1000011 test 1661: 1100101010110 test 1662: 0 10 test 1663: 1010101011010 test 1664: 00 test 1665: 1000001 test 1666: 1100101010101 test 1667: 0 10 test 1668: 1010101010110 test 1669: 00 test 1670: 0000001 test 1671: 1010101010101 test 1672: 0 10 test 1673: 1010101010110 test 1674: 00 comment: comment: comment: ; end of SECTION GENERATED BY A PROGRAM comment: comment: comment: ; CLEAR FFs test 1675: 0 010101010101 test 1676: 1 comment: test 1677: 11111110111111010100010101010101 comment: end: END summary column 1: offset 0, mask 0x4000 column 2: offset 1, mask 0x0002 column 3: offset 1, mask 0x0004 column 4: offset 1, mask 0x0008 column 5: offset 1, mask 0x0020 column 6: offset 2, mask 0x4000 column 7: offset 2, mask 0x0002 column 8: offset 1, mask 0x1000 column 9: offset 1, mask 0x0010 column 10: offset 1, mask 0x0400 column 11: offset 1, mask 0x0200 column 12: offset 2, mask 0x8000 column 13: offset 0, mask 0x8000 column 14: offset 1, mask 0x0080 column 15: offset 2, mask 0x0001 column 16: offset 1, mask 0x2000 column 17: offset 1, mask 0x4000 column 18: offset 1, mask 0x0040 column 19: offset 1, mask 0x0800 column 20: offset 0, mask 0x2000 column 21: offset 0, mask 0x1000 column 22: offset 0, mask 0x0010 column 23: offset 0, mask 0x0400 column 24: offset 0, mask 0x0800 column 25: offset 0, mask 0x0002 column 26: offset 0, mask 0x0008 column 27: offset 0, mask 0x0200 column 28: offset 0, mask 0x0004 column 29: offset 1, mask 0x0001 column 30: offset 0, mask 0x0001 column 31: offset 1, mask 0x8000 column 32: offset 0, mask 0x0100 direction bits (1=input) 0x1FFF 0x8101 0x3FF8 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x891D 0x26FE 0xC002 0x0000 0x0000 2: 0xC91D 0x26FE 0xC002 0x0000 0x0000 3: 0xC91D 0x36FE 0xC002 0x0000 0x0000 4: 0xC91D 0x36D0 0x8002 0x0000 0x0000 5: 0xE81D 0xB6D0 0x8002 0x0000 0x0000 6: 0xC81D 0xB6D0 0x8002 0x0000 0x0000 7: 0xC81D 0xB6D0 0xC002 0x0000 0x0000 8: 0xE81C 0xB6D1 0xC002 0x0000 0x0000 9: 0xC81C 0xB6D1 0xC002 0x0000 0x0000 10: 0xC81C 0xB6D1 0xC000 0x0000 0x0000 11: 0xE91C 0x36D1 0xC000 0x0000 0x0000 12: 0xC91C 0x36D1 0xC000 0x0000 0x0000 13: 0xC91C 0x36F1 0xC000 0x0000 0x0000 14: 0xEB18 0x36F1 0xC000 0x0000 0x0000 15: 0xCB18 0x36F1 0xC000 0x0000 0x0000 16: 0xCB18 0x36F1 0xC002 0x0000 0x0000 17: 0xEA18 0xB6F1 0xC002 0x0000 0x0000 18: 0xCA18 0xB6F1 0xC002 0x0000 0x0000 19: 0xCA18 0xB6F1 0x8002 0x0000 0x0000 20: 0xEA19 0xB6F0 0x8002 0x0000 0x0000 21: 0xCA19 0xB6F0 0x8002 0x0000 0x0000 22: 0xCA19 0xB6F0 0x8000 0x0000 0x0000 23: 0xEB19 0x36F0 0x8000 0x0000 0x0000 24: 0xCB19 0x36F0 0x8000 0x0000 0x0000 25: 0xCB19 0x36F8 0x8000 0x0000 0x0000 26: 0xEB13 0x36F8 0x8000 0x0000 0x0000 27: 0xCB13 0x36F8 0x8000 0x0000 0x0000 28: 0xCB13 0x36F8 0x8002 0x0000 0x0000 29: 0xEA13 0xB6F8 0x8002 0x0000 0x0000 30: 0xCA13 0xB6F8 0x8002 0x0000 0x0000 31: 0xCA13 0xB6F8 0xC002 0x0000 0x0000 32: 0xEA12 0xB6F9 0xC002 0x0000 0x0000 33: 0xCA12 0xB6F9 0xC002 0x0000 0x0000 34: 0xCA12 0xB6F9 0xC000 0x0000 0x0000 35: 0xEB12 0x36F9 0xC000 0x0000 0x0000 36: 0xCB12 0x36F9 0xC000 0x0000 0x0000 37: 0xCB12 0x36D9 0xC000 0x0000 0x0000 38: 0xE916 0x36D9 0xC000 0x0000 0x0000 39: 0xC916 0x36D9 0xC000 0x0000 0x0000 40: 0xC916 0x36D9 0xC002 0x0000 0x0000 41: 0xE816 0xB6D9 0xC002 0x0000 0x0000 42: 0xC816 0xB6D9 0xC002 0x0000 0x0000 43: 0xC816 0xB6D9 0x8002 0x0000 0x0000 44: 0xE817 0xB6D8 0x8002 0x0000 0x0000 45: 0xC817 0xB6D8 0x8002 0x0000 0x0000 46: 0xC817 0xB6D8 0x8000 0x0000 0x0000 47: 0xE917 0x36D8 0x8000 0x0000 0x0000 48: 0xC917 0x36D8 0x8000 0x0000 0x0000 49: 0xC917 0x36DC 0x8000 0x0000 0x0000 50: 0xE517 0x36DC 0x8000 0x0000 0x0000 51: 0xC517 0x36DC 0x8000 0x0000 0x0000 52: 0xC517 0x36DC 0x8002 0x0000 0x0000 53: 0xE417 0xB6DC 0x8002 0x0000 0x0000 54: 0xC417 0xB6DC 0x8002 0x0000 0x0000 55: 0xC417 0xB6DC 0xC002 0x0000 0x0000 56: 0xE416 0xB6DD 0xC002 0x0000 0x0000 57: 0xC416 0xB6DD 0xC002 0x0000 0x0000 58: 0xC416 0xB6DD 0xC000 0x0000 0x0000 59: 0xE516 0x36DD 0xC000 0x0000 0x0000 60: 0xC516 0x36DD 0xC000 0x0000 0x0000 61: 0xC516 0x36FD 0xC000 0x0000 0x0000 62: 0xE712 0x36FD 0xC000 0x0000 0x0000 63: 0xC712 0x36FD 0xC000 0x0000 0x0000 64: 0xC712 0x36FD 0xC002 0x0000 0x0000 65: 0xE612 0xB6FD 0xC002 0x0000 0x0000 66: 0xC612 0xB6FD 0xC002 0x0000 0x0000 67: 0xC612 0xB6FD 0x8002 0x0000 0x0000 68: 0xE613 0xB6FC 0x8002 0x0000 0x0000 69: 0xC613 0xB6FC 0x8002 0x0000 0x0000 70: 0xC613 0xB6FC 0x8000 0x0000 0x0000 71: 0xE713 0x36FC 0x8000 0x0000 0x0000 72: 0xC713 0x36FC 0x8000 0x0000 0x0000 73: 0xC713 0x36F4 0x8000 0x0000 0x0000 74: 0xE719 0x36F4 0x8000 0x0000 0x0000 75: 0xC719 0x36F4 0x8000 0x0000 0x0000 76: 0xC719 0x36F4 0x8002 0x0000 0x0000 77: 0xE619 0xB6F4 0x8002 0x0000 0x0000 78: 0xC619 0xB6F4 0x8002 0x0000 0x0000 79: 0xC619 0xB6F4 0xC002 0x0000 0x0000 80: 0xE618 0xB6F5 0xC002 0x0000 0x0000 81: 0xC618 0xB6F5 0xC002 0x0000 0x0000 82: 0xC618 0xB6F5 0xC000 0x0000 0x0000 83: 0xE718 0x36F5 0xC000 0x0000 0x0000 84: 0xC718 0x36F5 0xC000 0x0000 0x0000 85: 0xC718 0x36D5 0xC000 0x0000 0x0000 86: 0xE51C 0x36D5 0xC000 0x0000 0x0000 87: 0xC51C 0x36D5 0xC000 0x0000 0x0000 88: 0xC51C 0x36D5 0xC002 0x0000 0x0000 89: 0xE41C 0xB6D5 0xC002 0x0000 0x0000 90: 0xC41C 0xB6D5 0xC002 0x0000 0x0000 91: 0xC41C 0xB6D5 0x8002 0x0000 0x0000 92: 0xE41D 0xB6D4 0x8002 0x0000 0x0000 93: 0xC41D 0xB6D4 0x8002 0x0000 0x0000 94: 0xC41D 0xB6D4 0x8000 0x0000 0x0000 95: 0xE51D 0x36D4 0x8000 0x0000 0x0000 96: 0xC51D 0x36D4 0x8000 0x0000 0x0000 97: 0xC51D 0x36D6 0x8000 0x0000 0x0000 98: 0xF50D 0x36D6 0x8000 0x0000 0x0000 99: 0xD50D 0x36D6 0x8000 0x0000 0x0000 100: 0xD50D 0x36D6 0x8002 0x0000 0x0000 101: 0xF40D 0xB6D6 0x8002 0x0000 0x0000 102: 0xD40D 0xB6D6 0x8002 0x0000 0x0000 103: 0xD40D 0xB6D6 0xC002 0x0000 0x0000 104: 0xF40C 0xB6D7 0xC002 0x0000 0x0000 105: 0xD40C 0xB6D7 0xC002 0x0000 0x0000 106: 0xD40C 0xB6D7 0xC000 0x0000 0x0000 107: 0xF50C 0x36D7 0xC000 0x0000 0x0000 108: 0xD50C 0x36D7 0xC000 0x0000 0x0000 109: 0xD50C 0x36F7 0xC000 0x0000 0x0000 110: 0xF708 0x36F7 0xC000 0x0000 0x0000 111: 0xD708 0x36F7 0xC000 0x0000 0x0000 112: 0xD708 0x36F7 0xC002 0x0000 0x0000 113: 0xF608 0xB6F7 0xC002 0x0000 0x0000 114: 0xD608 0xB6F7 0xC002 0x0000 0x0000 115: 0xD608 0xB6F7 0x8002 0x0000 0x0000 116: 0xF609 0xB6F6 0x8002 0x0000 0x0000 117: 0xD609 0xB6F6 0x8002 0x0000 0x0000 118: 0xD609 0xB6F6 0x8000 0x0000 0x0000 119: 0xF709 0x36F6 0x8000 0x0000 0x0000 120: 0xD709 0x36F6 0x8000 0x0000 0x0000 121: 0xD709 0x36FE 0x8000 0x0000 0x0000 122: 0xF703 0x36FE 0x8000 0x0000 0x0000 123: 0xD703 0x36FE 0x8000 0x0000 0x0000 124: 0xD703 0x36FE 0x8002 0x0000 0x0000 125: 0xF603 0xB6FE 0x8002 0x0000 0x0000 126: 0xD603 0xB6FE 0x8002 0x0000 0x0000 127: 0xD603 0xB6FE 0xC002 0x0000 0x0000 128: 0xF602 0xB6FF 0xC002 0x0000 0x0000 129: 0xD602 0xB6FF 0xC002 0x0000 0x0000 130: 0xD602 0xB6FF 0xC000 0x0000 0x0000 131: 0xF702 0x36FF 0xC000 0x0000 0x0000 132: 0xD702 0x36FF 0xC000 0x0000 0x0000 133: 0xD702 0x36DF 0xC000 0x0000 0x0000 134: 0xF506 0x36DF 0xC000 0x0000 0x0000 135: 0xD506 0x36DF 0xC000 0x0000 0x0000 136: 0xD506 0x36DF 0xC002 0x0000 0x0000 137: 0xF406 0xB6DF 0xC002 0x0000 0x0000 138: 0xD406 0xB6DF 0xC002 0x0000 0x0000 139: 0xD406 0xB6DF 0x8002 0x0000 0x0000 140: 0xF407 0xB6DE 0x8002 0x0000 0x0000 141: 0xD407 0xB6DE 0x8002 0x0000 0x0000 142: 0xD407 0xB6DE 0x8000 0x0000 0x0000 143: 0xF507 0x36DE 0x8000 0x0000 0x0000 144: 0xD507 0x36DE 0x8000 0x0000 0x0000 145: 0xD507 0x36DA 0x8000 0x0000 0x0000 146: 0xF907 0x36DA 0x8000 0x0000 0x0000 147: 0xD907 0x36DA 0x8000 0x0000 0x0000 148: 0xD907 0x36DA 0x8002 0x0000 0x0000 149: 0xF807 0xB6DA 0x8002 0x0000 0x0000 150: 0xD807 0xB6DA 0x8002 0x0000 0x0000 151: 0xD807 0xB6DA 0xC002 0x0000 0x0000 152: 0xF806 0xB6DB 0xC002 0x0000 0x0000 153: 0xD806 0xB6DB 0xC002 0x0000 0x0000 154: 0xD806 0xB6DB 0xC000 0x0000 0x0000 155: 0xF906 0x36DB 0xC000 0x0000 0x0000 156: 0xD906 0x36DB 0xC000 0x0000 0x0000 157: 0xD906 0x36FB 0xC000 0x0000 0x0000 158: 0xFB02 0x36FB 0xC000 0x0000 0x0000 159: 0xDB02 0x36FB 0xC000 0x0000 0x0000 160: 0xDB02 0x36FB 0xC002 0x0000 0x0000 161: 0xFA02 0xB6FB 0xC002 0x0000 0x0000 162: 0xDA02 0xB6FB 0xC002 0x0000 0x0000 163: 0xDA02 0xB6FB 0x8002 0x0000 0x0000 164: 0xFA03 0xB6FA 0x8002 0x0000 0x0000 165: 0xDA03 0xB6FA 0x8002 0x0000 0x0000 166: 0xDA03 0xB6FA 0x8000 0x0000 0x0000 167: 0xFB03 0x36FA 0x8000 0x0000 0x0000 168: 0xDB03 0x36FA 0x8000 0x0000 0x0000 169: 0xDB03 0x36F2 0x8000 0x0000 0x0000 170: 0xFB09 0x36F2 0x8000 0x0000 0x0000 171: 0xDB09 0x36F2 0x8000 0x0000 0x0000 172: 0xDB09 0x36F2 0x8002 0x0000 0x0000 173: 0xFA09 0xB6F2 0x8002 0x0000 0x0000 174: 0xDA09 0xB6F2 0x8002 0x0000 0x0000 175: 0xDA09 0xB6F2 0xC002 0x0000 0x0000 176: 0xFA08 0xB6F3 0xC002 0x0000 0x0000 177: 0xDA08 0xB6F3 0xC002 0x0000 0x0000 178: 0xDA08 0xB6F3 0xC000 0x0000 0x0000 179: 0xFB08 0x36F3 0xC000 0x0000 0x0000 180: 0xDB08 0x36F3 0xC000 0x0000 0x0000 181: 0xDB08 0x36D3 0xC000 0x0000 0x0000 182: 0xF90C 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0x4002 0x0000 0x0000 1616: 0x7A02 0xB06B 0x4002 0x0000 0x0000 1617: 0x5A02 0xA86B 0x4002 0x0000 0x0000 1618: 0x6612 0xA86B 0x4002 0x0000 0x0000 1619: 0x4612 0xA06B 0x4002 0x0000 0x0000 1620: 0x4612 0xB06B 0x0002 0x0000 0x0000 1621: 0x7A03 0xB06A 0x0002 0x0000 0x0000 1622: 0x5A03 0xA86A 0x0002 0x0000 0x0000 1623: 0x6416 0xA86B 0x0002 0x0000 0x0000 1624: 0x4416 0xA06B 0x0002 0x0000 0x0000 1625: 0x4416 0xB06B 0x0000 0x0000 0x0000 1626: 0x7B03 0x306A 0x0000 0x0000 0x0000 1627: 0x5B03 0x286A 0x0000 0x0000 0x0000 1628: 0x6417 0xA86A 0x0000 0x0000 0x0000 1629: 0x4417 0xA06A 0x0000 0x0000 0x0000 1630: 0x4417 0xB062 0x0000 0x0000 0x0000 1631: 0x7B09 0x3062 0x0000 0x0000 0x0000 1632: 0x5B09 0x2862 0x0000 0x0000 0x0000 1633: 0x6817 0xA862 0x0000 0x0000 0x0000 1634: 0x4817 0xA062 0x0000 0x0000 0x0000 1635: 0x4817 0xB062 0x0002 0x0000 0x0000 1636: 0x7A09 0xB062 0x0002 0x0000 0x0000 1637: 0x5A09 0xA862 0x0002 0x0000 0x0000 1638: 0x6816 0xA863 0x0002 0x0000 0x0000 1639: 0x4816 0xA063 0x0002 0x0000 0x0000 1640: 0x4816 0xB063 0x4002 0x0000 0x0000 1641: 0x7A08 0xB063 0x4002 0x0000 0x0000 1642: 0x5A08 0xA863 0x4002 0x0000 0x0000 1643: 0x6A12 0xA863 0x4002 0x0000 0x0000 1644: 0x4A12 0xA063 0x4002 0x0000 0x0000 1645: 0x4A12 0xB063 0x4000 0x0000 0x0000 1646: 0x7B08 0x3063 0x4000 0x0000 0x0000 1647: 0x5B08 0x2863 0x4000 0x0000 0x0000 1648: 0x6A13 0xA862 0x4000 0x0000 0x0000 1649: 0x4A13 0xA062 0x4000 0x0000 0x0000 1650: 0x4A13 0xB042 0x4000 0x0000 0x0000 1651: 0x790C 0x3043 0x4000 0x0000 0x0000 1652: 0x590C 0x2843 0x4000 0x0000 0x0000 1653: 0x6A19 0xA842 0x4000 0x0000 0x0000 1654: 0x4A19 0xA042 0x4000 0x0000 0x0000 1655: 0x4A19 0xB042 0x4002 0x0000 0x0000 1656: 0x780C 0xB043 0x4002 0x0000 0x0000 1657: 0x580C 0xA843 0x4002 0x0000 0x0000 1658: 0x6A18 0xA843 0x4002 0x0000 0x0000 1659: 0x4A18 0xA043 0x4002 0x0000 0x0000 1660: 0x4A18 0xB043 0x0002 0x0000 0x0000 1661: 0x780D 0xB042 0x0002 0x0000 0x0000 1662: 0x580D 0xA842 0x0002 0x0000 0x0000 1663: 0x681C 0xA843 0x0002 0x0000 0x0000 1664: 0x481C 0xA043 0x0002 0x0000 0x0000 1665: 0x481C 0xB043 0x0000 0x0000 0x0000 1666: 0x790D 0x3042 0x0000 0x0000 0x0000 1667: 0x590D 0x2842 0x0000 0x0000 0x0000 1668: 0x681D 0xA842 0x0000 0x0000 0x0000 1669: 0x481D 0xA042 0x0000 0x0000 0x0000 1670: 0x481D 0xB040 0x0000 0x0000 0x0000 1671: 0x691D 0x3040 0x0000 0x0000 0x0000 1672: 0x491D 0x2840 0x0000 0x0000 0x0000 1673: 0x681D 0xA840 0x0000 0x0000 0x0000 1674: 0x481D 0xA040 0x0000 0x0000 0x0000 1675: 0x091D 0x2040 0x0000 0x0000 0x0000 1676: 0x491D 0x2040 0x0000 0x0000 0x0000 1677: 0xC91D 0x26FE 0xC002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIOOOOOOIIIIIIGIIP GOOOOOOIIIIIIIII G P G UUT inputs: 20 UUT outputs: 12 pins used: 32 not used: 34 1677 'test steps' 1775 lines ; M212 PCB REV B SCHEMATIC REV B 6-BIT L-R SHIFT REGISTER ; SCHEMATIC IS IN PDP-12 MAINTENANCE VOL 4 (MODULES) PINS Main menu Fri Jun 30 20:05:31 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Fri Jun 30 20:05:32 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER BLMNRVVNPRSUATUMLSPCDDFEHEHFKJKJ SIDE 12222121211112211211121122122211 DIRECTION IIIIIIIIIIIIIIIIIIIIOOOOOOOOOOOO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 6 Main menu Fri Jun 30 20:05:39 2017 test file is: tests\m212.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 07:51:10 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m160.tst reading test file: tests\m160.tst comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Sat Jul 01 07:51:20 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 07:51:39 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 44: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 44, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 45: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 45, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 46: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 46, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 47: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 47, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00000000000001000000000000100001 step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 48: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 48, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 27 O AT2 E3-8 OUTPUT SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO fails LO: fails LO: fails HI: 1 1111 1 fails HI: 0000000000000 00000000 0000 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 27 O AT2 E3-8 OUTPUT SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO fails LO: fails LO: fails HI: 1 1111 1 fails HI: 0000000000000 00000000 0000 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: step 1 00000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 2 00010000000001000000000000100001 step 3 00110000000001000000000000100001 step 4 00100000000001000000000000100001 step 5 01100000000001000000000000100001 step 6 01110000000001000000000000100001 step 7 01010000000001000000000000100001 step 8 01000000000001000000000000100001 step 9 11000000000001000000000000100001 step 10 11010000000001000000000000100001 step 11 11110000000000000000000000100001 step 12 11100000000001000000000000100001 step 13 10100000000001000000000000100001 step 14 10110000000001000000000000100001 step 15 10010000000001000000000000100001 step 16 10000000000001000000000000100001 step 17 00000000000001000000000000100001 step 18 00000100000001000000000000100001 step 19 00001000000001000000000000100001 step 20 00001100000000000000000000100001 step 21 00000100000001000000000000100001 step 22 00000000000001000000000000100001 step 23 00000001000001000000000000100001 step 24 00000010000001000000000000100001 step 25 00000011000000000000000000100001 step 26 00000001000001000000000000100001 step 27 00000000000001000000000000100001 step 28 00000000010001000000000000100001 step 29 00000000100001000000000000100001 step 30 00000000110000000000000000100001 step 31 00000000010001000000000000100001 step 32 00000000000001000000000000100001 step 33 00000000000011000000000000100001 step 34 00000000000111000000000000100001 step 35 00000000000101000000000000100001 step 36 00000000000101000000000000100001 step 37 00000000001110000000000000100001 step 38 00000000001011000000000000100001 step 39 00000000001001000000000000100001 step 40 00000000000001000000000000100001 step 41 00000000000001000100000000100001 step 42 00000000000001001100000000100001 step 43 00000000000001001000000000100001 step 44 00000000000001011000000000100001 step 45 00000000000001011100000000100001 step 46 00000000000001010100000000100001 step 47 00000000000001010000000000100001 step 48 00000000000001110000000000100001 step 49 00000000000001110100000000100001 step 50 00000000000001111100000000000001 step 51 00000000000001111000000000100001 step 52 00000000000001101000000000100001 step 53 00000000000001101100000000100001 step 54 00000000000001100100000000100001 step 55 00000000000001100000000000100001 step 56 00000000000001000000000000100001 step 57 00000000000001000001000000100001 step 58 00000000000001000010000000100001 step 59 00000000000001000011000000000001 step 60 00000000000001000001000000100001 step 61 00000000000001000000000000100001 step 62 00000000000001000000010000100001 step 63 00000000000001000000100000100001 step 64 00000000000001000000110000000001 step 65 00000000000001000000010000100001 step 66 00000000000001000000000000100001 step 67 00000000000001000000000001100001 step 68 00000000000001000000000011100001 step 69 00000000000001000000000010100001 step 70 00000000000001000000000110100001 step 71 00000000000001000000000111100001 step 72 00000000000001000000000101100001 step 73 00000000000001000000000100100001 step 74 00000000000001000000001100100001 step 75 00000000000001000000001101100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000001000000001111100001 fail ^ step 77 00000000000001000000001110100001 step 78 00000000000001000000001010100001 step 79 00000000000001000000001011100001 step 80 00000000000001000000001001100001 step 81 00000000000001000000001000100001 step 82 00000000000001000000000000100001 step 83 00000000000001000000000000101001 step 84 00000000000001000000000000110001 step 85 00000000000001000000000000111000 step 86 00000000000001000000000000101001 step 87 00000000000001000000000000100001 step 88 00000000000001000000000000100011 step 89 00000000000001000000000000100101 step 90 00000000000001000000000000100110 step 91 00000000000001000000000000100011 step 92 00000000000001000000000000100001 test 49: *** FAIL *************************** 1 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O all fails O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 49, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: step 1 00000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 2 00010000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 3 00110000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 4 00100000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 5 01100000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 6 01110000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 7 01010000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 8 01000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 9 11000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 10 11010000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 0 step 11 11110000000000000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 1 step 12 11100000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 13 10100000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 14 10110000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 15 10010000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 16 10000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 17 00000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 18 00000100000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 19 00001000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 0 step 20 00001100000000000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 1 step 21 00000100000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 22 00000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 23 00000001000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 24 00000010000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 0 step 25 00000011000000000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 1 step 26 00000001000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 27 00000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 28 00000000010001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 29 00000000100001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 0 step 30 00000000110000000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 1 step 31 00000000010001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 32 00000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 33 00000000000011000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 34 00000000000111000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 35 00000000000101000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: step 36 00000000000101000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 10 step 37 00000000001110000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 1 step 38 00000000001011000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 39 00000000001001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 40 00000000000001000000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 41 00000000000001000100000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 42 00000000000001001100000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 43 00000000000001001000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 44 00000000000001011000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 45 00000000000001011100000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 46 00000000000001010100000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 47 00000000000001010000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 48 00000000000001110000000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 49 00000000000001110100000000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 0 step 50 00000000000001111100000000000001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 0 0 step 51 00000000000000111000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 52 00000000000000101000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 53 00000000000000101100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 54 00000000000000100100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 55 00000000000000100000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 56 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 57 00000000000000000001000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 58 00000000000000000010000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 59 00000000000000000011000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 60 00000000000000000001000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 61 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 62 00000000000000000000010000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 63 00000000000000000000100000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 64 00000000000000000000110000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 65 00000000000000000000010000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 66 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 67 00000000000000000000000001000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 68 00000000000000000000000011000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 69 00000000000000000000000010000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 70 00000000000000000000000110000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 71 00000000000000000000000111000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 72 00000000000000000000000101000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 73 00000000000000000000000100000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 74 00000000000000000000001100000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 75 00000000000000000000001101000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 76 00000000000000000000001111000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 77 00000000000000000000001110000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 78 00000000000000000000001010000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 79 00000000000000000000001011000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 80 00000000000000000000001001000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 81 00000000000000000000001000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 82 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 83 00000000000000000000000000001000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 84 00000000000000000000000000010000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 85 00000000000000000000000000011000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 86 00000000000000000000000000001000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 87 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 88 00000000000000000000000000000010 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 10 step 89 00000000000000000000000000000100 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 1 step 90 00000000000000000000000000000110 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 91 00000000000000000000000000000010 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: 0 step 92 00000000000000000000000000000000 fail ^ ^ ^ test 50: *** FAIL *************************** 42 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O O O all fails O O O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 50, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO changed: step 1 00000000000000000000000000000000 fail ^ ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0001 1 changed: 1 step 2 00010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0011 1 changed: 1 step 3 00110000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0010 1 changed: 0 step 4 00100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0110 1 changed: 1 step 5 01100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0111 1 changed: 1 step 6 01110000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 1 changed: 0 step 7 01010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0100 1 changed: 0 step 8 01000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1100 1 changed: 1 step 9 11000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1101 1 changed: 1 step 10 11010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1111 0 changed: 1 step 11 11110000000000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1110 1 changed: 0 step 12 11100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1010 1 changed: 0 step 13 10100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1011 1 changed: 1 step 14 10110000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1001 1 changed: 0 step 15 10010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1000 1 changed: 0 step 16 10000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 17 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 18 00000100000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 19 00001000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 20 00001100000000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 21 00000100000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 22 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 23 00000001000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 24 00000010000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 25 00000011000000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 26 00000001000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 27 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 28 00000000010000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 29 00000000100000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 30 00000000110000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 31 00000000010000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 32 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0011 changed: 1 step 33 00000000000010000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0111 changed: 1 step 34 00000000000110000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 changed: 0 step 35 00000000000100000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 changed: step 36 00000000000100000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1110 changed: 1 1 step 37 00000000001110000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1011 changed: 0 step 38 00000000001010000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1001 changed: 0 step 39 00000000001000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 40 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0001 1 changed: 1 step 41 00000000000000000100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0011 1 changed: 1 step 42 00000000000000001100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0010 1 changed: 0 step 43 00000000000000001000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0110 1 changed: 1 step 44 00000000000000011000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0111 1 changed: 1 step 45 00000000000000011100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 1 changed: 0 step 46 00000000000000010100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0100 1 changed: 0 step 47 00000000000000010000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1100 1 changed: 1 step 48 00000000000000110000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1101 1 changed: 1 step 49 00000000000000110100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1111 0 changed: 1 step 50 00000000000000111100000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1110 1 changed: 0 step 51 00000000000000111000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1010 1 changed: 0 step 52 00000000000000101000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1011 1 changed: 1 step 53 00000000000000101100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1001 1 changed: 0 step 54 00000000000000100100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1000 1 changed: 0 step 55 00000000000000100000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 56 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 57 00000000000000000001000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 58 00000000000000000010000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 59 00000000000000000011000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 60 00000000000000000001000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 61 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 62 00000000000000000000010000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 63 00000000000000000000100000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 64 00000000000000000000110000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 65 00000000000000000000010000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 66 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00011 changed: 1 step 67 00000000000000000000000001000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00111 changed: 1 step 68 00000000000000000000000011000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00101 changed: 0 step 69 00000000000000000000000010000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01101 changed: 1 step 70 00000000000000000000000110000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01111 changed: 1 step 71 00000000000000000000000111000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01011 changed: 0 step 72 00000000000000000000000101000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01001 changed: 0 step 73 00000000000000000000000100000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11001 changed: 1 step 74 00000000000000000000001100000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11011 changed: 1 step 75 00000000000000000000001101000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11110 changed: 1 step 76 00000000000000000000001111000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11101 changed: 0 step 77 00000000000000000000001110000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10101 changed: 0 step 78 00000000000000000000001010000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10111 changed: 1 step 79 00000000000000000000001011000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10011 changed: 0 step 80 00000000000000000000001001000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10001 changed: 0 step 81 00000000000000000000001000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 82 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 83 00000000000000000000000000001000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 84 00000000000000000000000000010000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 85 00000000000000000000000000011000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 86 00000000000000000000000000001000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 87 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 011 changed: 1 step 88 00000000000000000000000000000010 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 101 changed: 10 step 89 00000000000000000000000000000100 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 110 changed: 1 step 90 00000000000000000000000000000110 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 011 changed: 0 step 91 00000000000000000000000000000010 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 92 00000000000000000000000000000000 fail ^ ^ ^ test 51: *** FAIL *************************** 92 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O O O all fails O O O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 51, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: step 1 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0001 1 changed: 1 step 2 00010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0011 1 changed: 1 step 3 00110000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0010 1 changed: 0 step 4 00100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0110 1 changed: 1 step 5 01100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0111 1 changed: 1 step 6 01110000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 1 changed: 0 step 7 01010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0100 1 changed: 0 step 8 01000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1100 1 changed: 1 step 9 11000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1101 1 changed: 1 step 10 11010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1111 0 changed: 1 step 11 11110000000000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1110 1 changed: 0 step 12 11100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1010 1 changed: 0 step 13 10100000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1011 1 changed: 1 step 14 10110000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1001 1 changed: 0 step 15 10010000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1000 1 changed: 0 step 16 10000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 17 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 18 00000100000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 19 00001000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 20 00001100000000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 21 00000100000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 22 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 23 00000001000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 24 00000010000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 25 00000011000000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 26 00000001000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 27 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 28 00000000010000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 29 00000000100000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 30 00000000110000000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 31 00000000010000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 32 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0011 changed: 1 step 33 00000000000010000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0111 changed: 1 step 34 00000000000110000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 changed: 0 step 35 00000000000100000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 changed: step 36 00000000000100000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1110 changed: 1 1 step 37 00000000001110000000000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1011 changed: 0 step 38 00000000001010000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1001 changed: 0 step 39 00000000001000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 40 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0001 1 changed: 1 step 41 00000000000000000100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0011 1 changed: 1 step 42 00000000000000001100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0010 1 changed: 0 step 43 00000000000000001000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0110 1 changed: 1 step 44 00000000000000011000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0111 1 changed: 1 step 45 00000000000000011100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0101 1 changed: 0 step 46 00000000000000010100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 0100 1 changed: 0 step 47 00000000000000010000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1100 1 changed: 1 step 48 00000000000000110000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1101 1 changed: 1 step 49 00000000000000110100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1111 0 changed: 1 step 50 00000000000000111100000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1110 1 changed: 0 step 51 00000000000000111000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1010 1 changed: 0 step 52 00000000000000101000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1011 1 changed: 1 step 53 00000000000000101100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1001 1 changed: 0 step 54 00000000000000100100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 1000 1 changed: 0 step 55 00000000000000100000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 56 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 57 00000000000000000001000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 58 00000000000000000010000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 59 00000000000000000011000000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 60 00000000000000000001000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 61 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 62 00000000000000000000010000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 63 00000000000000000000100000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 64 00000000000000000000110000000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 65 00000000000000000000010000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 66 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00011 changed: 1 step 67 00000000000000000000000001000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00111 changed: 1 step 68 00000000000000000000000011000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00101 changed: 0 step 69 00000000000000000000000010000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01101 changed: 1 step 70 00000000000000000000000110000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01111 changed: 1 step 71 00000000000000000000000111000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01011 changed: 0 step 72 00000000000000000000000101000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01001 changed: 0 step 73 00000000000000000000000100000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11001 changed: 1 step 74 00000000000000000000001100000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11011 changed: 1 step 75 00000000000000000000001101000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11110 changed: 1 step 76 00000000000000000000001111000000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11101 changed: 0 step 77 00000000000000000000001110000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10101 changed: 0 step 78 00000000000000000000001010000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10111 changed: 1 step 79 00000000000000000000001011000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10011 changed: 0 step 80 00000000000000000000001001000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10001 changed: 0 step 81 00000000000000000000001000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 82 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 1 step 83 00000000000000000000000000001000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 10 1 changed: 10 step 84 00000000000000000000000000010000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 11 0 changed: 1 step 85 00000000000000000000000000011000 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 01 1 changed: 0 step 86 00000000000000000000000000001000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 87 00000000000000000000000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 011 changed: 1 step 88 00000000000000000000000000000010 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 101 changed: 10 step 89 00000000000000000000000000000100 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 110 changed: 1 step 90 00000000000000000000000000000110 fail ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 011 changed: 0 step 91 00000000000000000000000000000010 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO source: 00000000000001000000000000100001 changed: 0 step 92 00000000000000000000000000000000 fail ^ ^ ^ test 52: *** FAIL *************************** 92 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO this fail O O O all fails O O O was hi 11111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 00000000000000000000000000000000 total fails 52, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails O O O was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 52, total passes 0 Main menu Sat Jul 01 08:07:19 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test delay (0 to 100)? test_delay must be 0 to 100) Main menu Sat Jul 01 08:37:05 2017 test file is: tests\m160.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = ?.??v, LO = ?.??V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 O AF2 E1-6 7450 PIN 6 2C pins: 10 O AL2 E1-10 7450 PIN 8 2D pins: 11 I AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 I AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII error: direction did not match PIN line bad test file Main menu Sat Jul 01 08:37:15 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 08:38:32 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = ?.??v, LO = ?.??V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: ; OUTPUT LO, EXPANDER 1X,2X = ?.??V; EXPANDER 1X-N,2X-N = ?.????V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT GOES HI, EXPANDER 1X,2X = ?.??V; EXPANDER 1X-N,2X-N = ?.????V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT GOES HI, EXPANDER 1X = ?.??V; EXPANDER 1X-N = ?.????V test 18: 1111 test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT GOES HI, EXPANDER 2X = ?.??V; EXPANDER 2X-N = ?.????V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT GOES HI, EXPANDER 1X = ?.??V; EXPANDER 1X-N = ?.????V test 45: 1111 comment: ; OUTPUT GOES LO, EXPANDER 1X = ?.??V; EXPANDER 1X-N = ?.????V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT GOES HI, EXPANDER 2X = ?.??V; EXPANDER 2X-N = ?.????V test 61: 1111 comment: ; OUTPUT GOES LO, EXPANDER 2X = ?.??V; EXPANDER 2X-N = ?.????V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 139 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = ?.??v, LO = ?.??V PINS Main menu Sat Jul 01 08:38:35 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 08:40:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 63 0000001010000000 step 64 0000001000000000 step 65 0000001001000000 step 66 0000001001000000 step 67 0000000000000000 test 37: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^ ^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 37 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0000000000000000 step 2 1111111111110000 step 3 1110111111110000 step 4 1100111111110000 step 5 1101111111110000 step 6 1001111111110000 step 7 1000101111110000 step 8 1010101111110000 step 9 1011101111110000 step 10 0011101111110000 step 11 0010001111110000 step 12 0000001111110000 step 13 0001001111110000 step 14 0101001111110000 step 15 0100001111110000 step 16 0110001111110000 step 17 0111001111110000 step 18 1111111111110000 step 19 1111111110110000 step 20 1111111100110000 step 21 1111111101110000 step 22 1111111001110000 step 23 1111111000100000 step 24 1111111010100000 step 25 1111111011100000 step 26 1111110011100000 step 27 1111110010100000 step 28 1111110000100000 step 29 1111110001100000 step 30 1111110101100000 step 31 1111110100100000 step 32 1111110110100000 step 33 1111110111100000 step 34 1111111111110000 step 35 0000110000110000 step 36 0010110000110000 step 37 0011100000100000 step 38 0111100000100000 step 39 0110100000100000 step 40 0100100000100000 step 41 0101100000100000 step 42 1101100000100000 step 43 1100000000100000 step 44 1110000000100000 step 45 1111110000100000 step 46 1011110000100000 step 47 1010000000100000 step 48 1000000000100000 step 49 1001000000100000 step 50 1001000000100000 step 51 0000000000100000 step 52 0000000010100000 step 53 0000000011100000 step 54 0000000111100000 step 55 0000000110100000 step 56 0000000100100000 step 57 0000000101100000 step 58 0000001101100000 step 59 0000001100100000 step 60 0000001110100000 step 61 0000001111110000 step 62 0000001011110000 step 63 0000001010110000 step 64 0000001000110000 step 65 0000001001110000 step 66 0000001001110000 step 67 0000000000100000 test 38: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 38 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; START WITH ALL INPUTS ZERO source: source: ; OUTPUT LO, EXPANDER 1X,2X = ?.??V; EXPANDER 1X-N,2X-N = ?.????V source: 0000XX0000XX0000 changed: 0 step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT GOES HI, EXPANDER 1X,2X = ?.??V; EXPANDER 1X-N,2X-N = ?.????V source: 1111XX1111XX changed: 111111111111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: 1110 changed: 0 step 3 1110111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 00 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES HI, EXPANDER 1X = ?.??V; EXPANDER 1X-N = ?.????V source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 00 step 19 1111111110010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 20 1111111100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES HI, EXPANDER 2X = ?.??V; EXPANDER 2X-N = ?.????V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 38 Main menu Sat Jul 01 08:43:17 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: ; OUTPUT LO, EXPANDER 1X,2X = 0.00V; EXPANDER 1X-N,2X-N = 3.2V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT GOES HI, EXPANDER 1X,2X = 3.2V; EXPANDER 1X-N,2X-N = 0.00V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT GOES HI, EXPANDER 1X = 3.2V; EXPANDER 1X-N = 0.00V test 18: 1111 comment: ; OUTPUT GOES LO, EXPANDER 1X = 0.00V; EXPANDER 1X-N = 3.2V comment: test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT GOES HI, EXPANDER 2X = 3.2V; EXPANDER 2X-N = 0.00V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: ; OUTPUT GOES LO, EXPANDER 1X,2X = 0.00V; EXPANDER 1X-N,2X-N = 3.2V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT GOES HI, EXPANDER 1X = 3.2V; EXPANDER 1X-N = 0.00V test 45: 1111 comment: ; OUTPUT GOES LO, EXPANDER 1X = 0.00V; EXPANDER 1X-N = 3.2V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT GOES HI, EXPANDER 2X = 3.2V; EXPANDER 2X-N = 0.00V test 61: 1111 comment: ; OUTPUT GOES LO, EXPANDER 2X = 0.00V; EXPANDER 2X-N = 3.2V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 142 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 08:47:12 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 08:47:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; START WITH ALL INPUTS ZERO source: source: ; OUTPUT LO, EXPANDER 1X,2X = 0.00V; EXPANDER 1X-N,2X-N = 3.2V source: 0000XX0000XX0000 changed: step 1 0000110000010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT GOES HI, EXPANDER 1X,2X = 3.2V; EXPANDER 1X-N,2X-N = 0.00V source: 1111XX1111XX changed: 1111 11111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: 1110 changed: 0 step 3 1110111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 00 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES HI, EXPANDER 1X = 3.2V; EXPANDER 1X-N = 0.00V source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES LO, EXPANDER 1X = 0.00V; EXPANDER 1X-N = 3.2V source: source: 1110 changed: 00 step 19 1111111110010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 20 1111111100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES HI, EXPANDER 2X = 3.2V; EXPANDER 2X-N = 0.00V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: ; OUTPUT GOES LO, EXPANDER 1X,2X = 0.00V; EXPANDER 1X-N,2X-N = 3.2V source: 0000 0000 changed: 0000 00000 step 35 0000110000010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 00 0 step 36 0010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES HI, EXPANDER 1X = 3.2V; EXPANDER 1X-N = 0.00V source: 1111 changed: 111 step 45 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES LO, EXPANDER 1X = 0.00V; EXPANDER 1X-N = 3.2V source: 1011 changed: 0 step 46 1011110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 000 step 47 1010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES HI, EXPANDER 2X = 3.2V; EXPANDER 2X-N = 0.00V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT GOES LO, EXPANDER 2X = 0.00V; EXPANDER 2X-N = 3.2V source: 1011 changed: 0 0 step 62 0000001011010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 0 0 step 63 0000001010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 66 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000000000 okay test 1: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; START WITH ALL INPUTS ZERO source: source: ; OUTPUT LO, EXPANDER 1X,2X = 0.00V; EXPANDER 1X-N,2X-N = 3.2V source: 0000XX0000XX0000 changed: step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT GOES HI, EXPANDER 1X,2X = 3.2V; EXPANDER 1X-N,2X-N = 0.00V source: 1111XX1111XX changed: 111111111111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 1 Main menu Sat Jul 01 08:49:40 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 08:59:40 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 18: 1111 comment: comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 45: 1111 comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 61: 1111 comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 148 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 08:59:45 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 08:59:51 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000XX0000XX0000 changed: step 1 0000110000010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V source: 1111XX1111XX changed: 1111 11111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V source: 1110 changed: 00 step 3 1110011111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V source: 1110 changed: 0 step 19 1111111110110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 20 1111111100100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 10 step 25 1111111011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000 0000 changed: 00000 0000 step 35 0000010000110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 0 00 step 36 0010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V source: 1111 changed: 111 step 45 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V source: 1011 changed: 0 0 step 46 1011010000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 0 0 step 47 1010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V source: 1011 changed: 0 step 62 0000001011110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 000 step 63 0000001010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 66 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000000000 okay test 1: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 1 Main menu Sat Jul 01 09:01:55 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 09:03:59 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 18: 1111 comment: comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 45: 1111 comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 61: 1111 comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 148 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 09:04:04 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 18: 1111 comment: comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 45: 1111 comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 61: 1111 comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 148 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 09:04:16 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 18: 1111 comment: comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 45: 1111 comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 61: 1111 comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 148 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 09:04:21 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:04:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000XX0000XX0000 changed: step 1 0000010000110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V source: 1111XX1111XX changed: 11111 1111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V source: 1110 changed: 00 step 3 1110011111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V source: 1110 changed: 0 step 19 1111111110110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 20 1111111100100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 00 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000 0000 changed: 00000 0000 step 35 0000010000110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 0 00 step 36 0010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V source: 1111 changed: 111 step 45 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V source: 1011 changed: 0 0 step 46 1011010000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 0 0 step 47 1010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V source: 1011 changed: 0 step 62 0000001011110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 0 0 step 63 0000001010100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 66 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000000000 okay test 1: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000XX0000XX0000 changed: step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 1 Main menu Sat Jul 01 09:07:20 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 18: 1111 comment: comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 45: 1111 comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 61: 1111 comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 148 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 09:07:26 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0020 Main menu Sat Jul 01 09:07:56 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = NOT(1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = NOT(2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 18: 1111 comment: comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: comment: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V test 45: 1111 comment: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V test 61: 1111 comment: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 148 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 09:08:02 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:08:05 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000XX0000XX0000 changed: step 1 0000100000110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V source: 1111XX1111XX changed: 1111 11111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V source: 1110 changed: 0 0 step 3 1110101111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V source: 1110 changed: 0 step 19 1111111110110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 20 1111111100100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V source: 1111 changed: 1 1 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000 0000 changed: 0000 00000 step 35 0000100000110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 0 0 step 36 0010000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2 1X 3.2v AR2 1X-N 0.0V source: 1111 changed: 111 1 step 45 1111110000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V source: 1011 changed: 0 0 step 46 1011100000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 00 step 47 1010000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 0 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2 2X 3.2V AM2 2X-N 0.0V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 LO: AN2 2X 0.0V AM2 2X-N 3.2V source: 1011 changed: 0 step 62 0000001011110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 0 0 step 63 0000001010100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 66 0000001001100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000100000 okay test 1: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2 1X 0.0v AR2 1X-N 3.2V AN2 2X 0.0V AM2 2X-N 3.2V source: 0000XX0000XX0000 changed: step 1 0000000000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2 1X 3.2v AR2 1X-N 0.0V AN2 2X 3.2V AM2 2X-N 0.0V source: 1111XX1111XX changed: 1111111111 1 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2 1X 0.0v AR2 1X-N 3.2V source: 1110 changed: 0 0 step 3 1110101111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 1 Main menu Sat Jul 01 09:09:31 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 09:14:38 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7460.TST reading test file: tests\7460.TST comment: 7460 DUAL 4-INPUT EXPANDER comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: comment: CONNECT DMM TO EXPANDER OUTPUTS!!!!!! comment: EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V comment: pins: PINS pins: 1 I AA1 E1-1 7450 PIN 1 1A pins: 2 I AB2 E1-2 7450 PIN 2 1B pins: 3 I AC1 E1-3 7450 PIN 3 1C pins: 4 I AS2 E1-15 7450 PIN 13 1D pins: 5 O AP2 E1-13 7450 PIN 11 1X = (1A AND 1B AND 1C AND 1C) pins: 6 O AR2 E1-14 7450 PIN 12 1X-N = (1A AND 1B AND 1C AND 1C) pins: 7 I AD2 E1-4 7450 PIN 4 2A pins: 8 I AE2 E1-5 7450 PIN 5 2B pins: 9 I AF2 E1-6 7450 PIN 6 2C pins: 10 I AL2 E1-10 7450 PIN 8 2D pins: 11 O AN2 E1-12 7450 PIN 10 2X = (2A AND 2B AND 2C AND 2C) pins: 12 O AM2 E1-11 7450 PIN 9 2X-N = (2A AND 2B AND 2C AND 2C) (EXPANDER, HI= ?V, LO= ?V) pins: 13 I AH2 E1-7 7450 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 7450 PIN 14 VCC pins: direction: IIIIOOIIIIOOIIII comment: comment: comment: comment: ; START WITH ALL INPUTS ZERO comment: comment: comment: comment: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V test 1: 0000XX0000XX0000 comment: comment: ; ALL INPUTS HI comment: comment: ; OUTPUT 1,2 HI: AP2,AR2 1X 3.2 AN2,AM2 2X 3.2V test 2: 1111XX1111XX comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE comment: comment: comment: comment: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v test 3: 1110 test 4: 1100 test 5: 1101 test 6: 1001 test 7: 1000 test 8: 1010 test 9: 1011 test 10: 0011 test 11: 0010 test 12: 0000 test 13: 0001 test 14: 0101 test 15: 0100 test 16: 0110 test 17: 0111 comment: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v test 18: 1111 comment: comment: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V test 19: 1110 test 20: 1100 test 21: 1101 test 22: 1001 test 23: 1000 test 24: 1010 test 25: 1011 test 26: 0011 test 27: 0010 test 28: 0000 test 29: 0001 test 30: 0101 test 31: 0100 test 32: 0110 test 33: 0111 comment: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V test 34: 1111 comment: comment: comment: ; ALL INPUTS LO comment: comment: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V test 35: 0000 0000 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE comment: test 36: 0010 test 37: 0011 test 38: 0111 test 39: 0110 test 40: 0100 test 41: 0101 test 42: 1101 test 43: 1100 test 44: 1110 comment: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v test 45: 1111 comment: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v test 46: 1011 test 47: 1010 test 48: 1000 test 49: 1001 test 50: 1001 test 51: 0000 test 52: 0010 test 53: 0011 test 54: 0111 test 55: 0110 test 56: 0100 test 57: 0101 test 58: 1101 test 59: 1100 test 60: 1110 comment: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V test 61: 1111 comment: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V test 62: 1011 test 63: 1010 test 64: 1000 test 65: 1001 test 66: 1001 test 67: 0000 comment: comment: comment: comment: ;**************************** comment: ; SHOULD TEST ALL 256 PATTERNS comment: ;**************************** comment: comment: end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 1, mask 0x0040 column 5: offset 1, mask 0x0010 column 6: offset 1, mask 0x0020 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 1, mask 0x0002 column 11: offset 1, mask 0x0008 column 12: offset 1, mask 0x0004 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x5FA0 0xFF3C 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 2: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 3: 0xA05C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 4: 0x805C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 5: 0x805C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 6: 0x801C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 7: 0x801C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 8: 0xA01C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 9: 0xA01C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 10: 0x201C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 11: 0x201C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 12: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 13: 0x001C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 14: 0x005C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 15: 0x005C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 16: 0x205C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 17: 0x205C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 18: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 19: 0xA05C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 20: 0xA058 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 21: 0xA058 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 22: 0xA050 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 23: 0xA050 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 24: 0xA054 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 25: 0xA054 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 26: 0xA044 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 27: 0xA044 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 28: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 29: 0xA040 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 30: 0xA048 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 31: 0xA048 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 32: 0xA04C 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 33: 0xA04C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 34: 0xA05C 0x0042 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 35: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 36: 0x2000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 37: 0x2000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 38: 0x2040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 39: 0x2040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 40: 0x0040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 41: 0x0040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 42: 0x8040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 43: 0x8040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 44: 0xA040 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 45: 0xA040 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 46: 0xA000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 47: 0xA000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 48: 0x8000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 49: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 50: 0x8000 0x0040 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 51: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 52: 0x0004 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 53: 0x0004 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 54: 0x000C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 55: 0x000C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 56: 0x0008 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 57: 0x0008 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 58: 0x0018 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 59: 0x0018 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 60: 0x001C 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 61: 0x001C 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 62: 0x0014 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 63: 0x0014 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 64: 0x0010 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 65: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 66: 0x0010 0x0002 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 67: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x003C 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I I G PIGIIIIIIIOOOOII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 67 'test steps' 148 lines 7460 DUAL 4-INPUT EXPANDER REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V CONNECT DMM TO EXPANDER OUTPUTS!!!!!! EXPANDER OUTPUTS ARE HI = 3.2v, LO = 0.00V PINS Main menu Sat Jul 01 09:14:43 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 01 09:14:45 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0043 Main menu Sat Jul 01 09:14:46 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:14:50 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 0 111 step 61 0000001111110000 source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1011 changed: 0 step 62 0000001011110000 source: 1010 changed: 0 step 63 0000001010110000 source: 1000 changed: 0 step 64 0000001000110000 source: 1001 changed: 100 step 65 0000001001000000 source: 1001 changed: step 66 0000001001000000 source: 0000 changed: 0 0 step 67 0000000000000000 test 53: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^ ^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 53 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000XX0000XX0000 changed: step 1 0000000000000000 source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2,AR2 1X 3.2 AN2,AM2 2X 3.2V source: 1111XX1111XX changed: 111111111111 step 2 1111111111110000 source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1110 changed: 0 step 3 1110111111110000 source: 1100 changed: 0 step 4 1100111111110000 source: 1101 changed: 1 0 step 5 1101101111110000 source: 1001 changed: 0 step 6 1001101111110000 source: 1000 changed: 0 step 7 1000101111110000 source: 1010 changed: 1 step 8 1010101111110000 source: 1011 changed: 1 step 9 1011101111110000 source: 0011 changed: 0 step 10 0011101111110000 source: 0010 changed: 0 step 11 0010101111110000 source: 0000 changed: 0 step 12 0000101111110000 source: 0001 changed: 1 step 13 0001101111110000 source: 0101 changed: 1 step 14 0101101111110000 source: 0100 changed: 00 step 15 0100001111110000 source: 0110 changed: 1 step 16 0110001111110000 source: 0111 changed: 1 step 17 0111001111110000 source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 1 11 step 18 1111111111110000 source: source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1110 changed: 0 step 19 1111111110110000 source: 1100 changed: 0 0 step 20 1111111100100000 source: 1101 changed: 1 step 21 1111111101100000 source: 1001 changed: 0 step 22 1111111001100000 source: 1000 changed: 00 step 23 1111111000000000 source: 1010 changed: 1 step 24 1111111010000000 source: 1011 changed: 1 step 25 1111111011000000 source: 0011 changed: 0 step 26 1111110011000000 source: 0010 changed: 0 step 27 1111110010000000 source: 0000 changed: 0 step 28 1111110000000000 source: 0001 changed: 1 step 29 1111110001000000 source: 0101 changed: 1 step 30 1111110101000000 source: 0100 changed: 0 step 31 1111110100000000 source: 0110 changed: 1 step 32 1111110110000000 source: 0111 changed: 1 step 33 1111110111000000 source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 1 11 step 34 1111111111110000 source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000 0000 changed: 0000 0000 step 35 0000110000110000 source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 0 00 step 36 0010100000000000 source: 0011 changed: 1 step 37 0011100000000000 source: 0111 changed: 1 step 38 0111100000000000 source: 0110 changed: 00 step 39 0110000000000000 source: 0100 changed: 0 step 40 0100000000000000 source: 0101 changed: 1 step 41 0101000000000000 source: 1101 changed: 1 step 42 1101000000000000 source: 1100 changed: 0 step 43 1100000000000000 source: 1110 changed: 1 step 44 1110000000000000 source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 111 step 45 1111110000000000 source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1011 changed: 0 step 46 1011110000000000 source: 1010 changed: 0 0 step 47 1010100000000000 source: 1000 changed: 0 step 48 1000100000000000 source: 1001 changed: 1 step 49 1001100000000000 source: 1001 changed: step 50 1001100000000000 source: 0000 changed: 0 00 step 51 0000000000000000 source: 0010 changed: 1 step 52 0000000010000000 source: 0011 changed: 1 step 53 0000000011000000 source: 0111 changed: 1 step 54 0000000111000000 source: 0110 changed: 0 step 55 0000000110000000 source: 0100 changed: 0 step 56 0000000100000000 source: 0101 changed: 1 step 57 0000000101000000 source: 1101 changed: 1 step 58 0000001101000000 source: 1100 changed: 0 step 59 0000001100000000 source: 1110 changed: 1 step 60 0000001110000000 source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 1 111 step 61 0000101111110000 source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1011 changed: 0 step 62 0000101011110000 source: 1010 changed: 0 step 63 0000101010110000 source: 1000 changed: 0 0 00 step 64 0000001000000000 source: 1001 changed: 1 step 65 0000001001000000 source: 1001 changed: step 66 0000001001000000 source: 0000 changed: 0 0 step 67 0000000000000000 test 54: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 54 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000XX0000XX0000 changed: step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2,AR2 1X 3.2 AN2,AM2 2X 3.2V source: 1111XX1111XX changed: 111111111111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1110 changed: 00 step 3 1110011111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1110 changed: 0 step 19 1111111110110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 00 step 20 1111111100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000 0000 changed: 00000 0000 step 35 0000010000110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 0 00 step 36 0010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 111 step 45 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1011 changed: 0 0 step 46 1011010000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 0 0 step 47 1010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1011 changed: 0 step 62 0000001011110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 000 step 63 0000001010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 66 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000000000 okay test 55: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 55 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000XX0000XX0000 changed: step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2,AR2 1X 3.2 AN2,AM2 2X 3.2V source: 1111XX1111XX changed: 111111111111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1110 changed: 0 0 step 3 1110101111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1110 changed: 0 step 19 1111111110110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 00 step 20 1111111100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000 0000 changed: 0000 00000 step 35 0000100000110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 0 00 step 36 0010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 111 step 45 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1011 changed: 0 0 step 46 1011100000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 00 step 47 1010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1011 changed: 0 step 62 0000001011110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 000 step 63 0000001010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 66 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000000000 okay test 56: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 56 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000XX0000XX0000 changed: step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2,AR2 1X 3.2 AN2,AM2 2X 3.2V source: 1111XX1111XX changed: 111111111111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1110 changed: 0 step 3 1110111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 00 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1110 changed: 00 step 19 1111111110010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 20 1111111100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000 0000 changed: 0000 00000 step 35 0000110000010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 00 0 step 36 0010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 111 step 45 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1011 changed: 0 step 46 1011110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 000 step 47 1010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1011 changed: 0 0 step 62 0000001011010000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 0 0 step 63 0000001010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 66 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000000000 okay test 57: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 57 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000XX0000XX0000 changed: step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; ALL INPUTS HI source: source: ; OUTPUT 1,2 HI: AP2,AR2 1X 3.2 AN2,AM2 2X 3.2V source: 1111XX1111XX changed: 111111111111 step 2 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE source: source: source: source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1110 changed: 0 step 3 1110111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 00 step 4 1100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 5 1101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 6 1001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 7 1000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 8 1010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 9 1011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 10 0011001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 11 0010001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 12 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 13 0001001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 14 0101001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 15 0100001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 16 0110001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 17 0111001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 1 11 step 18 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1110 changed: 0 0 step 19 1111111110100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 0 step 20 1111111100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 21 1111111101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 0 step 22 1111111001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 23 1111111000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 1 step 24 1111111010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1011 changed: 1 step 25 1111111011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 0 step 26 1111110011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 0 step 27 1111110010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 step 28 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0001 changed: 1 step 29 1111110001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 30 1111110101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 31 1111110100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 1 step 32 1111110110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 33 1111110111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 1 11 step 34 1111111111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: ; ALL INPUTS LO source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000 0000 changed: 0000 0000 0 step 35 0000110000100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE source: source: 0010 changed: 1 00 0 step 36 0010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 37 0011000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 38 0111000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 39 0110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 40 0100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 41 0101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 42 1101000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 43 1100000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 44 1110000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 HI: AP2,AR2 1X 3.2v source: 1111 changed: 111 step 45 1111110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 1 LO: AP2,AR2 1X 0.0v source: 1011 changed: 0 step 46 1011110000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 000 step 47 1010000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 48 1000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 49 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 50 1001000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 51 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0010 changed: 1 step 52 0000000010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0011 changed: 1 step 53 0000000011000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0111 changed: 1 step 54 0000000111000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0110 changed: 0 step 55 0000000110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0100 changed: 0 step 56 0000000100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0101 changed: 1 step 57 0000000101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1101 changed: 1 step 58 0000001101000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1100 changed: 0 step 59 0000001100000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1110 changed: 1 step 60 0000001110000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 HI: AN2,AM2 2X 3.2V source: 1111 changed: 111 step 61 0000001111110000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: ; OUTPUT 2 LO: AN2,AM2 2X 0.0V source: 1011 changed: 0 0 step 62 0000001011100000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1010 changed: 00 step 63 0000001010000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1000 changed: 0 step 64 0000001000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: 1 step 65 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 1001 changed: step 66 0000001001000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: 0000 changed: 0 0 step 67 0000000000000000 okay test 58: pass SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 0000000000000000 total fails 0, total passes 58 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII source: source: source: source: ; START WITH ALL INPUTS ZERO source: source: source: source: ; OUTPUT 1,2 LO: AP2,AR2 1X 0.0v AN2,AM2 2X 0.0V source: 0000XX0000XX0000 changed: step 1 0000000000000000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCSPRDEFLNMHJKT SIDE 1212222222222222 DIRECTION IIIIOOIIIIOOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 58 Main menu Sat Jul 01 09:22:55 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M160.LTST could not open test file. valid test files are: reverting back to test file: tests\7460.TST Main menu Sat Jul 01 09:22:59 2017 test file is: tests\7460.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M160.TST reading test file: tests\M160.TST comment: M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) comment: pins: PINS pins: 1 I AA1 E2-1 4-X-X-X-X pins: 2 I AB1 E2-2 4-X-X-X-X pins: 3 I AC1 E2-3 4-X-X-X-X pins: 4 I AD1 E2-13 4-X-X-X-X pins: 5 I AE1 E1-13 X-2-X-X-X pins: 6 I AF1 E1-1 X-2-X-X-X pins: 7 I AH1 E1-2 X-X-2-X-X pins: 8 I AJ1 E1-3 X-X-2-X-X pins: 9 I AK1 E1-5 X-X-X-2-X pins: 10 I AL1 E1-4 X-X-X-2-X pins: 11 I AM1 E2-6 X-X-X-X-3 pins: 12 I AN1 E2-5 X-X-X-X-3 pins: 13 I AP1 E2-4 X-X-X-X-3 pins: 14 O AR1 E1-8 OUPUT pins: 15 I AD2 E4-3 4-X-X-X pins: 16 I AE2 E4-2 4-X-X-X pins: 17 I AF2 E4-1 4-X-X-X pins: 18 I AH2 E4-13 4-X-X-X pins: 19 I AJ2 E3-1 X-2-X-X pins: 20 I AK2 E3-13 X-2-X-X pins: 21 I AL2 E3-10 X-X-2-X pins: 22 I AM2 E3-9 X-X-2-X pins: 23 I AN2 E4-8 X-X-X-4 pins: 24 I AP2 E4-5 X-X-X-4 pins: 25 I AR2 E4-6 X-X-X-4 pins: 26 I AS2 E4-4 X-X-X-4 pins: 27 O AT2 E3-8 OUTPUT pins: 28 I AS1 E3-5 2-X pins: 29 I AU1 E3-4 2-X pins: 30 I AV1 E3-2 X-2 pins: 31 I AU2 E3-3 X-2 pins: 32 O AV2 E3-6 OUTPUT pins: direction: IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO test 1: 00000000000001000000000000100001 test 2: 0001 1 test 3: 0011 1 test 4: 0010 1 test 5: 0110 1 test 6: 0111 1 test 7: 0101 1 test 8: 0100 1 test 9: 1100 1 test 10: 1101 1 test 11: 1111 0 test 12: 1110 1 test 13: 1010 1 test 14: 1011 1 test 15: 1001 1 test 16: 1000 1 test 17: 00000000000001000000000000100001 test 18: 01 1 test 19: 10 1 test 20: 11 0 test 21: 01 1 test 22: 00000000000001000000000000100001 test 23: 01 1 test 24: 10 1 test 25: 11 0 test 26: 01 1 test 27: 00000000000001000000000000100001 test 28: 01 1 test 29: 10 1 test 30: 11 0 test 31: 01 1 test 32: 00000000000001000000000000100001 test 33: 0011 test 34: 0111 test 35: 0101 test 36: 0101 test 37: 1110 test 38: 1011 test 39: 1001 test 40: 00000000000001000000000000100001 test 41: 0001 1 test 42: 0011 1 test 43: 0010 1 test 44: 0110 1 test 45: 0111 1 test 46: 0101 1 test 47: 0100 1 test 48: 1100 1 test 49: 1101 1 test 50: 1111 0 test 51: 1110 1 test 52: 1010 1 test 53: 1011 1 test 54: 1001 1 test 55: 1000 1 test 56: 00000000000001000000000000100001 test 57: 01 1 test 58: 10 1 test 59: 11 0 test 60: 01 1 test 61: 00000000000001000000000000100001 test 62: 01 1 test 63: 10 1 test 64: 11 0 test 65: 01 1 test 66: 00000000000001000000000000100001 test 67: 00011 test 68: 00111 test 69: 00101 test 70: 01101 test 71: 01111 test 72: 01011 test 73: 01001 test 74: 11001 test 75: 11011 test 76: 11110 test 77: 11101 test 78: 10101 test 79: 10111 test 80: 10011 test 81: 10001 test 82: 00000000000001000000000000100001 test 83: 01 1 test 84: 10 1 test 85: 11 0 test 86: 01 1 test 87: 00000000000001000000000000100001 test 88: 011 test 89: 101 test 90: 110 test 91: 011 test 92: 00000000000001000000000000100001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 0, mask 0x0010 column 16: offset 0, mask 0x0008 column 17: offset 0, mask 0x0004 column 18: offset 0, mask 0x0002 column 19: offset 0, mask 0x0001 column 20: offset 1, mask 0x0001 column 21: offset 1, mask 0x0002 column 22: offset 1, mask 0x0004 column 23: offset 1, mask 0x0008 column 24: offset 1, mask 0x0010 column 25: offset 1, mask 0x0020 column 26: offset 1, mask 0x0040 column 27: offset 1, mask 0x0080 column 28: offset 1, mask 0x0200 column 29: offset 2, mask 0x8000 column 30: offset 2, mask 0x4000 column 31: offset 2, mask 0x0001 column 32: offset 2, mask 0x0002 direction bits (1=input) 0x00E0 0x0580 0x3FFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0480 0x0002 0x0000 0x0000 2: 0x1000 0x0480 0x0002 0x0000 0x0000 3: 0x3000 0x0480 0x0002 0x0000 0x0000 4: 0x2000 0x0480 0x0002 0x0000 0x0000 5: 0x6000 0x0480 0x0002 0x0000 0x0000 6: 0x7000 0x0480 0x0002 0x0000 0x0000 7: 0x5000 0x0480 0x0002 0x0000 0x0000 8: 0x4000 0x0480 0x0002 0x0000 0x0000 9: 0xC000 0x0480 0x0002 0x0000 0x0000 10: 0xD000 0x0480 0x0002 0x0000 0x0000 11: 0xF000 0x0080 0x0002 0x0000 0x0000 12: 0xE000 0x0480 0x0002 0x0000 0x0000 13: 0xA000 0x0480 0x0002 0x0000 0x0000 14: 0xB000 0x0480 0x0002 0x0000 0x0000 15: 0x9000 0x0480 0x0002 0x0000 0x0000 16: 0x8000 0x0480 0x0002 0x0000 0x0000 17: 0x0000 0x0480 0x0002 0x0000 0x0000 18: 0x0400 0x0480 0x0002 0x0000 0x0000 19: 0x0800 0x0480 0x0002 0x0000 0x0000 20: 0x0C00 0x0080 0x0002 0x0000 0x0000 21: 0x0400 0x0480 0x0002 0x0000 0x0000 22: 0x0000 0x0480 0x0002 0x0000 0x0000 23: 0x0100 0x0480 0x0002 0x0000 0x0000 24: 0x0200 0x0480 0x0002 0x0000 0x0000 25: 0x0300 0x0080 0x0002 0x0000 0x0000 26: 0x0100 0x0480 0x0002 0x0000 0x0000 27: 0x0000 0x0480 0x0002 0x0000 0x0000 28: 0x0000 0x4480 0x0002 0x0000 0x0000 29: 0x0000 0x8480 0x0002 0x0000 0x0000 30: 0x0000 0xC080 0x0002 0x0000 0x0000 31: 0x0000 0x4480 0x0002 0x0000 0x0000 32: 0x0000 0x0480 0x0002 0x0000 0x0000 33: 0x0000 0x0C80 0x0002 0x0000 0x0000 34: 0x0000 0x1C80 0x0002 0x0000 0x0000 35: 0x0000 0x1480 0x0002 0x0000 0x0000 36: 0x0000 0x1480 0x0002 0x0000 0x0000 37: 0x0000 0x3880 0x0002 0x0000 0x0000 38: 0x0000 0x2C80 0x0002 0x0000 0x0000 39: 0x0000 0x2480 0x0002 0x0000 0x0000 40: 0x0000 0x0480 0x0002 0x0000 0x0000 41: 0x0002 0x0480 0x0002 0x0000 0x0000 42: 0x0006 0x0480 0x0002 0x0000 0x0000 43: 0x0004 0x0480 0x0002 0x0000 0x0000 44: 0x000C 0x0480 0x0002 0x0000 0x0000 45: 0x000E 0x0480 0x0002 0x0000 0x0000 46: 0x000A 0x0480 0x0002 0x0000 0x0000 47: 0x0008 0x0480 0x0002 0x0000 0x0000 48: 0x0018 0x0480 0x0002 0x0000 0x0000 49: 0x001A 0x0480 0x0002 0x0000 0x0000 50: 0x001E 0x0400 0x0002 0x0000 0x0000 51: 0x001C 0x0480 0x0002 0x0000 0x0000 52: 0x0014 0x0480 0x0002 0x0000 0x0000 53: 0x0016 0x0480 0x0002 0x0000 0x0000 54: 0x0012 0x0480 0x0002 0x0000 0x0000 55: 0x0010 0x0480 0x0002 0x0000 0x0000 56: 0x0000 0x0480 0x0002 0x0000 0x0000 57: 0x0000 0x0481 0x0002 0x0000 0x0000 58: 0x0001 0x0480 0x0002 0x0000 0x0000 59: 0x0001 0x0401 0x0002 0x0000 0x0000 60: 0x0000 0x0481 0x0002 0x0000 0x0000 61: 0x0000 0x0480 0x0002 0x0000 0x0000 62: 0x0000 0x0484 0x0002 0x0000 0x0000 63: 0x0000 0x0482 0x0002 0x0000 0x0000 64: 0x0000 0x0406 0x0002 0x0000 0x0000 65: 0x0000 0x0484 0x0002 0x0000 0x0000 66: 0x0000 0x0480 0x0002 0x0000 0x0000 67: 0x0000 0x04C0 0x0002 0x0000 0x0000 68: 0x0000 0x04E0 0x0002 0x0000 0x0000 69: 0x0000 0x04A0 0x0002 0x0000 0x0000 70: 0x0000 0x04B0 0x0002 0x0000 0x0000 71: 0x0000 0x04F0 0x0002 0x0000 0x0000 72: 0x0000 0x04D0 0x0002 0x0000 0x0000 73: 0x0000 0x0490 0x0002 0x0000 0x0000 74: 0x0000 0x0498 0x0002 0x0000 0x0000 75: 0x0000 0x04D8 0x0002 0x0000 0x0000 76: 0x0000 0x0478 0x0002 0x0000 0x0000 77: 0x0000 0x04B8 0x0002 0x0000 0x0000 78: 0x0000 0x04A8 0x0002 0x0000 0x0000 79: 0x0000 0x04E8 0x0002 0x0000 0x0000 80: 0x0000 0x04C8 0x0002 0x0000 0x0000 81: 0x0000 0x0488 0x0002 0x0000 0x0000 82: 0x0000 0x0480 0x0002 0x0000 0x0000 83: 0x0000 0x0480 0x8002 0x0000 0x0000 84: 0x0000 0x0680 0x0002 0x0000 0x0000 85: 0x0000 0x0680 0x8000 0x0000 0x0000 86: 0x0000 0x0480 0x8002 0x0000 0x0000 87: 0x0000 0x0480 0x0002 0x0000 0x0000 88: 0x0000 0x0480 0x0003 0x0000 0x0000 89: 0x0000 0x0480 0x4002 0x0000 0x0000 90: 0x0000 0x0480 0x4001 0x0000 0x0000 91: 0x0000 0x0480 0x0003 0x0000 0x0000 92: 0x0000 0x0480 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIIIIIIIIIIOIGIIP GIIIIIIIIIIIIOIO G P G UUT inputs: 29 UUT outputs: 3 pins used: 32 not used: 34 92 'test steps' 130 lines M160 3 AND-OR TREES (4-2-2-2-3;4-2-2-4;2-2) PINS Main menu Sat Jul 01 09:23:03 2017 test file is: tests\M160.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:23:07 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRDEFHJKLMNPRSTSUVUV SIDE 11111111111111222222222222211122 DIRECTION IIIIIIIIIIIIIOIIIIIIIIIIIIOIIIIO all fails was lo 00000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 11111111111111111111111111111111 total fails 0, total passes 38 Main menu Sat Jul 01 09:23:09 2017 test file is: tests\M160.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M113.TST reading test file: tests\M113.TST comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Sat Jul 01 09:24:17 2017 test file is: tests\M113.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:24:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 82 001001001001001001001001001100 fail ^ step 83 001001001001001001001001001001 test 39: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 39, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 41 110110110110110110110110110100 fail ^ step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 82 001001001001001001001001001100 fail ^ step 83 001001001001001001001001001001 test 40: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 40, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 step 3 011110110110110110110110110110 step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 step 27 110110110110110110011110110110 step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 1 0 step 41 110110110110110110110110110100 fail ^ step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 step 44 011001001001001001001001001001 step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 step 68 001001001001001001011001001001 step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 82 001001001001001001001001001100 fail ^ step 83 001001001001001001001001001001 test 41: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 41, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 0 0 0 0 0 0 0 0 0 step 1 000000000000000000000000000000 fail ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O O O O O O O O O O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 41, total passes 0 Main menu Sat Jul 01 09:28:26 2017 test file is: tests\M113.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:28:27 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: 001001001001001001001001001001 changed: step 1 001001001001001001001001001001 source: 110110110110110110110110110110 changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 source: 011 changed: 0 1 step 3 011110110110110110110110110110 source: 001 changed: 0 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 source: 011 changed: 0 1 step 23 110110110110110011110110110110 source: 001 changed: 0 step 24 110110110110110001110110110110 source: 101 changed: 1 step 25 110110110110110101110110110110 source: 110 changed: 10 step 26 110110110110110110110110110110 source: 011 changed: 0 1 step 27 110110110110110110011110110110 source: 001 changed: 0 step 28 110110110110110110001110110110 source: 101 changed: 1 step 29 110110110110110110101110110110 source: 110 changed: 10 step 30 110110110110110110110110110110 source: 011 changed: 0 1 step 31 110110110110110110110011110110 source: 001 changed: 0 step 32 110110110110110110110001110110 source: 101 changed: 1 step 33 110110110110110110110101110110 source: 110 changed: 10 step 34 110110110110110110110110110110 source: 011 changed: 0 1 step 35 110110110110110110110110011110 source: 001 changed: 0 step 36 110110110110110110110110001110 source: 101 changed: 1 step 37 110110110110110110110110101110 source: 110 changed: 10 step 38 110110110110110110110110110110 source: 011 changed: 0 1 step 39 110110110110110110110110110011 source: 001 changed: 0 step 40 110110110110110110110110110001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 1 0 step 41 110110110110110110110110110100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 1 step 42 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 1 step 44 011001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 1 0 step 45 110001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 101 changed: 01 step 46 101001001001001001001001001001 source: 001 changed: 0 step 47 001001001001001001001001001001 source: 011 changed: 1 step 48 001011001001001001001001001001 source: 110 changed: 1 0 step 49 001110001001001001001001001001 source: 101 changed: 01 step 50 001101001001001001001001001001 source: 001 changed: 0 step 51 001001001001001001001001001001 source: 011 changed: 1 step 52 001001011001001001001001001001 source: 110 changed: 1 0 step 53 001001110001001001001001001001 source: 101 changed: 01 step 54 001001101001001001001001001001 source: 001 changed: 0 step 55 001001001001001001001001001001 source: 011 changed: 1 step 56 001001001011001001001001001001 source: 110 changed: 1 0 step 57 001001001110001001001001001001 source: 101 changed: 01 step 58 001001001101001001001001001001 source: 001 changed: 0 step 59 001001001001001001001001001001 source: 011 changed: 1 step 60 001001001001011001001001001001 source: 110 changed: 1 0 step 61 001001001001110001001001001001 source: 101 changed: 01 step 62 001001001001101001001001001001 source: 001 changed: 0 step 63 001001001001001001001001001001 source: 011 changed: 1 step 64 001001001001001011001001001001 source: 110 changed: 1 0 step 65 001001001001001110001001001001 source: 101 changed: 01 step 66 001001001001001101001001001001 source: 001 changed: 0 step 67 001001001001001001001001001001 source: 011 changed: 1 step 68 001001001001001001011001001001 source: 110 changed: 1 0 step 69 001001001001001001110001001001 source: 101 changed: 01 step 70 001001001001001001101001001001 source: 001 changed: 0 step 71 001001001001001001001001001001 source: 011 changed: 1 step 72 001001001001001001001011001001 source: 110 changed: 1 0 step 73 001001001001001001001110001001 source: 101 changed: 01 step 74 001001001001001001001101001001 source: 001 changed: 0 step 75 001001001001001001001001001001 source: 011 changed: 1 step 76 001001001001001001001001011001 source: 110 changed: 1 0 step 77 001001001001001001001001110001 source: 101 changed: 01 step 78 001001001001001001001001101001 source: 001 changed: 0 step 79 001001001001001001001001001001 source: 011 changed: 1 step 80 001001001001001001001001001011 source: 110 changed: 1 0 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 0 step 82 001001001001001001001001001100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001 changed: 0 1 step 83 001001001001001001001001001001 test 1: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001001001001001001001001001001 changed: step 1 001001001001001001001001001001 source: 110110110110110110110110110110 changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 source: 011 changed: 0 1 step 3 011110110110110110110110110110 source: 001 changed: 0 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 source: 011 changed: 0 1 step 23 110110110110110011110110110110 source: 001 changed: 0 step 24 110110110110110001110110110110 source: 101 changed: 1 step 25 110110110110110101110110110110 source: 110 changed: 10 step 26 110110110110110110110110110110 source: 011 changed: 0 1 step 27 110110110110110110011110110110 source: 001 changed: 0 step 28 110110110110110110001110110110 source: 101 changed: 1 step 29 110110110110110110101110110110 source: 110 changed: 10 step 30 110110110110110110110110110110 source: 011 changed: 0 1 step 31 110110110110110110110011110110 source: 001 changed: 0 step 32 110110110110110110110001110110 source: 101 changed: 1 step 33 110110110110110110110101110110 source: 110 changed: 10 step 34 110110110110110110110110110110 source: 011 changed: 0 1 step 35 110110110110110110110110011110 source: 001 changed: 0 step 36 110110110110110110110110001110 source: 101 changed: 1 step 37 110110110110110110110110101110 source: 110 changed: 10 step 38 110110110110110110110110110110 source: 011 changed: 0 1 step 39 110110110110110110110110110011 source: 001 changed: 0 step 40 110110110110110110110110110001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 1 0 step 41 110110110110110110110110110100 fail ^ source: 110 changed: 1 step 42 110110110110110110110110110110 source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 source: 011 changed: 1 step 44 011001001001001001001001001001 source: 110 changed: 1 0 step 45 110001001001001001001001001001 source: 101 changed: 01 step 46 101001001001001001001001001001 source: 001 changed: 0 step 47 001001001001001001001001001001 source: 011 changed: 1 step 48 001011001001001001001001001001 source: 110 changed: 1 0 step 49 001110001001001001001001001001 source: 101 changed: 01 step 50 001101001001001001001001001001 source: 001 changed: 0 step 51 001001001001001001001001001001 source: 011 changed: 1 step 52 001001011001001001001001001001 source: 110 changed: 1 0 step 53 001001110001001001001001001001 source: 101 changed: 01 step 54 001001101001001001001001001001 source: 001 changed: 0 step 55 001001001001001001001001001001 source: 011 changed: 1 step 56 001001001011001001001001001001 source: 110 changed: 1 0 step 57 001001001110001001001001001001 source: 101 changed: 01 step 58 001001001101001001001001001001 source: 001 changed: 0 step 59 001001001001001001001001001001 source: 011 changed: 1 step 60 001001001001011001001001001001 source: 110 changed: 1 0 step 61 001001001001110001001001001001 source: 101 changed: 01 step 62 001001001001101001001001001001 source: 001 changed: 0 step 63 001001001001001001001001001001 source: 011 changed: 1 step 64 001001001001001011001001001001 source: 110 changed: 1 0 step 65 001001001001001110001001001001 source: 101 changed: 01 step 66 001001001001001101001001001001 source: 001 changed: 0 step 67 001001001001001001001001001001 source: 011 changed: 1 step 68 001001001001001001011001001001 source: 110 changed: 1 0 step 69 001001001001001001110001001001 source: 101 changed: 01 step 70 001001001001001001101001001001 source: 001 changed: 0 step 71 001001001001001001001001001001 source: 011 changed: 1 step 72 001001001001001001001011001001 source: 110 changed: 1 0 step 73 001001001001001001001110001001 source: 101 changed: 01 step 74 001001001001001001001101001001 source: 001 changed: 0 step 75 001001001001001001001001001001 source: 011 changed: 1 step 76 001001001001001001001001011001 source: 110 changed: 1 0 step 77 001001001001001001001001110001 source: 101 changed: 01 step 78 001001001001001001001001101001 source: 001 changed: 0 step 79 001001001001001001001001001001 source: 011 changed: 1 step 80 001001001001001001001001001011 source: 110 changed: 1 0 step 81 001001001001001001001001001110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 0 step 82 001001001001001001001001001100 fail ^ source: 001 changed: 0 1 step 83 001001001001001001001001001001 test 2: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 30 O AV2 E2-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO fails LO: 1111111111111111111111111111 fails LO: 000000000000000000000000000 0 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001001001001001001001001001001 changed: step 1 001001001001001001001001001001 source: 110110110110110110110110110110 changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 source: 011 changed: 0 1 step 3 011110110110110110110110110110 source: 001 changed: 0 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 source: 011 changed: 0 1 step 23 110110110110110011110110110110 source: 001 changed: 0 step 24 110110110110110001110110110110 source: 101 changed: 1 step 25 110110110110110101110110110110 source: 110 changed: 10 step 26 110110110110110110110110110110 source: 011 changed: 0 1 step 27 110110110110110110011110110110 source: 001 changed: 0 step 28 110110110110110110001110110110 source: 101 changed: 1 step 29 110110110110110110101110110110 source: 110 changed: 10 step 30 110110110110110110110110110110 source: 011 changed: 0 1 step 31 110110110110110110110011110110 source: 001 changed: 0 step 32 110110110110110110110001110110 source: 101 changed: 1 step 33 110110110110110110110101110110 source: 110 changed: 10 step 34 110110110110110110110110110110 source: 011 changed: 0 1 step 35 110110110110110110110110011110 source: 001 changed: 0 step 36 110110110110110110110110001110 source: 101 changed: 1 step 37 110110110110110110110110101110 source: 110 changed: 10 step 38 110110110110110110110110110110 source: 011 changed: 0 1 step 39 110110110110110110110110110011 source: 001 changed: 0 step 40 110110110110110110110110110001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 1 0 step 41 110110110110110110110110110100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 1 step 42 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 2, total passes 0 Main menu Sat Jul 01 09:34:54 2017 test file is: tests\M113.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Sat Jul 01 09:34:59 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:35:02 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 00101 changed: 10 step 124 111100010111110111101111011110 source: 00111 changed: 1 step 125 111100011111110111101111011110 source: 01001 changed: 100 step 126 111100100111110111101111011110 source: 01011 changed: 1 step 127 111100101111110111101111011110 source: 01101 changed: 10 step 128 111100110111110111101111011110 source: 01111 changed: 1 step 129 111100111111110111101111011110 source: 10001 changed: 1000 step 130 111101000111110111101111011110 source: 10011 changed: 1 step 131 111101001111110111101111011110 source: 10101 changed: 10 step 132 111101010111110111101111011110 source: 10111 changed: 1 step 133 111101011111110111101111011110 source: 11001 changed: 100 step 134 111101100111110111101111011110 source: 11011 changed: 1 step 135 111101101111110111101111011110 source: 11101 changed: 10 step 136 111101110111110111101111011110 source: 11110 changed: 10 step 137 111101111011110111101111011110 source: 00001 changed: 00001 step 138 111101111000001111101111011110 source: 00011 changed: 1 step 139 111101111000011111101111011110 source: 00101 changed: 10 step 140 111101111000101111101111011110 source: 00111 changed: 1 step 141 111101111000111111101111011110 source: 01001 changed: 100 step 142 111101111001001111101111011110 source: 01011 changed: 1 step 143 111101111001011111101111011110 source: 01101 changed: 10 step 144 111101111001101111101111011110 source: 01111 changed: 1 step 145 111101111001111111101111011110 source: 10001 changed: 1000 step 146 111101111010001111101111011110 source: 10011 changed: 1 step 147 111101111010011111101111011110 source: 10101 changed: 10 step 148 111101111010101111101111011110 source: 10111 changed: 1 step 149 111101111010111111101111011110 source: 11001 changed: 100 step 150 111101111011001111101111011110 source: 11011 changed: 1 step 151 111101111011011111101111011110 source: 11101 changed: 10 step 152 111101111011101111101111011110 source: 11110 changed: 10 step 153 111101111011110111101111011110 source: 00001 changed: 00001 step 154 111101111011110000011111011110 source: 00011 changed: 1 step 155 111101111011110000111111011110 source: 00101 changed: 10 step 156 111101111011110001011111011110 source: 00111 changed: 1 step 157 111101111011110001111111011110 source: 01001 changed: 100 step 158 111101111011110010011111011110 source: 01011 changed: 1 step 159 111101111011110010111111011110 source: 01101 changed: 10 step 160 111101111011110011011111011110 source: 01111 changed: 1 step 161 111101111011110011111111011110 source: 10001 changed: 1000 step 162 111101111011110100011111011110 source: 10011 changed: 1 step 163 111101111011110100111111011110 source: 10101 changed: 10 step 164 111101111011110101011111011110 source: 10111 changed: 1 step 165 111101111011110101111111011110 source: 11001 changed: 100 step 166 111101111011110110011111011110 source: 11011 changed: 1 step 167 111101111011110110111111011110 source: 11101 changed: 10 step 168 111101111011110111011111011110 source: 11110 changed: 10 step 169 111101111011110111101111011110 source: 00001 changed: 00001 step 170 111101111011110111100000111110 source: 00011 changed: 1 step 171 111101111011110111100001111110 source: 00101 changed: 10 step 172 111101111011110111100010111110 source: 00111 changed: 1 step 173 111101111011110111100011111110 source: 01001 changed: 100 step 174 111101111011110111100100111110 source: 01011 changed: 1 step 175 111101111011110111100101111110 source: 01101 changed: 10 step 176 111101111011110111100110111110 source: 01111 changed: 1 step 177 111101111011110111100111111110 source: 10001 changed: 1000 step 178 111101111011110111101000111110 source: 10011 changed: 1 step 179 111101111011110111101001111110 source: 10101 changed: 10 step 180 111101111011110111101010111110 source: 10111 changed: 1 step 181 111101111011110111101011111110 source: 11001 changed: 100 step 182 111101111011110111101100111110 source: 11011 changed: 1 step 183 111101111011110111101101111110 source: 11101 changed: 10 step 184 111101111011110111101110111110 source: 11110 changed: 10 step 185 111101111011110111101111011110 source: 00001 changed: 00001 step 186 111101111011110111101111000001 source: 00011 changed: 1 step 187 111101111011110111101111000011 source: 00101 changed: 10 step 188 111101111011110111101111000101 source: 00111 changed: 1 step 189 111101111011110111101111000111 source: 01001 changed: 100 step 190 111101111011110111101111001001 source: 01011 changed: 1 step 191 111101111011110111101111001011 source: 01101 changed: 10 step 192 111101111011110111101111001101 source: 01111 changed: 1 step 193 111101111011110111101111001111 source: 10001 changed: 1000 step 194 111101111011110111101111010001 source: 10011 changed: 1 step 195 111101111011110111101111010011 source: 10101 changed: 10 step 196 111101111011110111101111010101 source: 10111 changed: 1 step 197 111101111011110111101111010111 source: 11001 changed: 100 step 198 111101111011110111101111011001 source: 11011 changed: 1 step 199 111101111011110111101111011011 source: 11101 changed: 10 step 200 111101111011110111101111011101 source: 11110 changed: 10 step 201 111101111011110111101111011110 source: 111101111011110111101111011110 changed: step 202 111101111011110111101111011110 test 11: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 11, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 000010000100001000010000100001 changed: 000010000100001000010000100001 step 1 000010000100001000010000100001 source: 00001 changed: step 2 000010000100001000010000100001 source: 00011 changed: 1 step 3 000110000100001000010000100001 source: 00101 changed: 10 step 4 001010000100001000010000100001 source: 00111 changed: 1 step 5 001110000100001000010000100001 source: 01001 changed: 100 step 6 010010000100001000010000100001 source: 01011 changed: 1 step 7 010110000100001000010000100001 source: 01101 changed: 10 step 8 011010000100001000010000100001 source: 01111 changed: 1 step 9 011110000100001000010000100001 source: 10001 changed: 1000 step 10 100010000100001000010000100001 source: 10011 changed: 1 step 11 100110000100001000010000100001 source: 10101 changed: 10 step 12 101010000100001000010000100001 source: 10111 changed: 1 step 13 101110000100001000010000100001 source: 11001 changed: 100 step 14 110010000100001000010000100001 source: 11011 changed: 1 step 15 110110000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 100 step 16 111000000100001000010000100001 fail ^ source: 11110 changed: 1 step 17 111100000100001000010000100001 source: 00001 changed: 00001 step 18 000010000100001000010000100001 source: 00001 changed: step 19 000010000100001000010000100001 source: 00011 changed: 1 step 20 000010001100001000010000100001 source: 00101 changed: 10 step 21 000010010100001000010000100001 source: 00111 changed: 1 step 22 000010011100001000010000100001 source: 01001 changed: 100 step 23 000010100100001000010000100001 source: 01011 changed: 1 step 24 000010101100001000010000100001 source: 01101 changed: 10 step 25 000010110100001000010000100001 source: 01111 changed: 1 step 26 000010111100001000010000100001 source: 10001 changed: 1000 step 27 000011000100001000010000100001 source: 10011 changed: 1 step 28 000011001100001000010000100001 source: 10101 changed: 10 step 29 000011010100001000010000100001 source: 10111 changed: 1 step 30 000011011100001000010000100001 source: 11001 changed: 100 step 31 000011100100001000010000100001 source: 11011 changed: 1 step 32 000011101100001000010000100001 source: 11101 changed: 10 step 33 000011110100001000010000100001 source: 11110 changed: 10 step 34 000011111000001000010000100001 source: 00001 changed: 00001 step 35 000010000100001000010000100001 source: 00001 changed: step 36 000010000100001000010000100001 source: 00011 changed: 1 step 37 000010000100011000010000100001 source: 00101 changed: 10 step 38 000010000100101000010000100001 source: 00111 changed: 1 step 39 000010000100111000010000100001 source: 01001 changed: 100 step 40 000010000101001000010000100001 source: 01011 changed: 1 step 41 000010000101011000010000100001 source: 01101 changed: 10 step 42 000010000101101000010000100001 source: 01111 changed: 1 step 43 000010000101111000010000100001 source: 10001 changed: 1000 step 44 000010000110001000010000100001 source: 10011 changed: 1 step 45 000010000110011000010000100001 source: 10101 changed: 10 step 46 000010000110101000010000100001 source: 10111 changed: 1 step 47 000010000110111000010000100001 source: 11001 changed: 100 step 48 000010000111001000010000100001 source: 11011 changed: 1 step 49 000010000111011000010000100001 source: 11101 changed: 10 step 50 000010000111101000010000100001 source: 11110 changed: 10 step 51 000010000111110000010000100001 source: 00001 changed: 00001 step 52 000010000100001000010000100001 source: 00001 changed: step 53 000010000100001000010000100001 source: 00011 changed: 1 step 54 000010000100001000110000100001 source: 00101 changed: 10 step 55 000010000100001001010000100001 source: 00111 changed: 1 step 56 000010000100001001110000100001 source: 01001 changed: 100 step 57 000010000100001010010000100001 source: 01011 changed: 1 step 58 000010000100001010110000100001 source: 01101 changed: 10 step 59 000010000100001011010000100001 source: 01111 changed: 1 step 60 000010000100001011110000100001 source: 10001 changed: 1000 step 61 000010000100001100010000100001 source: 10011 changed: 1 step 62 000010000100001100110000100001 source: 10101 changed: 10 step 63 000010000100001101010000100001 source: 10111 changed: 1 step 64 000010000100001101110000100001 source: 11001 changed: 100 step 65 000010000100001110010000100001 source: 11011 changed: 1 step 66 000010000100001110110000100001 source: 11101 changed: 10 step 67 000010000100001111010000100001 source: 11110 changed: 10 step 68 000010000100001111100000100001 source: 00001 changed: 00001 step 69 000010000100001000010000100001 source: 00001 changed: step 70 000010000100001000010000100001 source: 00011 changed: 1 step 71 000010000100001000010001100001 source: 00101 changed: 10 step 72 000010000100001000010010100001 source: 00111 changed: 1 step 73 000010000100001000010011100001 source: 01001 changed: 100 step 74 000010000100001000010100100001 source: 01011 changed: 1 step 75 000010000100001000010101100001 source: 01101 changed: 10 step 76 000010000100001000010110100001 source: 01111 changed: 1 step 77 000010000100001000010111100001 source: 10001 changed: 1000 step 78 000010000100001000011000100001 source: 10011 changed: 1 step 79 000010000100001000011001100001 source: 10101 changed: 10 step 80 000010000100001000011010100001 source: 10111 changed: 1 step 81 000010000100001000011011100001 source: 11001 changed: 100 step 82 000010000100001000011100100001 source: 11011 changed: 1 step 83 000010000100001000011101100001 source: 11101 changed: 10 step 84 000010000100001000011110100001 source: 11110 changed: 10 step 85 000010000100001000011111000001 source: 00001 changed: 00001 step 86 000010000100001000010000100001 source: 00001 changed: step 87 000010000100001000010000100001 source: 00011 changed: 1 step 88 000010000100001000010000100011 source: 00101 changed: 10 step 89 000010000100001000010000100101 source: 00111 changed: 1 step 90 000010000100001000010000100111 source: 01001 changed: 100 step 91 000010000100001000010000101001 source: 01011 changed: 1 step 92 000010000100001000010000101011 source: 01101 changed: 10 step 93 000010000100001000010000101101 source: 01111 changed: 1 step 94 000010000100001000010000101111 source: 10001 changed: 1000 step 95 000010000100001000010000110001 source: 10011 changed: 1 step 96 000010000100001000010000110011 source: 10101 changed: 10 step 97 000010000100001000010000110101 source: 10111 changed: 1 step 98 000010000100001000010000110111 source: 11001 changed: 100 step 99 000010000100001000010000111001 source: 11011 changed: 1 step 100 000010000100001000010000111011 source: 11101 changed: 10 step 101 000010000100001000010000111101 source: 11110 changed: 10 step 102 000010000100001000010000111110 source: 00001 changed: 00001 step 103 000010000100001000010000100001 source: 000010000100001000010000100001 changed: step 104 000010000100001000010000100001 source: 111101111011110111101111011110 changed: 111101111011110111101111011110 step 105 111101111011110111101111011110 source: 00001 changed: 00001 step 106 000011111011110111101111011110 source: 00011 changed: 1 step 107 000111111011110111101111011110 source: 00101 changed: 10 step 108 001011111011110111101111011110 source: 00111 changed: 1 step 109 001111111011110111101111011110 source: 01001 changed: 100 step 110 010011111011110111101111011110 source: 01011 changed: 1 step 111 010111111011110111101111011110 source: 01101 changed: 10 step 112 011011111011110111101111011110 source: 01111 changed: 1 step 113 011111111011110111101111011110 source: 10001 changed: 1000 step 114 100011111011110111101111011110 source: 10011 changed: 1 step 115 100111111011110111101111011110 source: 10101 changed: 10 step 116 101011111011110111101111011110 source: 10111 changed: 1 step 117 101111111011110111101111011110 source: 11001 changed: 100 step 118 110011111011110111101111011110 source: 11011 changed: 1 step 119 110111111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 100 step 120 111001111011110111101111011110 fail ^ source: 11110 changed: 1 step 121 111101111011110111101111011110 source: 00001 changed: 00001 step 122 111100000111110111101111011110 source: 00011 changed: 1 step 123 111100001111110111101111011110 source: 00101 changed: 10 step 124 111100010111110111101111011110 source: 00111 changed: 1 step 125 111100011111110111101111011110 source: 01001 changed: 100 step 126 111100100111110111101111011110 source: 01011 changed: 1 step 127 111100101111110111101111011110 source: 01101 changed: 10 step 128 111100110111110111101111011110 source: 01111 changed: 1 step 129 111100111111110111101111011110 source: 10001 changed: 1000 step 130 111101000111110111101111011110 source: 10011 changed: 1 step 131 111101001111110111101111011110 source: 10101 changed: 10 step 132 111101010111110111101111011110 source: 10111 changed: 1 step 133 111101011111110111101111011110 source: 11001 changed: 100 step 134 111101100111110111101111011110 source: 11011 changed: 1 step 135 111101101111110111101111011110 source: 11101 changed: 10 step 136 111101110111110111101111011110 source: 11110 changed: 10 step 137 111101111011110111101111011110 source: 00001 changed: 00001 step 138 111101111000001111101111011110 source: 00011 changed: 1 step 139 111101111000011111101111011110 source: 00101 changed: 10 step 140 111101111000101111101111011110 source: 00111 changed: 1 step 141 111101111000111111101111011110 source: 01001 changed: 100 step 142 111101111001001111101111011110 source: 01011 changed: 1 step 143 111101111001011111101111011110 source: 01101 changed: 10 step 144 111101111001101111101111011110 source: 01111 changed: 1 step 145 111101111001111111101111011110 source: 10001 changed: 1000 step 146 111101111010001111101111011110 source: 10011 changed: 1 step 147 111101111010011111101111011110 source: 10101 changed: 10 step 148 111101111010101111101111011110 source: 10111 changed: 1 step 149 111101111010111111101111011110 source: 11001 changed: 100 step 150 111101111011001111101111011110 source: 11011 changed: 1 step 151 111101111011011111101111011110 source: 11101 changed: 10 step 152 111101111011101111101111011110 source: 11110 changed: 10 step 153 111101111011110111101111011110 source: 00001 changed: 00001 step 154 111101111011110000011111011110 source: 00011 changed: 1 step 155 111101111011110000111111011110 source: 00101 changed: 10 step 156 111101111011110001011111011110 source: 00111 changed: 1 step 157 111101111011110001111111011110 source: 01001 changed: 100 step 158 111101111011110010011111011110 source: 01011 changed: 1 step 159 111101111011110010111111011110 source: 01101 changed: 10 step 160 111101111011110011011111011110 source: 01111 changed: 1 step 161 111101111011110011111111011110 source: 10001 changed: 1000 step 162 111101111011110100011111011110 source: 10011 changed: 1 step 163 111101111011110100111111011110 source: 10101 changed: 10 step 164 111101111011110101011111011110 source: 10111 changed: 1 step 165 111101111011110101111111011110 source: 11001 changed: 100 step 166 111101111011110110011111011110 source: 11011 changed: 1 step 167 111101111011110110111111011110 source: 11101 changed: 10 step 168 111101111011110111011111011110 source: 11110 changed: 10 step 169 111101111011110111101111011110 source: 00001 changed: 00001 step 170 111101111011110111100000111110 source: 00011 changed: 1 step 171 111101111011110111100001111110 source: 00101 changed: 10 step 172 111101111011110111100010111110 source: 00111 changed: 1 step 173 111101111011110111100011111110 source: 01001 changed: 100 step 174 111101111011110111100100111110 source: 01011 changed: 1 step 175 111101111011110111100101111110 source: 01101 changed: 10 step 176 111101111011110111100110111110 source: 01111 changed: 1 step 177 111101111011110111100111111110 source: 10001 changed: 1000 step 178 111101111011110111101000111110 source: 10011 changed: 1 step 179 111101111011110111101001111110 source: 10101 changed: 10 step 180 111101111011110111101010111110 source: 10111 changed: 1 step 181 111101111011110111101011111110 source: 11001 changed: 100 step 182 111101111011110111101100111110 source: 11011 changed: 1 step 183 111101111011110111101101111110 source: 11101 changed: 10 step 184 111101111011110111101110111110 source: 11110 changed: 10 step 185 111101111011110111101111011110 source: 00001 changed: 00001 step 186 111101111011110111101111000001 source: 00011 changed: 1 step 187 111101111011110111101111000011 source: 00101 changed: 10 step 188 111101111011110111101111000101 source: 00111 changed: 1 step 189 111101111011110111101111000111 source: 01001 changed: 100 step 190 111101111011110111101111001001 source: 01011 changed: 1 step 191 111101111011110111101111001011 source: 01101 changed: 10 step 192 111101111011110111101111001101 source: 01111 changed: 1 step 193 111101111011110111101111001111 source: 10001 changed: 1000 step 194 111101111011110111101111010001 source: 10011 changed: 1 step 195 111101111011110111101111010011 source: 10101 changed: 10 step 196 111101111011110111101111010101 source: 10111 changed: 1 step 197 111101111011110111101111010111 source: 11001 changed: 100 step 198 111101111011110111101111011001 source: 11011 changed: 1 step 199 111101111011110111101111011011 source: 11101 changed: 10 step 200 111101111011110111101111011101 source: 11110 changed: 10 step 201 111101111011110111101111011110 source: 111101111011110111101111011110 changed: step 202 111101111011110111101111011110 test 12: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 12, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 000010000100001000010000100001 changed: 000010000100001000010000100001 step 1 000010000100001000010000100001 source: 00001 changed: step 2 000010000100001000010000100001 source: 00011 changed: 1 step 3 000110000100001000010000100001 source: 00101 changed: 10 step 4 001010000100001000010000100001 source: 00111 changed: 1 step 5 001110000100001000010000100001 source: 01001 changed: 100 step 6 010010000100001000010000100001 source: 01011 changed: 1 step 7 010110000100001000010000100001 source: 01101 changed: 10 step 8 011010000100001000010000100001 source: 01111 changed: 1 step 9 011110000100001000010000100001 source: 10001 changed: 1000 step 10 100010000100001000010000100001 source: 10011 changed: 1 step 11 100110000100001000010000100001 source: 10101 changed: 10 step 12 101010000100001000010000100001 source: 10111 changed: 1 step 13 101110000100001000010000100001 source: 11001 changed: 100 step 14 110010000100001000010000100001 source: 11011 changed: 1 step 15 110110000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 100 step 16 111000000100001000010000100001 fail ^ source: 11110 changed: 1 step 17 111100000100001000010000100001 source: 00001 changed: 00001 step 18 000010000100001000010000100001 source: 00001 changed: step 19 000010000100001000010000100001 source: 00011 changed: 1 step 20 000010001100001000010000100001 source: 00101 changed: 10 step 21 000010010100001000010000100001 source: 00111 changed: 1 step 22 000010011100001000010000100001 source: 01001 changed: 100 step 23 000010100100001000010000100001 source: 01011 changed: 1 step 24 000010101100001000010000100001 source: 01101 changed: 10 step 25 000010110100001000010000100001 source: 01111 changed: 1 step 26 000010111100001000010000100001 source: 10001 changed: 1000 step 27 000011000100001000010000100001 source: 10011 changed: 1 step 28 000011001100001000010000100001 source: 10101 changed: 10 step 29 000011010100001000010000100001 source: 10111 changed: 1 step 30 000011011100001000010000100001 source: 11001 changed: 100 step 31 000011100100001000010000100001 source: 11011 changed: 1 step 32 000011101100001000010000100001 source: 11101 changed: 10 step 33 000011110100001000010000100001 source: 11110 changed: 10 step 34 000011111000001000010000100001 source: 00001 changed: 00001 step 35 000010000100001000010000100001 source: 00001 changed: step 36 000010000100001000010000100001 source: 00011 changed: 1 step 37 000010000100011000010000100001 source: 00101 changed: 10 step 38 000010000100101000010000100001 source: 00111 changed: 1 step 39 000010000100111000010000100001 source: 01001 changed: 100 step 40 000010000101001000010000100001 source: 01011 changed: 1 step 41 000010000101011000010000100001 source: 01101 changed: 10 step 42 000010000101101000010000100001 source: 01111 changed: 1 step 43 000010000101111000010000100001 source: 10001 changed: 1000 step 44 000010000110001000010000100001 source: 10011 changed: 1 step 45 000010000110011000010000100001 source: 10101 changed: 10 step 46 000010000110101000010000100001 source: 10111 changed: 1 step 47 000010000110111000010000100001 source: 11001 changed: 100 step 48 000010000111001000010000100001 source: 11011 changed: 1 step 49 000010000111011000010000100001 source: 11101 changed: 10 step 50 000010000111101000010000100001 source: 11110 changed: 10 step 51 000010000111110000010000100001 source: 00001 changed: 00001 step 52 000010000100001000010000100001 source: 00001 changed: step 53 000010000100001000010000100001 source: 00011 changed: 1 step 54 000010000100001000110000100001 source: 00101 changed: 10 step 55 000010000100001001010000100001 source: 00111 changed: 1 step 56 000010000100001001110000100001 source: 01001 changed: 100 step 57 000010000100001010010000100001 source: 01011 changed: 1 step 58 000010000100001010110000100001 source: 01101 changed: 10 step 59 000010000100001011010000100001 source: 01111 changed: 1 step 60 000010000100001011110000100001 source: 10001 changed: 1000 step 61 000010000100001100010000100001 source: 10011 changed: 1 step 62 000010000100001100110000100001 source: 10101 changed: 10 step 63 000010000100001101010000100001 source: 10111 changed: 1 step 64 000010000100001101110000100001 source: 11001 changed: 100 step 65 000010000100001110010000100001 source: 11011 changed: 1 step 66 000010000100001110110000100001 source: 11101 changed: 10 step 67 000010000100001111010000100001 source: 11110 changed: 10 step 68 000010000100001111100000100001 source: 00001 changed: 00001 step 69 000010000100001000010000100001 source: 00001 changed: step 70 000010000100001000010000100001 source: 00011 changed: 1 step 71 000010000100001000010001100001 source: 00101 changed: 10 step 72 000010000100001000010010100001 source: 00111 changed: 1 step 73 000010000100001000010011100001 source: 01001 changed: 100 step 74 000010000100001000010100100001 source: 01011 changed: 1 step 75 000010000100001000010101100001 source: 01101 changed: 10 step 76 000010000100001000010110100001 source: 01111 changed: 1 step 77 000010000100001000010111100001 source: 10001 changed: 1000 step 78 000010000100001000011000100001 source: 10011 changed: 1 step 79 000010000100001000011001100001 source: 10101 changed: 10 step 80 000010000100001000011010100001 source: 10111 changed: 1 step 81 000010000100001000011011100001 source: 11001 changed: 100 step 82 000010000100001000011100100001 source: 11011 changed: 1 step 83 000010000100001000011101100001 source: 11101 changed: 10 step 84 000010000100001000011110100001 source: 11110 changed: 10 step 85 000010000100001000011111000001 source: 00001 changed: 00001 step 86 000010000100001000010000100001 source: 00001 changed: step 87 000010000100001000010000100001 source: 00011 changed: 1 step 88 000010000100001000010000100011 source: 00101 changed: 10 step 89 000010000100001000010000100101 source: 00111 changed: 1 step 90 000010000100001000010000100111 source: 01001 changed: 100 step 91 000010000100001000010000101001 source: 01011 changed: 1 step 92 000010000100001000010000101011 source: 01101 changed: 10 step 93 000010000100001000010000101101 source: 01111 changed: 1 step 94 000010000100001000010000101111 source: 10001 changed: 1000 step 95 000010000100001000010000110001 source: 10011 changed: 1 step 96 000010000100001000010000110011 source: 10101 changed: 10 step 97 000010000100001000010000110101 source: 10111 changed: 1 step 98 000010000100001000010000110111 source: 11001 changed: 100 step 99 000010000100001000010000111001 source: 11011 changed: 1 step 100 000010000100001000010000111011 source: 11101 changed: 10 step 101 000010000100001000010000111101 source: 11110 changed: 10 step 102 000010000100001000010000111110 source: 00001 changed: 00001 step 103 000010000100001000010000100001 source: 000010000100001000010000100001 changed: step 104 000010000100001000010000100001 source: 111101111011110111101111011110 changed: 111101111011110111101111011110 step 105 111101111011110111101111011110 source: 00001 changed: 00001 step 106 000011111011110111101111011110 source: 00011 changed: 1 step 107 000111111011110111101111011110 source: 00101 changed: 10 step 108 001011111011110111101111011110 source: 00111 changed: 1 step 109 001111111011110111101111011110 source: 01001 changed: 100 step 110 010011111011110111101111011110 source: 01011 changed: 1 step 111 010111111011110111101111011110 source: 01101 changed: 10 step 112 011011111011110111101111011110 source: 01111 changed: 1 step 113 011111111011110111101111011110 source: 10001 changed: 1000 step 114 100011111011110111101111011110 source: 10011 changed: 1 step 115 100111111011110111101111011110 source: 10101 changed: 10 step 116 101011111011110111101111011110 source: 10111 changed: 1 step 117 101111111011110111101111011110 source: 11001 changed: 100 step 118 110011111011110111101111011110 source: 11011 changed: 1 step 119 110111111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 100 step 120 111001111011110111101111011110 fail ^ source: 11110 changed: 1 step 121 111101111011110111101111011110 source: 00001 changed: 00001 step 122 111100000111110111101111011110 source: 00011 changed: 1 step 123 111100001111110111101111011110 source: 00101 changed: 10 step 124 111100010111110111101111011110 source: 00111 changed: 1 step 125 111100011111110111101111011110 source: 01001 changed: 100 step 126 111100100111110111101111011110 source: 01011 changed: 1 step 127 111100101111110111101111011110 source: 01101 changed: 10 step 128 111100110111110111101111011110 source: 01111 changed: 1 step 129 111100111111110111101111011110 source: 10001 changed: 1000 step 130 111101000111110111101111011110 source: 10011 changed: 1 step 131 111101001111110111101111011110 source: 10101 changed: 10 step 132 111101010111110111101111011110 source: 10111 changed: 1 step 133 111101011111110111101111011110 source: 11001 changed: 100 step 134 111101100111110111101111011110 source: 11011 changed: 1 step 135 111101101111110111101111011110 source: 11101 changed: 10 step 136 111101110111110111101111011110 source: 11110 changed: 10 step 137 111101111011110111101111011110 source: 00001 changed: 00001 step 138 111101111000001111101111011110 source: 00011 changed: 1 step 139 111101111000011111101111011110 source: 00101 changed: 10 step 140 111101111000101111101111011110 source: 00111 changed: 1 step 141 111101111000111111101111011110 source: 01001 changed: 100 step 142 111101111001001111101111011110 source: 01011 changed: 1 step 143 111101111001011111101111011110 source: 01101 changed: 10 step 144 111101111001101111101111011110 source: 01111 changed: 1 step 145 111101111001111111101111011110 source: 10001 changed: 1000 step 146 111101111010001111101111011110 source: 10011 changed: 1 step 147 111101111010011111101111011110 source: 10101 changed: 10 step 148 111101111010101111101111011110 source: 10111 changed: 1 step 149 111101111010111111101111011110 source: 11001 changed: 100 step 150 111101111011001111101111011110 source: 11011 changed: 1 step 151 111101111011011111101111011110 source: 11101 changed: 10 step 152 111101111011101111101111011110 source: 11110 changed: 10 step 153 111101111011110111101111011110 source: 00001 changed: 00001 step 154 111101111011110000011111011110 source: 00011 changed: 1 step 155 111101111011110000111111011110 source: 00101 changed: 10 step 156 111101111011110001011111011110 source: 00111 changed: 1 step 157 111101111011110001111111011110 source: 01001 changed: 100 step 158 111101111011110010011111011110 source: 01011 changed: 1 step 159 111101111011110010111111011110 source: 01101 changed: 10 step 160 111101111011110011011111011110 source: 01111 changed: 1 step 161 111101111011110011111111011110 source: 10001 changed: 1000 step 162 111101111011110100011111011110 source: 10011 changed: 1 step 163 111101111011110100111111011110 source: 10101 changed: 10 step 164 111101111011110101011111011110 source: 10111 changed: 1 step 165 111101111011110101111111011110 source: 11001 changed: 100 step 166 111101111011110110011111011110 source: 11011 changed: 1 step 167 111101111011110110111111011110 source: 11101 changed: 10 step 168 111101111011110111011111011110 source: 11110 changed: 10 step 169 111101111011110111101111011110 source: 00001 changed: 00001 step 170 111101111011110111100000111110 source: 00011 changed: 1 step 171 111101111011110111100001111110 source: 00101 changed: 10 step 172 111101111011110111100010111110 source: 00111 changed: 1 step 173 111101111011110111100011111110 source: 01001 changed: 100 step 174 111101111011110111100100111110 source: 01011 changed: 1 step 175 111101111011110111100101111110 source: 01101 changed: 10 step 176 111101111011110111100110111110 source: 01111 changed: 1 step 177 111101111011110111100111111110 source: 10001 changed: 1000 step 178 111101111011110111101000111110 source: 10011 changed: 1 step 179 111101111011110111101001111110 source: 10101 changed: 10 step 180 111101111011110111101010111110 source: 10111 changed: 1 step 181 111101111011110111101011111110 source: 11001 changed: 100 step 182 111101111011110111101100111110 source: 11011 changed: 1 step 183 111101111011110111101101111110 source: 11101 changed: 10 step 184 111101111011110111101110111110 source: 11110 changed: 10 step 185 111101111011110111101111011110 source: 00001 changed: 00001 step 186 111101111011110111101111000001 source: 00011 changed: 1 step 187 111101111011110111101111000011 source: 00101 changed: 10 step 188 111101111011110111101111000101 source: 00111 changed: 1 step 189 111101111011110111101111000111 source: 01001 changed: 100 step 190 111101111011110111101111001001 source: 01011 changed: 1 step 191 111101111011110111101111001011 source: 01101 changed: 10 step 192 111101111011110111101111001101 source: 01111 changed: 1 step 193 111101111011110111101111001111 source: 10001 changed: 1000 step 194 111101111011110111101111010001 source: 10011 changed: 1 step 195 111101111011110111101111010011 source: 10101 changed: 10 step 196 111101111011110111101111010101 source: 10111 changed: 1 step 197 111101111011110111101111010111 source: 11001 changed: 100 step 198 111101111011110111101111011001 source: 11011 changed: 1 step 199 111101111011110111101111011011 source: 11101 changed: 10 step 200 111101111011110111101111011101 source: 11110 changed: 10 step 201 111101111011110111101111011110 source: 111101111011110111101111011110 changed: step 202 111101111011110111101111011110 test 13: *** FAIL *************************** 2 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO this fail O all fails O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 13, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit up to this point: PINS that are always low PINS that are always high space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit failure mode analysis: pin: 5 O AE1 E1-8 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO fails LO: 111 1111111111111111111111111 fails LO: 0 0000000000000000000000000 fails HI: fails HI: space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 000010000100001000010000100001 changed: 000010000100001000010000100001 step 1 000010000100001000010000100001 source: 00001 changed: step 2 000010000100001000010000100001 source: 00011 changed: 1 step 3 000110000100001000010000100001 source: 00101 changed: 10 step 4 001010000100001000010000100001 source: 00111 changed: 1 step 5 001110000100001000010000100001 source: 01001 changed: 100 step 6 010010000100001000010000100001 source: 01011 changed: 1 step 7 010110000100001000010000100001 source: 01101 changed: 10 step 8 011010000100001000010000100001 source: 01111 changed: 1 step 9 011110000100001000010000100001 source: 10001 changed: 1000 step 10 100010000100001000010000100001 source: 10011 changed: 1 step 11 100110000100001000010000100001 source: 10101 changed: 10 step 12 101010000100001000010000100001 source: 10111 changed: 1 step 13 101110000100001000010000100001 source: 11001 changed: 100 step 14 110010000100001000010000100001 source: 11011 changed: 1 step 15 110110000100001000010000100001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 100 step 16 111000000100001000010000100001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 1 step 17 111100000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 18 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 19 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 20 000010001100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 21 000010010100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 22 000010011100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 23 000010100100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 24 000010101100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 25 000010110100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 26 000010111100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 27 000011000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 28 000011001100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 29 000011010100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 30 000011011100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 31 000011100100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 32 000011101100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 33 000011110100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 34 000011111000001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 35 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 36 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 37 000010000100011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 38 000010000100101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 39 000010000100111000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01001 changed: 100 step 40 000010000101001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01011 changed: 1 step 41 000010000101011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01101 changed: 10 step 42 000010000101101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 01111 changed: 1 step 43 000010000101111000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10001 changed: 1000 step 44 000010000110001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10011 changed: 1 step 45 000010000110011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10101 changed: 10 step 46 000010000110101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 10111 changed: 1 step 47 000010000110111000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11001 changed: 100 step 48 000010000111001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11011 changed: 1 step 49 000010000111011000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 10 step 50 000010000111101000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 10 step 51 000010000111110000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: 00001 step 52 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00001 changed: step 53 000010000100001000010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00011 changed: 1 step 54 000010000100001000110000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00101 changed: 10 step 55 000010000100001001010000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 00111 changed: 1 step 56 000010000100001001110000100001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 01001 changed: 100 step 57 000010000100001010010000100001 source: 01011 changed: 1 step 58 000010000100001010110000100001 source: 01101 changed: 10 step 59 000010000100001011010000100001 source: 01111 changed: 1 step 60 000010000100001011110000100001 source: 10001 changed: 1000 step 61 000010000100001100010000100001 source: 10011 changed: 1 step 62 000010000100001100110000100001 source: 10101 changed: 10 step 63 000010000100001101010000100001 source: 10111 changed: 1 step 64 000010000100001101110000100001 source: 11001 changed: 100 step 65 000010000100001110010000100001 source: 11011 changed: 1 step 66 000010000100001110110000100001 source: 11101 changed: 10 step 67 000010000100001111010000100001 source: 11110 changed: 10 step 68 000010000100001111100000100001 source: 00001 changed: 00001 step 69 000010000100001000010000100001 source: 00001 changed: step 70 000010000100001000010000100001 source: 00011 changed: 1 step 71 000010000100001000010001100001 source: 00101 changed: 10 step 72 000010000100001000010010100001 source: 00111 changed: 1 step 73 000010000100001000010011100001 source: 01001 changed: 100 step 74 000010000100001000010100100001 source: 01011 changed: 1 step 75 000010000100001000010101100001 source: 01101 changed: 10 step 76 000010000100001000010110100001 source: 01111 changed: 1 step 77 000010000100001000010111100001 source: 10001 changed: 1000 step 78 000010000100001000011000100001 source: 10011 changed: 1 step 79 000010000100001000011001100001 source: 10101 changed: 10 step 80 000010000100001000011010100001 source: 10111 changed: 1 step 81 000010000100001000011011100001 source: 11001 changed: 100 step 82 000010000100001000011100100001 source: 11011 changed: 1 step 83 000010000100001000011101100001 source: 11101 changed: 10 step 84 000010000100001000011110100001 source: 11110 changed: 10 step 85 000010000100001000011111000001 source: 00001 changed: 00001 step 86 000010000100001000010000100001 source: 00001 changed: step 87 000010000100001000010000100001 source: 00011 changed: 1 step 88 000010000100001000010000100011 source: 00101 changed: 10 step 89 000010000100001000010000100101 source: 00111 changed: 1 step 90 000010000100001000010000100111 source: 01001 changed: 100 step 91 000010000100001000010000101001 source: 01011 changed: 1 step 92 000010000100001000010000101011 source: 01101 changed: 10 step 93 000010000100001000010000101101 source: 01111 changed: 1 step 94 000010000100001000010000101111 source: 10001 changed: 1000 step 95 000010000100001000010000110001 source: 10011 changed: 1 step 96 000010000100001000010000110011 source: 10101 changed: 10 step 97 000010000100001000010000110101 source: 10111 changed: 1 step 98 000010000100001000010000110111 source: 11001 changed: 100 step 99 000010000100001000010000111001 source: 11011 changed: 1 step 100 000010000100001000010000111011 source: 11101 changed: 10 step 101 000010000100001000010000111101 source: 11110 changed: 10 step 102 000010000100001000010000111110 source: 00001 changed: 00001 step 103 000010000100001000010000100001 source: 000010000100001000010000100001 changed: step 104 000010000100001000010000100001 source: 111101111011110111101111011110 changed: 111101111011110111101111011110 step 105 111101111011110111101111011110 source: 00001 changed: 00001 step 106 000011111011110111101111011110 source: 00011 changed: 1 step 107 000111111011110111101111011110 source: 00101 changed: 10 step 108 001011111011110111101111011110 source: 00111 changed: 1 step 109 001111111011110111101111011110 source: 01001 changed: 100 step 110 010011111011110111101111011110 source: 01011 changed: 1 step 111 010111111011110111101111011110 source: 01101 changed: 10 step 112 011011111011110111101111011110 source: 01111 changed: 1 step 113 011111111011110111101111011110 source: 10001 changed: 1000 step 114 100011111011110111101111011110 source: 10011 changed: 1 step 115 100111111011110111101111011110 source: 10101 changed: 10 step 116 101011111011110111101111011110 source: 10111 changed: 1 step 117 101111111011110111101111011110 source: 11001 changed: 100 step 118 110011111011110111101111011110 source: 11011 changed: 1 step 119 110111111011110111101111011110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11101 changed: 100 step 120 111001111011110111101111011110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO source: 11110 changed: 1 step 121 111101111011110111101111011110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 13, total passes 0 Main menu Sat Jul 01 09:45:16 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\7400.tst could not open test file. valid test files are: reverting back to test file: tests\m617.tst Main menu Sat Jul 01 09:45:20 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\74h00.tst reading test file: tests\74h00.tst comment: 74H00 QUAD 2-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 74H00 PIN 1 1A pins: 2 I AB2 E1-2 74H00 PIN 2 1B pins: 3 O AC1 E1-3 74H00 PIN 3 1Y = 1A NAND 1B pins: 4 I AD2 E1-4 74H00 PIN 4 2A pins: 5 I AE2 E1-5 74H00 PIN 5 2B pins: 6 O AF2 E1-6 74H00 PIN 6 2Y = 2A NAND 2B pins: 7 I AM2 E1-11 74H00 PIN 9 3A pins: 8 I AN2 E1-12 74H00 PIN 10 3B pins: 9 O AL2 E1-10 74H00 PIN 8 3Y = 3A NAND 3B pins: 10 I AR2 E1-14 74H00 PIN 12 4A pins: 11 I AS2 E1-15 74H00 PIN 13 4B pins: 12 O AP2 E1-13 74H00 PIN 11 4Y pins: 13 I AH2 E1-7 74H00 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 74H00 PIN 14 VCC pins: direction: IIOIIOIIOIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 001001001001XXXX comment: comment: ; ALL INPUTS ONES test 2: 110110110110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 001001001001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 011 test 21: 110 test 22: 101 test 23: 001 test 24: 011 test 25: 110 test 26: 101 test 27: 001 test 28: 011 test 29: 110 test 30: 101 test 31: 001 test 32: 011 test 33: 110 test 34: 101 test 35: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x0010 column 5: offset 0, mask 0x0008 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x0004 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0020 column 11: offset 1, mask 0x0040 column 12: offset 1, mask 0x0010 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x7FA4 0xFF12 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 2: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 3: 0x2058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 4: 0x2018 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 5: 0xA018 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 6: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 7: 0x804C 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 8: 0x8044 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 9: 0x8054 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 10: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 11: 0x8058 0x006A 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 12: 0x8058 0x0062 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 13: 0x8058 0x0066 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 14: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 15: 0x8058 0x005C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 16: 0x8058 0x001C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 17: 0x8058 0x003C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 18: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 19: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 20: 0x2044 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 21: 0x8044 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 22: 0xA004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 23: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 24: 0x200C 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 25: 0x2018 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 26: 0x2014 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 27: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 28: 0x2004 0x001A 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 29: 0x2004 0x001C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 30: 0x2004 0x0016 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 31: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 32: 0x2004 0x0052 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 33: 0x2004 0x0062 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 34: 0x2004 0x0032 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 35: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I O G PIGIIOIIIOIIOIII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 81 lines 74H00 QUAD 2-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V PINS Main menu Sat Jul 01 09:45:25 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:45:27 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 31 0000000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 32 0000000000100000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 33 0000000001100000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 34 0000000001000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 35 0000000000000000 fail ^ ^ ^ ^ test 66: *** FAIL *************************** 30 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII this fail O O O O all fails O O O O was hi 11 11 11 11 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000000000000 total fails 66, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: step 1 0000000000000000 fail ^ ^ ^ ^ step 2 1101101101100000 SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 3 0101101101100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 4 0001101101100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 5 1001101101100000 fail ^ step 6 1101101101100000 SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 7 1100101101100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 8 1100001101100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 9 1101001101100000 fail ^ step 10 1101101101100000 SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 11 1101100101100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 12 1101100001100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 13 1101101001100000 fail ^ step 14 1101101101100000 SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 15 1101101100100000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 16 1101101100000000 fail ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 17 1101101101000000 fail ^ step 18 1101101101100000 SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 00 00 00 00 step 19 0000000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 20 0100000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 21 1100000000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 22 1000000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 23 0000000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 24 0000100000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 25 0001100000000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 26 0001000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 27 0000000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 28 0000000100000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 29 0000001100000000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 30 0000001000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 31 0000000000000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 32 0000000000100000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 1 step 33 0000000001100000 fail ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 34 0000000001000000 fail ^ ^ ^ ^ SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII changed: 0 step 35 0000000000000000 fail ^ ^ ^ ^ test 67: *** FAIL *************************** 30 steps failed SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII this fail O O O O all fails O O O O was hi 11 11 11 11 rising ^^ ^^ ^^ ^^ falling vv vv vv vv was lo 0000000000000000 total fails 67, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails O O O O was lo 0000000000000000 falling vv vv vv vv rising ^^ ^^ ^^ ^^ was hi 11 11 11 11 total fails 67, total passes 0 Main menu Sat Jul 01 09:46:12 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:46:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 116 Main menu Sat Jul 01 09:46:16 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:47:02 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 69 Main menu Sat Jul 01 09:47:04 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:50:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 74 Main menu Sat Jul 01 09:50:22 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:50:53 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 99 Main menu Sat Jul 01 09:50:56 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:51:52 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) Fpppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails O O O O was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 1, total passes 83 Main menu Sat Jul 01 09:51:55 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:52:25 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 60 Main menu Sat Jul 01 09:52:27 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:53:18 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 66 Main menu Sat Jul 01 09:53:20 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0066 Main menu Sat Jul 01 09:56:11 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m617.tst reading test file: tests\m617.tst comment: M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) comment: pins: PINS pins: 1 I AA1 E1-13 pins: 2 I AB1 E1-12 pins: 3 I AC1 E1-10 pins: 4 I AD1 E1-9 pins: 5 O AE1 E1-8 pins: 6 I AF1 E2-13 pins: 7 I AH1 E2-12 pins: 8 I AJ1 E2-10 pins: 9 I AK1 E2-9 pins: 10 O AL1 E2-8 pins: 11 I AM1 E3-13 pins: 12 I AN1 E3-12 pins: 13 I AP1 E3-10 pins: 14 I AR1 E3-9 pins: 15 O AS1 E3-8 pins: 16 I AD2 E1-5 pins: 17 I AE2 E1-4 pins: 18 I AF2 E1-2 pins: 19 I AH2 E1-1 pins: 20 O AJ2 E1-6 pins: 21 I AK2 E2-5 pins: 22 I AL2 E2-4 pins: 23 I AM2 E2-2 pins: 24 I AN2 E2-1 pins: 25 O AP2 E2-6 pins: 26 I AR2 E3-1 pins: 27 I AS2 E3-2 pins: 28 I AT2 E3-4 pins: 29 I AU2 E3-5 pins: 30 O AV2 E3-6 pins: direction: IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO test 1: 000010000100001000010000100001 test 2: 00001 test 3: 00011 test 4: 00101 test 5: 00111 test 6: 01001 test 7: 01011 test 8: 01101 test 9: 01111 test 10: 10001 test 11: 10011 test 12: 10101 test 13: 10111 test 14: 11001 test 15: 11011 test 16: 11101 test 17: 11110 test 18: 00001 test 19: 00001 test 20: 00011 test 21: 00101 test 22: 00111 test 23: 01001 test 24: 01011 test 25: 01101 test 26: 01111 test 27: 10001 test 28: 10011 test 29: 10101 test 30: 10111 test 31: 11001 test 32: 11011 test 33: 11101 test 34: 11110 test 35: 00001 test 36: 00001 test 37: 00011 test 38: 00101 test 39: 00111 test 40: 01001 test 41: 01011 test 42: 01101 test 43: 01111 test 44: 10001 test 45: 10011 test 46: 10101 test 47: 10111 test 48: 11001 test 49: 11011 test 50: 11101 test 51: 11110 test 52: 00001 test 53: 00001 test 54: 00011 test 55: 00101 test 56: 00111 test 57: 01001 test 58: 01011 test 59: 01101 test 60: 01111 test 61: 10001 test 62: 10011 test 63: 10101 test 64: 10111 test 65: 11001 test 66: 11011 test 67: 11101 test 68: 11110 test 69: 00001 test 70: 00001 test 71: 00011 test 72: 00101 test 73: 00111 test 74: 01001 test 75: 01011 test 76: 01101 test 77: 01111 test 78: 10001 test 79: 10011 test 80: 10101 test 81: 10111 test 82: 11001 test 83: 11011 test 84: 11101 test 85: 11110 test 86: 00001 test 87: 00001 test 88: 00011 test 89: 00101 test 90: 00111 test 91: 01001 test 92: 01011 test 93: 01101 test 94: 01111 test 95: 10001 test 96: 10011 test 97: 10101 test 98: 10111 test 99: 11001 test 100: 11011 test 101: 11101 test 102: 11110 test 103: 00001 test 104: 000010000100001000010000100001 test 105: 111101111011110111101111011110 test 106: 00001 test 107: 00011 test 108: 00101 test 109: 00111 test 110: 01001 test 111: 01011 test 112: 01101 test 113: 01111 test 114: 10001 test 115: 10011 test 116: 10101 test 117: 10111 test 118: 11001 test 119: 11011 test 120: 11101 test 121: 11110 test 122: 00001 test 123: 00011 test 124: 00101 test 125: 00111 test 126: 01001 test 127: 01011 test 128: 01101 test 129: 01111 test 130: 10001 test 131: 10011 test 132: 10101 test 133: 10111 test 134: 11001 test 135: 11011 test 136: 11101 test 137: 11110 test 138: 00001 test 139: 00011 test 140: 00101 test 141: 00111 test 142: 01001 test 143: 01011 test 144: 01101 test 145: 01111 test 146: 10001 test 147: 10011 test 148: 10101 test 149: 10111 test 150: 11001 test 151: 11011 test 152: 11101 test 153: 11110 test 154: 00001 test 155: 00011 test 156: 00101 test 157: 00111 test 158: 01001 test 159: 01011 test 160: 01101 test 161: 01111 test 162: 10001 test 163: 10011 test 164: 10101 test 165: 10111 test 166: 11001 test 167: 11011 test 168: 11101 test 169: 11110 test 170: 00001 test 171: 00011 test 172: 00101 test 173: 00111 test 174: 01001 test 175: 01011 test 176: 01101 test 177: 01111 test 178: 10001 test 179: 10011 test 180: 10101 test 181: 10111 test 182: 11001 test 183: 11011 test 184: 11101 test 185: 11110 test 186: 00001 test 187: 00011 test 188: 00101 test 189: 00111 test 190: 01001 test 191: 01011 test 192: 01101 test 193: 01111 test 194: 10001 test 195: 10011 test 196: 10101 test 197: 10111 test 198: 11001 test 199: 11011 test 200: 11101 test 201: 11110 test 202: 111101111011110111101111011110 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0200 column 8: offset 0, mask 0x0100 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x2000 column 12: offset 1, mask 0x1000 column 13: offset 1, mask 0x0800 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0010 column 17: offset 0, mask 0x0008 column 18: offset 0, mask 0x0004 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0001 column 22: offset 1, mask 0x0002 column 23: offset 1, mask 0x0004 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x08E1 0x4310 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0801 0x4210 0x0002 0x0000 0x0000 2: 0x0801 0x4210 0x0002 0x0000 0x0000 3: 0x1801 0x4210 0x0002 0x0000 0x0000 4: 0x2801 0x4210 0x0002 0x0000 0x0000 5: 0x3801 0x4210 0x0002 0x0000 0x0000 6: 0x4801 0x4210 0x0002 0x0000 0x0000 7: 0x5801 0x4210 0x0002 0x0000 0x0000 8: 0x6801 0x4210 0x0002 0x0000 0x0000 9: 0x7801 0x4210 0x0002 0x0000 0x0000 10: 0x8801 0x4210 0x0002 0x0000 0x0000 11: 0x9801 0x4210 0x0002 0x0000 0x0000 12: 0xA801 0x4210 0x0002 0x0000 0x0000 13: 0xB801 0x4210 0x0002 0x0000 0x0000 14: 0xC801 0x4210 0x0002 0x0000 0x0000 15: 0xD801 0x4210 0x0002 0x0000 0x0000 16: 0xE801 0x4210 0x0002 0x0000 0x0000 17: 0xF001 0x4210 0x0002 0x0000 0x0000 18: 0x0801 0x4210 0x0002 0x0000 0x0000 19: 0x0801 0x4210 0x0002 0x0000 0x0000 20: 0x0801 0xC210 0x0002 0x0000 0x0000 21: 0x0901 0x4210 0x0002 0x0000 0x0000 22: 0x0901 0xC210 0x0002 0x0000 0x0000 23: 0x0A01 0x4210 0x0002 0x0000 0x0000 24: 0x0A01 0xC210 0x0002 0x0000 0x0000 25: 0x0B01 0x4210 0x0002 0x0000 0x0000 26: 0x0B01 0xC210 0x0002 0x0000 0x0000 27: 0x0C01 0x4210 0x0002 0x0000 0x0000 28: 0x0C01 0xC210 0x0002 0x0000 0x0000 29: 0x0D01 0x4210 0x0002 0x0000 0x0000 30: 0x0D01 0xC210 0x0002 0x0000 0x0000 31: 0x0E01 0x4210 0x0002 0x0000 0x0000 32: 0x0E01 0xC210 0x0002 0x0000 0x0000 33: 0x0F01 0x4210 0x0002 0x0000 0x0000 34: 0x0F01 0x8210 0x0002 0x0000 0x0000 35: 0x0801 0x4210 0x0002 0x0000 0x0000 36: 0x0801 0x4210 0x0002 0x0000 0x0000 37: 0x0801 0x4610 0x0002 0x0000 0x0000 38: 0x0801 0x4A10 0x0002 0x0000 0x0000 39: 0x0801 0x4E10 0x0002 0x0000 0x0000 40: 0x0801 0x5210 0x0002 0x0000 0x0000 41: 0x0801 0x5610 0x0002 0x0000 0x0000 42: 0x0801 0x5A10 0x0002 0x0000 0x0000 43: 0x0801 0x5E10 0x0002 0x0000 0x0000 44: 0x0801 0x6210 0x0002 0x0000 0x0000 45: 0x0801 0x6610 0x0002 0x0000 0x0000 46: 0x0801 0x6A10 0x0002 0x0000 0x0000 47: 0x0801 0x6E10 0x0002 0x0000 0x0000 48: 0x0801 0x7210 0x0002 0x0000 0x0000 49: 0x0801 0x7610 0x0002 0x0000 0x0000 50: 0x0801 0x7A10 0x0002 0x0000 0x0000 51: 0x0801 0x7C10 0x0002 0x0000 0x0000 52: 0x0801 0x4210 0x0002 0x0000 0x0000 53: 0x0801 0x4210 0x0002 0x0000 0x0000 54: 0x0803 0x4210 0x0002 0x0000 0x0000 55: 0x0805 0x4210 0x0002 0x0000 0x0000 56: 0x0807 0x4210 0x0002 0x0000 0x0000 57: 0x0809 0x4210 0x0002 0x0000 0x0000 58: 0x080B 0x4210 0x0002 0x0000 0x0000 59: 0x080D 0x4210 0x0002 0x0000 0x0000 60: 0x080F 0x4210 0x0002 0x0000 0x0000 61: 0x0811 0x4210 0x0002 0x0000 0x0000 62: 0x0813 0x4210 0x0002 0x0000 0x0000 63: 0x0815 0x4210 0x0002 0x0000 0x0000 64: 0x0817 0x4210 0x0002 0x0000 0x0000 65: 0x0819 0x4210 0x0002 0x0000 0x0000 66: 0x081B 0x4210 0x0002 0x0000 0x0000 67: 0x081D 0x4210 0x0002 0x0000 0x0000 68: 0x081E 0x4210 0x0002 0x0000 0x0000 69: 0x0801 0x4210 0x0002 0x0000 0x0000 70: 0x0801 0x4210 0x0002 0x0000 0x0000 71: 0x0801 0x4218 0x0002 0x0000 0x0000 72: 0x0801 0x4214 0x0002 0x0000 0x0000 73: 0x0801 0x421C 0x0002 0x0000 0x0000 74: 0x0801 0x4212 0x0002 0x0000 0x0000 75: 0x0801 0x421A 0x0002 0x0000 0x0000 76: 0x0801 0x4216 0x0002 0x0000 0x0000 77: 0x0801 0x421E 0x0002 0x0000 0x0000 78: 0x0801 0x4211 0x0002 0x0000 0x0000 79: 0x0801 0x4219 0x0002 0x0000 0x0000 80: 0x0801 0x4215 0x0002 0x0000 0x0000 81: 0x0801 0x421D 0x0002 0x0000 0x0000 82: 0x0801 0x4213 0x0002 0x0000 0x0000 83: 0x0801 0x421B 0x0002 0x0000 0x0000 84: 0x0801 0x4217 0x0002 0x0000 0x0000 85: 0x0801 0x420F 0x0002 0x0000 0x0000 86: 0x0801 0x4210 0x0002 0x0000 0x0000 87: 0x0801 0x4210 0x0002 0x0000 0x0000 88: 0x0801 0x4210 0x0003 0x0000 0x0000 89: 0x0801 0x4290 0x0002 0x0000 0x0000 90: 0x0801 0x4290 0x0003 0x0000 0x0000 91: 0x0801 0x4250 0x0002 0x0000 0x0000 92: 0x0801 0x4250 0x0003 0x0000 0x0000 93: 0x0801 0x42D0 0x0002 0x0000 0x0000 94: 0x0801 0x42D0 0x0003 0x0000 0x0000 95: 0x0801 0x4230 0x0002 0x0000 0x0000 96: 0x0801 0x4230 0x0003 0x0000 0x0000 97: 0x0801 0x42B0 0x0002 0x0000 0x0000 98: 0x0801 0x42B0 0x0003 0x0000 0x0000 99: 0x0801 0x4270 0x0002 0x0000 0x0000 100: 0x0801 0x4270 0x0003 0x0000 0x0000 101: 0x0801 0x42F0 0x0002 0x0000 0x0000 102: 0x0801 0x42F0 0x0001 0x0000 0x0000 103: 0x0801 0x4210 0x0002 0x0000 0x0000 104: 0x0801 0x4210 0x0002 0x0000 0x0000 105: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 106: 0x0F1E 0xBCEF 0x0001 0x0000 0x0000 107: 0x1F1E 0xBCEF 0x0001 0x0000 0x0000 108: 0x2F1E 0xBCEF 0x0001 0x0000 0x0000 109: 0x3F1E 0xBCEF 0x0001 0x0000 0x0000 110: 0x4F1E 0xBCEF 0x0001 0x0000 0x0000 111: 0x5F1E 0xBCEF 0x0001 0x0000 0x0000 112: 0x6F1E 0xBCEF 0x0001 0x0000 0x0000 113: 0x7F1E 0xBCEF 0x0001 0x0000 0x0000 114: 0x8F1E 0xBCEF 0x0001 0x0000 0x0000 115: 0x9F1E 0xBCEF 0x0001 0x0000 0x0000 116: 0xAF1E 0xBCEF 0x0001 0x0000 0x0000 117: 0xBF1E 0xBCEF 0x0001 0x0000 0x0000 118: 0xCF1E 0xBCEF 0x0001 0x0000 0x0000 119: 0xDF1E 0xBCEF 0x0001 0x0000 0x0000 120: 0xEF1E 0xBCEF 0x0001 0x0000 0x0000 121: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 122: 0xF01E 0x7CEF 0x0001 0x0000 0x0000 123: 0xF01E 0xFCEF 0x0001 0x0000 0x0000 124: 0xF11E 0x7CEF 0x0001 0x0000 0x0000 125: 0xF11E 0xFCEF 0x0001 0x0000 0x0000 126: 0xF21E 0x7CEF 0x0001 0x0000 0x0000 127: 0xF21E 0xFCEF 0x0001 0x0000 0x0000 128: 0xF31E 0x7CEF 0x0001 0x0000 0x0000 129: 0xF31E 0xFCEF 0x0001 0x0000 0x0000 130: 0xF41E 0x7CEF 0x0001 0x0000 0x0000 131: 0xF41E 0xFCEF 0x0001 0x0000 0x0000 132: 0xF51E 0x7CEF 0x0001 0x0000 0x0000 133: 0xF51E 0xFCEF 0x0001 0x0000 0x0000 134: 0xF61E 0x7CEF 0x0001 0x0000 0x0000 135: 0xF61E 0xFCEF 0x0001 0x0000 0x0000 136: 0xF71E 0x7CEF 0x0001 0x0000 0x0000 137: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 138: 0xF71E 0x82EF 0x0001 0x0000 0x0000 139: 0xF71E 0x86EF 0x0001 0x0000 0x0000 140: 0xF71E 0x8AEF 0x0001 0x0000 0x0000 141: 0xF71E 0x8EEF 0x0001 0x0000 0x0000 142: 0xF71E 0x92EF 0x0001 0x0000 0x0000 143: 0xF71E 0x96EF 0x0001 0x0000 0x0000 144: 0xF71E 0x9AEF 0x0001 0x0000 0x0000 145: 0xF71E 0x9EEF 0x0001 0x0000 0x0000 146: 0xF71E 0xA2EF 0x0001 0x0000 0x0000 147: 0xF71E 0xA6EF 0x0001 0x0000 0x0000 148: 0xF71E 0xAAEF 0x0001 0x0000 0x0000 149: 0xF71E 0xAEEF 0x0001 0x0000 0x0000 150: 0xF71E 0xB2EF 0x0001 0x0000 0x0000 151: 0xF71E 0xB6EF 0x0001 0x0000 0x0000 152: 0xF71E 0xBAEF 0x0001 0x0000 0x0000 153: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 154: 0xF701 0xBCEF 0x0001 0x0000 0x0000 155: 0xF703 0xBCEF 0x0001 0x0000 0x0000 156: 0xF705 0xBCEF 0x0001 0x0000 0x0000 157: 0xF707 0xBCEF 0x0001 0x0000 0x0000 158: 0xF709 0xBCEF 0x0001 0x0000 0x0000 159: 0xF70B 0xBCEF 0x0001 0x0000 0x0000 160: 0xF70D 0xBCEF 0x0001 0x0000 0x0000 161: 0xF70F 0xBCEF 0x0001 0x0000 0x0000 162: 0xF711 0xBCEF 0x0001 0x0000 0x0000 163: 0xF713 0xBCEF 0x0001 0x0000 0x0000 164: 0xF715 0xBCEF 0x0001 0x0000 0x0000 165: 0xF717 0xBCEF 0x0001 0x0000 0x0000 166: 0xF719 0xBCEF 0x0001 0x0000 0x0000 167: 0xF71B 0xBCEF 0x0001 0x0000 0x0000 168: 0xF71D 0xBCEF 0x0001 0x0000 0x0000 169: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 170: 0xF71E 0xBCF0 0x0001 0x0000 0x0000 171: 0xF71E 0xBCF8 0x0001 0x0000 0x0000 172: 0xF71E 0xBCF4 0x0001 0x0000 0x0000 173: 0xF71E 0xBCFC 0x0001 0x0000 0x0000 174: 0xF71E 0xBCF2 0x0001 0x0000 0x0000 175: 0xF71E 0xBCFA 0x0001 0x0000 0x0000 176: 0xF71E 0xBCF6 0x0001 0x0000 0x0000 177: 0xF71E 0xBCFE 0x0001 0x0000 0x0000 178: 0xF71E 0xBCF1 0x0001 0x0000 0x0000 179: 0xF71E 0xBCF9 0x0001 0x0000 0x0000 180: 0xF71E 0xBCF5 0x0001 0x0000 0x0000 181: 0xF71E 0xBCFD 0x0001 0x0000 0x0000 182: 0xF71E 0xBCF3 0x0001 0x0000 0x0000 183: 0xF71E 0xBCFB 0x0001 0x0000 0x0000 184: 0xF71E 0xBCF7 0x0001 0x0000 0x0000 185: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 186: 0xF71E 0xBC0F 0x0002 0x0000 0x0000 187: 0xF71E 0xBC0F 0x0003 0x0000 0x0000 188: 0xF71E 0xBC8F 0x0002 0x0000 0x0000 189: 0xF71E 0xBC8F 0x0003 0x0000 0x0000 190: 0xF71E 0xBC4F 0x0002 0x0000 0x0000 191: 0xF71E 0xBC4F 0x0003 0x0000 0x0000 192: 0xF71E 0xBCCF 0x0002 0x0000 0x0000 193: 0xF71E 0xBCCF 0x0003 0x0000 0x0000 194: 0xF71E 0xBC2F 0x0002 0x0000 0x0000 195: 0xF71E 0xBC2F 0x0003 0x0000 0x0000 196: 0xF71E 0xBCAF 0x0002 0x0000 0x0000 197: 0xF71E 0xBCAF 0x0003 0x0000 0x0000 198: 0xF71E 0xBC6F 0x0002 0x0000 0x0000 199: 0xF71E 0xBC6F 0x0003 0x0000 0x0000 200: 0xF71E 0xBCEF 0x0002 0x0000 0x0000 201: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 202: 0xF71E 0xBCEF 0x0001 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIIOIIIIOIIIIOG P GIIIIOIIIIOIIIIO G P G UUT inputs: 24 UUT outputs: 6 pins used: 30 not used: 36 202 'test steps' 238 lines M617 REV E 6 4-INPUT NAND BUFFERS (48ma) (7440) PINS Main menu Sat Jul 01 09:56:19 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 09:56:34 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFHJKLMNPRSDEFHJKLMNPRSTUV SIDE 111111111111111222222222222222 DIRECTION IIIIOIIIIOIIIIOIIIIOIIIIOIIIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 24 Main menu Sat Jul 01 09:56:38 2017 test file is: tests\m617.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m623.new reading test file: tests\m623.new comment: M623 12 2-input OR bus buffer (open collector transistor outputs) comment: comment: WORKS, BUT NEEDS ALL INPUTS HI TESTS. comment: pins: PINS pins: 1 I AC1 E1-11,8 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 2 I AA1 E1-12 INPUT A pins: 3 I AB1 E1-9 INPUT B pins: 4 P AD1 E1-13,Q2 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 5 P AE1 E1-10,Q4 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: 6 I AJ1 E2-11,8 ENABLE C,D-N LOW TO ENABLE OUTPUT C AND D. pins: 7 I AF1 E2-12 INPUT C pins: 8 I AH1 E2-9 INPUT D pins: 9 P AK1 E2-13,Q6 OUTPUT C = INPUT C OR ENABLE C,D-N. pins: 10 P AL1 E2-10,Q8 OUTPUT D = INPUT D OR ENABLE C,D-N. pins: 11 I AP1 E3-11,8 ENABLE E,F-N LOW TO ENABLE OUTPUT E AND F. pins: 12 I AM1 E3-12 INPUT E pins: 13 I AN1 E3-9 INPUT F pins: 14 P AR1 E3-13,Q10 OUTPUT E = INPUT E OR ENABLE E,F-N. pins: 15 P AS1 E3-10,Q12 OUTPUT F = INPUT F OR ENABLE E,F-N. pins: 16 I AF2 E1-5,2 ENABLE H,J-N LOW TO ENABLE OUTPUT H AND J. pins: 17 I AD2 E1-6 INPUT H pins: 18 I AE2 E1-3 INPUT J pins: 19 P AH2 E1-4,Q1 OUTPUT H = INPUT H OR ENABLE H,J-N. pins: 20 P AJ2 E1-1,Q3 OUTPUT J = INPUT J OR ENABLE H,J-N. pins: 21 I AM2 E2-5,2 ENABLE K,L-N LOW TO ENABLE OUTPUT K AND L. pins: 22 I AK2 E2-6 INPUT K pins: 23 I AL2 E2-3 INPUT L pins: 24 P AN2 E2-4,Q5 OUTPUT K = INPUT K OR ENABLE K,L-N. pins: 25 P AP2 E2-1,Q7 OUTPUT L = INPUT L OR ENABLE K,L-N. pins: 26 I AT2 E3-5,2 ENABLE A,B-N LOW TO ENABLE OUTPUT A AND B. pins: 27 I AR2 E3-6 INPUT A pins: 28 I AS2 E3-3 INPUT B pins: 29 P AU2 E3-4,Q9 OUTPUT A = INPUT A OR ENABLE A,B-N. pins: 30 P AV2 E3-1,Q11 OUTPUT B = INPUT B OR ENABLE A,B-N. pins: direction: IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP test 1: 100111001110011100111001110011 test 2: 10111 test 3: 11111 test 4: 11011 test 5: 01010 test 6: 01111 test 7: 00101 test 8: 00000 test 9: 10011 test 10: 10111 test 11: 11111 test 12: 11011 test 13: 01010 test 14: 01111 test 15: 00101 test 16: 00000 test 17: 10011 test 18: 10111 test 19: 11111 test 20: 11011 test 21: 01010 test 22: 01111 test 23: 00101 test 24: 00000 test 25: 10011 test 26: 10111 test 27: 11111 test 28: 11011 test 29: 01010 test 30: 01111 test 31: 00101 test 32: 00000 test 33: 10011 test 34: 10111 test 35: 11111 test 36: 11011 test 37: 01010 test 38: 01111 test 39: 00101 test 40: 00000 test 41: 10011 test 42: 10111 test 43: 11111 test 44: 11011 test 45: 01010 test 46: 01111 test 47: 00101 test 48: 00000 test 49: 10011 end: END summary column 1: offset 0, mask 0x2000 column 2: offset 0, mask 0x8000 column 3: offset 0, mask 0x4000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0100 column 7: offset 0, mask 0x0400 column 8: offset 0, mask 0x0200 column 9: offset 1, mask 0x8000 column 10: offset 1, mask 0x4000 column 11: offset 1, mask 0x0800 column 12: offset 1, mask 0x2000 column 13: offset 1, mask 0x1000 column 14: offset 1, mask 0x0400 column 15: offset 1, mask 0x0200 column 16: offset 0, mask 0x0004 column 17: offset 0, mask 0x0010 column 18: offset 0, mask 0x0008 column 19: offset 0, mask 0x0002 column 20: offset 0, mask 0x0001 column 21: offset 1, mask 0x0004 column 22: offset 1, mask 0x0001 column 23: offset 1, mask 0x0002 column 24: offset 1, mask 0x0008 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0080 column 27: offset 1, mask 0x0020 column 28: offset 1, mask 0x0040 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x18E3 0xC718 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x1803 0xC618 0x0003 0x0000 0x0000 test step out_data dont care 1: 0x3907 0xCE9C 0x0003 0x0000 0x0000 2: 0x7907 0xCE9C 0x0003 0x0000 0x0000 3: 0xF907 0xCE9C 0x0003 0x0000 0x0000 4: 0xB907 0xCE9C 0x0003 0x0000 0x0000 5: 0x9107 0xCE9C 0x0003 0x0000 0x0000 6: 0xD907 0xCE9C 0x0003 0x0000 0x0000 7: 0x4907 0xCE9C 0x0003 0x0000 0x0000 8: 0x0107 0xCE9C 0x0003 0x0000 0x0000 9: 0x3907 0xCE9C 0x0003 0x0000 0x0000 10: 0x3B07 0xCE9C 0x0003 0x0000 0x0000 11: 0x3F07 0xCE9C 0x0003 0x0000 0x0000 12: 0x3D07 0xCE9C 0x0003 0x0000 0x0000 13: 0x3C07 0x8E9C 0x0003 0x0000 0x0000 14: 0x3E07 0xCE9C 0x0003 0x0000 0x0000 15: 0x3A07 0x4E9C 0x0003 0x0000 0x0000 16: 0x3807 0x0E9C 0x0003 0x0000 0x0000 17: 0x3907 0xCE9C 0x0003 0x0000 0x0000 18: 0x3907 0xDE9C 0x0003 0x0000 0x0000 19: 0x3907 0xFE9C 0x0003 0x0000 0x0000 20: 0x3907 0xEE9C 0x0003 0x0000 0x0000 21: 0x3907 0xE49C 0x0003 0x0000 0x0000 22: 0x3907 0xF69C 0x0003 0x0000 0x0000 23: 0x3907 0xD29C 0x0003 0x0000 0x0000 24: 0x3907 0xC09C 0x0003 0x0000 0x0000 25: 0x3907 0xCE9C 0x0003 0x0000 0x0000 26: 0x390F 0xCE9C 0x0003 0x0000 0x0000 27: 0x391F 0xCE9C 0x0003 0x0000 0x0000 28: 0x3917 0xCE9C 0x0003 0x0000 0x0000 29: 0x3912 0xCE9C 0x0003 0x0000 0x0000 30: 0x391B 0xCE9C 0x0003 0x0000 0x0000 31: 0x3909 0xCE9C 0x0003 0x0000 0x0000 32: 0x3900 0xCE9C 0x0003 0x0000 0x0000 33: 0x3907 0xCE9C 0x0003 0x0000 0x0000 34: 0x3907 0xCE9E 0x0003 0x0000 0x0000 35: 0x3907 0xCE9F 0x0003 0x0000 0x0000 36: 0x3907 0xCE9D 0x0003 0x0000 0x0000 37: 0x3907 0xCE89 0x0003 0x0000 0x0000 38: 0x3907 0xCE9B 0x0003 0x0000 0x0000 39: 0x3907 0xCE92 0x0003 0x0000 0x0000 40: 0x3907 0xCE80 0x0003 0x0000 0x0000 41: 0x3907 0xCE9C 0x0003 0x0000 0x0000 42: 0x3907 0xCEDC 0x0003 0x0000 0x0000 43: 0x3907 0xCEFC 0x0003 0x0000 0x0000 44: 0x3907 0xCEBC 0x0003 0x0000 0x0000 45: 0x3907 0xCE3C 0x0001 0x0000 0x0000 46: 0x3907 0xCE7C 0x0003 0x0000 0x0000 47: 0x3907 0xCE5C 0x0002 0x0000 0x0000 48: 0x3907 0xCE1C 0x0000 0x0000 0x0000 49: 0x3907 0xCE9C 0x0003 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIIPPIIIPPIIIPPG P GIIIPPIIIPPIIIPP G P G UUT inputs: 18 UUT outputs: 12 pins used: 30 not used: 36 49 'test steps' 87 lines M623 12 2-input OR bus buffer (open collector transistor outputs) WORKS, BUT NEEDS ALL INPUTS HI TESTS. PINS Main menu Sat Jul 01 10:00:27 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 01 10:00:31 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:00:34 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 1: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 1 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 2: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 2 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 3: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 3 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 4: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 4 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 5: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 5 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 6: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 6 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 7: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 7 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 8: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 8 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 9: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 9 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 10: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 10 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 11: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 11 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 12: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 12 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 13: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 13 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 14: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 14 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 15: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 15 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 16: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 16 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 17: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 17 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 18: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 18 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 19: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 19 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 20: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 20 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 21: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 21 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 22: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 22 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 23: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 23 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 24: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 24 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 25: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 25 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 26: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 26 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 27: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 27 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 28: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 28 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 29: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 29 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 30: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 30 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 31: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 31 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 32: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 32 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 source: 10011 changed: 1 11 step 41 100111001110011100111001110011 source: 10111 changed: 1 step 42 100111001110011100111001110111 source: 11111 changed: 1 step 43 100111001110011100111001111111 source: 11011 changed: 0 step 44 100111001110011100111001111011 source: 01010 changed: 0 0 step 45 100111001110011100111001101010 source: 01111 changed: 1 1 step 46 100111001110011100111001101111 source: 00101 changed: 0 0 step 47 100111001110011100111001100101 source: 00000 changed: 0 0 step 48 100111001110011100111001100000 source: 10011 changed: 1 11 step 49 100111001110011100111001110011 test 33: pass SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP this fail all fails was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 0, total passes 33 source: 100111001110011100111001110011 changed: step 1 100111001110011100111001110011 source: 10111 changed: 1 step 2 101111001110011100111001110011 source: 11111 changed: 1 step 3 111111001110011100111001110011 source: 11011 changed: 0 step 4 110111001110011100111001110011 source: 01010 changed: 0 0 step 5 010101001110011100111001110011 source: 01111 changed: 1 1 step 6 011111001110011100111001110011 source: 00101 changed: 0 0 step 7 001011001110011100111001110011 source: 00000 changed: 0 0 step 8 000001001110011100111001110011 source: 10011 changed: 1 11 step 9 100111001110011100111001110011 source: 10111 changed: 1 step 10 100111011110011100111001110011 source: 11111 changed: 1 step 11 100111111110011100111001110011 source: 11011 changed: 0 step 12 100111101110011100111001110011 source: 01010 changed: 0 0 step 13 100110101010011100111001110011 source: 01111 changed: 1 1 step 14 100110111110011100111001110011 source: 00101 changed: 0 0 step 15 100110010110011100111001110011 source: 00000 changed: 0 0 step 16 100110000010011100111001110011 source: 10011 changed: 1 11 step 17 100111001110011100111001110011 source: 10111 changed: 1 step 18 100111001110111100111001110011 source: 11111 changed: 1 step 19 100111001111111100111001110011 source: 11011 changed: 0 step 20 100111001111011100111001110011 source: 01010 changed: 0 0 step 21 100111001101010100111001110011 source: 01111 changed: 1 1 step 22 100111001101111100111001110011 source: 00101 changed: 0 0 step 23 100111001100101100111001110011 source: 00000 changed: 0 0 step 24 100111001100000100111001110011 source: 10011 changed: 1 11 step 25 100111001110011100111001110011 source: 10111 changed: 1 step 26 100111001110011101111001110011 source: 11111 changed: 1 step 27 100111001110011111111001110011 source: 11011 changed: 0 step 28 100111001110011110111001110011 source: 01010 changed: 0 0 step 29 100111001110011010101001110011 source: 01111 changed: 1 1 step 30 100111001110011011111001110011 source: 00101 changed: 0 0 step 31 100111001110011001011001110011 source: 00000 changed: 0 0 step 32 100111001110011000001001110011 source: 10011 changed: 1 11 step 33 100111001110011100111001110011 source: 10111 changed: 1 step 34 100111001110011100111011110011 source: 11111 changed: 1 step 35 100111001110011100111111110011 source: 11011 changed: 0 step 36 100111001110011100111101110011 source: 01010 changed: 0 0 step 37 100111001110011100110101010011 source: 01111 changed: 1 1 step 38 100111001110011100110111110011 source: 00101 changed: 0 0 step 39 100111001110011100110010110011 source: 00000 changed: 0 0 step 40 100111001110011100110000010011 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 322 Main menu Sat Jul 01 10:01:16 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:01:48 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 47 Main menu Sat Jul 01 10:01:50 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:02:03 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER CABDEJFHKLPMNRSFDEHJMKLNPTRSUV SIDE 111111111111111222222222222222 DIRECTION IIIPPIIIPPIIIPPIIIPPIIIPPIIIPP all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 40 Main menu Sat Jul 01 10:02:05 2017 test file is: tests\m623.new delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Sat Jul 01 10:02:33 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:02:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 33 Main menu Sat Jul 01 10:02:37 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Sat Jul 01 10:04:06 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 01 10:04:07 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0073 Main menu Sat Jul 01 10:04:08 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:04:13 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 28: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 28, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 3 010110110110110110110110110110 fail ^ step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 27 110110110110110110010110110110 fail ^ step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 44 010001001001001001001001001001 fail ^ step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 29: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 3 010110110110110110110110110110 fail ^ step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 27 110110110110110110010110110110 fail ^ step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 44 010001001001001001001001001001 fail ^ step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 30: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 30, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 3 010110110110110110110110110110 fail ^ step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 27 110110110110110110010110110110 fail ^ step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 44 010001001001001001001001001001 fail ^ step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 31: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 31, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 3 010110110110110110110110110110 fail ^ step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 27 110110110110110110010110110110 fail ^ step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 44 010001001001001001001001001001 fail ^ step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 32: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 32, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 32, total passes 0 Main menu Sat Jul 01 10:08:05 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m113.tst reading test file: tests\m113.tst comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Sat Jul 01 10:08:08 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:08:10 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 27 110110110110110110010110110110 fail ^ step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 44 010001001001001001001001001001 fail ^ step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 25: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 25, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 3 010110110110110110110110110110 fail ^ step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 27 110110110110110110010110110110 fail ^ step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 44 010001001001001001001001001001 fail ^ step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 26: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 26, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 3 010110110110110110110110110110 fail ^ step 4 001110110110110110110110110110 step 5 101110110110110110110110110110 step 6 110110110110110110110110110110 step 7 110011110110110110110110110110 step 8 110001110110110110110110110110 step 9 110101110110110110110110110110 step 10 110110110110110110110110110110 step 11 110110011110110110110110110110 step 12 110110001110110110110110110110 step 13 110110101110110110110110110110 step 14 110110110110110110110110110110 step 15 110110110011110110110110110110 step 16 110110110001110110110110110110 step 17 110110110101110110110110110110 step 18 110110110110110110110110110110 step 19 110110110110011110110110110110 step 20 110110110110001110110110110110 step 21 110110110110101110110110110110 step 22 110110110110110110110110110110 step 23 110110110110110011110110110110 step 24 110110110110110001110110110110 step 25 110110110110110101110110110110 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 27 110110110110110110010110110110 fail ^ step 28 110110110110110110001110110110 step 29 110110110110110110101110110110 step 30 110110110110110110110110110110 step 31 110110110110110110110011110110 step 32 110110110110110110110001110110 step 33 110110110110110110110101110110 step 34 110110110110110110110110110110 step 35 110110110110110110110110011110 step 36 110110110110110110110110001110 step 37 110110110110110110110110101110 step 38 110110110110110110110110110110 step 39 110110110110110110110110110011 step 40 110110110110110110110110110001 step 41 110110110110110110110110110101 step 42 110110110110110110110110110110 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 44 010001001001001001001001001001 fail ^ step 45 110001001001001001001001001001 step 46 101001001001001001001001001001 step 47 001001001001001001001001001001 step 48 001011001001001001001001001001 step 49 001110001001001001001001001001 step 50 001101001001001001001001001001 step 51 001001001001001001001001001001 step 52 001001011001001001001001001001 step 53 001001110001001001001001001001 step 54 001001101001001001001001001001 step 55 001001001001001001001001001001 step 56 001001001011001001001001001001 step 57 001001001110001001001001001001 step 58 001001001101001001001001001001 step 59 001001001001001001001001001001 step 60 001001001001011001001001001001 step 61 001001001001110001001001001001 step 62 001001001001101001001001001001 step 63 001001001001001001001001001001 step 64 001001001001001011001001001001 step 65 001001001001001110001001001001 step 66 001001001001001101001001001001 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 10 step 68 001001001001001001010001001001 fail ^ step 69 001001001001001001110001001001 step 70 001001001001001001101001001001 step 71 001001001001001001001001001001 step 72 001001001001001001001011001001 step 73 001001001001001001001110001001 step 74 001001001001001001001101001001 step 75 001001001001001001001001001001 step 76 001001001001001001001001011001 step 77 001001001001001001001001110001 step 78 001001001001001001001001101001 step 79 001001001001001001001001001001 step 80 001001001001001001001001001011 step 81 001001001001001001001001001110 step 82 001001001001001001001001001101 step 83 001001001001001001001001001001 test 27: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 27, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 001001001001001001001001001001 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO changed: 0 step 3 010110110110110110110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001 changed: 01 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 source: 011 changed: 0 1 step 23 110110110110110011110110110110 source: 001 changed: 0 step 24 110110110110110001110110110110 source: 101 changed: 1 step 25 110110110110110101110110110110 source: 110 changed: 10 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 step 27 110110110110110110010110110110 fail ^ source: 001 changed: 01 step 28 110110110110110110001110110110 source: 101 changed: 1 step 29 110110110110110110101110110110 source: 110 changed: 10 step 30 110110110110110110110110110110 source: 011 changed: 0 1 step 31 110110110110110110110011110110 source: 001 changed: 0 step 32 110110110110110110110001110110 source: 101 changed: 1 step 33 110110110110110110110101110110 source: 110 changed: 10 step 34 110110110110110110110110110110 source: 011 changed: 0 1 step 35 110110110110110110110110011110 source: 001 changed: 0 step 36 110110110110110110110110001110 source: 101 changed: 1 step 37 110110110110110110110110101110 source: 110 changed: 10 step 38 110110110110110110110110110110 source: 011 changed: 0 1 step 39 110110110110110110110110110011 source: 001 changed: 0 step 40 110110110110110110110110110001 source: 101 changed: 1 step 41 110110110110110110110110110101 source: 110 changed: 10 step 42 110110110110110110110110110110 source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 10 step 44 010001001001001001001001001001 fail ^ source: 110 changed: 1 step 45 110001001001001001001001001001 source: 101 changed: 01 step 46 101001001001001001001001001001 source: 001 changed: 0 step 47 001001001001001001001001001001 source: 011 changed: 1 step 48 001011001001001001001001001001 source: 110 changed: 1 0 step 49 001110001001001001001001001001 source: 101 changed: 01 step 50 001101001001001001001001001001 source: 001 changed: 0 step 51 001001001001001001001001001001 source: 011 changed: 1 step 52 001001011001001001001001001001 source: 110 changed: 1 0 step 53 001001110001001001001001001001 source: 101 changed: 01 step 54 001001101001001001001001001001 source: 001 changed: 0 step 55 001001001001001001001001001001 source: 011 changed: 1 step 56 001001001011001001001001001001 source: 110 changed: 1 0 step 57 001001001110001001001001001001 source: 101 changed: 01 step 58 001001001101001001001001001001 source: 001 changed: 0 step 59 001001001001001001001001001001 source: 011 changed: 1 step 60 001001001001011001001001001001 source: 110 changed: 1 0 step 61 001001001001110001001001001001 source: 101 changed: 01 step 62 001001001001101001001001001001 source: 001 changed: 0 step 63 001001001001001001001001001001 source: 011 changed: 1 step 64 001001001001001011001001001001 source: 110 changed: 1 0 step 65 001001001001001110001001001001 source: 101 changed: 01 step 66 001001001001001101001001001001 source: 001 changed: 0 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 10 step 68 001001001001001001010001001001 fail ^ source: 110 changed: 1 step 69 001001001001001001110001001001 source: 101 changed: 01 step 70 001001001001001001101001001001 source: 001 changed: 0 step 71 001001001001001001001001001001 source: 011 changed: 1 step 72 001001001001001001001011001001 source: 110 changed: 1 0 step 73 001001001001001001001110001001 source: 101 changed: 01 step 74 001001001001001001001101001001 source: 001 changed: 0 step 75 001001001001001001001001001001 source: 011 changed: 1 step 76 001001001001001001001001011001 source: 110 changed: 1 0 step 77 001001001001001001001001110001 source: 101 changed: 01 step 78 001001001001001001001001101001 source: 001 changed: 0 step 79 001001001001001001001001001001 source: 011 changed: 1 step 80 001001001001001001001001001011 source: 110 changed: 1 0 step 81 001001001001001001001001001110 source: 101 changed: 01 step 82 001001001001001001001001001101 source: 001 changed: 0 step 83 001001001001001001001001001001 test 28: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 28, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001001001001001001001001001001 changed: step 1 001001001001001001001001001001 source: 110110110110110110110110110110 changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 step 3 010110110110110110110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001 changed: 01 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 source: 011 changed: 0 1 step 23 110110110110110011110110110110 source: 001 changed: 0 step 24 110110110110110001110110110110 source: 101 changed: 1 step 25 110110110110110101110110110110 source: 110 changed: 10 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 step 27 110110110110110110010110110110 fail ^ source: 001 changed: 01 step 28 110110110110110110001110110110 source: 101 changed: 1 step 29 110110110110110110101110110110 source: 110 changed: 10 step 30 110110110110110110110110110110 source: 011 changed: 0 1 step 31 110110110110110110110011110110 source: 001 changed: 0 step 32 110110110110110110110001110110 source: 101 changed: 1 step 33 110110110110110110110101110110 source: 110 changed: 10 step 34 110110110110110110110110110110 source: 011 changed: 0 1 step 35 110110110110110110110110011110 source: 001 changed: 0 step 36 110110110110110110110110001110 source: 101 changed: 1 step 37 110110110110110110110110101110 source: 110 changed: 10 step 38 110110110110110110110110110110 source: 011 changed: 0 1 step 39 110110110110110110110110110011 source: 001 changed: 0 step 40 110110110110110110110110110001 source: 101 changed: 1 step 41 110110110110110110110110110101 source: 110 changed: 10 step 42 110110110110110110110110110110 source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 10 step 44 010001001001001001001001001001 fail ^ source: 110 changed: 1 step 45 110001001001001001001001001001 source: 101 changed: 01 step 46 101001001001001001001001001001 source: 001 changed: 0 step 47 001001001001001001001001001001 source: 011 changed: 1 step 48 001011001001001001001001001001 source: 110 changed: 1 0 step 49 001110001001001001001001001001 source: 101 changed: 01 step 50 001101001001001001001001001001 source: 001 changed: 0 step 51 001001001001001001001001001001 source: 011 changed: 1 step 52 001001011001001001001001001001 source: 110 changed: 1 0 step 53 001001110001001001001001001001 source: 101 changed: 01 step 54 001001101001001001001001001001 source: 001 changed: 0 step 55 001001001001001001001001001001 source: 011 changed: 1 step 56 001001001011001001001001001001 source: 110 changed: 1 0 step 57 001001001110001001001001001001 source: 101 changed: 01 step 58 001001001101001001001001001001 source: 001 changed: 0 step 59 001001001001001001001001001001 source: 011 changed: 1 step 60 001001001001011001001001001001 source: 110 changed: 1 0 step 61 001001001001110001001001001001 source: 101 changed: 01 step 62 001001001001101001001001001001 source: 001 changed: 0 step 63 001001001001001001001001001001 source: 011 changed: 1 step 64 001001001001001011001001001001 source: 110 changed: 1 0 step 65 001001001001001110001001001001 source: 101 changed: 01 step 66 001001001001001101001001001001 source: 001 changed: 0 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 10 step 68 001001001001001001010001001001 fail ^ source: 110 changed: 1 step 69 001001001001001001110001001001 source: 101 changed: 01 step 70 001001001001001001101001001001 source: 001 changed: 0 step 71 001001001001001001001001001001 source: 011 changed: 1 step 72 001001001001001001001011001001 source: 110 changed: 1 0 step 73 001001001001001001001110001001 source: 101 changed: 01 step 74 001001001001001001001101001001 source: 001 changed: 0 step 75 001001001001001001001001001001 source: 011 changed: 1 step 76 001001001001001001001001011001 source: 110 changed: 1 0 step 77 001001001001001001001001110001 source: 101 changed: 01 step 78 001001001001001001001001101001 source: 001 changed: 0 step 79 001001001001001001001001001001 source: 011 changed: 1 step 80 001001001001001001001001001011 source: 110 changed: 1 0 step 81 001001001001001001001001001110 source: 101 changed: 01 step 82 001001001001001001001001001101 source: 001 changed: 0 step 83 001001001001001001001001001001 test 29: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001001001001001001001001001001 changed: step 1 001001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110110110110110110110110110110 changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 step 3 010110110110110110110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001 changed: 01 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 source: 011 changed: 0 1 step 23 110110110110110011110110110110 source: 001 changed: 0 step 24 110110110110110001110110110110 source: 101 changed: 1 step 25 110110110110110101110110110110 source: 110 changed: 10 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 step 27 110110110110110110010110110110 fail ^ source: 001 changed: 01 step 28 110110110110110110001110110110 source: 101 changed: 1 step 29 110110110110110110101110110110 source: 110 changed: 10 step 30 110110110110110110110110110110 source: 011 changed: 0 1 step 31 110110110110110110110011110110 source: 001 changed: 0 step 32 110110110110110110110001110110 source: 101 changed: 1 step 33 110110110110110110110101110110 source: 110 changed: 10 step 34 110110110110110110110110110110 source: 011 changed: 0 1 step 35 110110110110110110110110011110 source: 001 changed: 0 step 36 110110110110110110110110001110 source: 101 changed: 1 step 37 110110110110110110110110101110 source: 110 changed: 10 step 38 110110110110110110110110110110 source: 011 changed: 0 1 step 39 110110110110110110110110110011 source: 001 changed: 0 step 40 110110110110110110110110110001 source: 101 changed: 1 step 41 110110110110110110110110110101 source: 110 changed: 10 step 42 110110110110110110110110110110 source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 10 step 44 010001001001001001001001001001 fail ^ source: 110 changed: 1 step 45 110001001001001001001001001001 source: 101 changed: 01 step 46 101001001001001001001001001001 source: 001 changed: 0 step 47 001001001001001001001001001001 source: 011 changed: 1 step 48 001011001001001001001001001001 source: 110 changed: 1 0 step 49 001110001001001001001001001001 source: 101 changed: 01 step 50 001101001001001001001001001001 source: 001 changed: 0 step 51 001001001001001001001001001001 source: 011 changed: 1 step 52 001001011001001001001001001001 source: 110 changed: 1 0 step 53 001001110001001001001001001001 source: 101 changed: 01 step 54 001001101001001001001001001001 source: 001 changed: 0 step 55 001001001001001001001001001001 source: 011 changed: 1 step 56 001001001011001001001001001001 source: 110 changed: 1 0 step 57 001001001110001001001001001001 source: 101 changed: 01 step 58 001001001101001001001001001001 source: 001 changed: 0 step 59 001001001001001001001001001001 source: 011 changed: 1 step 60 001001001001011001001001001001 source: 110 changed: 1 0 step 61 001001001001110001001001001001 source: 101 changed: 01 step 62 001001001001101001001001001001 source: 001 changed: 0 step 63 001001001001001001001001001001 source: 011 changed: 1 step 64 001001001001001011001001001001 source: 110 changed: 1 0 step 65 001001001001001110001001001001 source: 101 changed: 01 step 66 001001001001001101001001001001 source: 001 changed: 0 step 67 001001001001001001001001001001 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 10 step 68 001001001001001001010001001001 fail ^ source: 110 changed: 1 step 69 001001001001001001110001001001 source: 101 changed: 01 step 70 001001001001001001101001001001 source: 001 changed: 0 step 71 001001001001001001001001001001 source: 011 changed: 1 step 72 001001001001001001001011001001 source: 110 changed: 1 0 step 73 001001001001001001001110001001 source: 101 changed: 01 step 74 001001001001001001001101001001 source: 001 changed: 0 step 75 001001001001001001001001001001 source: 011 changed: 1 step 76 001001001001001001001001011001 source: 110 changed: 1 0 step 77 001001001001001001001001110001 source: 101 changed: 01 step 78 001001001001001001001001101001 source: 001 changed: 0 step 79 001001001001001001001001001001 source: 011 changed: 1 step 80 001001001001001001001001001011 source: 110 changed: 1 0 step 81 001001001001001001001001001110 source: 101 changed: 01 step 82 001001001001001001001001001101 source: 001 changed: 0 step 83 001001001001001001001001001001 test 30: *** FAIL *************************** 4 steps failed SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO this fail O O all fails O O was hi 111111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 000000000000000000000000000000 total fails 30, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001001001001001001001001001001 changed: step 1 001001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110110110110110110110110110110 changed: 110110110110110110110110110110 step 2 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 step 3 010110110110110110110110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 001 changed: 01 step 4 001110110110110110110110110110 source: 101 changed: 1 step 5 101110110110110110110110110110 source: 110 changed: 10 step 6 110110110110110110110110110110 source: 011 changed: 0 1 step 7 110011110110110110110110110110 source: 001 changed: 0 step 8 110001110110110110110110110110 source: 101 changed: 1 step 9 110101110110110110110110110110 source: 110 changed: 10 step 10 110110110110110110110110110110 source: 011 changed: 0 1 step 11 110110011110110110110110110110 source: 001 changed: 0 step 12 110110001110110110110110110110 source: 101 changed: 1 step 13 110110101110110110110110110110 source: 110 changed: 10 step 14 110110110110110110110110110110 source: 011 changed: 0 1 step 15 110110110011110110110110110110 source: 001 changed: 0 step 16 110110110001110110110110110110 source: 101 changed: 1 step 17 110110110101110110110110110110 source: 110 changed: 10 step 18 110110110110110110110110110110 source: 011 changed: 0 1 step 19 110110110110011110110110110110 source: 001 changed: 0 step 20 110110110110001110110110110110 source: 101 changed: 1 step 21 110110110110101110110110110110 source: 110 changed: 10 step 22 110110110110110110110110110110 source: 011 changed: 0 1 step 23 110110110110110011110110110110 source: 001 changed: 0 step 24 110110110110110001110110110110 source: 101 changed: 1 step 25 110110110110110101110110110110 source: 110 changed: 10 step 26 110110110110110110110110110110 SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 step 27 110110110110110110010110110110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001 changed: 01 step 28 110110110110110110001110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 1 step 29 110110110110110110101110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 10 step 30 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 1 step 31 110110110110110110110011110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001 changed: 0 step 32 110110110110110110110001110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 1 step 33 110110110110110110110101110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 10 step 34 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 1 step 35 110110110110110110110110011110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001 changed: 0 step 36 110110110110110110110110001110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 1 step 37 110110110110110110110110101110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 10 step 38 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 0 1 step 39 110110110110110110110110110011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001 changed: 0 step 40 110110110110110110110110110001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 1 step 41 110110110110110110110110110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 10 step 42 110110110110110110110110110110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 001001001001001001001001001001 changed: 001001001001001001001001001001 step 43 001001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 011 changed: 10 step 44 010001001001001001001001001001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 110 changed: 1 step 45 110001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO source: 101 changed: 01 step 46 101001001001001001001001001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails O O was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 30, total passes 0 Main menu Sat Jul 01 10:37:17 2017 test file is: tests\m113.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 10:43:31 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M113.TST reading test file: tests\M113.TST comment: M113 10 2-input NAND comment: pins: PINS pins: 1 I AA1 E1-1 pins: 2 I AB1 E1-2 pins: 3 O AC1 E1-3 pins: 4 I AD1 E1-4 pins: 5 I AE1 E1-5 pins: 6 O AF1 E1-6 pins: 7 I AD2 E1-13 pins: 8 I AE2 E1-12 pins: 9 O AF2 E1-11 pins: 10 I AH1 E3-4 pins: 11 I AJ1 E3-5 pins: 12 O AK1 E3-6 pins: 13 I AH2 E3-10 pins: 14 I AJ2 E3-9 pins: 15 O AK2 E3-8 pins: 16 I AL1 E2-1 pins: 17 I AM1 E2-2 pins: 18 O AN1 E2-3 pins: 19 I AL2 E3-10 pins: 20 I AM2 E3-9 pins: 21 O AN2 E3-8 pins: 22 I AP1 E2-4 pins: 23 I AR1 E2-5 pins: 24 O AS1 E2-6 pins: 25 I AP2 E2-13 pins: 26 I AR2 E2-12 pins: 27 O AS2 E2-11 pins: 28 I AT2 E2-10 pins: 29 I AU2 E2-9 pins: 30 O AV2 E2-8 pins: direction: IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO test 1: 001001001001001001001001001001 test 2: 110110110110110110110110110110 test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 test 19: 011 test 20: 001 test 21: 101 test 22: 110 test 23: 011 test 24: 001 test 25: 101 test 26: 110 test 27: 011 test 28: 001 test 29: 101 test 30: 110 test 31: 011 test 32: 001 test 33: 101 test 34: 110 test 35: 011 test 36: 001 test 37: 101 test 38: 110 test 39: 011 test 40: 001 test 41: 101 test 42: 110 test 43: 001001001001001001001001001001 test 44: 011 test 45: 110 test 46: 101 test 47: 001 test 48: 011 test 49: 110 test 50: 101 test 51: 001 test 52: 011 test 53: 110 test 54: 101 test 55: 001 test 56: 011 test 57: 110 test 58: 101 test 59: 001 test 60: 011 test 61: 110 test 62: 101 test 63: 001 test 64: 011 test 65: 110 test 66: 101 test 67: 001 test 68: 011 test 69: 110 test 70: 101 test 71: 001 test 72: 011 test 73: 110 test 74: 101 test 75: 001 test 76: 011 test 77: 110 test 78: 101 test 79: 001 test 80: 011 test 81: 110 test 82: 101 test 83: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x4000 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x1000 column 5: offset 0, mask 0x0800 column 6: offset 0, mask 0x0400 column 7: offset 0, mask 0x0010 column 8: offset 0, mask 0x0008 column 9: offset 0, mask 0x0004 column 10: offset 0, mask 0x0200 column 11: offset 0, mask 0x0100 column 12: offset 1, mask 0x8000 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x4000 column 17: offset 1, mask 0x2000 column 18: offset 1, mask 0x1000 column 19: offset 1, mask 0x0002 column 20: offset 1, mask 0x0004 column 21: offset 1, mask 0x0008 column 22: offset 1, mask 0x0800 column 23: offset 1, mask 0x0400 column 24: offset 1, mask 0x0200 column 25: offset 1, mask 0x0010 column 26: offset 1, mask 0x0020 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 column 29: offset 2, mask 0x0001 column 30: offset 2, mask 0x0002 direction bits (1=input) 0x24E4 0x9349 0xFFFA 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2404 0x9249 0x0002 0x0000 0x0000 2: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 3: 0x7B1B 0x6CB6 0x0001 0x0000 0x0000 4: 0x3B1B 0x6CB6 0x0001 0x0000 0x0000 5: 0xBB1B 0x6CB6 0x0001 0x0000 0x0000 6: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 7: 0xCF1B 0x6CB6 0x0001 0x0000 0x0000 8: 0xC71B 0x6CB6 0x0001 0x0000 0x0000 9: 0xD71B 0x6CB6 0x0001 0x0000 0x0000 10: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 11: 0xDB0F 0x6CB6 0x0001 0x0000 0x0000 12: 0xDB07 0x6CB6 0x0001 0x0000 0x0000 13: 0xDB17 0x6CB6 0x0001 0x0000 0x0000 14: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 15: 0xD91B 0xECB6 0x0001 0x0000 0x0000 16: 0xD81B 0xECB6 0x0001 0x0000 0x0000 17: 0xDA1B 0xECB6 0x0001 0x0000 0x0000 18: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 19: 0xDB19 0x6CB7 0x0001 0x0000 0x0000 20: 0xDB18 0x6CB7 0x0001 0x0000 0x0000 21: 0xDB1A 0x6CB7 0x0001 0x0000 0x0000 22: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 23: 0xDB1B 0x3CB6 0x0001 0x0000 0x0000 24: 0xDB1B 0x1CB6 0x0001 0x0000 0x0000 25: 0xDB1B 0x5CB6 0x0001 0x0000 0x0000 26: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 27: 0xDB1B 0x6CBC 0x0001 0x0000 0x0000 28: 0xDB1B 0x6CB8 0x0001 0x0000 0x0000 29: 0xDB1B 0x6CBA 0x0001 0x0000 0x0000 30: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 31: 0xDB1B 0x66B6 0x0001 0x0000 0x0000 32: 0xDB1B 0x62B6 0x0001 0x0000 0x0000 33: 0xDB1B 0x6AB6 0x0001 0x0000 0x0000 34: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 35: 0xDB1B 0x6CE6 0x0001 0x0000 0x0000 36: 0xDB1B 0x6CC6 0x0001 0x0000 0x0000 37: 0xDB1B 0x6CD6 0x0001 0x0000 0x0000 38: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 39: 0xDB1B 0x6C36 0x0003 0x0000 0x0000 40: 0xDB1B 0x6C36 0x0002 0x0000 0x0000 41: 0xDB1B 0x6CB6 0x0002 0x0000 0x0000 42: 0xDB1B 0x6CB6 0x0001 0x0000 0x0000 43: 0x2404 0x9249 0x0002 0x0000 0x0000 44: 0x6404 0x9249 0x0002 0x0000 0x0000 45: 0xC404 0x9249 0x0002 0x0000 0x0000 46: 0xA404 0x9249 0x0002 0x0000 0x0000 47: 0x2404 0x9249 0x0002 0x0000 0x0000 48: 0x2C04 0x9249 0x0002 0x0000 0x0000 49: 0x3804 0x9249 0x0002 0x0000 0x0000 50: 0x3404 0x9249 0x0002 0x0000 0x0000 51: 0x2404 0x9249 0x0002 0x0000 0x0000 52: 0x240C 0x9249 0x0002 0x0000 0x0000 53: 0x2418 0x9249 0x0002 0x0000 0x0000 54: 0x2414 0x9249 0x0002 0x0000 0x0000 55: 0x2404 0x9249 0x0002 0x0000 0x0000 56: 0x2504 0x9249 0x0002 0x0000 0x0000 57: 0x2704 0x1249 0x0002 0x0000 0x0000 58: 0x2604 0x9249 0x0002 0x0000 0x0000 59: 0x2404 0x9249 0x0002 0x0000 0x0000 60: 0x2405 0x9249 0x0002 0x0000 0x0000 61: 0x2407 0x9248 0x0002 0x0000 0x0000 62: 0x2406 0x9249 0x0002 0x0000 0x0000 63: 0x2404 0x9249 0x0002 0x0000 0x0000 64: 0x2404 0xB249 0x0002 0x0000 0x0000 65: 0x2404 0xE249 0x0002 0x0000 0x0000 66: 0x2404 0xD249 0x0002 0x0000 0x0000 67: 0x2404 0x9249 0x0002 0x0000 0x0000 68: 0x2404 0x924D 0x0002 0x0000 0x0000 69: 0x2404 0x9247 0x0002 0x0000 0x0000 70: 0x2404 0x924B 0x0002 0x0000 0x0000 71: 0x2404 0x9249 0x0002 0x0000 0x0000 72: 0x2404 0x9649 0x0002 0x0000 0x0000 73: 0x2404 0x9C49 0x0002 0x0000 0x0000 74: 0x2404 0x9A49 0x0002 0x0000 0x0000 75: 0x2404 0x9249 0x0002 0x0000 0x0000 76: 0x2404 0x9269 0x0002 0x0000 0x0000 77: 0x2404 0x9239 0x0002 0x0000 0x0000 78: 0x2404 0x9259 0x0002 0x0000 0x0000 79: 0x2404 0x9249 0x0002 0x0000 0x0000 80: 0x2404 0x9249 0x0003 0x0000 0x0000 81: 0x2404 0x92C9 0x0001 0x0000 0x0000 82: 0x2404 0x92C9 0x0002 0x0000 0x0000 83: 0x2404 0x9249 0x0002 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE IIOIIOIIOIIOIIOG P GIIOIIOIIOIIOIIO G P G UUT inputs: 20 UUT outputs: 10 pins used: 30 not used: 36 83 'test steps' 119 lines M113 10 2-input NAND PINS Main menu Sat Jul 01 10:43:36 2017 test file is: tests\M113.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:43:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) pppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA LETTER ABCDEFDEFHJKHJKLMNLMNPRSPRSTUV SIDE 111111222111222111222111222222 DIRECTION IIOIIOIIOIIOIIOIIOIIOIIOIIOIIO all fails was lo 000000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 111111111111111111111111111111 total fails 0, total passes 42 Main menu Sat Jul 01 10:43:39 2017 test file is: tests\M113.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: direction: IIOO comment: comment: ; ALL INPUTS LOW test 1: 00XX comment: comment: ; TEST SPARE FF test 2: 1O1 error: unexpect character: 0x4F O error: expected '0', '1', or 'X' for test step test 3: 0 error: unexpect character: 0x4F O error: expected '0', '1', or 'X' for test step test 4: 1 error: unexpect character: 0x4F O error: expected '0', '1', or 'X' for test step test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: end: END bad test file Main menu Sat Jul 01 10:53:25 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: direction: IIOO comment: comment: ; ALL INPUTS LOW test 1: 00XX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 direction bits (1=input) 0xFFFF 0xFFFF 0xFFFB 0xFFFF 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x000C 2: 0x0000 0x0000 0x0000 0x0000 0x000A 3: 0x0000 0x0000 0x0000 0x0000 0x0008 4: 0x0000 0x0000 0x0000 0x0000 0x0009 5: 0x0000 0x0000 0x0000 0x0000 0x0007 6: 0x0000 0x0000 0x0000 0x0000 0x0005 7: 0x0000 0x0000 0x0000 0x0000 0x0004 8: 0x0000 0x0000 0x0000 0x0000 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G G P G IIOO UUT inputs: 2 UUT outputs: 2 pins used: 4 not used: 62 8 'test steps' 24 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 10:54:14 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: direction: IIOO comment: comment: ; ALL INPUTS LOW test 1: 00XX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 direction bits (1=input) 0xFFFF 0xFFFF 0xFFFB 0xFFFF 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x000C 2: 0x0000 0x0000 0x0000 0x0000 0x000A 3: 0x0000 0x0000 0x0000 0x0000 0x0008 4: 0x0000 0x0000 0x0000 0x0000 0x0009 5: 0x0000 0x0000 0x0000 0x0000 0x0007 6: 0x0000 0x0000 0x0000 0x0000 0x0005 7: 0x0000 0x0000 0x0000 0x0000 0x0004 8: 0x0000 0x0000 0x0000 0x0000 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G G P G IIOO UUT inputs: 2 UUT outputs: 2 pins used: 4 not used: 62 8 'test steps' 24 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 10:54:34 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 10:54:35 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 0 changed: 0 step 7 0010 source: 101 changed: 101 step 8 0101 test 380: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 380 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW source: 00XX changed: 0 step 1 0001 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101 source: 0 changed: 0 step 3 0001 source: 1 changed: 1 step 4 1001 source: 110 changed: 110 step 5 1110 source: 0 changed: 0 step 6 1010 source: 0 changed: 0 step 7 0010 source: 101 changed: 101 step 8 0101 test 381: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 381 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW source: 00XX changed: 0 step 1 0001 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101 source: 0 changed: 0 step 3 0001 source: 1 changed: 1 step 4 1001 source: 110 changed: 110 step 5 1110 source: 0 changed: 0 step 6 1010 source: 0 changed: 0 step 7 0010 source: 101 changed: 101 step 8 0101 test 382: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 382 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001 step 2 0101 step 3 0001 step 4 1001 step 5 1110 step 6 1010 step 7 0010 step 8 0101 test 383: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 383 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001 step 2 0101 step 3 0001 step 4 1001 step 5 1110 step 6 1010 step 7 0010 step 8 0101 test 384: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 384 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001 step 2 0101 step 3 0001 step 4 1001 step 5 1110 step 6 1010 step 7 0010 step 8 0101 test 385: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 385 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001 step 2 0101 step 3 0001 step 4 1001 step 5 1110 step 6 1010 step 7 0010 step 8 0101 test 386: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 386 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001 step 2 0101 step 3 0001 step 4 1001 step 5 1110 step 6 1010 step 7 0010 step 8 0101 test 387: pass SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO this fail all fails was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 0, total passes 387 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBB LETTER STUV SIDE 2222 DIRECTION IIOO all fails was lo 0000 falling vvvv rising ^^^^ was hi 1111 total fails 0, total passes 387 Main menu Sat Jul 01 11:04:50 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '04' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '04' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '04' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '04' Q OUTPUT pins: direction: IIOOIIIO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 direction bits (1=input) 0xFFFF 0xFFFF 0xFFFB 0xFFA7 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x0048 0x0000 0x0000 0x0000 0x0000 0x0020 0x000C 2: 0x0000 0x0000 0x0000 0x0048 0x000A 0x0000 0x0000 0x0000 0x0020 0x0000 3: 0x0000 0x0000 0x0000 0x0048 0x0008 0x0000 0x0000 0x0000 0x0020 0x0000 4: 0x0000 0x0000 0x0000 0x0048 0x0009 0x0000 0x0000 0x0000 0x0020 0x0000 5: 0x0000 0x0000 0x0000 0x0048 0x0007 0x0000 0x0000 0x0000 0x0020 0x0000 6: 0x0000 0x0000 0x0000 0x0048 0x0005 0x0000 0x0000 0x0000 0x0020 0x0000 7: 0x0000 0x0000 0x0000 0x0048 0x0004 0x0000 0x0000 0x0000 0x0020 0x0000 8: 0x0000 0x0000 0x0000 0x0048 0x000A 0x0000 0x0000 0x0000 0x0020 0x0000 9: 0x0000 0x0000 0x0000 0x0028 0x000A 10: 0x0000 0x0000 0x0000 0x0068 0x000A 11: 0x0000 0x0000 0x0000 0x0040 0x000A 12: 0x0000 0x0000 0x0000 0x0048 0x000A 13: 0x0000 0x0000 0x0000 0x0078 0x000A 14: 0x0000 0x0000 0x0000 0x0068 0x000A 15: 0x0000 0x0000 0x0000 0x0058 0x000A 16: 0x0000 0x0000 0x0000 0x0048 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G G P G IIOI IIOO UUT inputs: 5 UUT outputs: 3 pins used: 8 not used: 58 16 'test steps' 39 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 11:04:55 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 11:04:59 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 4 10011100 step 5 11101100 step 6 10101100 step 7 00101100 step 8 01011100 step 9 01010101 step 10 01011101 step 11 01011000 step 12 01011100 step 13 01011111 step 14 01011101 step 15 01011110 step 16 01011100 test 144: pass SLOT BBBBBBBB LETTER STUVPLMN SIDE 22222222 DIRECTION IIOOIIIO this fail all fails was hi 11111111 rising ^^^^^^^^ falling vvvvvvvv was lo 00000000 total fails 0, total passes 144 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 00011100 step 2 01011100 step 3 00011100 step 4 10011100 step 5 11101100 step 6 10101100 step 7 00101100 step 8 01011100 step 9 01010101 step 10 01011101 step 11 01011000 step 12 01011100 step 13 01011111 step 14 01011101 step 15 01011110 step 16 01011100 test 145: pass SLOT BBBBBBBB LETTER STUVPLMN SIDE 22222222 DIRECTION IIOOIIIO this fail all fails was hi 11111111 rising ^^^^^^^^ falling vvvvvvvv was lo 00000000 total fails 0, total passes 145 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBB LETTER STUVPLMN SIDE 22222222 DIRECTION IIOOIIIO all fails was lo 00000000 falling vvvvvvvv rising ^^^^^^^^ was hi 11111111 total fails 0, total passes 145 Main menu Sat Jul 01 11:09:30 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '04' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '04' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '04' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '04' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '02' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '02' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '02' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '02' Q OUTPUT pins: direction: expected 'direction' (12 columns of 'I' or 'O' or 'P') bad test file Main menu Sat Jul 01 11:09:36 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Sat Jul 01 11:09:38 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0053 Main menu Sat Jul 01 11:09:39 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit there is no test file Main menu Sat Jul 01 11:09:41 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '04' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '04' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '04' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '04' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '02' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '02' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '02' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '02' Q OUTPUT pins: direction: expected 'direction' (12 columns of 'I' or 'O' or 'P') bad test file Main menu Sat Jul 01 11:09:47 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '04' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '04' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '04' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '04' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '02' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '02' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '02' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '02' Q OUTPUT pins: direction: expected 'direction' (12 columns of 'I' or 'O' or 'P') bad test file Main menu Sat Jul 01 11:10:54 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '04' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '04' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '04' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '04' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '02' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '02' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '02' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '02' Q OUTPUT pins: direction: expected 'direction' (12 columns of 'I' or 'O' or 'P') bad test file Main menu Sat Jul 01 11:11:48 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 11:13:51 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '04' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '04' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '04' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '04' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '02' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '02' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '02' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '02' Q OUTPUT pins: direction: IIOOIIIOIIIO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 direction bits (1=input) 0xFFFF 0xFFFF 0xFFFB 0xFFA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0000 0x004D 0x0000 0x0000 0x0000 0x0080 0x0020 0x000C 2: 0x0000 0x0000 0x0000 0x004D 0x000A 0x0000 0x0000 0x0080 0x0020 0x0000 3: 0x0000 0x0000 0x0000 0x004D 0x0008 0x0000 0x0000 0x0080 0x0020 0x0000 4: 0x0000 0x0000 0x0000 0x004D 0x0009 0x0000 0x0000 0x0080 0x0020 0x0000 5: 0x0000 0x0000 0x0000 0x004D 0x0007 0x0000 0x0000 0x0080 0x0020 0x0000 6: 0x0000 0x0000 0x0000 0x004D 0x0005 0x0000 0x0000 0x0080 0x0020 0x0000 7: 0x0000 0x0000 0x0000 0x004D 0x0004 0x0000 0x0000 0x0080 0x0020 0x0000 8: 0x0000 0x0000 0x0000 0x004D 0x000A 0x0000 0x0000 0x0080 0x0020 0x0000 9: 0x0000 0x0000 0x0000 0x002D 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 10: 0x0000 0x0000 0x0000 0x006D 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 11: 0x0000 0x0000 0x0000 0x0045 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 12: 0x0000 0x0000 0x0000 0x004D 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 13: 0x0000 0x0000 0x0000 0x007D 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 14: 0x0000 0x0000 0x0000 0x006D 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 15: 0x0000 0x0000 0x0000 0x005D 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 16: 0x0000 0x0000 0x0000 0x004D 0x000A 0x0000 0x0000 0x0080 0x0000 0x0000 17: 0x0000 0x0000 0x0080 0x004C 0x000A 18: 0x0000 0x0000 0x0080 0x004D 0x000A 19: 0x0000 0x0000 0x0000 0x0049 0x000A 20: 0x0000 0x0000 0x0000 0x004D 0x000A 21: 0x0000 0x0000 0x0080 0x004F 0x000A 22: 0x0000 0x0000 0x0080 0x004D 0x000A 23: 0x0000 0x0000 0x0000 0x004F 0x000A 24: 0x0000 0x0000 0x0000 0x004D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G P G G P G OIIIIIOI IIOO UUT inputs: 8 UUT outputs: 4 pins used: 12 not used: 54 24 'test steps' 54 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 11:13:56 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 11:14:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 14 010111011100 step 15 010111101100 step 16 010111001100 step 17 010111000101 step 18 010111001101 step 19 010111001000 step 20 010111001100 step 21 010111001111 step 22 010111001101 step 23 010111001110 step 24 010111001100 test 105: pass SLOT BBBBBBBBBBBB LETTER STUVPLMNHKJF SIDE 222222222222 DIRECTION IIOOIIIOIIIO this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 000000000000 total fails 0, total passes 105 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000111001100 step 2 010111001100 step 3 000111001100 step 4 100111001100 step 5 111011001100 step 6 101011001100 step 7 001011001100 step 8 010111001100 step 9 010101011100 step 10 010111011100 step 11 010110001100 step 12 010111001100 step 13 010111111100 step 14 010111011100 step 15 010111101100 step 16 010111001100 step 17 010111000101 step 18 010111001101 step 19 010111001000 step 20 010111001100 step 21 010111001111 step 22 010111001101 step 23 010111001110 step 24 010111001100 test 106: pass SLOT BBBBBBBBBBBB LETTER STUVPLMNHKJF SIDE 222222222222 DIRECTION IIOOIIIOIIIO this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 000000000000 total fails 0, total passes 106 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 000111001100 step 2 010111001100 step 3 000111001100 step 4 100111001100 step 5 111011001100 step 6 101011001100 step 7 001011001100 step 8 010111001100 step 9 010101011100 step 10 010111011100 step 11 010110001100 step 12 010111001100 step 13 010111111100 step 14 010111011100 step 15 010111101100 step 16 010111001100 step 17 010111000101 step 18 010111001101 step 19 010111001000 step 20 010111001100 step 21 010111001111 step 22 010111001101 step 23 010111001110 step 24 010111001100 test 107: pass SLOT BBBBBBBBBBBB LETTER STUVPLMNHKJF SIDE 222222222222 DIRECTION IIOOIIIOIIIO this fail all fails was hi 111111111111 rising ^^^^^^^^^^^^ falling vvvvvvvvvvvv was lo 000000000000 total fails 0, total passes 107 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBB LETTER STUVPLMNHKJF SIDE 222222222222 DIRECTION IIOOIIIOIIIO all fails was lo 000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 107 Main menu Sat Jul 01 11:51:22 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 1010 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 1010 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 10 test 62: 1 test 63: 0 test 64: 0 01 test 65: 1 test 66: 0 test 67: 1 10 test 68: 1 test 69: 0 test 70: 0 01 test 71: 1 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0080 0x0122 0x204D 0x000A 31: 0x0000 0x0080 0x0102 0x204D 0x000A 32: 0x0000 0x0888 0xC343 0x704D 0x000A 33: 0x0000 0x0848 0xC263 0xF04D 0x000A 34: 0x0000 0x0848 0xC363 0x504D 0x000A 35: 0x0000 0x0848 0xC363 0x704D 0x000A 36: 0x0000 0x0848 0xC363 0x704D 0x000A 37: 0x0000 0x0848 0xC263 0xF04D 0x000A 38: 0x0000 0x0888 0xC261 0xF04D 0x000A 39: 0x0000 0x0888 0xC263 0xF04D 0x000A 40: 0x0000 0x0080 0x0022 0xA04D 0x000A 41: 0x0000 0x0080 0x0022 0xA04D 0x000A 42: 0x0000 0x0080 0x0002 0xA04D 0x000A 43: 0x0000 0x0080 0x0042 0xA04D 0x000A 44: 0x0000 0x0080 0x0062 0xA04D 0x000A 45: 0x0000 0x0080 0x0042 0xA04D 0x000A 46: 0x0000 0x0080 0x0002 0xA04D 0x000A 47: 0x0000 0x0080 0x0022 0xA04D 0x000A 48: 0x0000 0x0080 0x0002 0xA04D 0x000A 49: 0x0000 0x0080 0x0002 0xB04D 0x000A 50: 0x0000 0x0080 0x0022 0xB04D 0x000A 51: 0x0000 0x0080 0x0002 0xB04D 0x000A 52: 0x0000 0x0080 0x0002 0xA04D 0x000A 53: 0x0000 0x0080 0x0022 0xA04D 0x000A 54: 0x0000 0x0080 0x0002 0xA04D 0x000A 55: 0x0000 0x0080 0x0002 0xE04D 0x000A 56: 0x0000 0x0080 0x0022 0xE04D 0x000A 57: 0x0000 0x0080 0x0002 0xE04D 0x000A 58: 0x0000 0x0080 0x0002 0xA04D 0x000A 59: 0x0000 0x0080 0x0022 0xA04D 0x000A 60: 0x0000 0x0080 0x0002 0xA04D 0x000A 61: 0x0000 0x0080 0x0202 0xA04D 0x000A 62: 0x0000 0x0080 0x0222 0xA04D 0x000A 63: 0x0000 0x0080 0x0202 0xA04D 0x000A 64: 0x0000 0x0080 0x0102 0x204D 0x000A 65: 0x0000 0x0080 0x0122 0x204D 0x000A 66: 0x0000 0x0080 0x0102 0x204D 0x000A 67: 0x0000 0x0040 0x0103 0x204D 0x000A 68: 0x0000 0x0040 0x0123 0x204D 0x000A 69: 0x0000 0x0040 0x0103 0x204D 0x000A 70: 0x0000 0x0080 0x0102 0x204D 0x000A 71: 0x0000 0x0080 0x0122 0x204D 0x000A 72: 0x0000 0x0080 0x0102 0x204D 0x000A 73: 0x0000 0x0080 0x4102 0x204D 0x000A 74: 0x0000 0x0080 0x4122 0x204D 0x000A 75: 0x0000 0x0080 0x4102 0x204D 0x000A 76: 0x0000 0x0080 0x0102 0x204D 0x000A 77: 0x0000 0x0080 0x0122 0x204D 0x000A 78: 0x0000 0x0080 0x0102 0x204D 0x000A 79: 0x0000 0x0080 0x8102 0x204D 0x000A 80: 0x0000 0x0080 0x8122 0x204D 0x000A 81: 0x0000 0x0080 0x8102 0x204D 0x000A 82: 0x0000 0x0080 0x0102 0x204D 0x000A 83: 0x0000 0x0080 0x0122 0x204D 0x000A 84: 0x0000 0x0080 0x0102 0x204D 0x000A 85: 0x0000 0x0880 0x0102 0x204D 0x000A 86: 0x0000 0x0880 0x0122 0x204D 0x000A 87: 0x0000 0x0880 0x0102 0x204D 0x000A 88: 0x0000 0x0080 0x0102 0x204D 0x000A 89: 0x0000 0x0080 0x0122 0x204D 0x000A 90: 0x0000 0x0080 0x0102 0x204D 0x000A 91: 0x0000 0x0088 0x0102 0x204D 0x000A 92: 0x0000 0x0088 0x0122 0x204D 0x000A 93: 0x0000 0x0088 0x0102 0x204D 0x000A 94: 0x0000 0x0080 0x0102 0x204D 0x000A 95: 0x0000 0x0080 0x0122 0x204D 0x000A 96: 0x0000 0x0080 0x0102 0x204D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 11:51:26 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 11:51:36 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 16 0101110011001100000000001010 step 17 0101110001011100000000001010 step 18 0101110011011100000000001010 step 19 0101110010001100000000001010 step 20 0101110011001100000000001010 step 21 0101110011111100000000001010 step 22 0101110011011100000000001010 step 23 0101110011101100000000001010 step 24 0101110011001100000000001010 step 25 0101110011000100000000000110 step 26 0101110011001100000000000110 step 27 0101110011001000000000000101 step 28 0101110011001100000000000101 step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 26: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 26, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001110011001100000000001010 step 2 0101110011001100000000001010 step 3 0001110011001100000000001010 step 4 1001110011001100000000001010 step 5 1110110011001100000000001010 step 6 1010110011001100000000001010 step 7 0010110011001100000000001010 step 8 0101110011001100000000001010 step 9 0101010111001100000000001010 step 10 0101110111001100000000001010 step 11 0101100011001100000000001010 step 12 0101110011001100000000001010 step 13 0101111111001100000000001010 step 14 0101110111001100000000001010 step 15 0101111011001100000000001010 step 16 0101110011001100000000001010 step 17 0101110001011100000000001010 step 18 0101110011011100000000001010 step 19 0101110010001100000000001010 step 20 0101110011001100000000001010 step 21 0101110011111100000000001010 step 22 0101110011011100000000001010 step 23 0101110011101100000000001010 step 24 0101110011001100000000001010 step 25 0101110011000100000000000110 step 26 0101110011001100000000000110 step 27 0101110011001000000000000101 step 28 0101110011001100000000000101 step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 27: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 27, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001110011001100000000001010 step 2 0101110011001100000000001010 step 3 0001110011001100000000001010 step 4 1001110011001100000000001010 step 5 1110110011001100000000001010 step 6 1010110011001100000000001010 step 7 0010110011001100000000001010 step 8 0101110011001100000000001010 step 9 0101010111001100000000001010 step 10 0101110111001100000000001010 step 11 0101100011001100000000001010 step 12 0101110011001100000000001010 step 13 0101111111001100000000001010 step 14 0101110111001100000000001010 step 15 0101111011001100000000001010 step 16 0101110011001100000000001010 step 17 0101110001011100000000001010 step 18 0101110011011100000000001010 step 19 0101110010001100000000001010 step 20 0101110011001100000000001010 step 21 0101110011111100000000001010 step 22 0101110011011100000000001010 step 23 0101110011101100000000001010 step 24 0101110011001100000000001010 step 25 0101110011000100000000000110 step 26 0101110011001100000000000110 step 27 0101110011001000000000000101 step 28 0101110011001100000000000101 step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 28: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 28, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 0001110011001100000000001010 step 2 0101110011001100000000001010 step 3 0001110011001100000000001010 step 4 1001110011001100000000001010 step 5 1110110011001100000000001010 step 6 1010110011001100000000001010 step 7 0010110011001100000000001010 step 8 0101110011001100000000001010 step 9 0101010111001100000000001010 step 10 0101110111001100000000001010 step 11 0101100011001100000000001010 step 12 0101110011001100000000001010 step 13 0101111111001100000000001010 step 14 0101110111001100000000001010 step 15 0101111011001100000000001010 step 16 0101110011001100000000001010 step 17 0101110001011100000000001010 step 18 0101110011011100000000001010 step 19 0101110010001100000000001010 step 20 0101110011001100000000001010 step 21 0101110011111100000000001010 step 22 0101110011011100000000001010 step 23 0101110011101100000000001010 step 24 0101110011001100000000001010 step 25 0101110011000100000000000110 step 26 0101110011001100000000000110 step 27 0101110011001000000000000101 step 28 0101110011001100000000000101 step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 29: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 29, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 30: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 30, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 31 0101110011001100000000001010 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 30, total passes 0 Main menu Sat Jul 01 11:58:27 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 1010 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 1010 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 10 test 62: 1 test 63: 0 test 64: 0 01 test 65: 1 test 66: 0 test 67: 1 10 test 68: 1 test 69: 0 test 70: 0 01 test 71: 1 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0080 0x0122 0x204D 0x000A 31: 0x0000 0x0080 0x0102 0x204D 0x000A 32: 0x0000 0x0888 0xC343 0x704D 0x000A 33: 0x0000 0x0848 0xC263 0xF04D 0x000A 34: 0x0000 0x0848 0xC363 0x504D 0x000A 35: 0x0000 0x0848 0xC363 0x704D 0x000A 36: 0x0000 0x0848 0xC363 0x704D 0x000A 37: 0x0000 0x0848 0xC263 0xF04D 0x000A 38: 0x0000 0x0888 0xC261 0xF04D 0x000A 39: 0x0000 0x0888 0xC263 0xF04D 0x000A 40: 0x0000 0x0080 0x0022 0xA04D 0x000A 41: 0x0000 0x0080 0x0022 0xA04D 0x000A 42: 0x0000 0x0080 0x0002 0xA04D 0x000A 43: 0x0000 0x0080 0x0042 0xA04D 0x000A 44: 0x0000 0x0080 0x0062 0xA04D 0x000A 45: 0x0000 0x0080 0x0042 0xA04D 0x000A 46: 0x0000 0x0080 0x0002 0xA04D 0x000A 47: 0x0000 0x0080 0x0022 0xA04D 0x000A 48: 0x0000 0x0080 0x0002 0xA04D 0x000A 49: 0x0000 0x0080 0x0002 0xB04D 0x000A 50: 0x0000 0x0080 0x0022 0xB04D 0x000A 51: 0x0000 0x0080 0x0002 0xB04D 0x000A 52: 0x0000 0x0080 0x0002 0xA04D 0x000A 53: 0x0000 0x0080 0x0022 0xA04D 0x000A 54: 0x0000 0x0080 0x0002 0xA04D 0x000A 55: 0x0000 0x0080 0x0002 0xE04D 0x000A 56: 0x0000 0x0080 0x0022 0xE04D 0x000A 57: 0x0000 0x0080 0x0002 0xE04D 0x000A 58: 0x0000 0x0080 0x0002 0xA04D 0x000A 59: 0x0000 0x0080 0x0022 0xA04D 0x000A 60: 0x0000 0x0080 0x0002 0xA04D 0x000A 61: 0x0000 0x0080 0x0202 0xA04D 0x000A 62: 0x0000 0x0080 0x0222 0xA04D 0x000A 63: 0x0000 0x0080 0x0202 0xA04D 0x000A 64: 0x0000 0x0080 0x0102 0x204D 0x000A 65: 0x0000 0x0080 0x0122 0x204D 0x000A 66: 0x0000 0x0080 0x0102 0x204D 0x000A 67: 0x0000 0x0040 0x0103 0x204D 0x000A 68: 0x0000 0x0040 0x0123 0x204D 0x000A 69: 0x0000 0x0040 0x0103 0x204D 0x000A 70: 0x0000 0x0080 0x0102 0x204D 0x000A 71: 0x0000 0x0080 0x0122 0x204D 0x000A 72: 0x0000 0x0080 0x0102 0x204D 0x000A 73: 0x0000 0x0080 0x4102 0x204D 0x000A 74: 0x0000 0x0080 0x4122 0x204D 0x000A 75: 0x0000 0x0080 0x4102 0x204D 0x000A 76: 0x0000 0x0080 0x0102 0x204D 0x000A 77: 0x0000 0x0080 0x0122 0x204D 0x000A 78: 0x0000 0x0080 0x0102 0x204D 0x000A 79: 0x0000 0x0080 0x8102 0x204D 0x000A 80: 0x0000 0x0080 0x8122 0x204D 0x000A 81: 0x0000 0x0080 0x8102 0x204D 0x000A 82: 0x0000 0x0080 0x0102 0x204D 0x000A 83: 0x0000 0x0080 0x0122 0x204D 0x000A 84: 0x0000 0x0080 0x0102 0x204D 0x000A 85: 0x0000 0x0880 0x0102 0x204D 0x000A 86: 0x0000 0x0880 0x0122 0x204D 0x000A 87: 0x0000 0x0880 0x0102 0x204D 0x000A 88: 0x0000 0x0080 0x0102 0x204D 0x000A 89: 0x0000 0x0080 0x0122 0x204D 0x000A 90: 0x0000 0x0080 0x0102 0x204D 0x000A 91: 0x0000 0x0088 0x0102 0x204D 0x000A 92: 0x0000 0x0088 0x0122 0x204D 0x000A 93: 0x0000 0x0088 0x0102 0x204D 0x000A 94: 0x0000 0x0080 0x0102 0x204D 0x000A 95: 0x0000 0x0080 0x0122 0x204D 0x000A 96: 0x0000 0x0080 0x0102 0x204D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 11:58:34 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 11:58:36 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: step 1 0001110011001100000000000101 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000000101 source: 0 changed: 0 step 3 0001110011001100000000000101 source: 1 changed: 1 step 4 1001110011001100000000000101 source: 110 changed: 110 step 5 1110110011001100000000000101 source: 0 changed: 0 step 6 1010110011001100000000000101 source: 0 changed: 0 step 7 0010110011001100000000000101 source: 101 changed: 101 step 8 0101110011001100000000000101 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000000101 source: 1 changed: 1 step 10 0101110111001100000000000101 source: 0 0 changed: 0 0 step 11 0101100011001100000000000101 source: 1 changed: 1 step 12 0101110011001100000000000101 source: 11 changed: 11 step 13 0101111111001100000000000101 source: 0 changed: 0 step 14 0101110111001100000000000101 source: 10 changed: 10 step 15 0101111011001100000000000101 source: 0 changed: 0 step 16 0101110011001100000000000101 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000000101 source: 1 changed: 1 step 18 0101110011011100000000000101 source: 0 0 changed: 0 0 step 19 0101110010001100000000000101 source: 1 changed: 1 step 20 0101110011001100000000000101 source: 11 changed: 11 step 21 0101110011111100000000000101 source: 0 changed: 0 step 22 0101110011011100000000000101 source: 10 changed: 10 step 23 0101110011101100000000000101 source: 0 changed: 0 step 24 0101110011001100000000000101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 25 0101110011000100000000000101 source: 1 changed: 1 step 26 0101110011001100000000000101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 1: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 1, total passes 0 Main menu Sat Jul 01 11:59:05 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 11:59:12 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 0101 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 1010 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 1010 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 10 test 62: 1 test 63: 0 test 64: 0 01 test 65: 1 test 66: 0 test 67: 1 10 test 68: 1 test 69: 0 test 70: 0 01 test 71: 1 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0080 0x0122 0x204D 0x000A 31: 0x0000 0x0080 0x0102 0x204D 0x000A 32: 0x0000 0x0888 0xC343 0x704D 0x000A 33: 0x0000 0x0848 0xC263 0xF04D 0x000A 34: 0x0000 0x0848 0xC363 0x504D 0x000A 35: 0x0000 0x0848 0xC363 0x704D 0x000A 36: 0x0000 0x0848 0xC363 0x704D 0x000A 37: 0x0000 0x0848 0xC263 0xF04D 0x000A 38: 0x0000 0x0888 0xC261 0xF04D 0x000A 39: 0x0000 0x0888 0xC263 0xF04D 0x000A 40: 0x0000 0x0080 0x0022 0xA04D 0x000A 41: 0x0000 0x0080 0x0022 0xA04D 0x000A 42: 0x0000 0x0080 0x0002 0xA04D 0x000A 43: 0x0000 0x0080 0x0042 0xA04D 0x000A 44: 0x0000 0x0080 0x0062 0xA04D 0x000A 45: 0x0000 0x0080 0x0042 0xA04D 0x000A 46: 0x0000 0x0080 0x0002 0xA04D 0x000A 47: 0x0000 0x0080 0x0022 0xA04D 0x000A 48: 0x0000 0x0080 0x0002 0xA04D 0x000A 49: 0x0000 0x0080 0x0002 0xB04D 0x000A 50: 0x0000 0x0080 0x0022 0xB04D 0x000A 51: 0x0000 0x0080 0x0002 0xB04D 0x000A 52: 0x0000 0x0080 0x0002 0xA04D 0x000A 53: 0x0000 0x0080 0x0022 0xA04D 0x000A 54: 0x0000 0x0080 0x0002 0xA04D 0x000A 55: 0x0000 0x0080 0x0002 0xE04D 0x000A 56: 0x0000 0x0080 0x0022 0xE04D 0x000A 57: 0x0000 0x0080 0x0002 0xE04D 0x000A 58: 0x0000 0x0080 0x0002 0xA04D 0x000A 59: 0x0000 0x0080 0x0022 0xA04D 0x000A 60: 0x0000 0x0080 0x0002 0xA04D 0x000A 61: 0x0000 0x0080 0x0202 0xA04D 0x000A 62: 0x0000 0x0080 0x0222 0xA04D 0x000A 63: 0x0000 0x0080 0x0202 0xA04D 0x000A 64: 0x0000 0x0080 0x0102 0x204D 0x000A 65: 0x0000 0x0080 0x0122 0x204D 0x000A 66: 0x0000 0x0080 0x0102 0x204D 0x000A 67: 0x0000 0x0040 0x0103 0x204D 0x000A 68: 0x0000 0x0040 0x0123 0x204D 0x000A 69: 0x0000 0x0040 0x0103 0x204D 0x000A 70: 0x0000 0x0080 0x0102 0x204D 0x000A 71: 0x0000 0x0080 0x0122 0x204D 0x000A 72: 0x0000 0x0080 0x0102 0x204D 0x000A 73: 0x0000 0x0080 0x4102 0x204D 0x000A 74: 0x0000 0x0080 0x4122 0x204D 0x000A 75: 0x0000 0x0080 0x4102 0x204D 0x000A 76: 0x0000 0x0080 0x0102 0x204D 0x000A 77: 0x0000 0x0080 0x0122 0x204D 0x000A 78: 0x0000 0x0080 0x0102 0x204D 0x000A 79: 0x0000 0x0080 0x8102 0x204D 0x000A 80: 0x0000 0x0080 0x8122 0x204D 0x000A 81: 0x0000 0x0080 0x8102 0x204D 0x000A 82: 0x0000 0x0080 0x0102 0x204D 0x000A 83: 0x0000 0x0080 0x0122 0x204D 0x000A 84: 0x0000 0x0080 0x0102 0x204D 0x000A 85: 0x0000 0x0880 0x0102 0x204D 0x000A 86: 0x0000 0x0880 0x0122 0x204D 0x000A 87: 0x0000 0x0880 0x0102 0x204D 0x000A 88: 0x0000 0x0080 0x0102 0x204D 0x000A 89: 0x0000 0x0080 0x0122 0x204D 0x000A 90: 0x0000 0x0080 0x0102 0x204D 0x000A 91: 0x0000 0x0088 0x0102 0x204D 0x000A 92: 0x0000 0x0088 0x0122 0x204D 0x000A 93: 0x0000 0x0088 0x0102 0x204D 0x000A 94: 0x0000 0x0080 0x0102 0x204D 0x000A 95: 0x0000 0x0080 0x0122 0x204D 0x000A 96: 0x0000 0x0080 0x0102 0x204D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 11:59:16 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 11:59:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 0101 changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 20: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 20, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 0101 changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 31 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: 1 0101 step 33 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 35 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: step 37 0101110011001111111111110101 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 39 0101110011001111111111110101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: step 41 0101110011001110000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 42 0101110011001100000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 43 0101110011001101000000000101 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 44 0101110011001111000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 45 0101110011001101000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 46 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 47 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 48 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 49 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 50 0101110011001110100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 51 0101110011001100100000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 52 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 53 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 54 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 55 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 56 0101110011001110010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 57 0101110011001100010000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 58 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 59 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 60 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 21: *** FAIL *************************** 67 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 21, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 0101 changed: 1 1010 step 30 0101110011001110000000001010 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 21, total passes 0 Main menu Sat Jul 01 12:00:22 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 1010 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 0101 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 1010 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 10 test 62: 1 test 63: 0 test 64: 0 01 test 65: 1 test 66: 0 test 67: 1 10 test 68: 1 test 69: 0 test 70: 0 01 test 71: 1 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0040 0x0022 0xA04D 0x000A 31: 0x0000 0x0040 0x0002 0xA04D 0x000A 32: 0x0000 0x0848 0xC243 0xF04D 0x000A 33: 0x0000 0x0888 0xC363 0x704D 0x000A 34: 0x0000 0x0888 0xC363 0x504D 0x000A 35: 0x0000 0x0888 0xC363 0x704D 0x000A 36: 0x0000 0x0888 0xC363 0x704D 0x000A 37: 0x0000 0x0848 0xC263 0xF04D 0x000A 38: 0x0000 0x0888 0xC261 0xF04D 0x000A 39: 0x0000 0x0888 0xC263 0xF04D 0x000A 40: 0x0000 0x0080 0x0022 0xA04D 0x000A 41: 0x0000 0x0080 0x0022 0xA04D 0x000A 42: 0x0000 0x0080 0x0002 0xA04D 0x000A 43: 0x0000 0x0080 0x0042 0xA04D 0x000A 44: 0x0000 0x0080 0x0062 0xA04D 0x000A 45: 0x0000 0x0080 0x0042 0xA04D 0x000A 46: 0x0000 0x0080 0x0002 0xA04D 0x000A 47: 0x0000 0x0080 0x0022 0xA04D 0x000A 48: 0x0000 0x0080 0x0002 0xA04D 0x000A 49: 0x0000 0x0080 0x0002 0xB04D 0x000A 50: 0x0000 0x0080 0x0022 0xB04D 0x000A 51: 0x0000 0x0080 0x0002 0xB04D 0x000A 52: 0x0000 0x0080 0x0002 0xA04D 0x000A 53: 0x0000 0x0080 0x0022 0xA04D 0x000A 54: 0x0000 0x0080 0x0002 0xA04D 0x000A 55: 0x0000 0x0080 0x0002 0xE04D 0x000A 56: 0x0000 0x0080 0x0022 0xE04D 0x000A 57: 0x0000 0x0080 0x0002 0xE04D 0x000A 58: 0x0000 0x0080 0x0002 0xA04D 0x000A 59: 0x0000 0x0080 0x0022 0xA04D 0x000A 60: 0x0000 0x0080 0x0002 0xA04D 0x000A 61: 0x0000 0x0080 0x0202 0xA04D 0x000A 62: 0x0000 0x0080 0x0222 0xA04D 0x000A 63: 0x0000 0x0080 0x0202 0xA04D 0x000A 64: 0x0000 0x0080 0x0102 0x204D 0x000A 65: 0x0000 0x0080 0x0122 0x204D 0x000A 66: 0x0000 0x0080 0x0102 0x204D 0x000A 67: 0x0000 0x0040 0x0103 0x204D 0x000A 68: 0x0000 0x0040 0x0123 0x204D 0x000A 69: 0x0000 0x0040 0x0103 0x204D 0x000A 70: 0x0000 0x0080 0x0102 0x204D 0x000A 71: 0x0000 0x0080 0x0122 0x204D 0x000A 72: 0x0000 0x0080 0x0102 0x204D 0x000A 73: 0x0000 0x0080 0x4102 0x204D 0x000A 74: 0x0000 0x0080 0x4122 0x204D 0x000A 75: 0x0000 0x0080 0x4102 0x204D 0x000A 76: 0x0000 0x0080 0x0102 0x204D 0x000A 77: 0x0000 0x0080 0x0122 0x204D 0x000A 78: 0x0000 0x0080 0x0102 0x204D 0x000A 79: 0x0000 0x0080 0x8102 0x204D 0x000A 80: 0x0000 0x0080 0x8122 0x204D 0x000A 81: 0x0000 0x0080 0x8102 0x204D 0x000A 82: 0x0000 0x0080 0x0102 0x204D 0x000A 83: 0x0000 0x0080 0x0122 0x204D 0x000A 84: 0x0000 0x0080 0x0102 0x204D 0x000A 85: 0x0000 0x0880 0x0102 0x204D 0x000A 86: 0x0000 0x0880 0x0122 0x204D 0x000A 87: 0x0000 0x0880 0x0102 0x204D 0x000A 88: 0x0000 0x0080 0x0102 0x204D 0x000A 89: 0x0000 0x0080 0x0122 0x204D 0x000A 90: 0x0000 0x0080 0x0102 0x204D 0x000A 91: 0x0000 0x0088 0x0102 0x204D 0x000A 92: 0x0000 0x0088 0x0122 0x204D 0x000A 93: 0x0000 0x0088 0x0102 0x204D 0x000A 94: 0x0000 0x0080 0x0102 0x204D 0x000A 95: 0x0000 0x0080 0x0122 0x204D 0x000A 96: 0x0000 0x0080 0x0102 0x204D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 12:00:27 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 12:00:29 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 20: *** FAIL *************************** 60 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 20, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 1010 changed: step 37 0101110011001111111111110101 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 20, total passes 0 Main menu Sat Jul 01 12:01:48 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 1010 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 0101 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 0101 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 10 test 62: 1 test 63: 0 test 64: 0 01 test 65: 1 test 66: 0 test 67: 1 10 test 68: 1 test 69: 0 test 70: 0 01 test 71: 1 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0040 0x0022 0xA04D 0x000A 31: 0x0000 0x0040 0x0002 0xA04D 0x000A 32: 0x0000 0x0848 0xC243 0xF04D 0x000A 33: 0x0000 0x0888 0xC363 0x704D 0x000A 34: 0x0000 0x0888 0xC363 0x504D 0x000A 35: 0x0000 0x0888 0xC363 0x704D 0x000A 36: 0x0000 0x0888 0xC363 0x704D 0x000A 37: 0x0000 0x0888 0xC363 0x704D 0x000A 38: 0x0000 0x0888 0xC361 0x704D 0x000A 39: 0x0000 0x0888 0xC363 0x704D 0x000A 40: 0x0000 0x0080 0x0122 0x204D 0x000A 41: 0x0000 0x0080 0x0122 0x204D 0x000A 42: 0x0000 0x0080 0x0102 0x204D 0x000A 43: 0x0000 0x0080 0x0142 0x204D 0x000A 44: 0x0000 0x0080 0x0162 0x204D 0x000A 45: 0x0000 0x0080 0x0142 0x204D 0x000A 46: 0x0000 0x0080 0x0102 0x204D 0x000A 47: 0x0000 0x0080 0x0122 0x204D 0x000A 48: 0x0000 0x0080 0x0102 0x204D 0x000A 49: 0x0000 0x0080 0x0102 0x304D 0x000A 50: 0x0000 0x0080 0x0122 0x304D 0x000A 51: 0x0000 0x0080 0x0102 0x304D 0x000A 52: 0x0000 0x0080 0x0102 0x204D 0x000A 53: 0x0000 0x0080 0x0122 0x204D 0x000A 54: 0x0000 0x0080 0x0102 0x204D 0x000A 55: 0x0000 0x0080 0x0102 0x604D 0x000A 56: 0x0000 0x0080 0x0122 0x604D 0x000A 57: 0x0000 0x0080 0x0102 0x604D 0x000A 58: 0x0000 0x0080 0x0102 0x204D 0x000A 59: 0x0000 0x0080 0x0122 0x204D 0x000A 60: 0x0000 0x0080 0x0102 0x204D 0x000A 61: 0x0000 0x0080 0x0202 0xA04D 0x000A 62: 0x0000 0x0080 0x0222 0xA04D 0x000A 63: 0x0000 0x0080 0x0202 0xA04D 0x000A 64: 0x0000 0x0080 0x0102 0x204D 0x000A 65: 0x0000 0x0080 0x0122 0x204D 0x000A 66: 0x0000 0x0080 0x0102 0x204D 0x000A 67: 0x0000 0x0040 0x0103 0x204D 0x000A 68: 0x0000 0x0040 0x0123 0x204D 0x000A 69: 0x0000 0x0040 0x0103 0x204D 0x000A 70: 0x0000 0x0080 0x0102 0x204D 0x000A 71: 0x0000 0x0080 0x0122 0x204D 0x000A 72: 0x0000 0x0080 0x0102 0x204D 0x000A 73: 0x0000 0x0080 0x4102 0x204D 0x000A 74: 0x0000 0x0080 0x4122 0x204D 0x000A 75: 0x0000 0x0080 0x4102 0x204D 0x000A 76: 0x0000 0x0080 0x0102 0x204D 0x000A 77: 0x0000 0x0080 0x0122 0x204D 0x000A 78: 0x0000 0x0080 0x0102 0x204D 0x000A 79: 0x0000 0x0080 0x8102 0x204D 0x000A 80: 0x0000 0x0080 0x8122 0x204D 0x000A 81: 0x0000 0x0080 0x8102 0x204D 0x000A 82: 0x0000 0x0080 0x0102 0x204D 0x000A 83: 0x0000 0x0080 0x0122 0x204D 0x000A 84: 0x0000 0x0080 0x0102 0x204D 0x000A 85: 0x0000 0x0880 0x0102 0x204D 0x000A 86: 0x0000 0x0880 0x0122 0x204D 0x000A 87: 0x0000 0x0880 0x0102 0x204D 0x000A 88: 0x0000 0x0080 0x0102 0x204D 0x000A 89: 0x0000 0x0080 0x0122 0x204D 0x000A 90: 0x0000 0x0080 0x0102 0x204D 0x000A 91: 0x0000 0x0088 0x0102 0x204D 0x000A 92: 0x0000 0x0088 0x0122 0x204D 0x000A 93: 0x0000 0x0088 0x0102 0x204D 0x000A 94: 0x0000 0x0080 0x0102 0x204D 0x000A 95: 0x0000 0x0080 0x0122 0x204D 0x000A 96: 0x0000 0x0080 0x0102 0x204D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 12:01:52 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 12:01:54 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 source: 1 0101 changed: step 37 0101110011001111111111110101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 source: 1 changed: 1 step 39 0101110011001111111111110101 source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 source: 1 changed: step 41 0101110011001110000000000101 source: 0 changed: 0 step 42 0101110011001100000000000101 source: 1 changed: 1 step 43 0101110011001101000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 44 0101110011001111000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 45 0101110011001101000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 46 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 47 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 48 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 49 0101110011001100100000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 50 0101110011001110100000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 51 0101110011001100100000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 52 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 53 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 54 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 55 0101110011001100010000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 56 0101110011001110010000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 57 0101110011001100010000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 58 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 59 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 60 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 24: *** FAIL *************************** 53 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 24, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 source: 1 0101 changed: step 37 0101110011001111111111110101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 source: 1 changed: 1 step 39 0101110011001111111111110101 source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 source: 1 changed: step 41 0101110011001110000000000101 source: 0 changed: 0 step 42 0101110011001100000000000101 source: 1 changed: 1 step 43 0101110011001101000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 44 0101110011001111000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 45 0101110011001101000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 46 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 47 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 48 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 49 0101110011001100100000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 50 0101110011001110100000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 51 0101110011001100100000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 52 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 53 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 54 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 55 0101110011001100010000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 56 0101110011001110010000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 57 0101110011001100010000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 58 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 59 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 60 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 61 0101110011001100001000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 63 0101110011001100001000000110 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 64 0101110011001100000000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 65 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 25: *** FAIL *************************** 53 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 25, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 source: 1 0101 changed: step 37 0101110011001111111111110101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 source: 1 changed: 1 step 39 0101110011001111111111110101 source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 source: 1 changed: step 41 0101110011001110000000000101 source: 0 changed: 0 step 42 0101110011001100000000000101 source: 1 changed: 1 step 43 0101110011001101000000000101 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 1010 step 44 0101110011001111000000001010 fail ^^^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 25, total passes 0 Main menu Sat Jul 01 12:04:56 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 1010 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 0101 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 0101 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 1010 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 10 test 62: 1 test 63: 0 test 64: 0 01 test 65: 1 test 66: 0 test 67: 1 10 test 68: 1 test 69: 0 test 70: 0 01 test 71: 1 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0040 0x0022 0xA04D 0x000A 31: 0x0000 0x0040 0x0002 0xA04D 0x000A 32: 0x0000 0x0848 0xC243 0xF04D 0x000A 33: 0x0000 0x0888 0xC363 0x704D 0x000A 34: 0x0000 0x0888 0xC363 0x504D 0x000A 35: 0x0000 0x0888 0xC363 0x704D 0x000A 36: 0x0000 0x0888 0xC363 0x704D 0x000A 37: 0x0000 0x0888 0xC363 0x704D 0x000A 38: 0x0000 0x0888 0xC361 0x704D 0x000A 39: 0x0000 0x0888 0xC363 0x704D 0x000A 40: 0x0000 0x0080 0x0122 0x204D 0x000A 41: 0x0000 0x0080 0x0122 0x204D 0x000A 42: 0x0000 0x0080 0x0102 0x204D 0x000A 43: 0x0000 0x0080 0x0142 0x204D 0x000A 44: 0x0000 0x0040 0x0062 0xA04D 0x000A 45: 0x0000 0x0040 0x0042 0xA04D 0x000A 46: 0x0000 0x0040 0x0002 0xA04D 0x000A 47: 0x0000 0x0040 0x0022 0xA04D 0x000A 48: 0x0000 0x0040 0x0002 0xA04D 0x000A 49: 0x0000 0x0040 0x0002 0xB04D 0x000A 50: 0x0000 0x0040 0x0022 0xB04D 0x000A 51: 0x0000 0x0040 0x0002 0xB04D 0x000A 52: 0x0000 0x0040 0x0002 0xA04D 0x000A 53: 0x0000 0x0040 0x0022 0xA04D 0x000A 54: 0x0000 0x0040 0x0002 0xA04D 0x000A 55: 0x0000 0x0040 0x0002 0xE04D 0x000A 56: 0x0000 0x0040 0x0022 0xE04D 0x000A 57: 0x0000 0x0040 0x0002 0xE04D 0x000A 58: 0x0000 0x0040 0x0002 0xA04D 0x000A 59: 0x0000 0x0040 0x0022 0xA04D 0x000A 60: 0x0000 0x0040 0x0002 0xA04D 0x000A 61: 0x0000 0x0040 0x0202 0xA04D 0x000A 62: 0x0000 0x0040 0x0222 0xA04D 0x000A 63: 0x0000 0x0040 0x0202 0xA04D 0x000A 64: 0x0000 0x0040 0x0102 0x204D 0x000A 65: 0x0000 0x0040 0x0122 0x204D 0x000A 66: 0x0000 0x0040 0x0102 0x204D 0x000A 67: 0x0000 0x0040 0x0103 0x204D 0x000A 68: 0x0000 0x0040 0x0123 0x204D 0x000A 69: 0x0000 0x0040 0x0103 0x204D 0x000A 70: 0x0000 0x0080 0x0102 0x204D 0x000A 71: 0x0000 0x0080 0x0122 0x204D 0x000A 72: 0x0000 0x0080 0x0102 0x204D 0x000A 73: 0x0000 0x0080 0x4102 0x204D 0x000A 74: 0x0000 0x0080 0x4122 0x204D 0x000A 75: 0x0000 0x0080 0x4102 0x204D 0x000A 76: 0x0000 0x0080 0x0102 0x204D 0x000A 77: 0x0000 0x0080 0x0122 0x204D 0x000A 78: 0x0000 0x0080 0x0102 0x204D 0x000A 79: 0x0000 0x0080 0x8102 0x204D 0x000A 80: 0x0000 0x0080 0x8122 0x204D 0x000A 81: 0x0000 0x0080 0x8102 0x204D 0x000A 82: 0x0000 0x0080 0x0102 0x204D 0x000A 83: 0x0000 0x0080 0x0122 0x204D 0x000A 84: 0x0000 0x0080 0x0102 0x204D 0x000A 85: 0x0000 0x0880 0x0102 0x204D 0x000A 86: 0x0000 0x0880 0x0122 0x204D 0x000A 87: 0x0000 0x0880 0x0102 0x204D 0x000A 88: 0x0000 0x0080 0x0102 0x204D 0x000A 89: 0x0000 0x0080 0x0122 0x204D 0x000A 90: 0x0000 0x0080 0x0102 0x204D 0x000A 91: 0x0000 0x0088 0x0102 0x204D 0x000A 92: 0x0000 0x0088 0x0122 0x204D 0x000A 93: 0x0000 0x0088 0x0102 0x204D 0x000A 94: 0x0000 0x0080 0x0102 0x204D 0x000A 95: 0x0000 0x0080 0x0122 0x204D 0x000A 96: 0x0000 0x0080 0x0102 0x204D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 12:05:00 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 12:05:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: step 1 0001110011001100000000000101 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000000101 source: 0 changed: 0 step 3 0001110011001100000000000101 source: 1 changed: 1 step 4 1001110011001100000000000101 source: 110 changed: 110 step 5 1110110011001100000000000101 source: 0 changed: 0 step 6 1010110011001100000000000101 source: 0 changed: 0 step 7 0010110011001100000000000101 source: 101 changed: 101 step 8 0101110011001100000000000101 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000000101 source: 1 changed: 1 step 10 0101110111001100000000000101 source: 0 0 changed: 0 0 step 11 0101100011001100000000000101 source: 1 changed: 1 step 12 0101110011001100000000000101 source: 11 changed: 11 step 13 0101111111001100000000000101 source: 0 changed: 0 step 14 0101110111001100000000000101 source: 10 changed: 10 step 15 0101111011001100000000000101 source: 0 changed: 0 step 16 0101110011001100000000000101 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000000101 source: 1 changed: 1 step 18 0101110011011100000000000101 source: 0 0 changed: 0 0 step 19 0101110010001100000000000101 source: 1 changed: 1 step 20 0101110011001100000000000101 source: 11 changed: 11 step 21 0101110011111100000000000101 source: 0 changed: 0 step 22 0101110011011100000000000101 source: 10 changed: 10 step 23 0101110011101100000000000101 source: 0 changed: 0 step 24 0101110011001100000000000101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 25 0101110011000100000000000101 source: 1 changed: 1 step 26 0101110011001100000000000101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 source: 1 0101 changed: step 37 0101110011001111111111110101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 source: 1 changed: 1 step 39 0101110011001111111111110101 source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 source: 1 changed: step 41 0101110011001110000000000101 source: 0 changed: 0 step 42 0101110011001100000000000101 source: 1 changed: 1 step 43 0101110011001101000000000101 source: 1 1010 changed: 1 1010 step 44 0101110011001111000000001010 source: 0 changed: 0 step 45 0101110011001101000000001010 source: 0 changed: 0 step 46 0101110011001100000000001010 source: 1 changed: 1 step 47 0101110011001110000000001010 source: 0 changed: 0 step 48 0101110011001100000000001010 source: 1 changed: 1 step 49 0101110011001100100000001010 source: 1 changed: 1 step 50 0101110011001110100000001010 source: 0 changed: 0 step 51 0101110011001100100000001010 source: 0 changed: 0 step 52 0101110011001100000000001010 source: 1 changed: 1 step 53 0101110011001110000000001010 source: 0 changed: 0 step 54 0101110011001100000000001010 source: 1 changed: 1 step 55 0101110011001100010000001010 source: 1 changed: 1 step 56 0101110011001110010000001010 source: 0 changed: 0 step 57 0101110011001100010000001010 source: 0 changed: 0 step 58 0101110011001100000000001010 source: 1 changed: 1 step 59 0101110011001110000000001010 source: 0 changed: 0 step 60 0101110011001100000000001010 source: 1 10 changed: 1 step 61 0101110011001100001000001010 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 63 0101110011001100001000000110 fail ^^ source: 0 01 changed: 0 step 64 0101110011001100000000000110 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 65 0101110011001110000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 66 0101110011001100000000001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 10 changed: 1 step 67 0101110011001100000100001010 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 68 0101110011001110000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 69 0101110011001100000100001001 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 01 changed: 0 step 70 0101110011001100000000001001 fail ^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 10 step 71 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 72 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 73 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 74 0101110011001110000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 75 0101110011001100000010001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 76 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 77 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 78 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 79 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 80 0101110011001110000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 81 0101110011001100000001001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 82 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 83 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 84 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 85 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 86 0101110011001110000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 87 0101110011001100000000101010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 88 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 89 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 90 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 91 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 92 0101110011001110000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 93 0101110011001100000000011010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 94 0101110011001100000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 step 95 0101110011001110000000001010 fail ^^^^ SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 changed: 0 step 96 0101110011001100000000001010 fail ^^^^ test 1: *** FAIL *************************** 34 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OOOO all fails OOOO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 source: 1 0101 changed: step 37 0101110011001111111111110101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 source: 1 changed: 1 step 39 0101110011001111111111110101 source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 source: 1 changed: step 41 0101110011001110000000000101 source: 0 changed: 0 step 42 0101110011001100000000000101 source: 1 changed: 1 step 43 0101110011001101000000000101 source: 1 1010 changed: 1 1010 step 44 0101110011001111000000001010 source: 0 changed: 0 step 45 0101110011001101000000001010 source: 0 changed: 0 step 46 0101110011001100000000001010 source: 1 changed: 1 step 47 0101110011001110000000001010 source: 0 changed: 0 step 48 0101110011001100000000001010 source: 1 changed: 1 step 49 0101110011001100100000001010 source: 1 changed: 1 step 50 0101110011001110100000001010 source: 0 changed: 0 step 51 0101110011001100100000001010 source: 0 changed: 0 step 52 0101110011001100000000001010 source: 1 changed: 1 step 53 0101110011001110000000001010 source: 0 changed: 0 step 54 0101110011001100000000001010 source: 1 changed: 1 step 55 0101110011001100010000001010 source: 1 changed: 1 step 56 0101110011001110010000001010 source: 0 changed: 0 step 57 0101110011001100010000001010 source: 0 changed: 0 step 58 0101110011001100000000001010 source: 1 changed: 1 step 59 0101110011001110000000001010 source: 0 changed: 0 step 60 0101110011001100000000001010 source: 1 10 changed: 1 step 61 0101110011001100001000001010 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 1 changed: 1 01 step 62 0101110011001110001000000110 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 1, total passes 0 Main menu Sat Jul 01 12:07:18 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 1010 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 0101 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 0101 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 1010 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 test 62: 1 01 test 63: 0 test 64: 0 test 65: 1 10 test 66: 0 test 67: 1 test 68: 1 01 test 69: 0 test 70: 0 10 test 71: 1 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0040 0x0022 0xA04D 0x000A 31: 0x0000 0x0040 0x0002 0xA04D 0x000A 32: 0x0000 0x0848 0xC243 0xF04D 0x000A 33: 0x0000 0x0888 0xC363 0x704D 0x000A 34: 0x0000 0x0888 0xC363 0x504D 0x000A 35: 0x0000 0x0888 0xC363 0x704D 0x000A 36: 0x0000 0x0888 0xC363 0x704D 0x000A 37: 0x0000 0x0888 0xC363 0x704D 0x000A 38: 0x0000 0x0888 0xC361 0x704D 0x000A 39: 0x0000 0x0888 0xC363 0x704D 0x000A 40: 0x0000 0x0080 0x0122 0x204D 0x000A 41: 0x0000 0x0080 0x0122 0x204D 0x000A 42: 0x0000 0x0080 0x0102 0x204D 0x000A 43: 0x0000 0x0080 0x0142 0x204D 0x000A 44: 0x0000 0x0040 0x0062 0xA04D 0x000A 45: 0x0000 0x0040 0x0042 0xA04D 0x000A 46: 0x0000 0x0040 0x0002 0xA04D 0x000A 47: 0x0000 0x0040 0x0022 0xA04D 0x000A 48: 0x0000 0x0040 0x0002 0xA04D 0x000A 49: 0x0000 0x0040 0x0002 0xB04D 0x000A 50: 0x0000 0x0040 0x0022 0xB04D 0x000A 51: 0x0000 0x0040 0x0002 0xB04D 0x000A 52: 0x0000 0x0040 0x0002 0xA04D 0x000A 53: 0x0000 0x0040 0x0022 0xA04D 0x000A 54: 0x0000 0x0040 0x0002 0xA04D 0x000A 55: 0x0000 0x0040 0x0002 0xE04D 0x000A 56: 0x0000 0x0040 0x0022 0xE04D 0x000A 57: 0x0000 0x0040 0x0002 0xE04D 0x000A 58: 0x0000 0x0040 0x0002 0xA04D 0x000A 59: 0x0000 0x0040 0x0022 0xA04D 0x000A 60: 0x0000 0x0040 0x0002 0xA04D 0x000A 61: 0x0000 0x0040 0x0202 0xA04D 0x000A 62: 0x0000 0x0040 0x0322 0x204D 0x000A 63: 0x0000 0x0040 0x0302 0x204D 0x000A 64: 0x0000 0x0040 0x0102 0x204D 0x000A 65: 0x0000 0x0040 0x0022 0xA04D 0x000A 66: 0x0000 0x0040 0x0002 0xA04D 0x000A 67: 0x0000 0x0040 0x0003 0xA04D 0x000A 68: 0x0000 0x0080 0x0023 0xA04D 0x000A 69: 0x0000 0x0080 0x0003 0xA04D 0x000A 70: 0x0000 0x0040 0x0002 0xA04D 0x000A 71: 0x0000 0x0040 0x0022 0xA04D 0x000A 72: 0x0000 0x0040 0x0002 0xA04D 0x000A 73: 0x0000 0x0040 0x4002 0xA04D 0x000A 74: 0x0000 0x0040 0x4022 0xA04D 0x000A 75: 0x0000 0x0040 0x4002 0xA04D 0x000A 76: 0x0000 0x0040 0x0002 0xA04D 0x000A 77: 0x0000 0x0040 0x0022 0xA04D 0x000A 78: 0x0000 0x0040 0x0002 0xA04D 0x000A 79: 0x0000 0x0040 0x8002 0xA04D 0x000A 80: 0x0000 0x0040 0x8022 0xA04D 0x000A 81: 0x0000 0x0040 0x8002 0xA04D 0x000A 82: 0x0000 0x0040 0x0002 0xA04D 0x000A 83: 0x0000 0x0040 0x0022 0xA04D 0x000A 84: 0x0000 0x0040 0x0002 0xA04D 0x000A 85: 0x0000 0x0840 0x0002 0xA04D 0x000A 86: 0x0000 0x0840 0x0022 0xA04D 0x000A 87: 0x0000 0x0840 0x0002 0xA04D 0x000A 88: 0x0000 0x0040 0x0002 0xA04D 0x000A 89: 0x0000 0x0040 0x0022 0xA04D 0x000A 90: 0x0000 0x0040 0x0002 0xA04D 0x000A 91: 0x0000 0x0048 0x0002 0xA04D 0x000A 92: 0x0000 0x0048 0x0022 0xA04D 0x000A 93: 0x0000 0x0048 0x0002 0xA04D 0x000A 94: 0x0000 0x0040 0x0002 0xA04D 0x000A 95: 0x0000 0x0040 0x0022 0xA04D 0x000A 96: 0x0000 0x0040 0x0002 0xA04D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 12:07:23 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 12:07:24 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 source: 1 0101 changed: step 37 0101110011001111111111110101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 source: 1 changed: 1 step 39 0101110011001111111111110101 source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 source: 1 changed: step 41 0101110011001110000000000101 source: 0 changed: 0 step 42 0101110011001100000000000101 source: 1 changed: 1 step 43 0101110011001101000000000101 source: 1 1010 changed: 1 1010 step 44 0101110011001111000000001010 source: 0 changed: 0 step 45 0101110011001101000000001010 source: 0 changed: 0 step 46 0101110011001100000000001010 source: 1 changed: 1 step 47 0101110011001110000000001010 source: 0 changed: 0 step 48 0101110011001100000000001010 source: 1 changed: 1 step 49 0101110011001100100000001010 source: 1 changed: 1 step 50 0101110011001110100000001010 source: 0 changed: 0 step 51 0101110011001100100000001010 source: 0 changed: 0 step 52 0101110011001100000000001010 source: 1 changed: 1 step 53 0101110011001110000000001010 source: 0 changed: 0 step 54 0101110011001100000000001010 source: 1 changed: 1 step 55 0101110011001100010000001010 source: 1 changed: 1 step 56 0101110011001110010000001010 source: 0 changed: 0 step 57 0101110011001100010000001010 source: 0 changed: 0 step 58 0101110011001100000000001010 source: 1 changed: 1 step 59 0101110011001110000000001010 source: 0 changed: 0 step 60 0101110011001100000000001010 source: 1 changed: 1 step 61 0101110011001100001000001010 source: 1 01 changed: 1 01 step 62 0101110011001110001000000110 source: 0 changed: 0 step 63 0101110011001100001000000110 source: 0 changed: 0 step 64 0101110011001100000000000110 source: 1 10 changed: 1 10 step 65 0101110011001110000000001010 source: 0 changed: 0 step 66 0101110011001100000000001010 source: 1 changed: 1 step 67 0101110011001100000100001010 source: 1 01 changed: 1 01 step 68 0101110011001110000100001001 source: 0 changed: 0 step 69 0101110011001100000100001001 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 10 changed: 0 step 70 0101110011001100000000001001 fail ^^ source: 1 changed: 1 10 step 71 0101110011001110000000001010 source: 0 changed: 0 step 72 0101110011001100000000001010 source: 1 changed: 1 step 73 0101110011001100000010001010 source: 1 changed: 1 step 74 0101110011001110000010001010 source: 0 changed: 0 step 75 0101110011001100000010001010 source: 0 changed: 0 step 76 0101110011001100000000001010 source: 1 changed: 1 step 77 0101110011001110000000001010 source: 0 changed: 0 step 78 0101110011001100000000001010 source: 1 changed: 1 step 79 0101110011001100000001001010 source: 1 changed: 1 step 80 0101110011001110000001001010 source: 0 changed: 0 step 81 0101110011001100000001001010 source: 0 changed: 0 step 82 0101110011001100000000001010 source: 1 changed: 1 step 83 0101110011001110000000001010 source: 0 changed: 0 step 84 0101110011001100000000001010 source: 1 changed: 1 step 85 0101110011001100000000101010 source: 1 changed: 1 step 86 0101110011001110000000101010 source: 0 changed: 0 step 87 0101110011001100000000101010 source: 0 changed: 0 step 88 0101110011001100000000001010 source: 1 changed: 1 step 89 0101110011001110000000001010 source: 0 changed: 0 step 90 0101110011001100000000001010 source: 1 changed: 1 step 91 0101110011001100000000011010 source: 1 changed: 1 step 92 0101110011001110000000011010 source: 0 changed: 0 step 93 0101110011001100000000011010 source: 0 changed: 0 step 94 0101110011001100000000001010 source: 1 changed: 1 step 95 0101110011001110000000001010 source: 0 changed: 0 step 96 0101110011001100000000001010 test 22: *** FAIL *************************** 1 steps failed SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail OO all fails OO was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 22, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 00XX110X110X110000000000XXXX changed: 0 step 1 0001110011001100000000001010 source: source: ; TEST SPARE FF source: 101 changed: 1 step 2 0101110011001100000000001010 source: 0 changed: 0 step 3 0001110011001100000000001010 source: 1 changed: 1 step 4 1001110011001100000000001010 source: 110 changed: 110 step 5 1110110011001100000000001010 source: 0 changed: 0 step 6 1010110011001100000000001010 source: 0 changed: 0 step 7 0010110011001100000000001010 source: 101 changed: 101 step 8 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '04' FLIP FLOP source: source: 0 1 changed: 0 1 step 9 0101010111001100000000001010 source: 1 changed: 1 step 10 0101110111001100000000001010 source: 0 0 changed: 0 0 step 11 0101100011001100000000001010 source: 1 changed: 1 step 12 0101110011001100000000001010 source: 11 changed: 11 step 13 0101111111001100000000001010 source: 0 changed: 0 step 14 0101110111001100000000001010 source: 10 changed: 10 step 15 0101111011001100000000001010 source: 0 changed: 0 step 16 0101110011001100000000001010 source: source: ; TEST TOGGLE WEIGTH '02' FLIP FLOP source: source: 0 1 changed: 0 1 step 17 0101110001011100000000001010 source: 1 changed: 1 step 18 0101110011011100000000001010 source: 0 0 changed: 0 0 step 19 0101110010001100000000001010 source: 1 changed: 1 step 20 0101110011001100000000001010 source: 11 changed: 11 step 21 0101110011111100000000001010 source: 0 changed: 0 step 22 0101110011011100000000001010 source: 10 changed: 10 step 23 0101110011101100000000001010 source: 0 changed: 0 step 24 0101110011001100000000001010 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 01 step 25 0101110011000100000000000110 source: 1 changed: 1 step 26 0101110011001100000000000110 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 01 step 27 0101110011001000000000000101 source: 1 changed: 1 step 28 0101110011001100000000000101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: step 29 0101110011001100000000000101 source: 1 1010 changed: 1 1010 step 30 0101110011001110000000001010 source: 0 changed: 0 step 31 0101110011001100000000001010 source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: 111111111 step 32 0101110011001101111111111010 source: 1 0101 changed: 1 0101 step 33 0101110011001111111111110101 source: source: ; CLEAR WEIGHTS '001' THRU '010' source: 0 01 changed: 0 step 34 0101110011000111111111110101 source: 1 changed: 1 step 35 0101110011001111111111110101 source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 1S source: 111111111 changed: step 36 0101110011001111111111110101 source: 1 0101 changed: step 37 0101110011001111111111110101 source: source: ; CLEAR WEIGHT '020' source: 0 01 changed: 0 step 38 0101110011001011111111110101 source: 1 changed: 1 step 39 0101110011001111111111110101 source: source: source: ; WALK A ONE '001' THRU '400' source: source: source: ; LOAD WEIGHTS '001' THRU '400' WITH 0 source: 000000000 changed: 000000000 step 40 0101110011001110000000000101 source: 1 changed: step 41 0101110011001110000000000101 source: 0 changed: 0 step 42 0101110011001100000000000101 source: 1 changed: 1 step 43 0101110011001101000000000101 source: 1 1010 changed: 1 1010 step 44 0101110011001111000000001010 source: 0 changed: 0 step 45 0101110011001101000000001010 source: 0 changed: 0 step 46 0101110011001100000000001010 source: 1 changed: 1 step 47 0101110011001110000000001010 source: 0 changed: 0 step 48 0101110011001100000000001010 source: 1 changed: 1 step 49 0101110011001100100000001010 source: 1 changed: 1 step 50 0101110011001110100000001010 source: 0 changed: 0 step 51 0101110011001100100000001010 source: 0 changed: 0 step 52 0101110011001100000000001010 source: 1 changed: 1 step 53 0101110011001110000000001010 source: 0 changed: 0 step 54 0101110011001100000000001010 source: 1 changed: 1 step 55 0101110011001100010000001010 source: 1 changed: 1 step 56 0101110011001110010000001010 source: 0 changed: 0 step 57 0101110011001100010000001010 source: 0 changed: 0 step 58 0101110011001100000000001010 source: 1 changed: 1 step 59 0101110011001110000000001010 source: 0 changed: 0 step 60 0101110011001100000000001010 source: 1 changed: 1 step 61 0101110011001100001000001010 source: 1 01 changed: 1 01 step 62 0101110011001110001000000110 source: 0 changed: 0 step 63 0101110011001100001000000110 source: 0 changed: 0 step 64 0101110011001100000000000110 source: 1 10 changed: 1 10 step 65 0101110011001110000000001010 source: 0 changed: 0 step 66 0101110011001100000000001010 source: 1 changed: 1 step 67 0101110011001100000100001010 source: 1 01 changed: 1 01 step 68 0101110011001110000100001001 source: 0 changed: 0 step 69 0101110011001100000100001001 SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO source: 0 10 changed: 0 step 70 0101110011001100000000001001 fail ^^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 22, total passes 0 Main menu Sat Jul 01 12:08:10 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\A615.TST reading test file: tests\A615.TST comment: A615 DIGITAL-TO-ANALOG CONVERTER comment: pins: PINS pins: 1 I BS2 E6-12 SPARE FF DATA IN pins: 2 I BT2 E6-13 SPARE FF CLOCK IN pins: 3 O BU2 E6-9 SPARE FF Q OUTPUT pins: 4 O BV2 E6-8 SPARE FF Q-N OUTPUT pins: 5 I BP2 E6-1 TOGGLE WEIGHT '004' SET-N pins: 6 I BL2 E6-4 TOGGLE WEIGHT '004' CLEAR-N pins: 7 I BM2 E6-3 TOGGLE WEIGHT '004' CLOCK pins: 8 O BN2 E6-6 TOGGLE WEIGHT '004' Q OUTPUT pins: 9 I BH2 E5-13 TOGGLE WEIGHT '002' SET-N pins: 10 I BK2 E5-10 TOGGLE WEIGHT '002' CLEAR-N pins: 11 I BJ2 E5-11 TOGGLE WEIGHT '002' CLOCK pins: 12 O BF2 E5-8 TOGGLE WEIGHT '002' Q OUTPUT pins: 13 I BK1 E3-10,E4-4+++ CLEAR-N; CLEARS WEIGHT '001' THRU '010' pins: 14 I AV2 E3-4 WEIGHT '020' CLEAR-N (BIT 7) pins: 15 I BD2 E5-3,E4-11+++ LOAD (CLOCKS WEIGHT '001' THRU WEIGHT '400' FLIP FLOPS pins: 16 I BE2 E5-2 WEIGHT '001' DATA IN (BIT 11 LSB) pins: 17 I BL1 E4-12 WEIGHT '002' DATA IN (BIT 10) pins: 18 I BJ1 E4-2 WEIGHT '004' DATA IN (BIT 9) pins: 19 I BE1 E3-12 WEIGHT '010' DATA IN (BIT 8) pins: 20 I AU2 E3-2 WEIGHT '020' DATA IN (BIT 7) pins: 21 I AV1 E2-12 WEIGHT '040' DATA IN (BIT 6) pins: 22 I AU1 E2-2 WEIGHT '100' DATA IN (BIT 5) pins: 23 I AP1 E1-12 WEIGHT '200' DATA IN (BIT 4) pins: 24 I AN2 E1-2 WEIGHT '400' DATA IN (BIT 3) pins: 25 O BH1 E3-8 WEIGHT '010' Q OUTPUT (BIT 8) pins: 26 O BF1 E3-9 WEIGHT '010' Q-N OUTPUT (BIT 8) pins: 27 O AS2 E3-6 WEIGHT '020' Q OUTPUT (BIT 7) pins: 28 O AT2 E3-5 WEIGHT '020' Q-N OUTPUT (BIT 7) pins: direction: IIOOIIIOIIIOIIIIIIIIIIIIOOOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 00XX110X110X110000000000XXXX comment: comment: ; TEST SPARE FF test 2: 101 test 3: 0 test 4: 1 test 5: 110 test 6: 0 test 7: 0 test 8: 101 comment: comment: ; TEST TOGGLE WEIGTH '04' FLIP FLOP comment: test 9: 0 1 test 10: 1 test 11: 0 0 test 12: 1 test 13: 11 test 14: 0 test 15: 10 test 16: 0 comment: comment: ; TEST TOGGLE WEIGTH '02' FLIP FLOP comment: test 17: 0 1 test 18: 1 test 19: 0 0 test 20: 1 test 21: 11 test 22: 0 test 23: 10 test 24: 0 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 25: 0 01 test 26: 1 comment: comment: ; CLEAR WEIGHT '020' test 27: 0 01 test 28: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 29: 000000000 test 30: 1 1010 test 31: 0 comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 32: 111111111 test 33: 1 0101 comment: comment: ; CLEAR WEIGHTS '001' THRU '010' test 34: 0 01 test 35: 1 comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 1S test 36: 111111111 test 37: 1 0101 comment: comment: ; CLEAR WEIGHT '020' test 38: 0 01 test 39: 1 comment: comment: comment: ; WALK A ONE '001' THRU '400' comment: comment: comment: ; LOAD WEIGHTS '001' THRU '400' WITH 0 test 40: 000000000 test 41: 1 test 42: 0 test 43: 1 test 44: 1 1010 test 45: 0 test 46: 0 test 47: 1 test 48: 0 test 49: 1 test 50: 1 test 51: 0 test 52: 0 test 53: 1 test 54: 0 test 55: 1 test 56: 1 test 57: 0 test 58: 0 test 59: 1 test 60: 0 test 61: 1 test 62: 1 01 test 63: 0 test 64: 0 test 65: 1 10 test 66: 0 test 67: 1 test 68: 1 01 test 69: 0 test 70: 0 test 71: 1 10 test 72: 0 test 73: 1 test 74: 1 test 75: 0 test 76: 0 test 77: 1 test 78: 0 test 79: 1 test 80: 1 test 81: 0 test 82: 0 test 83: 1 test 84: 0 test 85: 1 test 86: 1 test 87: 0 test 88: 0 test 89: 1 test 90: 0 test 91: 1 test 92: 1 test 93: 0 test 94: 0 test 95: 1 test 96: 0 comment: comment: comment: comment: end: END summary column 1: offset 4, mask 0x0001 column 2: offset 4, mask 0x0002 column 3: offset 4, mask 0x0004 column 4: offset 4, mask 0x0008 column 5: offset 3, mask 0x0040 column 6: offset 3, mask 0x0008 column 7: offset 3, mask 0x0010 column 8: offset 3, mask 0x0020 column 9: offset 3, mask 0x0001 column 10: offset 3, mask 0x0004 column 11: offset 3, mask 0x0002 column 12: offset 2, mask 0x0080 column 13: offset 3, mask 0x2000 column 14: offset 2, mask 0x0002 column 15: offset 2, mask 0x0020 column 16: offset 2, mask 0x0040 column 17: offset 3, mask 0x1000 column 18: offset 3, mask 0x4000 column 19: offset 2, mask 0x0200 column 20: offset 2, mask 0x0001 column 21: offset 2, mask 0x4000 column 22: offset 2, mask 0x8000 column 23: offset 1, mask 0x0800 column 24: offset 1, mask 0x0008 column 25: offset 3, mask 0x8000 column 26: offset 2, mask 0x0100 column 27: offset 1, mask 0x0040 column 28: offset 1, mask 0x0080 direction bits (1=input) 0xFFFF 0xF7F7 0x3D98 0x8FA0 0xF0FC pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0000 0x0002 0x204D 0x0000 0x0000 0x00C0 0x0180 0x8020 0x000C 2: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 3: 0x0000 0x0000 0x0002 0x204D 0x0008 0x0000 0x00C0 0x0180 0x8020 0x0000 4: 0x0000 0x0000 0x0002 0x204D 0x0009 0x0000 0x00C0 0x0180 0x8020 0x0000 5: 0x0000 0x0000 0x0002 0x204D 0x0007 0x0000 0x00C0 0x0180 0x8020 0x0000 6: 0x0000 0x0000 0x0002 0x204D 0x0005 0x0000 0x00C0 0x0180 0x8020 0x0000 7: 0x0000 0x0000 0x0002 0x204D 0x0004 0x0000 0x00C0 0x0180 0x8020 0x0000 8: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8020 0x0000 9: 0x0000 0x0000 0x0002 0x202D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 10: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 11: 0x0000 0x0000 0x0002 0x2045 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 12: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 13: 0x0000 0x0000 0x0002 0x207D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 14: 0x0000 0x0000 0x0002 0x206D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 15: 0x0000 0x0000 0x0002 0x205D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 16: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0180 0x8000 0x0000 17: 0x0000 0x0000 0x0082 0x204C 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 18: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 19: 0x0000 0x0000 0x0002 0x2049 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 20: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 21: 0x0000 0x0000 0x0082 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 22: 0x0000 0x0000 0x0082 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 23: 0x0000 0x0000 0x0002 0x204F 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 24: 0x0000 0x0000 0x0002 0x204D 0x000A 0x0000 0x00C0 0x0100 0x8000 0x0000 25: 0x0000 0x0000 0x0102 0x004D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 26: 0x0000 0x0000 0x0102 0x204D 0x000A 0x0000 0x00C0 0x0000 0x0000 0x0000 27: 0x0000 0x0080 0x0100 0x204D 0x000A 28: 0x0000 0x0080 0x0102 0x204D 0x000A 29: 0x0000 0x0080 0x0102 0x204D 0x000A 30: 0x0000 0x0040 0x0022 0xA04D 0x000A 31: 0x0000 0x0040 0x0002 0xA04D 0x000A 32: 0x0000 0x0848 0xC243 0xF04D 0x000A 33: 0x0000 0x0888 0xC363 0x704D 0x000A 34: 0x0000 0x0888 0xC363 0x504D 0x000A 35: 0x0000 0x0888 0xC363 0x704D 0x000A 36: 0x0000 0x0888 0xC363 0x704D 0x000A 37: 0x0000 0x0888 0xC363 0x704D 0x000A 38: 0x0000 0x0888 0xC361 0x704D 0x000A 39: 0x0000 0x0888 0xC363 0x704D 0x000A 40: 0x0000 0x0080 0x0122 0x204D 0x000A 41: 0x0000 0x0080 0x0122 0x204D 0x000A 42: 0x0000 0x0080 0x0102 0x204D 0x000A 43: 0x0000 0x0080 0x0142 0x204D 0x000A 44: 0x0000 0x0040 0x0062 0xA04D 0x000A 45: 0x0000 0x0040 0x0042 0xA04D 0x000A 46: 0x0000 0x0040 0x0002 0xA04D 0x000A 47: 0x0000 0x0040 0x0022 0xA04D 0x000A 48: 0x0000 0x0040 0x0002 0xA04D 0x000A 49: 0x0000 0x0040 0x0002 0xB04D 0x000A 50: 0x0000 0x0040 0x0022 0xB04D 0x000A 51: 0x0000 0x0040 0x0002 0xB04D 0x000A 52: 0x0000 0x0040 0x0002 0xA04D 0x000A 53: 0x0000 0x0040 0x0022 0xA04D 0x000A 54: 0x0000 0x0040 0x0002 0xA04D 0x000A 55: 0x0000 0x0040 0x0002 0xE04D 0x000A 56: 0x0000 0x0040 0x0022 0xE04D 0x000A 57: 0x0000 0x0040 0x0002 0xE04D 0x000A 58: 0x0000 0x0040 0x0002 0xA04D 0x000A 59: 0x0000 0x0040 0x0022 0xA04D 0x000A 60: 0x0000 0x0040 0x0002 0xA04D 0x000A 61: 0x0000 0x0040 0x0202 0xA04D 0x000A 62: 0x0000 0x0040 0x0322 0x204D 0x000A 63: 0x0000 0x0040 0x0302 0x204D 0x000A 64: 0x0000 0x0040 0x0102 0x204D 0x000A 65: 0x0000 0x0040 0x0022 0xA04D 0x000A 66: 0x0000 0x0040 0x0002 0xA04D 0x000A 67: 0x0000 0x0040 0x0003 0xA04D 0x000A 68: 0x0000 0x0080 0x0023 0xA04D 0x000A 69: 0x0000 0x0080 0x0003 0xA04D 0x000A 70: 0x0000 0x0080 0x0002 0xA04D 0x000A 71: 0x0000 0x0040 0x0022 0xA04D 0x000A 72: 0x0000 0x0040 0x0002 0xA04D 0x000A 73: 0x0000 0x0040 0x4002 0xA04D 0x000A 74: 0x0000 0x0040 0x4022 0xA04D 0x000A 75: 0x0000 0x0040 0x4002 0xA04D 0x000A 76: 0x0000 0x0040 0x0002 0xA04D 0x000A 77: 0x0000 0x0040 0x0022 0xA04D 0x000A 78: 0x0000 0x0040 0x0002 0xA04D 0x000A 79: 0x0000 0x0040 0x8002 0xA04D 0x000A 80: 0x0000 0x0040 0x8022 0xA04D 0x000A 81: 0x0000 0x0040 0x8002 0xA04D 0x000A 82: 0x0000 0x0040 0x0002 0xA04D 0x000A 83: 0x0000 0x0040 0x0022 0xA04D 0x000A 84: 0x0000 0x0040 0x0002 0xA04D 0x000A 85: 0x0000 0x0840 0x0002 0xA04D 0x000A 86: 0x0000 0x0840 0x0022 0xA04D 0x000A 87: 0x0000 0x0840 0x0002 0xA04D 0x000A 88: 0x0000 0x0040 0x0002 0xA04D 0x000A 89: 0x0000 0x0040 0x0022 0xA04D 0x000A 90: 0x0000 0x0040 0x0002 0xA04D 0x000A 91: 0x0000 0x0048 0x0002 0xA04D 0x000A 92: 0x0000 0x0048 0x0022 0xA04D 0x000A 93: 0x0000 0x0048 0x0002 0xA04D 0x000A 94: 0x0000 0x0040 0x0002 0xA04D 0x000A 95: 0x0000 0x0040 0x0022 0xA04D 0x000A 96: 0x0000 0x0040 0x0002 0xA04D 0x000A PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I GIIP G I OOII IOOIII G P GIIOIIIIIOI IIOO UUT inputs: 20 UUT outputs: 8 pins used: 28 not used: 38 96 'test steps' 163 lines A615 DIGITAL-TO-ANALOG CONVERTER PINS Main menu Sat Jul 01 12:08:14 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 12:08:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppFppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 61 0101110011001100001000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 62 0101110011001110001000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 63 0101110011001100001000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 64 0101110011001100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 65 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 66 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 67 0101110011001100000100001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 68 0101110011001110000100001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 69 0101110011001100000100001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 70 0101110011001100000000001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 71 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 72 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 73 0101110011001100000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 74 0101110011001110000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 75 0101110011001100000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 76 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 77 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 78 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 79 0101110011001100000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 80 0101110011001110000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 81 0101110011001100000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 82 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 83 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 84 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 85 0101110011001100000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 86 0101110011001110000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 87 0101110011001100000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 88 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 89 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 90 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 91 0101110011001100000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 92 0101110011001110000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 93 0101110011001100000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 94 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 95 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 96 0101110011001100000000001010 okay test 2348: pass SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail all fails I was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 1, total passes 2347 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 1 0001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 2 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 3 0001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 4 1001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 110 step 5 1110110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 6 1010110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 7 0010110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 101 step 8 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 1 step 9 0101010111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 10 0101110111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 0 step 11 0101100011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 12 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 11 step 13 0101111111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 14 0101110111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 10 step 15 0101111011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 16 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 1 step 17 0101110001011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 18 0101110011011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 0 step 19 0101110010001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 20 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 11 step 21 0101110011111100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 22 0101110011011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 10 step 23 0101110011101100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 24 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 01 step 25 0101110011000100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 26 0101110011001100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 01 step 27 0101110011001000000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 28 0101110011001100000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 29 0101110011001100000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 30 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 31 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 111111111 step 32 0101110011001101111111111010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 0101 step 33 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 34 0101110011000111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 35 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 36 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 37 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 38 0101110011001011111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 39 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 000000000 step 40 0101110011001110000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 41 0101110011001110000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 42 0101110011001100000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 43 0101110011001101000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 44 0101110011001111000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 45 0101110011001101000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 46 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 47 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 48 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 49 0101110011001100100000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 50 0101110011001110100000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 51 0101110011001100100000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 52 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 53 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 54 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 55 0101110011001100010000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 56 0101110011001110010000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 57 0101110011001100010000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 58 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 59 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 60 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 61 0101110011001100001000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 62 0101110011001110001000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 63 0101110011001100001000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 64 0101110011001100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 65 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 66 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 67 0101110011001100000100001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 68 0101110011001110000100001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 69 0101110011001100000100001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 70 0101110011001100000000001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 71 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 72 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 73 0101110011001100000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 74 0101110011001110000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 75 0101110011001100000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 76 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 77 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 78 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 79 0101110011001100000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 80 0101110011001110000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 81 0101110011001100000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 82 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 83 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 84 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 85 0101110011001100000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 86 0101110011001110000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 87 0101110011001100000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 88 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 89 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 90 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 91 0101110011001100000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 92 0101110011001110000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 93 0101110011001100000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 94 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 95 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 96 0101110011001100000000001010 okay test 2349: pass SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail all fails I was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 1, total passes 2348 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 1 0001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 2 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 3 0001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 4 1001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 110 step 5 1110110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 6 1010110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 7 0010110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 101 step 8 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 1 step 9 0101010111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 10 0101110111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 0 step 11 0101100011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 12 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 11 step 13 0101111111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 14 0101110111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 10 step 15 0101111011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 16 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 1 step 17 0101110001011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 18 0101110011011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 0 step 19 0101110010001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 20 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 11 step 21 0101110011111100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 22 0101110011011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 10 step 23 0101110011101100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 24 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 01 step 25 0101110011000100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 26 0101110011001100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 01 step 27 0101110011001000000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 28 0101110011001100000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 29 0101110011001100000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 30 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 31 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 111111111 step 32 0101110011001101111111111010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 0101 step 33 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 34 0101110011000111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 35 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 36 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 37 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 38 0101110011001011111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 39 0101110011001111111111110101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 000000000 step 40 0101110011001110000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: step 41 0101110011001110000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 42 0101110011001100000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 43 0101110011001101000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 1010 step 44 0101110011001111000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 45 0101110011001101000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 46 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 47 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 48 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 49 0101110011001100100000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 50 0101110011001110100000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 51 0101110011001100100000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 52 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 53 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 54 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 55 0101110011001100010000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 56 0101110011001110010000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 57 0101110011001100010000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 58 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 59 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 60 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 61 0101110011001100001000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 62 0101110011001110001000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 63 0101110011001100001000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 64 0101110011001100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 65 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 66 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 67 0101110011001100000100001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 01 step 68 0101110011001110000100001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 69 0101110011001100000100001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 70 0101110011001100000000001001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 10 step 71 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 72 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 73 0101110011001100000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 74 0101110011001110000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 75 0101110011001100000010001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 76 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 77 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 78 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 79 0101110011001100000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 80 0101110011001110000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 81 0101110011001100000001001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 82 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 83 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 84 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 85 0101110011001100000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 86 0101110011001110000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 87 0101110011001100000000101010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 88 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 89 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 90 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 91 0101110011001100000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 92 0101110011001110000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 93 0101110011001100000000011010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 94 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 95 0101110011001110000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 96 0101110011001100000000001010 okay test 2350: pass SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO this fail all fails I was hi 1111111111111111111111111111 rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv was lo 0000000000000000000000000000 total fails 1, total passes 2349 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 1 0001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 2 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 3 0001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 4 1001110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 110 step 5 1110110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 6 1010110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 7 0010110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 101 step 8 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 1 step 9 0101010111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 10 0101110111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 0 step 11 0101100011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 12 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 11 step 13 0101111111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 14 0101110111001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 10 step 15 0101111011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 16 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 1 step 17 0101110001011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 18 0101110011011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 0 step 19 0101110010001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 20 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 11 step 21 0101110011111100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 22 0101110011011100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 10 step 23 0101110011101100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 step 24 0101110011001100000000001010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 01 step 25 0101110011000100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 1 step 26 0101110011001100000000000110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO changed: 0 01 step 27 0101110011001000000000000101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit scope (run, no print) ppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails IIIIIIIIIII was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 5, total passes 8907 Main menu Sat Jul 01 12:17:06 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 12:17:08 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp 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FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails OOIIIOIIIOI II OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 817, total passes 8819 Main menu Sat Jul 01 12:25:36 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 12:25:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode 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FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT BBBBBBBBBBBBBABBBBBAAAAABBAA LETTER STUVPLMNHKJFKVDELJEUVUPNHFST SIDE 2222222222221222111211121122 DIRECTION IIOOIIIOIIIOIIIIIIIIIIIIOOOO all fails IIOO O O OOOO was lo 0000000000000000000000000000 falling vvvvvvvvvvvvvvvvvvvvvvvvvvvv rising ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ was hi 1111111111111111111111111111 total fails 139075, total passes 1601 Main menu Sat Jul 01 14:29:12 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M760.TST could not open test file. valid test files are: reverting back to test file: tests\A615.TST Main menu Sat Jul 01 14:45:07 2017 test file is: tests\A615.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M760_AC5.TST reading test file: tests\M760_AC5.TST comment: M760 A-D CONTROL PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS FAST SAM FF (HAS AC5 INPUT). comment: pins: PINS pins: 1 I AE2 E1-1 FAST SAM CLEAR-N (IO PRESET L) pins: 2 I AJ2 E1-2 FAST SAM DATA IN (AC05(1)H) pins: 3 I AH2 E1-3 FAST SAM CLOCK pins: 4 O AC1 E1-5 FAST SAM Q OUTPUT (FAST SAM(1)H) pins: 5 O AF2 E1-6 FAST SAM Q-N OUTPUT (FAST SAM(0)H) pins: direction: IIIOO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 100XX comment: comment: ; TEST FAST SAM FF comment: comment: ; CLEAR IT test 2: 00001 test 3: 1 comment: comment: ;LATCH A ONE test 4: 1 test 5: 110 test 6: 0 comment: ; LATCH A ZERO test 7: 0 test 8: 101 test 9: 0 comment: comment: end: END summary column 1: offset 0, mask 0x0008 column 2: offset 0, mask 0x0001 column 3: offset 0, mask 0x0002 column 4: offset 0, mask 0x2000 column 5: offset 0, mask 0x0004 direction bits (1=input) 0xFFF4 0xFFFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0008 0x0000 0x0000 0x0000 0x0000 0x2004 0x0000 0x0000 0x0000 0x0000 2: 0x0004 0x0000 0x0000 0x0000 0x0000 3: 0x000C 0x0000 0x0000 0x0000 0x0000 4: 0x000D 0x0000 0x0000 0x0000 0x0000 5: 0x200B 0x0000 0x0000 0x0000 0x0000 6: 0x2009 0x0000 0x0000 0x0000 0x0000 7: 0x2008 0x0000 0x0000 0x0000 0x0000 8: 0x000E 0x0000 0x0000 0x0000 0x0000 9: 0x000C 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE O G P G IOII G P G UUT inputs: 3 UUT outputs: 2 pins used: 5 not used: 61 9 'test steps' 33 lines M760 A-D CONTROL PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS FAST SAM FF (HAS AC5 INPUT). PINS Main menu Sat Jul 01 14:45:32 2017 test file is: tests\M760_AC5.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 14:45:36 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 4 11001 step 5 11110 step 6 11010 step 7 10010 step 8 10101 step 9 10001 test 302: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 302 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 10001 step 2 00001 step 3 10001 step 4 11001 step 5 11110 step 6 11010 step 7 10010 step 8 10101 step 9 10001 test 303: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 303 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 source: 1 changed: 1 step 3 10001 source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 source: 110 changed: 110 step 5 11110 source: 0 changed: 0 step 6 11010 source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 source: 101 changed: 101 step 8 10101 source: 0 changed: 0 step 9 10001 test 304: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 304 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 source: 1 changed: 1 step 3 10001 source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 source: 110 changed: 110 step 5 11110 source: 0 changed: 0 step 6 11010 source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 source: 101 changed: 101 step 8 10101 source: 0 changed: 0 step 9 10001 test 305: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 305 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 1 changed: 1 step 3 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 110 changed: 110 step 5 11110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 6 11010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 101 changed: 101 step 8 10101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 9 10001 okay test 306: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 306 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 1 changed: 1 step 3 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 110 changed: 110 step 5 11110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 6 11010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 101 changed: 101 step 8 10101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 9 10001 okay test 307: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 307 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 1 changed: 1 step 3 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 110 changed: 110 step 5 11110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 6 11010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 101 changed: 101 step 8 10101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 9 10001 okay test 308: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 308 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 1 changed: 1 step 3 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 110 changed: 110 step 5 11110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 6 11010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 101 changed: 101 step 8 10101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 9 10001 okay test 309: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 309 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 1 changed: 1 step 3 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 110 changed: 110 step 5 11110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 6 11010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 101 changed: 101 step 8 10101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 9 10001 okay test 310: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 310 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100XX changed: step 1 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ; TEST FAST SAM FF source: source: ; CLEAR IT source: 00001 changed: 0 step 2 00001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 1 changed: 1 step 3 10001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 11001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 110 changed: 110 step 5 11110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 6 11010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: ; LATCH A ZERO source: 0 changed: 0 step 7 10010 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 101 changed: 101 step 8 10101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO source: 0 changed: 0 step 9 10001 okay test 311: pass SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO this fail all fails was hi 11111 rising ^^^^^ falling vvvvv was lo 00000 total fails 0, total passes 311 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAA LETTER EJHCF SIDE 22212 DIRECTION IIIOO all fails was lo 00000 falling vvvvv rising ^^^^^ was hi 11111 total fails 0, total passes 311 Main menu Sat Jul 01 14:49:25 2017 test file is: tests\M760_AC5.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M711_AC4.TST reading test file: tests\M711_AC4.TST comment: M711 SCOPE CONTROL PCB REV C, SCHEMATIC REV C comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS SIZE FF (HAS AC4 INPUT). comment: pins: PINS pins: 1 I AR2 E6-10+++ SIZE FF CLEAR-N (IO PRESET) pins: 2 I BD1 E6-12 SIZE FF DATA IN (AC04(1)H) pins: 3 I AV1 E6-11 SIZE FF CLOCK (LOAD TRAP) pins: 4 O BU2 E6-8 SIZE FF Q-N OUTPUT pins: direction: IIIO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 100X comment: comment: ; TEST SIZE FF comment: comment: ; CLEAR IT test 2: 0001 test 3: 1 comment: comment: ;LATCH A ONE test 4: 1 test 5: 10 test 6: 0 comment: ; LATCH A ZERO test 7: 0 test 8: 11 test 9: 0 comment: comment: end: END summary column 1: offset 1, mask 0x0020 column 2: offset 2, mask 0x0400 column 3: offset 2, mask 0x4000 column 4: offset 4, mask 0x0004 direction bits (1=input) 0xFFFF 0xFFDF 0xBBFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0020 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0004 2: 0x0000 0x0000 0x0000 0x0000 0x0004 3: 0x0000 0x0020 0x0000 0x0000 0x0004 4: 0x0000 0x0020 0x0400 0x0000 0x0004 5: 0x0000 0x0020 0x4400 0x0000 0x0000 6: 0x0000 0x0020 0x0400 0x0000 0x0000 7: 0x0000 0x0020 0x0000 0x0000 0x0000 8: 0x0000 0x0020 0x4000 0x0000 0x0004 9: 0x0000 0x0020 0x0000 0x0000 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G IP G I I G P G O UUT inputs: 3 UUT outputs: 1 pins used: 4 not used: 62 9 'test steps' 32 lines M711 SCOPE CONTROL PCB REV C, SCHEMATIC REV C ****************EXTREMELY LIMITED, ONLY CHECKS SIZE FF (HAS AC4 INPUT). PINS Main menu Sat Jul 01 15:05:12 2017 test file is: tests\M711_AC4.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 15:05:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 222: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 222, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 10 changed: 1 step 5 1110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 6 1100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 11 changed: 11 step 8 1011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 9 1001 okay test 223: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 223, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO all fails O was lo 0000 falling vvvv rising ^^^^ was hi 1111 total fails 223, total passes 0 Main menu Sat Jul 01 15:12:28 2017 test file is: tests\M711_AC4.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m711_ac4.tst reading test file: tests\m711_ac4.tst comment: M711 SCOPE CONTROL PCB REV C, SCHEMATIC REV C comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS SIZE FF (HAS AC4 INPUT). comment: pins: PINS pins: 1 I AR2 E6-10+++ SIZE FF CLEAR-N (IO PRESET) pins: 2 I BD1 E6-12 SIZE FF DATA IN (AC04(1)H) pins: 3 I AV1 E6-11 SIZE FF CLOCK (LOAD TRAP) pins: 4 O BU2 E6-8 SIZE FF Q-N OUTPUT pins: direction: IIIO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 100X comment: comment: ; TEST SIZE FF comment: comment: ; CLEAR IT test 2: 0001 test 3: 1 comment: comment: ;LATCH A ONE test 4: 1 test 5: 10 test 6: 0 comment: ; LATCH A ZERO test 7: 0 test 8: 11 test 9: 0 comment: comment: end: END summary column 1: offset 1, mask 0x0020 column 2: offset 2, mask 0x0400 column 3: offset 2, mask 0x4000 column 4: offset 4, mask 0x0004 direction bits (1=input) 0xFFFF 0xFFDF 0xBBFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0020 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0004 2: 0x0000 0x0000 0x0000 0x0000 0x0004 3: 0x0000 0x0020 0x0000 0x0000 0x0004 4: 0x0000 0x0020 0x0400 0x0000 0x0004 5: 0x0000 0x0020 0x4400 0x0000 0x0000 6: 0x0000 0x0020 0x0400 0x0000 0x0000 7: 0x0000 0x0020 0x0000 0x0000 0x0000 8: 0x0000 0x0020 0x4000 0x0000 0x0004 9: 0x0000 0x0020 0x0000 0x0000 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G IP G I I G P G O UUT inputs: 3 UUT outputs: 1 pins used: 4 not used: 62 9 'test steps' 32 lines M711 SCOPE CONTROL PCB REV C, SCHEMATIC REV C ****************EXTREMELY LIMITED, ONLY CHECKS SIZE FF (HAS AC4 INPUT). PINS Main menu Sat Jul 01 15:12:35 2017 test file is: tests\m711_ac4.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Sat Jul 01 15:21:03 2017 test file is: tests\m711_ac4.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 01 15:21:08 2017 test file is: tests\m711_ac4.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 15:21:09 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 5 1110 step 6 1100 step 7 1000 step 8 1011 step 9 1001 test 169: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 169, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO changed: 1 step 4 1100 fail ^ step 5 1110 step 6 1100 step 7 1000 step 8 1011 step 9 1001 test 170: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 170, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 10 changed: 1 step 5 1110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 6 1100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 11 changed: 11 step 8 1011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 9 1001 okay test 171: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 171, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 10 changed: 1 step 5 1110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 6 1100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 11 changed: 11 step 8 1011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 9 1001 okay test 172: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 172, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 10 changed: 1 step 5 1110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 6 1100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 11 changed: 11 step 8 1011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 9 1001 okay test 173: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 173, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 174: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 174, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 175: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 175, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 176: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 176, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 177: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 177, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 178: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 178, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 179: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 179, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 10 changed: 1 step 5 1110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 6 1100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 11 changed: 11 step 8 1011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 9 1001 okay test 180: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 180, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 3 I AV1 E6-11 SIZE FF CLOCK (LOAD TRAP) space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit 1 I AR2 E6-10+++ SIZE FF CLEAR-N (IO PRESET) 2 I BD1 E6-12 SIZE FF DATA IN (AC04(1)H) 3 I AV1 E6-11 SIZE FF CLOCK (LOAD TRAP) 4 O BU2 E6-8 SIZE FF Q-N OUTPUT space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ source: 10 changed: 1 step 5 1110 source: 0 changed: 0 step 6 1100 source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 source: 11 changed: 11 step 8 1011 source: 0 changed: 0 step 9 1001 test 181: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 181, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 10 changed: 1 step 5 1110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 6 1100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 11 changed: 11 step 8 1011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 9 1001 okay test 182: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 182, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 1 changed: 1 step 3 1000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ;LATCH A ONE source: 1 changed: 1 step 4 1100 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 10 changed: 1 step 5 1110 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 6 1100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: ; LATCH A ZERO source: 0 changed: 0 step 7 1000 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 11 changed: 11 step 8 1011 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: 0 changed: 0 step 9 1001 okay test 183: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 183, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; ALL INPUTS LOW/NEUTRAL source: 100X changed: step 1 1001 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO source: source: ; TEST SIZE FF source: source: ; CLEAR IT source: 0001 changed: 0 0 step 2 0000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO all fails O was lo 0000 falling vvvv rising ^^^^ was hi 1111 total fails 183, total passes 0 Main menu Sat Jul 01 15:32:12 2017 test file is: tests\m711_ac4.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\x could not open test file. valid test files are: reverting back to test file: tests\m711_ac4.tst Main menu Sat Jul 01 15:32:14 2017 test file is: tests\m711_ac4.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 15:45:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 6 1100 step 7 1000 step 8 1011 step 9 1001 test 218: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 218, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 1001 SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO changed: 0 0 step 2 0000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO changed: 1 step 3 1000 fail ^ SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO changed: 1 step 4 1100 fail ^ step 5 1110 step 6 1100 step 7 1000 step 8 1011 step 9 1001 test 219: *** FAIL *************************** 3 steps failed SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO this fail O all fails O was hi 1111 rising ^^^^ falling vvvv was lo 0000 total fails 219, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO all fails O was lo 0000 falling vvvv rising ^^^^ was hi 1111 total fails 219, total passes 0 Main menu Sat Jul 01 15:46:40 2017 test file is: tests\m711_ac4.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M711_AC4.TST reading test file: tests\M711_AC4.TST comment: M711 SCOPE CONTROL PCB REV C, SCHEMATIC REV C comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS SIZE FF (HAS AC4 INPUT). comment: pins: PINS pins: 1 I AR2 E6-10+++ SIZE FF SET-N (IO PRESET) pins: 2 I BD1 E6-12 SIZE FF DATA IN (AC04(1)H) pins: 3 I AV1 E6-11 SIZE FF CLOCK (LOAD TRAP) pins: 4 O BU2 E6-8 SIZE FF Q-N OUTPUT pins: direction: IIIO comment: comment: ; ALL INPUTS LOW/NEUTRAL test 1: 100X comment: comment: ; TEST SIZE FF comment: comment: ; SET IT test 2: 0000 test 3: 1 comment: comment: ;LATCH A ONE test 4: 1 test 5: 10 test 6: 0 comment: ; LATCH A ZERO test 7: 0 test 8: 11 test 9: 0 comment: end: END summary column 1: offset 1, mask 0x0020 column 2: offset 2, mask 0x0400 column 3: offset 2, mask 0x4000 column 4: offset 4, mask 0x0004 direction bits (1=input) 0xFFFF 0xFFDF 0xBBFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0000 0x0020 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0004 2: 0x0000 0x0000 0x0000 0x0000 0x0000 3: 0x0000 0x0020 0x0000 0x0000 0x0000 4: 0x0000 0x0020 0x0400 0x0000 0x0000 5: 0x0000 0x0020 0x4400 0x0000 0x0000 6: 0x0000 0x0020 0x0400 0x0000 0x0000 7: 0x0000 0x0020 0x0000 0x0000 0x0000 8: 0x0000 0x0020 0x4000 0x0000 0x0004 9: 0x0000 0x0020 0x0000 0x0000 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE G IP G I I G P G O UUT inputs: 3 UUT outputs: 1 pins used: 4 not used: 62 9 'test steps' 31 lines M711 SCOPE CONTROL PCB REV C, SCHEMATIC REV C ****************EXTREMELY LIMITED, ONLY CHECKS SIZE FF (HAS AC4 INPUT). PINS Main menu Sat Jul 01 15:53:14 2017 test file is: tests\M711_AC4.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 15:53:17 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT ABAB LETTER RDVU SIDE 2112 DIRECTION IIIO all fails was lo 0000 falling vvvv rising ^^^^ was hi 1111 total fails 0, total passes 810 Main menu Sat Jul 01 15:53:24 2017 test file is: tests\M711_AC4.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 15:59:34 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M719_AC.TST reading test file: tests\M719_AC.TST comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AH2 E5-9 AC(N-1) INPUT pins: 2 I AK1 E8-1,E8-9 AC(N) INPUT pins: 3 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: direction: III comment: comment: ; E8-3 HI E5-8 HI test 1: 100 test 2: E5-8 LO 'test step' is too long expected 'test step' (3 columns of '0','1','X', or ' ') bad test file Main menu Sat Jul 01 16:26:26 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M719_AC.TST reading test file: tests\M719_AC.TST comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AH2 E5-9 AC(N-1) INPUT pins: 2 I AK1 E8-1,E8-9 AC(N) INPUT pins: 3 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: direction: III comment: comment: ; E8-3 HI E5-8 HI test 1: 100 comment: ; E5-8 LO test 2: 01 comment: ; E8-3 LO test 3: 11 comment: ; E5-8 HI test 4: 00 comment: end: END summary column 1: offset 0, mask 0x0002 column 2: offset 1, mask 0x8000 column 3: offset 0, mask 0x0100 direction bits (1=input) 0xFEFD 0x7FFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0002 0x0000 0x0000 0x0000 0x0000 2: 0x0102 0x0000 0x0000 0x0000 0x0000 3: 0x0102 0x8000 0x0000 0x0000 0x0000 4: 0x0002 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE II G P G I G P G UUT inputs: 3 UUT outputs: 0 pins used: 3 not used: 63 4 'test steps' 23 lines M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. *************** USE DMM AND SINGLE STEP. PINS Main menu Sat Jul 01 16:26:59 2017 test file is: tests\M719_AC.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 16:27:05 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III changed: 00 step 4 000 fail ^ test 765: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 765, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 766: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 766, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 767: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 767, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 768: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 768, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 769: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 769, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 770: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 770, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 771: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 771, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 772: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 772, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 773: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 773, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 774: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 774, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 011 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 000 fail ^ test 775: *** FAIL *************************** 4 steps failed SLOT AAA LETTER HKJ SIDE 211 DIRECTION III this fail I all fails I was hi 11 rising ^^ falling vv was lo 000 total fails 775, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 000 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 001 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER HKJ SIDE 211 DIRECTION III all fails I was lo 000 falling vv rising ^^ was hi 11 total fails 775, total passes 0 Main menu Sat Jul 01 16:29:43 2017 test file is: tests\M719_AC.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\M719_AC.TST reading test file: tests\M719_AC.TST comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: 2 I AH2 E5-9 AC(N-1) INPUT pins: 3 I AK1 E8-1,E8-9 AC(N) INPUT pins: direction: III comment: comment: ; E8-3 HI E5-8 HI test 1: 100 comment: ; E5-8 LO test 2: 01 comment: ; E8-3 LO test 3: 11 comment: ; E5-8 HI test 4: 00 comment: end: END summary column 1: offset 0, mask 0x0100 column 2: offset 0, mask 0x0002 column 3: offset 1, mask 0x8000 direction bits (1=input) 0xFEFD 0x7FFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0100 0x0000 0x0000 0x0000 0x0000 2: 0x0100 0x8000 0x0000 0x0000 0x0000 3: 0x0102 0x8000 0x0000 0x0000 0x0000 4: 0x0100 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE II G P G I G P G UUT inputs: 3 UUT outputs: 0 pins used: 3 not used: 63 4 'test steps' 23 lines M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. *************** USE DMM AND SINGLE STEP. PINS Main menu Sat Jul 01 16:30:16 2017 test file is: tests\M719_AC.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 16:30:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 3 101 fail ^ step 4 100 test 501: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 501, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ source: ; E5-8 HI source: 00 changed: 0 step 4 100 test 502: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 502, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 503: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 503, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 504: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 504, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 505: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 505, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 506: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 506, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 00 falling v rising ^ was hi 1 1 total fails 506, total passes 0 Main menu Sat Jul 01 16:32:28 2017 test file is: tests\M719_AC.TST delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m719_ac.tst reading test file: tests\m719_ac.tst comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: 2 I AH2 E5-9 AC(N-1) INPUT pins: 3 I AK1 E8-1,E8-9 AC(N) INPUT pins: direction: III comment: comment: ; E8-3 HI E5-8 HI test 1: 100 comment: ; E5-8 LO test 2: 01 comment: ; E8-3 LO test 3: 11 comment: ; E5-8 HI test 4: 00 comment: end: END summary column 1: offset 0, mask 0x0100 column 2: offset 0, mask 0x0002 column 3: offset 1, mask 0x8000 direction bits (1=input) 0xFEFD 0x7FFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0100 0x0000 0x0000 0x0000 0x0000 2: 0x0100 0x8000 0x0000 0x0000 0x0000 3: 0x0102 0x8000 0x0000 0x0000 0x0000 4: 0x0100 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE II G P G I G P G UUT inputs: 3 UUT outputs: 0 pins used: 3 not used: 63 4 'test steps' 23 lines M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. *************** USE DMM AND SINGLE STEP. PINS Main menu Sat Jul 01 16:32:34 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 16:36:15 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test step 1 100 step 2 101 SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 3 101 fail ^ step 4 100 test 1: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 0 step 4 100 okay test 2: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 00 falling v rising ^ was hi 1 1 total fails 2, total passes 0 Main menu Sat Jul 01 16:46:01 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 16:46:03 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 1: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 00 falling v rising ^ was hi 1 1 total fails 1, total passes 0 Main menu Sat Jul 01 16:50:53 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 16:50:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 0 falling v rising ^ was hi 111 total fails 672, total passes 0 Main menu Sat Jul 01 16:52:12 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Sat Jul 01 16:52:20 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006F Main menu Sat Jul 01 16:52:21 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 16:52:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 110 fail ^ SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 1 step 2 111 fail ^ step 3 111 SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 0 step 4 110 fail ^ test 1: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 110 fail ^ SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 1 step 2 111 fail ^ step 3 111 SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 0 step 4 110 fail ^ test 2: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 1 step 2 111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 0 step 4 110 fail ^ test 3: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 4: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 4, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ source: ; E8-3 LO source: 11 changed: step 3 111 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 5: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 5, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 6: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 6, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 7: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 7, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 8: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 8, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 0 falling v rising ^ was hi 111 total fails 8, total passes 0 Main menu Sat Jul 01 16:56:03 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 16:56:36 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; E5-8 HI source: 00 changed: 0 step 4 100 test 393: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 393, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ source: ; E5-8 HI source: 00 changed: 0 step 4 100 test 394: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 394, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 395: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 395, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 396: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 396, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 00 falling v rising ^ was hi 1 1 total fails 396, total passes 0 Main menu Sat Jul 01 17:03:48 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m719_ac.tst reading test file: tests\m719_ac.tst comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: 2 I AH2 E5-9 AC(N-1) INPUT pins: 3 I AK1 E8-1,E8-9 AC(N) INPUT pins: direction: III comment: comment: ; E8-3 HI E5-8 HI test 1: 100 comment: ; E5-8 LO test 2: 01 comment: ; E8-3 LO test 3: 11 comment: ; E5-8 HI test 4: 00 comment: end: END summary column 1: offset 0, mask 0x0100 column 2: offset 0, mask 0x0002 column 3: offset 1, mask 0x8000 direction bits (1=input) 0xFEFD 0x7FFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0100 0x0000 0x0000 0x0000 0x0000 2: 0x0100 0x8000 0x0000 0x0000 0x0000 3: 0x0102 0x8000 0x0000 0x0000 0x0000 4: 0x0100 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE II G P G I G P G UUT inputs: 3 UUT outputs: 0 pins used: 3 not used: 63 4 'test steps' 23 lines M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. *************** USE DMM AND SINGLE STEP. PINS Main menu Sat Jul 01 17:03:56 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:03:59 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ source: ; E8-3 LO source: 11 changed: step 3 111 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 1: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 1, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ source: ; E8-3 LO source: 11 changed: step 3 111 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 2: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 2, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 3: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 3, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 111 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 110 fail ^ test 4: *** FAIL *************************** 3 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 111 rising ^ falling v was lo 0 total fails 4, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 110 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 0 falling v rising ^ was hi 111 total fails 4, total passes 0 Main menu Sat Jul 01 17:14:53 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:14:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 1390 Main menu Sat Jul 01 17:15:35 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:15:37 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100 step 2 101 step 3 111 step 4 100 test 570: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 570 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 1 100 step 2 101 step 3 111 step 4 100 test 571: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 571 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 00 changed: 00 step 4 100 test 572: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 572 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 00 changed: 00 step 4 100 test 573: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 573 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 00 changed: 00 step 4 100 test 574: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 574 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 00 changed: 00 step 4 100 test 575: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 575 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 575 Main menu Sat Jul 01 17:20:54 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:20:56 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 1389: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1389 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 1390: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1390 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 1390 Main menu Sat Jul 01 17:21:59 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:22:01 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 3: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 3 Main menu Sat Jul 01 17:25:34 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:26:16 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 00 changed: 00 step 4 100 test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 3: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 3 Main menu Sat Jul 01 17:30:18 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:30:20 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit step 4 100 test 364: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 364, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ source: ; E5-8 HI source: 00 changed: 0 step 4 100 test 365: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 365, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ source: ; E5-8 HI source: 00 changed: 0 step 4 100 test 366: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 366, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 00 falling v rising ^ was hi 1 1 total fails 366, total passes 0 Main menu Sat Jul 01 17:31:39 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 17:31:41 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ source: ; E5-8 HI source: 00 changed: 0 step 4 100 test 432: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 432, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; E5-8 LO source: 01 changed: 1 step 2 101 SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: step 3 101 fail ^ space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 0 step 4 100 okay test 433: *** FAIL *************************** 1 steps failed SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail I all fails I was hi 1 1 rising ^ falling v was lo 00 total fails 433, total passes 0 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails I was lo 00 falling v rising ^ was hi 1 1 total fails 433, total passes 0 Main menu Sat Jul 01 18:01:32 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:01:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 00 changed: 00 step 4 100 test 1415: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1415 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 1416: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1416 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 1417: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1417 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 1417 Main menu Sat Jul 01 18:13:30 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 01 18:13:35 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:13:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: 00 step 4 100 okay test 572: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 572 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 573: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 573 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 573 Main menu Sat Jul 01 18:14:26 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:14:28 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 HI source: 00 changed: 00 step 4 100 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 1 Main menu Sat Jul 01 18:15:13 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sat Jul 01 18:18:09 2017 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m719_ac.tst reading test file: tests\m719_ac.tst comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: 2 I AH2 E5-9 AC(N-1) INPUT pins: 3 I AK1 E8-1,E8-9 AC(N) INPUT (E8-3 INVERTED OUTPUT) pins: direction: III comment: comment: ; E8-3 HI E5-8 HI test 1: 100 comment: ; E5-8 LO test 2: 01 comment: ; E8-3 LO test 3: 11 comment: ; E5-8 HI test 4: 10 comment: end: END summary column 1: offset 0, mask 0x0100 column 2: offset 0, mask 0x0002 column 3: offset 1, mask 0x8000 direction bits (1=input) 0xFEFD 0x7FFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0100 0x0000 0x0000 0x0000 0x0000 2: 0x0100 0x8000 0x0000 0x0000 0x0000 3: 0x0102 0x8000 0x0000 0x0000 0x0000 4: 0x0102 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE II G P G I G P G UUT inputs: 3 UUT outputs: 0 pins used: 3 not used: 63 4 'test steps' 23 lines M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. *************** USE DMM AND SINGLE STEP. PINS Main menu Sat Jul 01 18:18:13 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:18:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 10 changed: 0 step 4 110 test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling v was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E8-3 HI E5-8 HI source: 100 changed: 0 step 1 100 source: ; E5-8 LO source: 01 changed: 1 step 2 101 source: ; E8-3 LO source: 11 changed: 1 step 3 111 source: ; E5-8 HI source: 10 changed: 0 step 4 110 test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 2 Main menu Sat Jul 01 18:19:15 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 01 18:19:18 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:19:21 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E8-3 HI E5-8 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling rising was hi 1 total fails 0, total passes 0 Main menu Sat Jul 01 18:22:51 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m79_ac.tst could not open test file. valid test files are: reverting back to test file: tests\m719_ac.tst Main menu Sat Jul 01 18:22:57 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Sat Jul 01 18:23:08 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m719_ac.tst reading test file: tests\m719_ac.tst comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: 2 I AH2 E5-9 AC(N-1) INPUT (E5-8 INVERTED OUTPUT) pins: 3 I AK1 E8-1,E8-9 AC(N) INPUT (E8-3 INVERTED OUTPUT WHEN AJ1 E8-2 IS HI) pins: direction: III comment: comment: ; E5-8 HI E8-3 HI test 1: 100 comment: ; E8-3 LO test 2: 01 comment: ; E5-8 LO test 3: 11 comment: ; E8-3 HI test 4: 10 comment: end: END summary column 1: offset 0, mask 0x0100 column 2: offset 0, mask 0x0002 column 3: offset 1, mask 0x8000 direction bits (1=input) 0xFEFD 0x7FFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0100 0x0000 0x0000 0x0000 0x0000 2: 0x0100 0x8000 0x0000 0x0000 0x0000 3: 0x0102 0x8000 0x0000 0x0000 0x0000 4: 0x0102 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE II G P G I G P G UUT inputs: 3 UUT outputs: 0 pins used: 3 not used: 63 4 'test steps' 23 lines M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. *************** USE DMM AND SINGLE STEP. PINS Main menu Sat Jul 01 18:23:14 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:23:19 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling v was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 3: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 4: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 4 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 5: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 5 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 6: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 6 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 6 Main menu Sat Jul 01 18:25:30 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:25:34 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 609: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 609 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 610: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 610 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 611: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 611 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 611 Main menu Sat Jul 01 18:27:07 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:27:09 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling v was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 2 Main menu Sat Jul 01 18:27:58 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:28:00 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 source: ; E8-3 LO source: 01 changed: 1 step 2 101 source: ; E5-8 LO source: 11 changed: 1 step 3 111 source: ; E8-3 HI source: 10 changed: 0 step 4 110 test 457: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 457 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 457 Main menu Sat Jul 01 18:28:45 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:28:50 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling v was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 2 Main menu Sat Jul 01 18:29:41 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit ***************************** UUT power is OFF * ***************************** Main menu Sat Jul 01 18:29:43 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x0063 Main menu Sat Jul 01 18:29:43 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:29:46 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling v was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 2 Main menu Sat Jul 01 18:30:40 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:30:42 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling v was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 3: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 3 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 4: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 4 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 5: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 5 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 5 Main menu Sat Jul 01 18:35:27 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\74h00.tst reading test file: tests\74h00.tst comment: 74H00 QUAD 2-INPUT NAND comment: comment: REMOVE JUMPERS: comment: AA1 comment: AC1 comment: AA2 comment: AC2 comment: AH2 comment: AT2 comment: CONNECT: comment: AA1 tester to AA2 UUT comment: AC1 tester to AC2 UUT comment: AH2 UUT to GROUND comment: AT2 UUT to +5V comment: comment: pins: PINS pins: 1 I AA1 E1-1 74H00 PIN 1 1A pins: 2 I AB2 E1-2 74H00 PIN 2 1B pins: 3 O AC1 E1-3 74H00 PIN 3 1Y = 1A NAND 1B pins: 4 I AD2 E1-4 74H00 PIN 4 2A pins: 5 I AE2 E1-5 74H00 PIN 5 2B pins: 6 O AF2 E1-6 74H00 PIN 6 2Y = 2A NAND 2B pins: 7 I AM2 E1-11 74H00 PIN 9 3A pins: 8 I AN2 E1-12 74H00 PIN 10 3B pins: 9 O AL2 E1-10 74H00 PIN 8 3Y = 3A NAND 3B pins: 10 I AR2 E1-14 74H00 PIN 12 4A pins: 11 I AS2 E1-15 74H00 PIN 13 4B pins: 12 O AP2 E1-13 74H00 PIN 11 4Y pins: 13 I AH2 E1-7 74H00 PIN 7 GROUND pins: 14 I AJ2 E1-8 (UNUSED PIN OF 16-PIN SOCKET) pins: 15 I AK2 E1-9 (UNUSED PIN OF 16-PIN SOCKET) pins: 16 I AT2 E1-16 74H00 PIN 14 VCC pins: direction: IIOIIOIIOIIOIIII comment: comment: ; START WITH ALL INPUTS ZERO test 1: 001001001001XXXX comment: comment: ; ALL INPUTS ONES test 2: 110110110110 comment: comment: ; WITH ALL OTHER INPUTS HI, GRAY CODE EACH GATE test 3: 011 test 4: 001 test 5: 101 test 6: 110 test 7: 011 test 8: 001 test 9: 101 test 10: 110 test 11: 011 test 12: 001 test 13: 101 test 14: 110 test 15: 011 test 16: 001 test 17: 101 test 18: 110 comment: comment: ; ALL INPUTS LO test 19: 001001001001 comment: comment: ; WITH ALL OTHER INPUTS LO, GRAY CODE EACH GATE test 20: 011 test 21: 110 test 22: 101 test 23: 001 test 24: 011 test 25: 110 test 26: 101 test 27: 001 test 28: 011 test 29: 110 test 30: 101 test 31: 001 test 32: 011 test 33: 110 test 34: 101 test 35: 001 end: END summary column 1: offset 0, mask 0x8000 column 2: offset 0, mask 0x0040 column 3: offset 0, mask 0x2000 column 4: offset 0, mask 0x0010 column 5: offset 0, mask 0x0008 column 6: offset 0, mask 0x0004 column 7: offset 1, mask 0x0004 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0020 column 11: offset 1, mask 0x0040 column 12: offset 1, mask 0x0010 column 13: offset 0, mask 0x0002 column 14: offset 0, mask 0x0001 column 15: offset 1, mask 0x0001 column 16: offset 1, mask 0x0080 direction bits (1=input) 0x7FA4 0xFF12 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 2: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 3: 0x2058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 4: 0x2018 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 5: 0xA018 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 6: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 7: 0x804C 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 8: 0x8044 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 9: 0x8054 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 10: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 11: 0x8058 0x006A 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 12: 0x8058 0x0062 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 13: 0x8058 0x0066 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 14: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 15: 0x8058 0x005C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 16: 0x8058 0x001C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 17: 0x8058 0x003C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 18: 0x8058 0x006C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 19: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 20: 0x2044 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 21: 0x8044 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 22: 0xA004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 23: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 24: 0x200C 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 25: 0x2018 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 26: 0x2014 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 27: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 28: 0x2004 0x001A 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 29: 0x2004 0x001C 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 30: 0x2004 0x0016 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 31: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 32: 0x2004 0x0052 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 33: 0x2004 0x0062 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 34: 0x2004 0x0032 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 35: 0x2004 0x0012 0x0000 0x0000 0x0000 0x0003 0x0081 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE I O G PIGIIOIIIOIIOIII G P G UUT inputs: 12 UUT outputs: 4 pins used: 16 not used: 50 35 'test steps' 81 lines 74H00 QUAD 2-INPUT NAND REMOVE JUMPERS: AA1 AC1 AA2 AC2 AH2 AT2 CONNECT: AA1 tester to AA2 UUT AC1 tester to AC2 UUT AH2 UUT to GROUND AT2 UUT to +5V PINS Main menu Sat Jul 01 18:36:27 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:36:28 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 91 Main menu Sat Jul 01 18:36:32 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:37:38 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 79 Main menu Sat Jul 01 18:37:39 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:40:32 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 98 Main menu Sat Jul 01 18:40:35 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:41:23 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 67 Main menu Sat Jul 01 18:41:24 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:42:07 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAAAAAAAAAAAAAAA LETTER ABCDEFMNLRSPHJKT SIDE 1212222222222222 DIRECTION IIOIIOIIOIIOIIII all fails was lo 0000000000000000 falling vvvvvvvvvvvv rising ^^^^^^^^^^^^ was hi 111111111111 total fails 0, total passes 65 Main menu Sat Jul 01 18:42:09 2017 test file is: tests\74h00.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m719_ac.tst reading test file: tests\m719_ac.tst comment: M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) comment: comment: ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. comment: comment: *************** USE DMM AND SINGLE STEP. comment: pins: PINS pins: 1 I AJ1 E8-2+++ IOT LOAD CONTROL 2H pins: 2 I AH2 E5-9 AC(N-1) INPUT (E5-8 INVERTED OUTPUT) pins: 3 I AK1 E8-1,E8-9 AC(N) INPUT (E8-3 INVERTED OUTPUT WHEN AJ1 E8-2 IS HI) pins: direction: III comment: comment: ; E5-8 HI E8-3 HI test 1: 100 comment: ; E8-3 LO test 2: 01 comment: ; E5-8 LO test 3: 11 comment: ; E8-3 HI test 4: 10 comment: end: END summary column 1: offset 0, mask 0x0100 column 2: offset 0, mask 0x0002 column 3: offset 1, mask 0x8000 direction bits (1=input) 0xFEFD 0x7FFF 0xFFFB 0xFFFF 0xF0FF pullup bits (1=pullup) 0x0000 0x0000 0x0000 0x0000 0x0000 test step out_data dont care 1: 0x0100 0x0000 0x0000 0x0000 0x0000 2: 0x0100 0x8000 0x0000 0x0000 0x0000 3: 0x0102 0x8000 0x0000 0x0000 0x0000 4: 0x0102 0x0000 0x0000 0x0000 0x0000 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE II G P G I G P G UUT inputs: 3 UUT outputs: 0 pins used: 3 not used: 63 4 'test steps' 23 lines M719 KW12 CLOCK INPUT SYNCHRONIZER PCB REV A, SCHEMATIC REV (BLANK) ****************EXTREMELY LIMITED, ONLY CHECKS THE TWO AC INPUTS. *************** USE DMM AND SINGLE STEP. PINS Main menu Sat Jul 01 18:43:35 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:43:39 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test scope (run, no print) ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp ppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp pppppppp space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn on comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit comment_flag is 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 641: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 641 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 642: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 642 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 642 Main menu Sat Jul 01 18:44:33 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit UUT power is okay Sat Jul 01 18:44:40 2017 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn on comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test comment_flag is 1 space single step O run once (one test, all steps) F run, stop on fail G go (run tests N run, stop on fail, no print S scope (run, no print) C turn off comment printout + increase speed (less delay) - decrease speed (more delay)(slower) Q quit test SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 1: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling v was lo 00 total fails 0, total passes 1 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 LO source: 01 changed: 1 step 2 101 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E5-8 LO source: 11 changed: 1 step 3 111 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: ; E8-3 HI source: 10 changed: 0 step 4 110 okay test 2: pass SLOT AAA LETTER JHK SIDE 121 DIRECTION III this fail all fails was hi 111 rising ^^ falling vv was lo 00 total fails 0, total passes 2 space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III source: source: ; E5-8 HI E8-3 HI source: 100 changed: 0 step 1 100 okay space single step B go back one step T toggle (previous and current step) O run one test (all steps) G go F go, stop on failure N run, stop on fail, no print S scope (run, no print) P show pins M mapping R show registers D diagnostics C turn off comment printout A failure mode analysis + increase speed (less delay) - decrease speed (more delay)(slower) Q quit SLOT AAA LETTER JHK SIDE 121 DIRECTION III all fails was lo 00 falling vv rising ^^ was hi 111 total fails 0, total passes 2 Main menu Sat Jul 01 18:45:31 2017 test file is: tests\m719_ac.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting