M222 PCB REV B SCHEMATIC REV A LINC TAPE REGISTERS TERMINOLOGY- SIGNALS REFER TO PDP12 MAINT VOL4 M222 SCHEMATIC. BUT... DEC USES AND-NOR GATES TO ROUTE THE ADDER A AND B INPUTS, SO... DEC RENAMED THE ADDER TO NEGATIVE LOGIC TERMS (I.E. A-N + B-N + C-N -> SUM-N, C1-N). (NOT THE 7482 DATASHEET NAMES OF A + B + C -> SUM, C1). SO, WITH ALL 'AND ENABLES' LOW, THE AND-NOR OUTPUTS = HIGH. WITH C-L HIGH, THE ADDER OUTPUT IS SUM-N=1, C1-N=1; THE INVERTED ADDER OUTPUT IS LOW (TAPE BUS). AND THERE IS NO CARRY (C1-N IS HI). THE TWO ADDERS, TWO REGISTER BITS, ETC ARE LABELED BIT 2 (EVEN, MSB) AND BIT 3 (ODD, LSB). THE ADDERS ARE REFERRED TO AS 'ADDER2' (MSB) AND 'ADDER3' (LSB). POWER PINS: +5v AA2, BA2 GROUND AC2, AT1, BC2, BT1 (ALL PINS ARE USED). PINS 1 I BA1 CARRY IN-N, (TO E9-5 7482 C0) C-N TO ADDER2 2 I AL2 AND-NOR ENABLE: TAC TAC3 TO PIN BB2 (TO ADDER3) TAC2 TO PIN AN2 (TO ADDER2) 3 I AP1 AND-NOR ENABLE: TMA SETUP (TMAS)3 TO PIN BB2 (TO ADDER3), (TMAS)3 TO PIN AN2 (TO ADDER2) 4 I AS2 AND-NOR ENABLE: TMA TMA3 TO PIN BB2 (TO ADDER3), TMA2 TO PIN AN2 (TO ADDER2) 5 I AL1 AND-NOR ENABLE: PIN AF2 TO PIN BB2 (TO ADDER3), PIN AM1 TO PIN AN2 (TO ADDER2) 6 I AF2 AND-NOR INPUT (AL1 ENABLES) TO PIN BB2 (TO ADDER3). 7 I AM1 AND-NOR INPUT (AL1 ENABLES) TO PIN AN2 (TO ADDER2) 8 I AD2 AND-NOR ENABLE: RWB RWB3 TO PIN BB2 (TO ADDER3), RWB2 TO PIN AN2 (TO ADDER2) 9 I AE2 AND-NOR ENABLE: PIN AE1 TO PIN BB2 (TO ADDER3), PIN AM2 TO PIN AN2 (TO ADDER2) 10 I AE1 AND-NOR INPUT (AE2 ENABLES) TO PIN BB2 (TO ADDER3). 11 I AM2 AND-NOR INPUT (AE2 ENABLES) TO PIN AN2 (TO ADDER2) 12 I AC1 AND-NOR INPUT, AND WITH PIN AB2 TO PIN BB2 (TO ADDER3) 13 I AB2 AND-NOR INPUT, AND WITH PIN AC1 TO PIN BB2 (TO ADDER3) 14 I AF1 AND-NOR INPUT (AND WITH ITSELF) TO PIN BB2 (TO ADDER3) 15 I AR2 AND-NOR INPUT, AND WITH PIN AS1 TO PIN AN2 (TO ADDER2) 16 I AS1 AND-NOR INPUT, AND WITH PIN AR2 TO PIN AN2 (TO ADDER2) 17 I AP2 AND-NOR INPUT (AND WITH ITSELF) TO PIN AN2 (TO ADDER2) 18 I BK1 AND-NOR ENABLE: TB3 TO PIN BB1 (TO ADDER3), TB2 TO PIN BN1 (TO ADDER2) 19 I BL1 AND-NOR ENABLE: PIN BE1 TO PIN BB1 (TO ADDER3), PIN BM1 TO PIN BN1 (TO ADDER2) 20 I BE1 AND-NOR INPUT (BL1 ENABLES) TO PIN BB1 (TO ADDER3). 21 I BM1 AND-NOR INPUT (BL1 ENABLES) TO PIN BN1 (TO ADDER2) 22 I BF1 AND-NOR ENABLE: PIN BH1 TO PIN BB1 (TO ADDER3), PIN BR1 TO PIN BN1 (TO ADDER2) 23 I BH1 AND-NOR INPUT (BF1 ENABLES): TO PIN BB1 (TO ADDER3), 24 I BR1 AND-NOR INPUT (BF1 ENABLES): TO PIN BN1 (TO ADDER2) 25 I BS1 AND-NOR ENABLE: PIN BC1 TO PIN BB1 (TO ADDER3), PIN BJ2 TO PIN BN1 (TO ADDER2) 26 I BC1 AND-NOR INPUT (BS1 ENABLES): TO PIN BB1 (TO ADDER3), 27 I BJ2 AND-NOR INPUT (BS1 ENABLES): TO PIN BN1 (TO ADDER2) 28 I BL2 AND-NOR ENABLE: PIN BJ1 TO PIN BB1 (TO ADDER3), PIN BK2 TO PIN BN1 (TO ADDER2) 29 I BJ1 AND-NOR INPUT (BL2 ENABLES): TO PIN BB1 (TO ADDER3), 30 I BK2 AND-NOR INPUT (BL2 ENABLES): TO PIN BN1 (TO ADDER2) 31 I BU1 AND-NOR ENABLE: PIN BH2 TO PIN BB1 (TO ADDER3), PIN BP2 TO PIN BN1 (TO ADDER2) 32 I BH2 AND-NOR INPUT (BU1 ENABLES): TO PIN BB1 (TO ADDER3), 33 I BP2 AND-NOR INPUT (BU1 ENABLES): TO PIN BN1 (TO ADDER2) 34 I BN2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 35 I BM2 AND-NOR INPUT (AND WITH BM2): TO PIN BN1 (TO ADDER2) 36 O BB2 AND-NOR OUTPUT, (DRIVES E9-2 7482 A1) TO ADDER3 INPUT 37 O BB1 AND-NOR OUTPUT, (DRIVES E9-3 7482 B1) TO ADDER3 INPUT 38 O BN1 AND-NOR OUTPUT, (DRIVES E9-14 7482 A2) TO ADDER2 INPUT 39 O AN2 AND-NOR OUTPUT, (DRIVES E9-13 7482 B2) TO ADDER2 INPUT 40 O AV2 CARRY OUT-N (E9-10 7482 C2) 41 O BV2 TAPE BUS 2 OUTPUT (INVERTED ADDER2 SUM-N (E9-12 7482 SUM2) 42 O BR2 TAPE BUS 3 OUTPUT (INVERTED ADDER3 SUM-N (E9-1 7482 SUM1) 43 I AK1 LOAD TMA SETUP (FROM TAPE BUS) (RISING EDGE CLOCK) 44 O AR1 TMA SETUP 2 45 O AH1 TMA SETUP 3 46 I AU2 LOAD TMA (FROM TAPE BUS) (RISING EDGE CLOCK) 47 O AT2 TMA 2 48 O AD1 TMA 3 49 I AJ1 LOAD TBN (FROM TAPE BUS) (RISING EDGE CLOCK) 50 O AU1 TBN 2 51 O AK2 TBN 3 52 I AA1 LOAD TAC (FROM TAPE BUS) (RISING EDGE CLOCK) 53 O AN1 TAC 2 54 O AJ2 TAC 2-N 55 O AH2 TAC 3 56 O AB1 TAC 3-N 57 I BT2 LOAD TB (FROM TAPE BUS) (RISING EDGE CLOCK) 58 O BP1 TB 2 59 O BD1 TB 3 60 I BF2 LOAD RWB (FROM TB) (JAMS CLEAR,SET) 61 I BS2 PHASE (SELECTS POLARITY OF RWB OUT, 0 -> INVERTED) 62 I AV1 RWB IN (SHIFTED INTO RWB 3) 63 I BE2 SHIFT RWB (SHIFTS PIN AV1 INTO RWB 3, SHIFTS RWB3 TO RWB2) (RISING CLOCK) 64 O BV1 RWB OUT (IF PHASE=1, =RWB 2; IF PHASE=0; =RWB 2-N) 65 O BD2 RWB 3 66 O BU2 +3.5V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOOOIOOIOOIOOIOOOOIOOIIIIOOO ; all registers are unknown ; turn on C0, PHASE ; with no ENABLES, BUS2,BUS3 is 11, C2 is 1 1000000000000000000000000000000000011111000XX0XX0XX0XXXX0XX0110XX1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; set all registers LOW ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; load TMA SETUP from tape bus (00) 100 0 ; load TMA from tape bus (00) 100 0 ; load TBN from tape bus (00) 100 0 ; load TAC from tape bus (00) 10101 0 ; load TB from tape bus (00) 100 0 ; load RWB from TB (JAMS CLEAR AND PRESET) 1 00 0 ; (no change) 100000000000000000000000000000000001111100000000000001010000110001 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; set all registers HIGH ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; load TMA SETUP from tape bus (11) 111 0 ; load TMA from tape bus (11) 111 0 ; load TBN from tape bus (11) 111 0 ; load TAC from tape bus (11) 11010 0 ; load TB from tape bus (11) 111 0 ; load RWB from TB (JAMS CLEAR AND PRESET) 1 11 0 ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; (no change) 100000000000000000000000000000000001111100011011011010100110110111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; will all registers high, walk a 0 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; walk a 0, TMA SETUP 2 ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TMA SETUP from tape bus (01) 101 0 ; restore TMA SETUP 2 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; load TMA SETUP from tape bus (11) 111 0 ; walk a 0, TMA SETUP 3 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; load TMA SETUP from tape bus (10) 110 0 ; restore TMA SETUP 3 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TMA SETUP from tape bus (11) 111 0 ; walk a 0, TMA 2 ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TMA from tape bus (01) 101 0 ; restore TMA 2 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; load TMA from tape bus (11) 111 0 ; walk a 0, TMA 3 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; load TMA from tape bus (10) 110 0 ; restore TMA 3 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TMA from tape bus (11) 111 0 ; walk a 0, TBN 2 ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TBN from tape bus (01) 101 0 ; restore TBN 2 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; load TBN from tape bus (11) 111 0 ; walk a 0, TBN 3 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; load TBN from tape bus (10) 110 0 ; restore TBN 3 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TBN from tape bus (11) 111 0 ; walk a 0, TAC 2 ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TAC from tape bus (01) 10110 0 ; restore TAC 2 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; load TAC from tape bus (11) 11010 0 ; walk a 0, TAC 3 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; load TAC from tape bus (10) 11001 0 ; restore TAC 3 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TAC from tape bus (11) 11010 0 ; walk a 0, TB 2 ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TB from tape bus (01) 101 0 ; restore TB 2 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; load TB from tape bus (11) 111 0 ; walk a 0, TB 3 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; load TB from tape bus (10) 110 0 ; restore TB 3 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TB from tape bus (11) 111 0 ; walk a 0, RWB 2 ; clear pin AP2 which sets pin AN2 and clears pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TB from tape bus (01) 101 0 ; load RWB from TB (JAMS CLEAR AND PRESET) 1 01 0 ; restore TB 2 and RWB 2 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; load TB from tape bus (11) 111 0 ; load RWB from TB (JAMS CLEAR AND PRESET) 1 11 0 ; walk a 0, RWB 3 ; set pin AP2 which clears pin AN2 and sets pin BV2 TAPE BUS 2 OUTPUT 1 0 1 ; clear pin AF1 which sets pin BB2 and clears pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; load TB from tape bus (10) 110 0 ; load RWB from TB (JAMS CLEAR AND PRESET) 1 10 0 ; restore TB 3 and RWB 3 ; set pin AF1 which clears pin BB2 and sets pin BR2 TAPE BUS 3 OUTPUT 1 0 1 ; load TB from tape bus (11) 111 0 ; load RWB from TB (JAMS CLEAR AND PRESET) 1 11 0 ; clear pin AF1 (AND with itself) to set pin BB2 (AND-NOR output) and clear pin BR2 TAPE BUS 3 OUTPUT 0 1 0 ; clear pin AP2 (AND with itself) to set pin AN2 (AND-NOR output) and clear pin BV2 TAPE BUS 2 OUTPUT 0 1 0 ; (no change) 100000000000000000000000000000000001111100011011011010100110110111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;********************* need to walk a one ********************** ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; test AND-NOR logic ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; (all registers are HIGH) ; set all pins HIGH except ENABLES ; set pin AF2 HIGH 1 ; set pin AM1 HIGH 1 ; set pin AE1 HIGH 1 ; set pin AM2 HIGH 1 ; set pin AB2 HIGH 1 ; set pin AS1 HIGH 1 ; set pin BE1 HIGH 1 ; set pin BM1 HIGH 1 ; set pin BH1 HIGH 1 ; set pin BR1 HIGH 1 ; set pin BC1 HIGH 1 ; set pin BJ2 HIGH 1 ; set pin BJ1 HIGH 1 ; set pin BK2 HIGH 1 ; set pin BH2 HIGH 1 ; set pin BP2 HIGH 1 ; set pin BN2 HIGH 1 ; toggle each ENABLE ; set pin AL2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 0 0 11 0 1 1 00 ; set pin AP1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 0 0 11 0 1 1 00 ; set pin AS2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 0 0 11 0 1 1 00 ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 0 0 11 0 1 1 00 ; set pin AL1 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 0 0 11 0 1 1 00 ; set pin AE2 to clear pin BB2 and pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 0 0 11 0 1 1 00 ; set pin AC1 to clear pin BB2 and set TAPE BUS 3 OUTPUT 1 0 1 0 1 0 ; set pin AF1 to clear pin BB2 and set TAPE BUS 3 OUTPUT 1 0 1 0 1 0 ; set pin AR2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT 1 0 1 0 1 0 ; set pin AP2 to clear pin AN2 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT 1 0 1 0 1 0 ; set pin BK1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 00 11 0 11 00 ; set pin BL1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 00 11 0 11 00 ; set pin BF1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 00 11 0 11 00 ; set pin BS1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 00 11 0 11 00 ; set pin BL2 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 00 11 0 11 00 ; set pin BU1 to clear pin BB1 and pin BN1 AND-NOR OUTPUTS and set TAPE BUS 2 OUTPUT and TAPE BUS 3 OUTPUT 1 00 11 0 11 00 ; set pin BM2 to clear pin BB1 and TAPE BUS 3 OUTPUT 1 0 1 0 1 0 ; no change 100000000000000000000000000000000001111100011011011010100110110111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; test shifting the RWB ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; shift in 0, expect 10 0 110 0 ; toggle phase should toggle RWB 2 0 0 1 1 ; shift in 0, expect 00 0 100 0 ; toggle phase should toggle RWB 2 0 1 1 0 ; shift in 0, expect 00 0 100 0 ; shift in 1, expect 01 1 101 0 ; shift in 1, expect 11 1 111 0 ; shift in 1, expect 11 1 111 0 ; shift in 0, expect 10 0 110 0 ; shift in 1, expect 01 1 101 0 ; shift in 0, expect 10 0 110 0 ; shift in 1, expect 01 1 101 0 ; shift in 1, expect 11 1 111 0 ; no change 100000000000000000000000000000000001111100011011011010100110110111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; needs work (more adder tests, more register tests) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; END