tester- PDP8 card tester via printer port version 0.91 November 27, 2015 mapping[] is verified Main menu Sun Nov 29 15:08:00 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102 could not open test file. valid test files are: reverting back to test file: Main menu Sun Nov 29 15:08:26 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Sun Nov 29 15:08:28 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\ could not open test file. valid test files are: reverting back to test file: Main menu Sun Nov 29 15:08:30 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit key is 0x006D Main menu Sun Nov 29 15:08:32 2015 test file is: delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit Enter test file name? trying to open test file: tests\m7102_2.tst reading test file: tests\m7102_2.tst comment: M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) comment: comment: PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. comment: (See PART 1 for Posibus driving Omnibus. comment: comment: (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). comment: comment: Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): comment: BK2 Omnibus DATA00 (bidirectional, input + open collector output) comment: BL2 Omnibus DATA01 (bidirectional, input + open collector output) comment: BM2 Omnibus DATA02 (bidirectional, input + open collector output) comment: pins: PINS pins: 1 I AN1 E6-9 INPUT 1 pins: 2 P BF2 E13-8 OUTPUT A-N (7416 OPEN COLLECTOR OUTPUT) pins: 3 I AP1 E6-6 INPUT 2 pins: 4 P BH2 E13-7 OUTPUT 2-N (7416 OPEN COLLECTOR OUTPUT) pins: 5 I AR1 E6-5 INPUT 3 pins: 6 P BJ2 E13-6 OUTPUT 3-N (7416 OPEN COLLECTOR OUTPUT) pins: 7 I AK2 E9-11 INPUT 4 pins: 8 O AN2 E9-13 OUTPUT 4 (384 OUTPUT) pins: 9 I AL2 E9-9 INPUT 5 pins: 10 O AM2 E9-14 OUTPUT 5 (384 OUTPUT) pins: 11 I AP2 E9-6 INPUT 6 pins: 12 O AT2 E9-2 OUTPUT 6 (384 OUTPUT) pins: 13 O BB1 E11-6 OUTPUT 6-N (74H04 OUTPUT) pins: 14 I AR2 E9-5 INPUT 7 pins: 15 O AS2 E9-3 OUTPUT 7 (384 OUTPUT) pins: 16 O BA1 E11-10 OUTPUT 7-N (74H04 OUTPUT) pins: 17 I BD1 E11-1 INPUT 8 pins: 18 P BV2 E13-12 OUTPUT 8 (7416 OPEN COLLECTOR OUTPUT) pins: 19 O BC1 E11-2 OUTPUT 8-N (74H04 OUTPUT) pins: 20 I AV1 E11-13 INPUT 9 pins: 21 O AU1 E11-12 OUTPUT 9-N (74H04 OUTPUT) pins: 22 I BL1 E12-4 INPUT 10A pins: 23 I BK1 E12-5 INPUT 10B pins: 24 O BM1 E12-3 OUTPUT 10 = INPUT 10A NOR INPUT 10B (380 OUTPUT) pins: 25 I BJ1 E12-9 INPUT 11A pins: 26 I BH1 E12-10 INPUT 11B pins: 27 O BF1 E12-14 OUTPUT 11 = INPUT 11A NOR INPUT 11B (M380 OUTPUT) pins: 28 I BR1 E15-12 INPUT 12A pins: 29 I BS1 E15-11 INPUT 12B pins: 30 O BP1 E15-? OUTPUT 12 = INPUT 12A NAND INPUT 12B (8881 OPEN COLLECTOR OUTPUT WITH 3.3K PULLUP) pins: 31 I BN2 E10-6,7 INPUT 13 pins: 32 P AD1 E1-3 OUTPUT 13 (75452 OPEN COLLECTOR OUTPUT) pins: 33 I BP2 E14-11,12 INPUT 14 pins: 34 P AE1 E2-3 OUTPUT 14 (75452 OPEN COLLECTOR OUTPUT) pins: 35 I BR2 E14-9,10 INPUT 15 pins: 36 P AD2 E5-5 OUTPUT 15 (75452 OPEN COLLECTOR OUTPUT) pins: 37 I BS2 E14-6,7 INPUT 16 pins: 38 P AE2 E4-5 OUTPUT 16 (75452 OPEN COLLECTOR OUTPUT) pins: 39 I BU1 E14-4,5 INPUT 17 pins: 40 P AB1 E4-5 OUTPUT 17 (75452 OPEN COLLECTOR OUTPUT) pins: 41 O BU2 E14-3 OUTPUT 17-N (380 OUTPUT) pins: 42 I BV1 E2-6,7 INPUT 18 pins: 43 P AA1 E2-5 OUTPUT 18-N (75452 OPEN COLLECTOR OUTPUT) pins: 44 I BD2 E11-3 OMNIBUS DATA TO I/O DATA-N (LOW ALSO DISABLES BAC <> OMNIBUS) pins: 45 O BE1 E11-4 OMNIBUS DATA TO I/O DATA (74H04 OUTPUT) pins: 46 I BE2 E12-12 INPUT OUT-N (L -> BAC TO OMNIBUS, H -> OMNIBUS TO BAC) pins: 47 I AK1 E3-6 INPUT BAC0 (DATA FROM I/O BUS) pins: 48 I AL1 E3-5 INPUT BAC1 (DATA FROM I/O BUS) pins: 49 I AM1 E6-11 INPUT BAC2 (DATA FROM I/O BUS) pins: 50 I BK2 E15-1 INPUT DATA00-N (OMNIBUS DATA00) (8881 OPEN COLLECTOR OUTPUT) pins: 51 I BL2 E15-4 INPUT DATA01-N (OMNIBUS DATA01) (8881 OPEN COLLECTOR OUTPUT) pins: 52 I BM2 E15-10 INPUT DATA02-N (OMNIBUS DATA02) (8881 OPEN COLLECTOR OUTPUT) pins: 53 P AF1 E4-3 OUTPUT I/O BUS ACIN0-N (75452 OPEN COLLECTOR OUTPUT) pins: 54 P AH1 E5-3 OUTPUT I/O BUS ACIN1-N (75452 OPEN COLLECTOR OUTPUT) pins: 55 P AJ1 E8-5 OUTPUT I/O BUS ACIN2-N (75452 OPEN COLLECTOR OUTPUT) pins: 56 P AF2 E7-5 OUTPUT I/O BUS DATA0-N (75452 OPEN COLLECTOR OUTPUT) pins: 57 P AH2 E3-3 OUTPUT I/O BUS DATA1-N (75452 OPEN COLLECTOR OUTPUT) pins: 58 P AJ2 E7-3 OUTPUT I/O BUS DATA2-N (75452 OPEN COLLECTOR OUTPUT) pins: direction: IPIPIPIOIOIOOIOOIPOIOIIOIIOIIOIPIPIPIPIPOIPIOIIIIIIIPPPPPP test 1: 0101010000001001001010010010010000000000101010000111111111 comment: comment: ; INPUT 1 -> OUTPUT 1-N test 2: 10 test 3: 01 comment: comment: ; INPUT 2 -> OUTPUT 2-N test 4: 10 test 5: 01 comment: comment: ; INPUT 3 -> OUTPUT 3-N test 6: 10 test 7: 01 comment: comment: ; INPUT 4 -> OUTPUT 4 test 8: 11 test 9: 00 comment: comment: ; INPUT 5 -> OUTPUT 5 test 10: 11 test 11: 00 comment: comment: ; INPUT 6 -> OUTPUT 6, OUTPUT 6-N test 12: 110 test 13: 001 comment: comment: ; INPUT 7 -> OUTPUT 7, OUTPUT 7-N test 14: 110 test 15: 001 comment: comment: ; INPUT 8 -> OUTPUT 8, OUTPUT 8-N test 16: 110 test 17: 001 comment: comment: ; INPUT 9 -> OOUTPUT 9-N test 18: 10 test 19: 01 comment: comment: ; INPUT 10A NOR INPUT 10B -> OUTPUT 10 test 20: 010 test 21: 110 test 22: 100 test 23: 001 comment: comment: ; INPUT 11A NOR INPUT 11B -> OUTPUT 11 test 24: 010 test 25: 110 test 26: 100 test 27: 001 comment: comment: ; INPUT 12A NAND INPUT 12B -> OUTPUT 12 test 28: 011 test 29: 110 test 30: 101 test 31: 001 comment: comment: ; INPUT 13 -> OUTPUT 13 test 32: 11 test 33: 00 comment: comment: ; INPUT 14 -> OUTPUT 14 test 34: 11 test 35: 00 comment: comment: ; INPUT 15 -> OUTPUT 15 test 36: 11 test 37: 00 comment: comment: ; INPUT 16 -> OUTPUT 16 test 38: 11 test 39: 00 comment: comment: ; INPUT 17 -> OUTPUT 17, OUTPUT 17-N test 40: 110 test 41: 001 comment: comment: ; INPUT 18 -> OUTPUT 18-N test 42: 10 test 43: 01 comment: comment: ; (no change) test 44: 0101010000001001001010010010010000000000101010000111111111 comment: comment: comment: comment: ; PART 2 unique tests (Omnibus DATA00:02-N driving Posibus ACIN and DATA) comment: comment: ; (See PART 1 for Posibus driving Omnibus). comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 45: 011 comment: ; (no change) test 46: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 47: 101 101 test 48: 100 100 test 49: 000 000 test 50: 001 001 test 51: 011 011 test 52: 010 010 test 53: 110 110 test 54: 111 111 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> PosiBus ACIN0:2-N comment: comment: ; OMNIBUS DATA TO I/O DATA-N HI, OUT-N HI; OMNIBUS DATA TO I/O DATA -> LO test 55: 101 comment: ; (no change) test 56: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus DATA0:2-N always HI). test 57: 101101 test 58: 100100 test 59: 000000 test 60: 001001 test 61: 011011 test 62: 010010 test 63: 110110 test 64: 111111 comment: comment: comment: ; Do not select Posibus BAC0:2 -> Omnibus DATA00:02-N comment: ; (we drive Omnibus DATA00:02-N in PART 2). comment: ; skip >>>>> 100 comment: comment: comment: comment: ; Select Omnibus DATA00:02-N -> Posibus DATA0:2-N comment: comment: ; Do 2 steps to avoid >>>>> 100 comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N HI; OMNIBUS DATA TO I/O DATA -> HI test 65: 011 comment: comment: ; OMNIBUS DATA TO I/O DATA-N LO, OUT-N LO; OMNIBUS DATA TO I/O DATA -> HI test 66: 010 comment: ; (no change) test 67: 000111111111 comment: comment: ; All DATA00:02-N patterns (Posibus ACIN0:2-N always HI). test 68: 101 101 test 69: 100 100 test 70: 000 000 test 71: 001 001 test 72: 011 011 test 73: 010 010 test 74: 110 110 test 75: 111 111 comment: comment: ; (no change) test 76: 0101010000001001001010010010010000000000101010000111111111 end: END summary column 1: offset 1, mask 0x1000 column 2: offset 2, mask 0x0080 column 3: offset 1, mask 0x0800 column 4: offset 3, mask 0x0001 column 5: offset 1, mask 0x0400 column 6: offset 3, mask 0x0002 column 7: offset 1, mask 0x0001 column 8: offset 1, mask 0x0008 column 9: offset 1, mask 0x0002 column 10: offset 1, mask 0x0004 column 11: offset 1, mask 0x0010 column 12: offset 1, mask 0x0080 column 13: offset 2, mask 0x1000 column 14: offset 1, mask 0x0020 column 15: offset 1, mask 0x0040 column 16: offset 2, mask 0x2000 column 17: offset 2, mask 0x0400 column 18: offset 4, mask 0x0008 column 19: offset 2, mask 0x0800 column 20: offset 2, mask 0x4000 column 21: offset 2, mask 0x8000 column 22: offset 3, mask 0x1000 column 23: offset 3, mask 0x2000 column 24: offset 3, mask 0x0800 column 25: offset 3, mask 0x4000 column 26: offset 3, mask 0x8000 column 27: offset 2, mask 0x0100 column 28: offset 3, mask 0x0100 column 29: offset 4, mask 0x8000 column 30: offset 3, mask 0x0200 column 31: offset 3, mask 0x0020 column 32: offset 0, mask 0x1000 column 33: offset 3, mask 0x0040 column 34: offset 0, mask 0x0800 column 35: offset 3, mask 0x0080 column 36: offset 0, mask 0x0010 column 37: offset 4, mask 0x0001 column 38: offset 0, mask 0x0008 column 39: offset 4, mask 0x2000 column 40: offset 0, mask 0x4000 column 41: offset 4, mask 0x0004 column 42: offset 4, mask 0x1000 column 43: offset 0, mask 0x8000 column 44: offset 2, mask 0x0020 column 45: offset 2, mask 0x0200 column 46: offset 2, mask 0x0040 column 47: offset 1, mask 0x8000 column 48: offset 1, mask 0x4000 column 49: offset 1, mask 0x2000 column 50: offset 3, mask 0x0004 column 51: offset 3, mask 0x0008 column 52: offset 3, mask 0x0010 column 53: offset 0, mask 0x0400 column 54: offset 0, mask 0x0200 column 55: offset 0, mask 0x0100 column 56: offset 0, mask 0x0004 column 57: offset 0, mask 0x0002 column 58: offset 0, mask 0x0001 direction bits (1=input) 0xFFFF 0x03CC 0xBB9B 0x0E03 0x40FE pullup bits (1=pullup) 0xDF1F 0x0000 0x0080 0x0003 0x0008 test step out_data dont care 1: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 2: 0x8707 0x1000 0xBB00 0x0A1F 0x0004 3: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 4: 0x8707 0x0800 0xBB80 0x0A1E 0x0004 5: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 6: 0x8707 0x0400 0xBB80 0x0A1D 0x0004 7: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 8: 0x8707 0x0009 0xBB80 0x0A1F 0x0004 9: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 10: 0x8707 0x0006 0xBB80 0x0A1F 0x0004 11: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 12: 0x8707 0x0090 0xAB80 0x0A1F 0x0004 13: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 14: 0x8707 0x0060 0x9B80 0x0A1F 0x0004 15: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 16: 0x8707 0x0000 0xB780 0x0A1F 0x000C 17: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 18: 0x8707 0x0000 0x7B80 0x0A1F 0x0004 19: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 20: 0x8707 0x0000 0xBB80 0x221F 0x0004 21: 0x8707 0x0000 0xBB80 0x321F 0x0004 22: 0x8707 0x0000 0xBB80 0x121F 0x0004 23: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 24: 0x8707 0x0000 0xBA80 0x8A1F 0x0004 25: 0x8707 0x0000 0xBA80 0xCA1F 0x0004 26: 0x8707 0x0000 0xBA80 0x4A1F 0x0004 27: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 28: 0x8707 0x0000 0xBB80 0x0A1F 0x8004 29: 0x8707 0x0000 0xBB80 0x091F 0x8004 30: 0x8707 0x0000 0xBB80 0x0B1F 0x0004 31: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 32: 0x9707 0x0000 0xBB80 0x0A3F 0x0004 33: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 34: 0x8F07 0x0000 0xBB80 0x0A5F 0x0004 35: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 36: 0x8717 0x0000 0xBB80 0x0A9F 0x0004 37: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 38: 0x870F 0x0000 0xBB80 0x0A1F 0x0005 39: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 40: 0xC707 0x0000 0xBB80 0x0A1F 0x2000 41: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 42: 0x0707 0x0000 0xBB80 0x0A1F 0x1004 43: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 44: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 45: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 46: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 47: 0x8705 0x0000 0xBBC0 0x0A17 0x0004 48: 0x8704 0x0000 0xBBC0 0x0A07 0x0004 49: 0x8700 0x0000 0xBBC0 0x0A03 0x0004 50: 0x8701 0x0000 0xBBC0 0x0A13 0x0004 51: 0x8703 0x0000 0xBBC0 0x0A1B 0x0004 52: 0x8702 0x0000 0xBBC0 0x0A0B 0x0004 53: 0x8706 0x0000 0xBBC0 0x0A0F 0x0004 54: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 55: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 56: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 57: 0x8507 0x0000 0xB9E0 0x0A17 0x0004 58: 0x8407 0x0000 0xB9E0 0x0A07 0x0004 59: 0x8007 0x0000 0xB9E0 0x0A03 0x0004 60: 0x8107 0x0000 0xB9E0 0x0A13 0x0004 61: 0x8307 0x0000 0xB9E0 0x0A1B 0x0004 62: 0x8207 0x0000 0xB9E0 0x0A0B 0x0004 63: 0x8607 0x0000 0xB9E0 0x0A0F 0x0004 64: 0x8707 0x0000 0xB9E0 0x0A1F 0x0004 65: 0x8707 0x0000 0xBBC0 0x0A1F 0x0004 66: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 67: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 68: 0x8705 0x0000 0xBB80 0x0A17 0x0004 69: 0x8704 0x0000 0xBB80 0x0A07 0x0004 70: 0x8700 0x0000 0xBB80 0x0A03 0x0004 71: 0x8701 0x0000 0xBB80 0x0A13 0x0004 72: 0x8703 0x0000 0xBB80 0x0A1B 0x0004 73: 0x8702 0x0000 0xBB80 0x0A0B 0x0004 74: 0x8706 0x0000 0xBB80 0x0A0F 0x0004 75: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 76: 0x8707 0x0000 0xBB80 0x0A1F 0x0004 PINs used (in edge connector order) (G=ground,P=power) SLOT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB LETTER ABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUVABCDEFHJKLMNPRSTUV SIDE 111111111111111111222222222222222222111111111111111111222222222222222222 USAGE PP PPPPPIIIIII GOIP GPPPPPIIOOIIOO OOOIOOIIIIO OIIGIIP GIIPPPIIIIIII OP UUT inputs: 29 UUT outputs: 29 pins used: 58 not used: 8 76 'test steps' 231 lines M7102 PCB REV D SCHEMATIC REV C Positive I/O Bus Converter (DW08E) PART 2 Tests Omnibus DATA BUS driving Posibus ACIN and DATA. (See PART 1 for Posibus driving Omnibus. (Two parts are necessary due to the Omnibus DATA00:02-N is a bidirectional bus). Tolerates 3.3k ohm pullups to +5v on pin (are needed for PART 1): BK2 Omnibus DATA00 (bidirectional, input + open collector output) BL2 Omnibus DATA01 (bidirectional, input + open collector output) BM2 Omnibus DATA02 (bidirectional, input + open collector output) PINS Main menu Sun Nov 29 15:08:39 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit *************************************************************************** * did not verify registers after initialize (chip reset). * * check that the tester is cabled to LPT port and that the power is on. * *************************************************************************** Main menu Sun Nov 29 15:08:47 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit *************************************************************************** * did not verify registers after initialize (chip reset). * * check that the tester is cabled to LPT port and that the power is on. * *************************************************************************** Main menu Sun Nov 29 15:08:53 2015 test file is: tests\m7102_2.tst delay is: 0 trigger is: 1 1 read test file 2 set test delay 3 set test trigger 4 run test 5 output loading test 8 diags 9 exit exiting